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hpw421初始版本

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xushaoxiang
2026-06-06 16:49:48 +08:00
commit 2339bbfd1f
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component/rf24/Drivers/xc6xxx_rf_2_4g/xc6xxx_rf_2_4g.c
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/*!J
* \file rf_2_4g.c
*
* \brief Target RF 2.4g implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx_rf_2_4g.h"
#include "xc60xx.h"
#if RF_MOUSE
#include "rf_mouse.h"
#endif
#ifdef RF_ADV_INTER
#include "rf_adv_config.h"
#endif
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define AD_RCCAL_FINISH_VAL 0x8000
#define RX_ON 0x01
#define PIPE0_LEN XINCX_2_4G_PIPE0_LEN
#define PIPE1_LEN XINCX_2_4G_PIPE1_LEN
#define PIPE2_LEN XINCX_2_4G_PIPE2_LEN
#define PIPE3_LEN XINCX_2_4G_PIPE3_LEN
#define PIPE4_LEN XINCX_2_4G_PIPE4_LEN
#define PIPE5_LEN XINCX_2_4G_PIPE5_LEN
#define TX_ADDR_L_VAL XINCX_2_4G_ADDR_L
#define TX_ADDR_H_VAL XINCX_2_4G_ADDR_H
#define RX_ADDR_L_VAL TX_ADDR_L_VAL
#define RX_ADDR_H_VAL TX_ADDR_H_VAL
#ifdef RF_ADV_INTER
extern uint8_t recv_adv_buf[XINCX_ADV_PIPE0_LEN];
#endif
uint8_t recv_len = 0;
uint8_t recv_buf[BUFF_LEN] = {0};
bool rf24g_handler_flag = false;
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
void nop_cnt(uint32_t cnt)
{
for (uint32_t i = 0; i < cnt; i++)
__nop();
}
/**
* @brief Reverse bits
* @param uint8_t - input
* @retval uint8_t - temp
*/
uint8_t reverseBits(uint8_t input)
{
uint8_t i = 0, temp = 0;
for (; i < 8; i++) {
temp <<= 1;
temp = ((input >> i) & 0x01) ? (temp | 0x01) : (temp | 0x00);
}
return temp;
}
/**
* @brief Ble whiten channel
* @param uint16_t - fre
* @retval uint8_t - temp | 2
*/
uint8_t bleWhitenStart(uint16_t Fre)
{
uint8_t chan = (Fre == 2426) ? 38 : ((Fre == 2402) ? 37 : 39);
return reverseBits(chan) | 2;
}
/**
* @brief Ble whiten
* @param uint8_t * - data
* @param uint8_t - len
* @param uint8_t - whitenCoeff
* @retval void
*/
void ble_whiten(uint8_t *data, uint8_t len, uint8_t whitenCoeff)
{
uint8_t m;
while (len--) {
for (m = 1; m; m <<= 1) {
if (whitenCoeff & 0x80) {
whitenCoeff ^= 0x11;
(*data) ^= m;
}
whitenCoeff <<= 1;
}
// Flip variables
*data = reverseBits(*data);
data++;
}
}
/**
* @brief
* @param void
* @retval void
*/
void ble_crc(uint8_t *data, uint8_t len, uint8_t *dst)
{
// calculating the CRC based on a LFSR
uint8_t i, temp, tempData;
while (len--) {
tempData = *data++;
for (i = 0; i < 8; i++, tempData >>= 1) {
temp = dst[0] >> 7;
dst[0] <<= 1;
if (dst[1] & 0x80) {
dst[0] |= 1;
}
dst[1] <<= 1;
if (dst[2] & 0x80) {
dst[1] |= 1;
}
dst[2] <<= 1;
if (temp != (tempData & 1)) {
dst[2] ^= 0x5B;
dst[1] ^= 0x06;
}
}
}
dst[2] = reverseBits(dst[2]);
dst[1] = reverseBits(dst[1]);
dst[0] = reverseBits(dst[0]);
}
/**
* @brief RF rc calibration
* @param void
* @retval void
*/
void rf_rc_calib(void)
{
static uint8_t calib_flag = false;
uint8_t delay_cnt = 20;
if (calib_flag)
return;
uint16_t r_val = 0;
// RG_ RCCAL_ CTRL (Rccal output code value control) def"101"
XC_BT_RF->rccal_reg_l &= ~(0x7 << 8);
XC_BT_RF->rccal_reg_l |= (0x5 << 8);
delay_us(delay_cnt);
// RG_RCCAL_RESETN = 1
XC_BT_RF->rccal_reg_l |= (0x1 << 5);
delay_us(delay_cnt);
// RG_RCCAL_SEL = 0
XC_BT_RF->rccal_reg_l &= ~(0x1 << 3);
delay_us(delay_cnt);
// RG_RCCAL_EN = 1
XC_BT_RF->rccal_reg_l |= (0x1 << 2);
delay_us(delay_cnt);
// RG_RCCAL_START = 1
XC_BT_RF->rccal_reg_l |= (0x1 << 4);
delay_us(delay_cnt);
r_val = XC_BT_RF->rccal_rslt_l;
// Waiting for AD_ RCCAL_ FINISH raises the calibration value AD_ RCCAL_
// CTRIM
while (!(r_val & AD_RCCAL_FINISH_VAL)) {
r_val = XC_BT_RF->rccal_rslt_l;
}
r_val = (XC_BT_RF->rccal_rslt_l & 0x7FFF) >> 10;
// RG_RCCAL_SEL = 1
XC_BT_RF->rccal_reg_l |= (0x1 << 3);
// RG_RCCAL_EN = 0
XC_BT_RF->rccal_reg_l &= ~(0x1 << 2);
// RG_RCCAL_START = 0
XC_BT_RF->rccal_reg_l &= ~(0x1 << 4);
XC_BT_RF->rccal_reg_l &= ~(0x1F << 11);
XC_BT_RF->rccal_reg_l |= r_val << 11;
calib_flag = true;
}
/**
* @brief Reset rf 2.4g modem
* @param void
* @retval void
*/
void reset_rf2_4g(void)
{
uint32_t value = 0;
value = cpr_rf_reg1_get();
cpr_rf_reg1_set(value & ~(1 << 21));
delay_ms(2);
cpr_rf_reg1_set(value | (1 << 21));
delay_ms(1);
}
/**
* @brief Frequency offset tune
* @param uint8_t - val
* @retval void
*/
void freq_ctune(uint8_t val)
{
uint32_t value = 0;
value = cprao_aon_rf_aonreg_get();
cprao_aon_rf_aonreg_set((value & (~(0x3f << 20))) | ((val & 0x3f) << 20));
}
/**
* @brief Rf modem init
* @param void
* @retval void
*/
void rf24g_modem_init(void)
{
// open bt clock
/* BT_CLK clock control register */
cpr_bt_clk_ctl__bt_clk_en__setf(ENABLE);
/* BT_ MODEM_ CLK clock control register */
cpr_bt_modem_clk_ctl__bt_modem_clk_en__setf(ENABLE);
/* Configure BT_ PCLK_ EN enable */
cpr_ctlapbclken_grctl__bt_pclk_en__setf(ENABLE);
// CPR_AO BB_CORELDORF_EN
// XC_CPR_AO->AON_CORERFLDO_EN = 0x1;
cprao_aon_coreldo_en_set(ENABLE);
/* detrefbias */
XC_BT_RF->ana18_reg_l &= ~((0x7 << 3) | (0x7));
XC_BT_RF->ana18_reg_l |= (0x1 << 3);
}
/**
* @brief Config 2.4g rf parameters
* @param void
* @retval void
*/
void rf24g_config(void)
{
// Set sel_24G_rfchan, sel_24G_rfldoen, sel_24G_rampout regs to use 2.4G signal
XC_BT_RF->BT.rx_ctrl_sel_l |= 0xE000;
#if (XINCX_RF_TRANS_RATE == DR_1M)
XC_BT_RF->ana21_reg_l = (XC_BT_RF->ana21_reg_l & (0xFFFF8FFF)) | 0x3000;
#elif (XINCX_RF_TRANS_RATE == DR_2M)
XC_BT_RF->ana21_reg_l = (XC_BT_RF->ana21_reg_l & (0xFFFF8FFF)) | 0x2000;
XC_BT_RF->ana3_reg_l |= 0x01;
#else
XC_BT_RF->ana21_reg_l = (XC_BT_RF->ana21_reg_l & (0xFFFF8FFF)) | 0x6000;
#endif
// Manual afc
XC_BT_RF->ana29_reg_l |= 0x02;
// Afc pulse
XC_BT_RF->ana28_reg_l |= 0x01;
reset_rf2_4g();
// enable 2.4G_mclk 2.4G_hclk 2div of 32MHz
cpr_rf_reg1__rf24g_mclk_div__setf(1);
cpr_rf_reg1__rf24g_hclk_en__setf(ENABLE);
cpr_rf_reg1__rf24g_mclk_en__setf(ENABLE);
// set 2.4G agc and iq from 2.4 modem
cpr_rf_reg0__sel__24g_agc__setf(ENABLE);
cpr_rf_reg0__sel__24g_hwpin__setf(ENABLE);
*BLE_COMN_RF24G_CTRL |= 0x700;
XC_BT_RF->BT.rf_ctrl1_l |= (1 << 13);
XC_BT_RF->BT.rf_ctrl1_l &= ~(1 << 12);
XC_BT_RF->ana2_reg_l &= ~((0xf << 5) | (0x7 << 13));
XC_BT_RF->ana2_reg_l |= (0x9 << 5) | (0x3 << 13);
}
/**
* @brief Set rf dynpd
* @param uint8_t - dynpd
* @retval void
*/
void set_rf_dynpd(uint8_t dynpd) { XC_RF_2_4G->DYNPD = dynpd; }
/**
* @brief Set rf tx power
* @param uint8_t - tx_pwr
* @retval void
*/
void set_rf_power(uint8_t tx_pwr)
{
XC_BT_RF->ana21_reg_l = (XC_BT_RF->ana21_reg_l & (~0xfc0)) | ((tx_pwr & 0x3f) << 6);
XC_RF_2_4G->RF_CH = (XC_RF_2_4G->RF_CH & (~0x3f0000)) | (tx_pwr << 16);
}
/**
* @brief Set rf channel
* @param uint16_t - channel
* @retval void
*/
void set_rf_channel(uint16_t channel)
{
#if (XINCX_RF_TRANS_RATE == RATE_2M)
XC_RF_2_4G->RF_CH = ((XC_RF_2_4G->CFG_TOP & RX_ON) ? (channel - 2) : channel);
#else
XC_RF_2_4G->RF_CH = ((XC_RF_2_4G->CFG_TOP & RX_ON) ? (channel - 1) : channel);
#endif // XINCX_RF_TRANS_RATE
delay_us(1);
XC_BT_RF->ana28_reg_l &= (~0x1); // Afc pulse
delay_us(1);
XC_BT_RF->ana28_reg_l |= 0x1; // Afc pulse
delay_us(1);
}
/**
* @brief Set rf tx addr
* @param uint32_t - addr_l
* uint32_t - addr_h
* @retval void
*/
void set_rf_txaddr(uint32_t addr_l, uint32_t addr_h)
{
XC_RF_2_4G->TX_ADDR_L = addr_l;
XC_RF_2_4G->TX_ADDR_H = (XC_RF_2_4G->TX_ADDR_H & 0xFF00) | (addr_h & 0xFF);
}
/**
* @brief Set rf pipe0 tx addr
* @param uint32_t - addr_l
* uint32_t - addr_h
* @retval void
*/
void set_rf_pipe0_rxaddr(uint32_t addr_l, uint32_t addr_h)
{
XC_RF_2_4G->RX_ADDR_P0_L = addr_l;
XC_RF_2_4G->RX_ADDR_P0_H = addr_h & 0xff;
}
/**
* @brief Set rf tx addr width
* @param uint8_t - bytes
*
* @retval void
*/
void set_rf_tx_addr_width(uint8_t bytes)
{
switch (bytes) {
case 3:
XC_RF_2_4G->SETUP_AW = 0xa5;
break;
case 4:
XC_RF_2_4G->SETUP_AW = 0xaa;
break;
case 5:
XC_RF_2_4G->SETUP_AW = 0xaf;
break;
}
}
/**
* @brief Set rf data rate
* @param uint8_t - rate
*
* @retval void
*/
void set_rf_DR(uint8_t rate) { XC_RF_2_4G->SETUP_RF = rate; }
/**
* @brief Set rf feature
* @param uint8_t - long_pld
* uint8_t - fec
* uint8_t - whiten
* uint8_t - dpl
* uint8_t - ack_pay
* uint8_t - dyn_ack
* @retval void
*/
void set_rf_feature(uint8_t long_pld, uint8_t fec, uint8_t whiten, uint8_t dpl, uint8_t ack_pay, uint8_t dyn_ack)
{
XC_RF_2_4G->FEATURE = (long_pld << 5) | (fec << 4) | (whiten << 3) | (dpl << 2) | (ack_pay << 1) | dyn_ack;
}
/**
* @brief Set rf compatility feature
* @param uint8_t - guard_cfg
* uint8_t - long_pld_type
* uint8_t - preamble_num
* uint8_t - preamble_type
* uint8_t - crc_scope_header
* uint8_t - crc_scope_addr
* @retval void
*/
void set_rf_compatility_featue(uint8_t guard_cfg, uint8_t long_pld_type, uint8_t preamble_num, uint8_t preamble_type,
uint8_t crc_scope_header, uint8_t crc_scope_addr)
{
XC_RF_2_4G->FEATURE = (XC_RF_2_4G->FEATURE & ~(0xff << 8)) | (guard_cfg << 15) | (long_pld_type << 14) |
(preamble_num << 12) | (preamble_type << 11) | (crc_scope_header << 9) |
(crc_scope_addr << 8);
}
/**
* @brief Set rf preamble
* @param uint8_t - preamble_word
*
* @retval void
*/
uint8_t set_rf_preamble(uint32_t preamble_word)
{
if (!(XC_RF_2_4G->FEATURE & ~(1 << 11)))
return 1;
XC_RF_2_4G->PREAMBLE = preamble_word;
return 0;
}
/**
* @brief Set rf guard woard
* @param uint8_t - guard_word
*
* @retval void
*/
void set_rf_guard_woard(uint16_t guard_word) { XC_RF_2_4G->GUARD = guard_word; }
/**
* @brief Set rf mode
* @param uint8_t - mode
*
* @retval void
*/
void set_rf_mode(uint8_t mode)
{
#if (XINCX_RF_TRANS_RATE == RATE_2M)
XC_RF_2_4G->CFG_TOP = (XC_RF_2_4G->CFG_TOP & (~0x1ffff3)) | (mode & 0x01) | 0x1b8672;
#else
XC_RF_2_4G->CFG_TOP = (XC_RF_2_4G->CFG_TOP & (~0x1ffff3)) | (mode & 0x01) | 0x0b8272;
#endif
}
/**
* @brief Set rf crc
* @param uint8_t - enable
* uint8_t - crc_bit
* @retval void
*/
void set_rf_crc(uint8_t enable, uint8_t crc_bit)
{
uint32_t val = 0x0c;
if (enable) {
if (crc_bit == CRC_1BIT) {
XC_RF_2_4G->CFG_TOP |= ~val;
XC_RF_2_4G->CFG_TOP |= 0x08;
} else {
XC_RF_2_4G->CFG_TOP |= val;
}
} else {
val = 0x08;
XC_RF_2_4G->CFG_TOP &= ~val;
}
}
/**
* @brief Set rf pipe rx payload len
* @param uint8_t - p0_len
* uint8_t - p1_len
* uint8_t - p2_len
* uint8_t - p3_len
* uint8_t - p4_len
* uint8_t - p5_len
* @retval void
*/
void set_rf_pipe_rx_payLen(uint8_t p0_len, uint8_t p1_len, uint8_t p2_len, uint8_t p3_len, uint8_t p4_len,
uint8_t p5_len)
{
XC_RF_2_4G->RX_PW_Px_L = p0_len | (p1_len << 8) | (p2_len << 16) | (p3_len << 24);
XC_RF_2_4G->RX_PW_Px_H = p4_len | (p5_len << 8);
}
/**
* @brief Set rf retry parameters
* @param uint8_t - cnt
* uint8_t - delay
* @retval void
*/
void set_rf_retr(uint8_t cnt, uint8_t delay) { XC_RF_2_4G->SETUP_RETR = cnt | (delay << 4); }
/**
* @brief Set rf pipe en_aa
* @param uint8_t - pipe0_enaa
* uint8_t - pipe1_enaa
* uint8_t - pipe2_enaa
* uint8_t - pipe3_enaa
* uint8_t - pipe4_enaa
* uint8_t - pipe5_enaa
* @retval void
*/
void set_rf_enaa(uint8_t pipe0_enaa, uint8_t pipe1_enaa, uint8_t pipe2_enaa, uint8_t pipe3_enaa, uint8_t pipe4_enaa,
uint8_t pipe5_enaa)
{
XC_RF_2_4G->EN_AA = (pipe0_enaa << 0) | (pipe1_enaa << 1) | (pipe2_enaa << 2) | (pipe3_enaa << 3) |
(pipe4_enaa << 4) | (pipe5_enaa << 5);
}
/**
* @brief Rf tx packet
* @param uint8_t * - data
* uint8_t - len
* @retval uint8_t - ret = 0 or 1
*/
__RAM_CODE uint8_t rf_tx_packet(uint8_t *data, uint8_t len)
{
uint8_t ret;
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
XC_RF_2_4G->STATUS = MASK_TX_DS | MASK_MAX_RT;
if (!((XC_RF_2_4G->STATUS_FIFO & STAT_TX_FULL) == STAT_TX_FULL)) {
for (uint8_t i = 0; i < RF_SEND_CMD_CNT; i++)
XC_RF_2_4G->CMD_CFG = CMD_DONE | W_TX_PLOAD;
for (uint8_t i = 0; i < len; i++)
XC_RF_2_4G->TX_FIFO_DATA = data[i];
CE_CTL_HIGH;
delay_us(100); // 100
CE_CTL_LOW;
ret = false;
} else {
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
ret = true;
}
return ret;
}
/**
* @brief Rf rx packet
* @param uint8_t * - buff
*
* @retval uint8_t - len
*/
__RAM_CODE uint8_t rf_rx_packet(uint8_t *buff)
{
uint8_t len = 0;
if ((XC_RF_2_4G->STATUS & MASK_RX_DR) == MASK_RX_DR) {
CE_CTL_LOW;
XC_RF_2_4G->CMD_CFG = CMD_DONE | R_RX_PL_WID;
len = XC_RF_2_4G->RX_FIFO_LEN & 0xff;
if (len) {
for (uint8_t i = 0; i < RF_RECV_CMD_CNT; i++) {
nop_cnt(16);
XC_RF_2_4G->CMD_CFG = CMD_DONE | R_RX_PLOAD;
nop_cnt(16);
}
for (uint8_t i = 0; i < len; i++) {
buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
}
}
XC_RF_2_4G->CMD_CFG = FLUSH_RX | CMD_DONE;
XC_RF_2_4G->STATUS = MASK_RX_DR;
}
return len;
}
/**
* @brief Rf set channel
* @param uint16_t - channel
*
* @retval void
*/
void rf_set_channel(uint16_t channel)
{
set_rf_channel(channel);
#if XINCX_RF_MODE
#if (XINCX_RF_NVIC_MODE)
NVIC_EnableIRQ(RF24G_IRQn);
#endif // XINCX_RF_NVIC_MODE
#endif // XINCX_RF_MODE
}
/**
* @brief Rf 2.4g Initialization
* @param void
*
* @retval void
*/
void rf24g_init(void)
{
/* Rf modem init*/
rf24g_modem_init();
/* Set up 2.4G RF modem*/
rf24g_config();
/* Set up crystal oscillator capacitor array */
freq_ctune(XINCX_2_4G_CRY_CPT_ARRAY);
/* Set up dynamic load */
set_rf_dynpd(XINCX_2_4G_DYNPD);
/* Set retransmission delay and retransmission frequency */
set_rf_retr(XINCX_2_4G_RETRANS_CNT, XINCX_2_4G_RETRANS_DELAY);
/* Set address width */
set_rf_tx_addr_width(XINCX_RF_TX_ADDR_WIDTH);
/* Set PTX address */
set_rf_txaddr(TX_ADDR_L_VAL, TX_ADDR_H_VAL);
/* Set PRX address */
set_rf_pipe0_rxaddr(RX_ADDR_L_VAL, RX_ADDR_H_VAL);
/* Set transfer rate */
set_rf_DR(XINCX_RF_TRANS_RATE);
/* Set CRC */
set_rf_crc(XINCX_RF_CRC_ENABLE, XINCX_2_4G_CRC_BYTE);
/* Set data frame format */
set_rf_feature(XINCX_2_4G_LONG_PLD, XINCX_2_4G_FEC, XINCX_2_4G_WHITEN, XINCX_2_4G_DPL, XINCX_2_4G_ACK_PAY,
XINCX_2_4G_DYN_ACK);
set_rf_compatility_featue(XINCX_2_4G_GUARD_CFG, XINCX_2_4G_LONG_PLD_TYPE, XINCX_2_4G_PREAMBLE_NUM,
XINCX_2_4G_PREAMBLE_TYPE, XINCX_2_4G_CRC_SCOPE_HEADER, XINCX_2_4G_CRC_SCOPE_ADDR);
/* Set the leading code */
set_rf_preamble(XINCX_2_4G_PREAMBLE);
/* Set guard field */
set_rf_guard_woard(XINCX_2_4G_GUARD);
/* Set Payload */
set_rf_pipe_rx_payLen(PIPE0_LEN, PIPE1_LEN, PIPE2_LEN, PIPE3_LEN, PIPE4_LEN, PIPE5_LEN);
/* Set mode */
set_rf_mode(XINCX_RF_MODE);
/* Set transmission power */
set_rf_power(XINCX_POWER);
/*Set ack pipe*/
set_rf_enaa(XINCX_2_4G_PIPE0_ENAA, XINCX_2_4G_PIPE1_ENAA, XINCX_2_4G_PIPE2_ENAA, XINCX_2_4G_PIPE3_ENAA,
XINCX_2_4G_PIPE4_ENAA, XINCX_2_4G_PIPE5_ENAA);
/* RC filtering calibration */
rf_rc_calib();
}
/**
* @brief Rf 2.4g tx event
* @param uint8_t - buff
* uint8_t - len
* @retval eRF_Tx_Status - ret
*/
__RAM_CODE eRF_Tx_Status rf_tx_event(uint8_t *buff, uint8_t len)
{
eRF_Tx_Status ret = TX_DATA_INVALID;
static uint32_t send_cnt = 0;
if (len == 0) {
return ret;
}
while (rf_tx_packet(buff, len))
;
do {
if ((XC_RF_2_4G->STATUS & MASK_TX_DS) == MASK_TX_DS) {
XC_RF_2_4G->STATUS |= MASK_ALL_INTER;
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
ret = TX_DATA_OK;
break;
} else if ((XC_RF_2_4G->STATUS & MASK_MAX_RT) == MASK_MAX_RT) {
XC_RF_2_4G->STATUS |= MASK_ALL_INTER;
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
ret = TX_RETRANS_MAX;
break;
}
} while (1);
send_cnt++;
return ret;
}
/**
* @brief Rf 2.4g rx event
* @param uint8_t * - buff
*
* @retval uint8_t - len
*/
__RAM_CODE uint8_t rf_rx_event(uint8_t *buff) { return rf_rx_packet(buff); }
/**
* @brief Rf 2.4g rx handler
* @param void
*
* @retval void
*/
__RAM_CODE void RF24G_Handler(void)
{
CE_CTL_LOW;
rf24g_handler_flag = true;
#if (1 == XINCX_RF_ADV_NVIC_MODE)
recv_len = rf_rx_event(recv_adv_buf);
#endif // XINCX_RF_ADV_NVIC_MODE
#if (1 == XINCX_RF_NVIC_MODE)
recv_len = rf_rx_event(recv_buf);
#endif // XINCX_RF_NVIC_MODE
XC_RF_2_4G->CMD_CFG = FLUSH_TX | CMD_DONE;
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
rf_24g_callback(NULL);
/* The stable time of receiving dynamic ACK is interrupted */
nop_cnt(4);
}
__WEAK void rf_24g_callback(void *context) {}
/**
* @brief rf_2M_config
* @param void
* @return void
*/
void rf_2M_config(void)
{
XC_BT_RF->BT.rf_ctrl1_l |= (1 << 12) | (1 << 13);
/* 2M Frequency select */
XC_RF_2_4G->CFG_TOP = (XC_RF_2_4G->CFG_TOP & 0xFFFFFFFF) | (1 << 10) | (1 << 20);
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | 0x158); // 0x158
XC_BT_RF->ana5_reg_l &= ~(0x1f);
XC_BT_RF->ana5_reg_l |= 0x06;
XC_BT_RF->ana19_reg_l &= ~((0x7 << 11) | (0xf << 4));
XC_BT_RF->ana19_reg_l |= (3 << 11);
uint8_t agc_buff[5] = {0};
for (uint8_t i = 0; i < 5; i++) {
agc_buff[i] = 0x42 - 10 * i;
if (i == 4) {
agc_buff[i] = agc_buff[i - 1] - 12;
}
}
XC_RF_2_4G->PGA_SETTING = (agc_buff[0] << 0) | (agc_buff[1] << 8) | (agc_buff[2] << 16) | (agc_buff[3] << 24);
XC_RF_2_4G->TX_ADDR_H = (XC_RF_2_4G->TX_ADDR_H & ~(0xff << 8)) | (agc_buff[4] << 8);
XC_BT_RF->ana24_reg_l &= ~(0x7);
XC_BT_RF->ana24_reg_l |= (0x2);
XC_BT_RF->ana19_reg_l &= ~(0xf);
XC_BT_RF->ana19_reg_l |= 0x4;
XC_BT_RF->ana8_reg_l &= ~(0x3 << 2);
XC_BT_RF->ana11_reg_l &= ~(0x1f << 6);
XC_BT_RF->ana11_reg_l |= (0x7 << 6);
}
component/rf24/Drivers/xc6xxx_rf_2_4g/xc6xxx_rf_2_4g.h
+173
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@@ -0,0 +1,173 @@
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RF_2_4G_H__
#define __RF_2_4G_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_config.h"
#include "xc6xxx.h"
#include "xc_rf_24g_register.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* RF Command Code */
#define R_REG 0x00
#define W_REG 0x20
#define R_RX_PL_WID 0x60
#define R_RX_PLOAD 0x61
#define W_TX_PLOAD 0xA0
#define W_TX_PLOAD_NOACK 0xB0
#define W_ACK_PLOAD 0xA8
#define FLUSH_TX 0xE1
#define FLUSH_RX 0xE2
#define REUSE_TX_PL 0xE3
#define CMD_NOP 0xFF
#define CMD_DONE 0x100
/* FIFO status */
#define STAT_TX_REUSE (0x1 << 6)
#define STAT_TX_FULL (0x1 << 5)
#define STAT_TX_EMPTY (0x1 << 4)
#define STAT_RX_FULL (0x02)
#define STAT_RX_EMPTY (0x01)
/* STATUS Interrupt status */
#define MASK_RX_DR (0x1 << 6)
#define MASK_TX_DS (0x1 << 5)
#define MASK_MAX_RT (0x1 << 4)
#define MASK_ALL_INTER (MASK_RX_DR | MASK_TX_DS| MASK_MAX_RT)
#define CRC_1BIT 1U
#define CRC_2BIT 2U
#define DR_1M 0x02
#define DR_2M 0x0A
#define DR_250K 0x22
#define DR_125K 0x2A
#define TX_MODE 0
#define RX_MODE 1
#define CE_CTL_HIGH XC_RF_2_4G->CFG_TOP |= 0x4000
#define CE_CTL_LOW XC_RF_2_4G->CFG_TOP &= ~0x4000
#define DELAY_CNT 0U
#define RATE_1M 0x02
#define RATE_2M 0x0A
#define RATE_250K 0x22
#define RATE_125K 0x2A
#define LOGI(...) printf(__VA_ARGS__)
#ifdef RF_DEMO
#define FAIL 0U
#define SUCCESS 1U
#define ASSERT while(1)
#endif
#define RF_SEND_CMD_CNT 6U
#define RF_RECV_CMD_CNT 4U
#define BUFF_LEN XINCX_2_4G_PIPE0_LEN
/* RF Tx Status Typedef */
typedef enum
{
TX_DATA_OK = 0,
TX_DATA_INVALID = 1,
TX_RETRANS_MAX = 2
}eRF_Tx_Status;
typedef struct
{
uint8_t buff[BUFF_LEN];
uint32_t cnt;
uint32_t temp;
uint8_t data_length;
} rf_data_typedef_t;
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern uint8_t recv_len;
extern uint8_t recv_buf[BUFF_LEN];
extern bool rf24g_send_timer_flag;
extern bool rf24g_handler_flag;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void nop_cnt(uint32_t cnt);
uint8_t reverseBits(uint8_t input);
uint8_t bleWhitenStart(uint16_t Fre);
void ble_whiten(uint8_t *data, uint8_t len, uint8_t whitenCoeff);
void ble_crc(uint8_t *data, uint8_t len, uint8_t *dst);
void rf_rc_calib(void);
void reset_rf2_4g(void);
void freq_ctune(uint8_t val);
void rf24g_modem_init(void);
void rf24g_config(void);
void rf24g_init(void);
void set_rf_dynpd(uint8_t dynpd);
void set_rf_power(uint8_t tx_pwr);
void rf_set_channel(uint16_t channel);
void set_rf_txaddr(uint32_t addr_l, uint32_t addr_h);
void set_rf_pipe0_rxaddr(uint32_t addr_l, uint32_t addr_h);
void set_rf_tx_addr_width(uint8_t bytes);
void set_rf_DR(uint8_t rate);
void set_rf_feature(uint8_t long_pld, uint8_t fec, uint8_t whiten, uint8_t dpl, uint8_t ack_pay, uint8_t dyn_ack);
void set_rf_compatility_featue(uint8_t guard_cfg, uint8_t long_pld_type, uint8_t preamble_num,
uint8_t preamble_type, uint8_t crc_scope_header, uint8_t crc_scope_addr);
uint8_t set_rf_preamble(uint32_t preamble_word);
void set_rf_guard_woard(uint16_t guard_word);
void set_rf_mode(uint8_t mode);
void set_rf_crc(uint8_t enable, uint8_t crc_bit);
void set_rf_pipe_rx_payLen(uint8_t p0_len, uint8_t p1_len, uint8_t p2_len, uint8_t p3_len, uint8_t p4_len,
uint8_t p5_len);
void set_rf_retr(uint8_t cnt, uint8_t delay);
void set_rf_enaa(uint8_t pipe0_enaa, uint8_t pipe1_enaa, uint8_t pipe2_enaa, uint8_t pipe3_enaa, uint8_t pipe4_enaa,
uint8_t pipe5_enaa);
void rf_24g_callback(void *context);
void rf_2M_config(void);
uint8_t rf_tx_packet(uint8_t *data, uint8_t len);
uint8_t rf_rx_packet(uint8_t *buff);
eRF_Tx_Status rf_tx_event(uint8_t *buff, uint8_t len);
uint8_t rf_rx_event(uint8_t *buff);
#define INFO_BUFF(buff, len) rf_buff_info(buff, len)
#ifdef __cplusplus
}
#endif
#endif /* __RF_2_4G__ */
component/rf24/Drivers/xc6xxx_rf_ADV/xc6xxx_rf_ADV.c
+135
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@@ -0,0 +1,135 @@
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:24:01
* @LastEditors: sueRimn
* @LastEditTime: 2023-12-13 10:32:28
*/
/*!
* \file rf_2_4g.c
*
* \brief Target RF 2.4g implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx_rf_ADV.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
extern int sendchar(int c);
extern uint8_t recv_len ;
extern uint8_t recv_buf[BUFF_LEN];
extern uint8_t recv_adv_buf[ADV_LENGTH];
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
* @brief RF ADV Initialization
* @param void
*
* @retval void
*/
void rf24g_adv_init(void)
{
/* Rf modem init*/
rf24g_modem_init();
/* Set up 2.4G RF modem*/
rf24g_config();
set_rf_dynpd(XINCX_2_4G_DYNPD);
/* Set PTX address */
set_rf_txaddr(TX_ADDR_L_VAL, TX_ADDR_H_VAL);
/* Set PRX address */
set_rf_pipe0_rxaddr(RX_ADDR_L_VAL, RX_ADDR_H_VAL);
/* Set address width */
set_rf_tx_addr_width(XINCX_RF_TX_ADDR_WIDTH);
/* Set transfer rate */
set_rf_DR(XINCX_RF_TRANS_RATE);
/* Set CRC */
set_rf_crc(XINCX_RF_CRC_ENABLE, XINCX_2_4G_CRC_BYTE);
/* Set data frame format */
set_rf_feature(XINCX_ADV_LONG_PLD, XINCX_ADV_FEC, XINCX_ADV_WHITEN,
XINCX_ADV_DPL, XINCX_ADV_ACK_PAY, XINCX_ADV_DYN_ACK);
/* Set Payload */
set_rf_pipe_rx_payLen(PIPE0_LEN, PIPE1_LEN, PIPE2_LEN, PIPE3_LEN, PIPE4_LEN,
PIPE5_LEN);
/* Set mode */
set_rf_mode(XINCX_ADV_MODE);
/* Set transmission power */
set_rf_power(XINCX_POWER);
/* RC filtering calibration */
rf_rc_calib();
}
/**
* @brief RF ADV packet whiten
* @param uint8_t * - len
* @return uint32_t - blecrc
*/
uint32_t rf_adv_packet_whiten(uint8_t *len)
{
for (int i = 0; i < recv_len; i++)
recv_adv_buf[i] = reverseBits(recv_adv_buf[i]);
ble_whiten(recv_adv_buf, recv_len, bleWhitenStart(XINCX_ADV_CHANNEL));
for (int i = 0; i < recv_len; i++)
recv_adv_buf[i] = reverseBits(recv_adv_buf[i]);
*len = (recv_adv_buf[1] > (ADV_LENGTH - 5)) ? (ADV_LENGTH - 5)
: recv_adv_buf[1];
uint32_t blecrc = (recv_adv_buf[*len + 5 - 1] << 16) +
(recv_adv_buf[*len + 5 - 2] << 8) +
recv_adv_buf[*len + 5 - 3];
recv_adv_buf[*len + 5 - 1] = recv_adv_buf[*len + 5 - 2] =
recv_adv_buf[*len + 5 - 3] = 0x55;
ble_crc(recv_adv_buf, *len + 5 - 3, recv_adv_buf + *len + 5 - 3);
return blecrc;
}
/**
* @brief RF ADV software CRC determination
* @param uint8_t * - adv_buff
* @param uint8_t * - len
* @param uint32_t - blecrc
* @return uint8_t - 0
*/
uint8_t rf_adv_crc(uint8_t *adv_buff, uint8_t *len, uint32_t blecrc)
{
if (blecrc == ((adv_buff[*len + 5 - 1] << 16) +
(adv_buff[*len + 5 - 2] << 8) + adv_buff[*len + 5 - 3]))
return 1;
else
return 0;
}
component/rf24/Drivers/xc6xxx_rf_ADV/xc6xxx_rf_ADV.h
+90
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@@ -0,0 +1,90 @@
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:24:01
* @LastEditors: sueRimn
* @LastEditTime: 2023-12-13 13:56:02
*/
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6XXX_RF_ADV_H__
#define __XC6XXX_RF_ADV_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_adv_config.h"
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define PIPE0_LEN XINCX_ADV_PIPE0_LEN
#define PIPE1_LEN XINCX_ADV_PIPE1_LEN
#define PIPE2_LEN XINCX_ADV_PIPE2_LEN
#define PIPE3_LEN XINCX_ADV_PIPE3_LEN
#define PIPE4_LEN XINCX_ADV_PIPE4_LEN
#define PIPE5_LEN XINCX_ADV_PIPE5_LEN
#define MAC_ADDR_0 XINC_ADV_MAC_ADDR_0
#define MAC_ADDR_1 XINC_ADV_MAC_ADDR_1
#define MAC_ADDR_2 XINC_ADV_MAC_ADDR_2
#define MAC_ADDR_3 XINC_ADV_MAC_ADDR_3
#define MAC_ADDR_4 XINC_ADV_MAC_ADDR_4
#define MAC_ADDR_5 XINC_ADV_MAC_ADDR_5
#define TX_ADDR_L_VAL XINCX_ADV_ADDR_L
#define TX_ADDR_H_VAL XINCX_ADV_ADDR_H
#define RX_ADDR_L_VAL TX_ADDR_L_VAL
#define RX_ADDR_H_VAL TX_ADDR_H_VAL
#define ADV_LENGTH XINCX_ADV_PIPE0_LEN
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
typedef enum
{
CRC_ERROR = 0,
CRC_OK,
CRC_IDLE
} rf_adv_crc_stat;
void rf24g_adv_init(void);
uint32_t rf_adv_packet_whiten(uint8_t *len);
uint8_t rf_adv_crc(uint8_t *adv_buff, uint8_t *len, uint32_t blecrc);
#ifdef __cplusplus
}
#endif
#endif /* __XC6XXX_RF_ADV_H__ */
component/rf24/Drivers/xc6xxx_rf_single/xc6xxx_rf_single.c
+63
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@@ -0,0 +1,63 @@
/*!
* \file rf_2_4g.c
*
* \brief Target RF 2.4g implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx_rf_single.h"
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define RF_SINGLE 0x01
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
* @brief RF single initialization
* @param void
*
* @retval void
*/
void rf_single_init(void)
{
/* Rf modem init*/
rf24g_modem_init();
/* Set up 2.4G RF modem*/
rf24g_config();
/* Set modulation frequency offset to 0 */
XC_RF_2_4G->TXPROC_CFG = 0x00;
/* Set to enter single carrier mode */
set_rf_DR(XINCX_RF_TRANS_RATE | RF_SINGLE);
/* Set configuration register */
XC_RF_2_4G->CFG_TOP = 0x298272;
/* Set transmission power */
set_rf_power(XINCX_POWER);
}
component/rf24/Drivers/xc6xxx_rf_single/xc6xxx_rf_single.h
+54
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@@ -0,0 +1,54 @@
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6XXX_RF_SINGLE_H__
#define __XC6XXX_RF_SINGLE_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void rf_single_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __XC6XXX_RF_SINGLE_H__ */
component/rf24/Drivers/xc_rf24g_register/xc_rf_24g_register.h
+190
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@@ -0,0 +1,190 @@
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2024-03-21 10:47:04
* @LastEditors: sueRimn
* @LastEditTime: 2024-03-21 13:50:06
*/
#ifndef __XC_RF_24G_REGISTER_H__
#define __XC_RF_24G_REGISTER_H__
#include "xc60xx.h"
#include <stdint.h>
/* ===========================================================================================================================
*/
/* ================ BT RF ================ */
/* ===========================================================================================================================
*/
/* BT RF Register Typedef */
typedef struct
{
__IOM uint16_t ana0_reg_l; /* RF analog0 Reg (0x000) */
__IOM uint16_t ana0_reg_h;
__IOM uint16_t ana1_reg_l; /* RF analog1 Reg (0x004) */
__IOM uint16_t ana1_reg_h;
__IOM uint16_t ana2_reg_l; /* RF analog2 Reg (0x008) */
__IOM uint16_t ana2_reg_h;
__IOM uint16_t ana3_reg_l; /* RF analog3 Reg (0x00C) */
__IOM uint16_t ana3_reg_h;
__IOM uint16_t ana4_reg_l; /* RF analog4 Reg (0x010) */
__IOM uint16_t ana4_reg_h;
__IOM uint16_t ana5_reg_l; /* RF analog5 Reg (0x014) */
__IOM uint16_t ana5_reg_h;
__IOM uint16_t ana6_reg_l; /* RF analog6 Reg (0x018) */
__IOM uint16_t ana6_reg_h;
__IOM uint16_t ana7_reg_l; /* RF analog7 Reg (0x01C) */
__IOM uint16_t ana7_reg_h;
__IOM uint16_t ana8_reg_l; /* RF analog8 Reg (0x020) */
__IOM uint16_t ana8_reg_h;
__IOM uint16_t ana9_reg_l; /* RF analog9 Reg (0x024) */
__IOM uint16_t ana9_reg_h;
__IOM uint16_t ana10_reg_l; /* RF analog10 Reg (0x028) */
__IOM uint16_t ana10_reg_h;
__IOM uint16_t ana11_reg_l; /* RF analog11 Reg (0x02C) */
__IOM uint16_t ana11_reg_h;
__IOM uint16_t ana12_reg_l; /* RF analog12 Reg (0x030) */
__IOM uint16_t ana12_reg_h;
__IOM uint16_t ana13_reg_l; /* RF analog13 Reg (0x034) */
__IOM uint16_t ana13_reg_h;
__IOM uint16_t ana14_reg_l; /* RF analog14 Reg (0x038) */
__IOM uint16_t ana14_reg_h;
__IOM uint16_t ana15_reg_l; /* RF analog15 Reg (0x03C) */
__IOM uint16_t ana15_reg_h;
__IOM uint16_t ana16_reg_l; /* RF analog16 Reg (0x040) */
__IOM uint16_t ana16_reg_h;
__IOM uint16_t ana17_reg_l; /* RF analog17 Reg (0x044) */
__IOM uint16_t ana17_reg_h;
__IOM uint16_t ana18_reg_l; /* RF analog18 Reg (0x048) */
__IOM uint16_t ana18_reg_h;
__IOM uint16_t ana19_reg_l; /* RF analog19 Reg (0x04C) */
__IOM uint16_t ana19_reg_h;
__IOM uint16_t ana20_reg_l; /* RF analog20 Reg (0x050) */
__IOM uint16_t ana20_reg_h;
__IOM uint16_t ana21_reg_l; /* RF analog21 Reg (0x054) */
__IOM uint16_t ana21_reg_h;
__IOM uint32_t reserved1[1]; /* Reserved (0x058) - (0x05c) */
__IOM uint16_t ana23_reg_l;
__IOM uint16_t ana23_reg_h;
__IOM uint16_t ana24_reg_l; /* RF analog24 Reg (0x060) */
__IOM uint16_t ana24_reg_h;
__IOM uint16_t ana25_reg_l; /* RF analog25 Reg (0x064) */
__IOM uint16_t ana25_reg_h;
__IOM uint16_t ana26_reg_l; /* RF analog26 Reg (0x068) */
__IOM uint16_t ana26_reg_h;
__IOM uint16_t ana27_reg_l; /* RF analog27 Reg (0x06C) */
__IOM uint16_t ana27_reg_h;
__IOM uint16_t ana28_reg_l; /* RF analog28 Reg (0x070) */
__IOM uint16_t ana28_reg_h;
__IOM uint16_t ana29_reg_l; /* RF analog29 Reg (0x074) */
__IOM uint16_t ana29_reg_h;
__IOM uint16_t ana30_reg_l; /* RF analog30 Reg (0x078) */
__IOM uint16_t ana30_reg_h;
__IOM uint16_t ana31_reg_l; /* RF analog31 Reg (0x07C) */
__IOM uint16_t ana31_reg_h;
__IOM uint16_t rccal_reg_l; /* RF rccal Reg (0x080) */
__IOM uint16_t rccal_reg_h;
__IOM uint16_t rccal_rslt_l; /* RF rccal result Reg (0x084) */
__IOM uint16_t rccal_rslt_h;
struct
{
__IOM uint16_t rx_lna_map0_l; /* BT rx lna map0 Reg (0x088) */
__IOM uint16_t rx_lna_map0_h;
__IOM uint16_t rx_lna_map1_l; /* BT rx lna map1 Reg (0x08C) */
__IOM uint16_t rx_lna_map1_h;
__IOM uint16_t rx_vga_map0_l; /* BT rx vga map0 Reg (0x090) */
__IOM uint16_t rx_vga_map0_h;
__IOM uint16_t rx_vga_map1_l; /* BT rx vga map1 Reg (0x094) */
__IOM uint16_t rx_vga_map1_h;
__IOM uint16_t rx_vga_map2_l; /* BT rx vga map2 Reg (0x098) */
__IOM uint16_t rx_vga_map2_h;
__IOM uint16_t rx_vga_map3_l; /* BT rx vga map3 Reg (0x09C) */
__IOM uint16_t rx_vga_map3_h;
__IOM uint16_t rx_vga_map4_l; /* BT rx vga map4 Reg (0x0A0) */
__IOM uint16_t rx_vga_map4_h;
__IOM uint16_t rx_vga_map5_l; /* BT rx vga map5 Reg (0x0A4) */
__IOM uint16_t rx_vga_map5_h;
__IOM uint16_t rx_vga_map6_l; /* BT rx vga map6 Reg (0x0A8) */
__IOM uint16_t rx_vga_map6_h;
__IOM uint16_t rx_vga_map7_l; /* BT rx vga map7 Reg (0x0AC) */
__IOM uint16_t rx_vga_map7_h;
__IOM uint16_t rx_pm_reg_l; /* BT rx pm Reg (0x0B0) */
__IOM uint16_t rx_pm_reg_h;
__IOM uint16_t rx_chan_reg_l; /* BT rx chan Reg (0x0B4) */
__IOM uint16_t rx_chan_reg_h;
__IOM uint16_t rx_ctrl_sel_l; /* BT rx control select Reg (0x0B8) */
__IOM uint16_t rx_ctrl_sel_h;
__IOM uint16_t rf_ctrl1_l;
__IOM uint16_t rf_ctrl1_h;
} BT;
} BT_RF_TypeDef;
/* ===========================================================================================================================
*/
/* ================ 2.4G ================ */
/* ===========================================================================================================================
*/
/* RF 2.4G Module Register Typedef */
typedef struct
{
__IOM uint32_t CFG_TOP; /*!< Top-level configuration (0x000) */
__IOM uint32_t EN_AA; /*!< Auto-acknowledgement settings (0x004) */
__IOM uint32_t EN_RXADDR; /*!< Enable RX addresses (0x008) */
__IOM uint32_t SETUP_AW; /*!< Address width & timing stup (0x00C) */
__IOM uint32_t SETUP_RETR; /*!< Automatic retransmission setup (0x010) */
__IOM uint32_t RF_CH; /*!< RF channel (0x014) */
__IOM uint32_t SETUP_RF; /*!< RF settings (0x018) */
__IOM uint32_t STATUS; /*!< Status, SDO output may be adjusted (0x01C) */
__IOM uint32_t OBSERVE_TX; /*!< Transmission observation (0x020) */
__IOM uint32_t RSSI; /*!< TSSI and RSSI indicator/control (0x024) */
__IOM uint32_t RX_ADDR_P0_L; /*!< RX address low 32bit for data pipe 0 (0x028) */
__IOM uint32_t RX_ADDR_P0_H; /*!< RX address high 8bit for data pipe 0 (0x02C) */
__IOM uint32_t RX_ADDR_P1_L; /*!< RX address low 32bit for data pipe 1 (0x030) */
__IOM uint32_t RX_ADDR_P1_H; /*!< RX address high 8bit for data pipe 1 (0x034) */
__IOM uint32_t RX_ADDR_P2TOP5; /*!< Only LSB are set, MSB use RX_ADDR_P1 (0x038) */
__IOM uint32_t BER_RECV_CNT; /*!< Receive total Bit Counter for BER Test (0x03C) */
__IOM uint32_t BER_ERR_CNT; /*!< Receive error Bit Counter for BER Test (0x040) */
__IOM uint32_t AGC_SETTING; /*!< AGC setting (0x044) */
__IOM uint32_t PGA_SETTING; /*!< PGA setting (0x048) */
__IOM uint32_t TX_ADDR_L; /*!< TX address low 32bit (0x04C) */
__IOM uint32_t TX_ADDR_H; /*!< TX address high 8bit (0x050) */
__IOM uint32_t RX_PW_Px_L; /*!< Number of bytes in data pipe0~3 (0x054) */
__IOM uint32_t RX_PW_Px_H; /*!< Number of bytes in data pipe4~5 (0x058) */
__IOM uint32_t ANALOG_CFG0_L; /*!< Analog register 0 low 32bit (0x05C) */
__IOM uint32_t ANALOG_CFG0_H; /*!< Analog register 0 high 32bit (0x060) */
__IOM uint32_t ANALOG_CFG1_L; /*!< Analog register 1 low 32bit (0x064) */
__IOM uint32_t ANALOG_CFG1_H; /*!< Analog register 1 high 32bit (0x068) */
__IOM uint32_t ANALOG_CFG2_L; /*!< Analog register 2 low 32bit (0x06C) */
__IOM uint32_t ANALOG_CFG2_H; /*!< Analog register 2 high 32bit (0x070) */
__IOM uint32_t ANALOG_CFG3_L; /*!< Analog register 3 low 32bit (0x074) */
__IOM uint32_t ANALOG_CFG3_H; /*!< Analog register 3 high 32bit (0x078) */
__IM uint32_t Reserved1; /*!< Reserved1 (0x07C) */
__IOM uint32_t STATUS_FIFO; /*!< FIFO status (0x080) */
__IOM uint32_t RSSIREC; /*!< RSSI recorder feature (0x084) */
__IOM uint32_t TXPROC_CFG; /*!< TX Process configuration (0x088) */
__IOM uint32_t RXPROC_CFG_L; /*!< RX Process configuration (0x08C) */
__IM uint32_t Reserved2; /*!< Reserved2 (0x090) */
__IOM uint32_t DYNPD; /*!< Dynamic payload length (0x094) */
__IOM uint32_t FEATURE; /*!< Features (0x098) */
__IM uint32_t Reserved3[3]; /*!< Reserved3 (0x09C - 0x0A4) */
__IOM uint32_t RXPROC_CFG_H; /*!< PA Ramp Configuration (0x0A8) */
__IOM uint32_t Reserved4; /*!< Reserved4 (0x0AC) */
__IOM uint32_t PREAMBLE; /*!< PREAMBLE (0x0B0) */
__IOM uint32_t GUARD; /*!< PA Ramp Configuration (0x0B4) */
__IM uint32_t Reserved5[2]; /*!< Reserved4 (0x0B8 - 0x0BC) */
__IOM uint32_t CMD_CFG; /*!< Command Configuration (0x0C0) */
__IOM uint32_t TX_FIFO_DATA; /*!< Tx Fifo Data (0x0C4) */
__IOM uint32_t RX_FIFO_DATA; /*!< Rx Fifo Data (0x0C8) */
__IOM uint32_t RX_FIFO_LEN; /*!< Tx Fifo Data Len (0x0CC) */
} RF_2_4G_TypeDef;
#define XC_BT_RF_BASE 0x53021000UL
#define XC_RF_2_4G_BASE 0x53023000UL
#define XC_BT_RF ((BT_RF_TypeDef *)XC_BT_RF_BASE)
#define XC_RF_2_4G ((RF_2_4G_TypeDef *)XC_RF_2_4G_BASE)
#define BLE_COMMON_BASE 0x53022000UL
#define BLE_COMN_RF24G_CTRL ((volatile uint32_t *)(BLE_COMMON_BASE + 0x40))
#endif //__XC_RF_24G_REGISTER_H__
component/rf24/Drivers/xc_rf24g_register/xc_software_crc.c
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#include "xc_software_crc.h"
#include <stdio.h>
/**
* CRC16-CCITT-FALSE 多项式计算
*/
uint16_t crc16_ccitt_false(uint8_t *crc_data, uint8_t data_len)
{
uint16_t crc_shift = 0xFFFF;
uint16_t poly = 0x1021;
for (uint8_t i = 0; i < data_len; i++) {
crc_shift ^= crc_data[i] << 8;
for (uint8_t j = 0; j < 8; j++) {
if (crc_shift & 0x8000)
crc_shift = (crc_shift << 1) ^ poly;
else
crc_shift = crc_shift << 1;
}
}
return crc_shift;
}
/**
* CRC16-CCITT-FALSE 多项式计算（动态包）
*/
uint16_t crc16_ccitt_false_d(uint8_t *crc_data, uint8_t data_len)
{
uint16_t crc_shift = 0xFFFF;
uint16_t poly = 0x1021;
for (uint8_t i = 0; i < data_len - 1; i++) {
printf("%02x ", crc_data[i]);
crc_shift ^= crc_data[i] << 8;
for (uint8_t j = 0; j < 8; j++) {
if (crc_shift & 0x8000)
crc_shift = (crc_shift << 1) ^ poly;
else
crc_shift = crc_shift << 1;
// printf("%04x ", crc_shift);
}
// printf("\r\n");
}
uint8_t i;
crc_shift ^= crc_data[data_len - 1] << 8;
for (i = 0; i < SURPLUS_UNIT; i++) {
if (crc_shift & 0x8000)
crc_shift = (crc_shift << 1) ^ poly;
else
crc_shift = crc_shift << 1;
// printf("%04x\r\n", crc_shift);
}
printf("\r\n");
return crc_shift;
}
/**
CRC 8/ ROHC 多项式计算
*/
uint8_t crc8_rohc(uint8_t *crc_data, uint8_t data_len)
{
uint8_t crc_shift = 0xFF;
for (uint8_t i = 0; i < data_len; i++) {
crc_shift ^= crc_data[i];
for (uint8_t j = 0; j < 8; j++) {
if (crc_shift & 0x01)
crc_shift = (crc_shift >> 1) ^ 0xE0;
else
crc_shift = (crc_shift >> 1);
}
}
return crc_shift;
}
/**
* 数据字节取反
*/
uint8_t bit_negation(uint8_t data)
{
uint8_t temp = 0;
for (uint8_t i = 0; i < 8; i++) {
if ((data >> i) & 0x1)
temp &= ~(0x1 << i);
else
temp |= (0x1 << i);
}
return temp;
}
/* 字节大小端 */
void byte_bigandsmallend(uint8_t data)
{
uint8_t temp_num = data;
data = 0;
for (uint8_t i = 0; i < 8; i++) {
if (temp_num & 0x80)
data |= 1;
data <<= 1;
}
}
/* 数组每字节大小端 */
void buff_bigandsmallend(uint8_t *buff, uint8_t buff_len)
{
for (uint8_t i = 0; i < buff_len; i++) {
byte_bigandsmallend(buff[i]);
}
}
/**
* 数据白化
*/
void whiten_shift(uint8_t *shifter)
{
*shifter = ((*shifter & 0x30) << 1) | (((*shifter & 0x08) << 1) ^ ((*shifter & 0x40) >> 2)) |
(((*shifter) & 0x7) << 1) | ((*shifter & 0x40) >> 6);
}
/**
* 磐启数据白化公式
*/
uint8_t whiten_data(uint8_t *whiten_data_in, uint8_t data_in_len)
{
uint8_t shift_buffer = 0x7F;
uint8_t whiten_data_out[DATA_NUM];
uint8_t whiten_data_code;
for (uint8_t i = 0; i < data_in_len; i++) {
whiten_data_code = 0x00;
for (uint8_t j = 0; j < 8; j++) {
if (j == 0) {
whiten_data_code = ((shift_buffer & 0x40) << 1) | whiten_data_code;
} else if (j == 1) {
whiten_data_code = (shift_buffer & 0x40) | whiten_data_code;
} else {
whiten_data_code = ((shift_buffer & 0x40) >> (j - 1)) | whiten_data_code;
}
whiten_shift(&shift_buffer);
}
whiten_data_out[i] = whiten_data_in[i] ^ whiten_data_code;
printf("%02x ", whiten_data_out[i]);
whiten_data_in[i] = whiten_data_out[i];
}
printf("\r\n");
return shift_buffer;
}
component/rf24/Drivers/xc_rf24g_register/xc_software_crc.h
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#ifndef __XC_SOFTWARE_CRC_H__
#define __XC_SOFTWARE_CRC_H__
#include <stdint.h>
#define TELINK_MODE
#define SUPPLEMENTARY_DATA 0x50
#ifdef TELINK_MODE
#define SURPLUS_UNIT 1
#define NUMBER 0x1
#endif
#ifdef BEKEN_MODE
#define SURPLUS_UNIT 1
#define NUMBER 0x1
#endif
#ifdef PANCHIP_MODE
#define SURPLUS_UNIT 2
#define NUMBER 0x3
#endif
typedef struct
{
uint8_t preamble[3];
uint8_t addr_buff[5];
uint16_t contorl;
uint8_t data_buff[32];
uint8_t crc_data[2];
} packet_t;
typedef struct
{
packet_t packt;
uint8_t crc_dat[64];
} sf_crc_t;
#define DATA_NUM 32
uint16_t crc16_ccitt_false(uint8_t *crc_data, uint8_t data_len);
uint16_t crc16_ccitt_false_d(uint8_t *crc_data, uint8_t data_len);
uint8_t crc8_rohc(uint8_t *crc_data, uint8_t data_len);
uint8_t bit_negation(uint8_t data);
void byte_bigandsmallend(uint8_t data);
void buff_bigandsmallend(uint8_t *buff, uint8_t buff_len);
void whiten_shift(uint8_t *shifter);
uint8_t whiten_data(uint8_t *whiten_data_in, uint8_t data_in_len);
#endif //__XC_SOFTWARE_CRC_H__
component/rf24/README.md
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# RF24
## Getting started
To make it easy for you to get started with GitLab, here's a list of recommended next steps.
Already a pro? Just edit this README.md and make it your own. Want to make it easy? [Use the template at the bottom](#editing-this-readme)!
## Add your files
- [ ] [Create](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#create-a-file) or [upload](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#upload-a-file) files
- [ ] [Add files using the command line](https://docs.gitlab.com/ee/gitlab-basics/add-file.html#add-a-file-using-the-command-line) or push an existing Git repository with the following command:
```
cd existing_repo
git remote add origin http://192.168.3.251/mahaitao/rf24.git
git branch -M main
git push -uf origin main
```
## Integrate with your tools
- [ ] [Set up project integrations](http://192.168.3.251/mahaitao/rf24/-/settings/integrations)
## Collaborate with your team
- [ ] [Invite team members and collaborators](https://docs.gitlab.com/ee/user/project/members/)
- [ ] [Create a new merge request](https://docs.gitlab.com/ee/user/project/merge_requests/creating_merge_requests.html)
- [ ] [Automatically close issues from merge requests](https://docs.gitlab.com/ee/user/project/issues/managing_issues.html#closing-issues-automatically)
- [ ] [Enable merge request approvals](https://docs.gitlab.com/ee/user/project/merge_requests/approvals/)
- [ ] [Set auto-merge](https://docs.gitlab.com/ee/user/project/merge_requests/merge_when_pipeline_succeeds.html)
## Test and Deploy
Use the built-in continuous integration in GitLab.
- [ ] [Get started with GitLab CI/CD](https://docs.gitlab.com/ee/ci/quick_start/index.html)
- [ ] [Analyze your code for known vulnerabilities with Static Application Security Testing(SAST)](https://docs.gitlab.com/ee/user/application_security/sast/)
- [ ] [Deploy to Kubernetes, Amazon EC2, or Amazon ECS using Auto Deploy](https://docs.gitlab.com/ee/topics/autodevops/requirements.html)
- [ ] [Use pull-based deployments for improved Kubernetes management](https://docs.gitlab.com/ee/user/clusters/agent/)
- [ ] [Set up protected environments](https://docs.gitlab.com/ee/ci/environments/protected_environments.html)
***
# Editing this README
When you're ready to make this README your own, just edit this file and use the handy template below (or feel free to structure it however you want - this is just a starting point!). Thank you to [makeareadme.com](https://www.makeareadme.com/) for this template.
## Suggestions for a good README
Every project is different, so consider which of these sections apply to yours. The sections used in the template are suggestions for most open source projects. Also keep in mind that while a README can be too long and detailed, too long is better than too short. If you think your README is too long, consider utilizing another form of documentation rather than cutting out information.
## Name
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## Description
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## Usage
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## Support
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## Contributing
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