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hpw421初始版本

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xushaoxiang
2026-06-06 16:49:48 +08:00
commit 2339bbfd1f
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component/rf24/Drivers/xc6xxx_rf_2_4g/xc6xxx_rf_2_4g.c
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/*!J
* \file rf_2_4g.c
*
* \brief Target RF 2.4g implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx_rf_2_4g.h"
#include "xc60xx.h"
#if RF_MOUSE
#include "rf_mouse.h"
#endif
#ifdef RF_ADV_INTER
#include "rf_adv_config.h"
#endif
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define AD_RCCAL_FINISH_VAL 0x8000
#define RX_ON 0x01
#define PIPE0_LEN XINCX_2_4G_PIPE0_LEN
#define PIPE1_LEN XINCX_2_4G_PIPE1_LEN
#define PIPE2_LEN XINCX_2_4G_PIPE2_LEN
#define PIPE3_LEN XINCX_2_4G_PIPE3_LEN
#define PIPE4_LEN XINCX_2_4G_PIPE4_LEN
#define PIPE5_LEN XINCX_2_4G_PIPE5_LEN
#define TX_ADDR_L_VAL XINCX_2_4G_ADDR_L
#define TX_ADDR_H_VAL XINCX_2_4G_ADDR_H
#define RX_ADDR_L_VAL TX_ADDR_L_VAL
#define RX_ADDR_H_VAL TX_ADDR_H_VAL
#ifdef RF_ADV_INTER
extern uint8_t recv_adv_buf[XINCX_ADV_PIPE0_LEN];
#endif
uint8_t recv_len = 0;
uint8_t recv_buf[BUFF_LEN] = {0};
bool rf24g_handler_flag = false;
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
void nop_cnt(uint32_t cnt)
{
for (uint32_t i = 0; i < cnt; i++)
__nop();
}
/**
* @brief Reverse bits
* @param uint8_t - input
* @retval uint8_t - temp
*/
uint8_t reverseBits(uint8_t input)
{
uint8_t i = 0, temp = 0;
for (; i < 8; i++) {
temp <<= 1;
temp = ((input >> i) & 0x01) ? (temp | 0x01) : (temp | 0x00);
}
return temp;
}
/**
* @brief Ble whiten channel
* @param uint16_t - fre
* @retval uint8_t - temp | 2
*/
uint8_t bleWhitenStart(uint16_t Fre)
{
uint8_t chan = (Fre == 2426) ? 38 : ((Fre == 2402) ? 37 : 39);
return reverseBits(chan) | 2;
}
/**
* @brief Ble whiten
* @param uint8_t * - data
* @param uint8_t - len
* @param uint8_t - whitenCoeff
* @retval void
*/
void ble_whiten(uint8_t *data, uint8_t len, uint8_t whitenCoeff)
{
uint8_t m;
while (len--) {
for (m = 1; m; m <<= 1) {
if (whitenCoeff & 0x80) {
whitenCoeff ^= 0x11;
(*data) ^= m;
}
whitenCoeff <<= 1;
}
// Flip variables
*data = reverseBits(*data);
data++;
}
}
/**
* @brief
* @param void
* @retval void
*/
void ble_crc(uint8_t *data, uint8_t len, uint8_t *dst)
{
// calculating the CRC based on a LFSR
uint8_t i, temp, tempData;
while (len--) {
tempData = *data++;
for (i = 0; i < 8; i++, tempData >>= 1) {
temp = dst[0] >> 7;
dst[0] <<= 1;
if (dst[1] & 0x80) {
dst[0] |= 1;
}
dst[1] <<= 1;
if (dst[2] & 0x80) {
dst[1] |= 1;
}
dst[2] <<= 1;
if (temp != (tempData & 1)) {
dst[2] ^= 0x5B;
dst[1] ^= 0x06;
}
}
}
dst[2] = reverseBits(dst[2]);
dst[1] = reverseBits(dst[1]);
dst[0] = reverseBits(dst[0]);
}
/**
* @brief RF rc calibration
* @param void
* @retval void
*/
void rf_rc_calib(void)
{
static uint8_t calib_flag = false;
uint8_t delay_cnt = 20;
if (calib_flag)
return;
uint16_t r_val = 0;
// RG_ RCCAL_ CTRL (Rccal output code value control) def"101"
XC_BT_RF->rccal_reg_l &= ~(0x7 << 8);
XC_BT_RF->rccal_reg_l |= (0x5 << 8);
delay_us(delay_cnt);
// RG_RCCAL_RESETN = 1
XC_BT_RF->rccal_reg_l |= (0x1 << 5);
delay_us(delay_cnt);
// RG_RCCAL_SEL = 0
XC_BT_RF->rccal_reg_l &= ~(0x1 << 3);
delay_us(delay_cnt);
// RG_RCCAL_EN = 1
XC_BT_RF->rccal_reg_l |= (0x1 << 2);
delay_us(delay_cnt);
// RG_RCCAL_START = 1
XC_BT_RF->rccal_reg_l |= (0x1 << 4);
delay_us(delay_cnt);
r_val = XC_BT_RF->rccal_rslt_l;
// Waiting for AD_ RCCAL_ FINISH raises the calibration value AD_ RCCAL_
// CTRIM
while (!(r_val & AD_RCCAL_FINISH_VAL)) {
r_val = XC_BT_RF->rccal_rslt_l;
}
r_val = (XC_BT_RF->rccal_rslt_l & 0x7FFF) >> 10;
// RG_RCCAL_SEL = 1
XC_BT_RF->rccal_reg_l |= (0x1 << 3);
// RG_RCCAL_EN = 0
XC_BT_RF->rccal_reg_l &= ~(0x1 << 2);
// RG_RCCAL_START = 0
XC_BT_RF->rccal_reg_l &= ~(0x1 << 4);
XC_BT_RF->rccal_reg_l &= ~(0x1F << 11);
XC_BT_RF->rccal_reg_l |= r_val << 11;
calib_flag = true;
}
/**
* @brief Reset rf 2.4g modem
* @param void
* @retval void
*/
void reset_rf2_4g(void)
{
uint32_t value = 0;
value = cpr_rf_reg1_get();
cpr_rf_reg1_set(value & ~(1 << 21));
delay_ms(2);
cpr_rf_reg1_set(value | (1 << 21));
delay_ms(1);
}
/**
* @brief Frequency offset tune
* @param uint8_t - val
* @retval void
*/
void freq_ctune(uint8_t val)
{
uint32_t value = 0;
value = cprao_aon_rf_aonreg_get();
cprao_aon_rf_aonreg_set((value & (~(0x3f << 20))) | ((val & 0x3f) << 20));
}
/**
* @brief Rf modem init
* @param void
* @retval void
*/
void rf24g_modem_init(void)
{
// open bt clock
/* BT_CLK clock control register */
cpr_bt_clk_ctl__bt_clk_en__setf(ENABLE);
/* BT_ MODEM_ CLK clock control register */
cpr_bt_modem_clk_ctl__bt_modem_clk_en__setf(ENABLE);
/* Configure BT_ PCLK_ EN enable */
cpr_ctlapbclken_grctl__bt_pclk_en__setf(ENABLE);
// CPR_AO BB_CORELDORF_EN
// XC_CPR_AO->AON_CORERFLDO_EN = 0x1;
cprao_aon_coreldo_en_set(ENABLE);
/* detrefbias */
XC_BT_RF->ana18_reg_l &= ~((0x7 << 3) | (0x7));
XC_BT_RF->ana18_reg_l |= (0x1 << 3);
}
/**
* @brief Config 2.4g rf parameters
* @param void
* @retval void
*/
void rf24g_config(void)
{
// Set sel_24G_rfchan, sel_24G_rfldoen, sel_24G_rampout regs to use 2.4G signal
XC_BT_RF->BT.rx_ctrl_sel_l |= 0xE000;
#if (XINCX_RF_TRANS_RATE == DR_1M)
XC_BT_RF->ana21_reg_l = (XC_BT_RF->ana21_reg_l & (0xFFFF8FFF)) | 0x3000;
#elif (XINCX_RF_TRANS_RATE == DR_2M)
XC_BT_RF->ana21_reg_l = (XC_BT_RF->ana21_reg_l & (0xFFFF8FFF)) | 0x2000;
XC_BT_RF->ana3_reg_l |= 0x01;
#else
XC_BT_RF->ana21_reg_l = (XC_BT_RF->ana21_reg_l & (0xFFFF8FFF)) | 0x6000;
#endif
// Manual afc
XC_BT_RF->ana29_reg_l |= 0x02;
// Afc pulse
XC_BT_RF->ana28_reg_l |= 0x01;
reset_rf2_4g();
// enable 2.4G_mclk 2.4G_hclk 2div of 32MHz
cpr_rf_reg1__rf24g_mclk_div__setf(1);
cpr_rf_reg1__rf24g_hclk_en__setf(ENABLE);
cpr_rf_reg1__rf24g_mclk_en__setf(ENABLE);
// set 2.4G agc and iq from 2.4 modem
cpr_rf_reg0__sel__24g_agc__setf(ENABLE);
cpr_rf_reg0__sel__24g_hwpin__setf(ENABLE);
*BLE_COMN_RF24G_CTRL |= 0x700;
XC_BT_RF->BT.rf_ctrl1_l |= (1 << 13);
XC_BT_RF->BT.rf_ctrl1_l &= ~(1 << 12);
XC_BT_RF->ana2_reg_l &= ~((0xf << 5) | (0x7 << 13));
XC_BT_RF->ana2_reg_l |= (0x9 << 5) | (0x3 << 13);
}
/**
* @brief Set rf dynpd
* @param uint8_t - dynpd
* @retval void
*/
void set_rf_dynpd(uint8_t dynpd) { XC_RF_2_4G->DYNPD = dynpd; }
/**
* @brief Set rf tx power
* @param uint8_t - tx_pwr
* @retval void
*/
void set_rf_power(uint8_t tx_pwr)
{
XC_BT_RF->ana21_reg_l = (XC_BT_RF->ana21_reg_l & (~0xfc0)) | ((tx_pwr & 0x3f) << 6);
XC_RF_2_4G->RF_CH = (XC_RF_2_4G->RF_CH & (~0x3f0000)) | (tx_pwr << 16);
}
/**
* @brief Set rf channel
* @param uint16_t - channel
* @retval void
*/
void set_rf_channel(uint16_t channel)
{
#if (XINCX_RF_TRANS_RATE == RATE_2M)
XC_RF_2_4G->RF_CH = ((XC_RF_2_4G->CFG_TOP & RX_ON) ? (channel - 2) : channel);
#else
XC_RF_2_4G->RF_CH = ((XC_RF_2_4G->CFG_TOP & RX_ON) ? (channel - 1) : channel);
#endif // XINCX_RF_TRANS_RATE
delay_us(1);
XC_BT_RF->ana28_reg_l &= (~0x1); // Afc pulse
delay_us(1);
XC_BT_RF->ana28_reg_l |= 0x1; // Afc pulse
delay_us(1);
}
/**
* @brief Set rf tx addr
* @param uint32_t - addr_l
* uint32_t - addr_h
* @retval void
*/
void set_rf_txaddr(uint32_t addr_l, uint32_t addr_h)
{
XC_RF_2_4G->TX_ADDR_L = addr_l;
XC_RF_2_4G->TX_ADDR_H = (XC_RF_2_4G->TX_ADDR_H & 0xFF00) | (addr_h & 0xFF);
}
/**
* @brief Set rf pipe0 tx addr
* @param uint32_t - addr_l
* uint32_t - addr_h
* @retval void
*/
void set_rf_pipe0_rxaddr(uint32_t addr_l, uint32_t addr_h)
{
XC_RF_2_4G->RX_ADDR_P0_L = addr_l;
XC_RF_2_4G->RX_ADDR_P0_H = addr_h & 0xff;
}
/**
* @brief Set rf tx addr width
* @param uint8_t - bytes
*
* @retval void
*/
void set_rf_tx_addr_width(uint8_t bytes)
{
switch (bytes) {
case 3:
XC_RF_2_4G->SETUP_AW = 0xa5;
break;
case 4:
XC_RF_2_4G->SETUP_AW = 0xaa;
break;
case 5:
XC_RF_2_4G->SETUP_AW = 0xaf;
break;
}
}
/**
* @brief Set rf data rate
* @param uint8_t - rate
*
* @retval void
*/
void set_rf_DR(uint8_t rate) { XC_RF_2_4G->SETUP_RF = rate; }
/**
* @brief Set rf feature
* @param uint8_t - long_pld
* uint8_t - fec
* uint8_t - whiten
* uint8_t - dpl
* uint8_t - ack_pay
* uint8_t - dyn_ack
* @retval void
*/
void set_rf_feature(uint8_t long_pld, uint8_t fec, uint8_t whiten, uint8_t dpl, uint8_t ack_pay, uint8_t dyn_ack)
{
XC_RF_2_4G->FEATURE = (long_pld << 5) | (fec << 4) | (whiten << 3) | (dpl << 2) | (ack_pay << 1) | dyn_ack;
}
/**
* @brief Set rf compatility feature
* @param uint8_t - guard_cfg
* uint8_t - long_pld_type
* uint8_t - preamble_num
* uint8_t - preamble_type
* uint8_t - crc_scope_header
* uint8_t - crc_scope_addr
* @retval void
*/
void set_rf_compatility_featue(uint8_t guard_cfg, uint8_t long_pld_type, uint8_t preamble_num, uint8_t preamble_type,
uint8_t crc_scope_header, uint8_t crc_scope_addr)
{
XC_RF_2_4G->FEATURE = (XC_RF_2_4G->FEATURE & ~(0xff << 8)) | (guard_cfg << 15) | (long_pld_type << 14) |
(preamble_num << 12) | (preamble_type << 11) | (crc_scope_header << 9) |
(crc_scope_addr << 8);
}
/**
* @brief Set rf preamble
* @param uint8_t - preamble_word
*
* @retval void
*/
uint8_t set_rf_preamble(uint32_t preamble_word)
{
if (!(XC_RF_2_4G->FEATURE & ~(1 << 11)))
return 1;
XC_RF_2_4G->PREAMBLE = preamble_word;
return 0;
}
/**
* @brief Set rf guard woard
* @param uint8_t - guard_word
*
* @retval void
*/
void set_rf_guard_woard(uint16_t guard_word) { XC_RF_2_4G->GUARD = guard_word; }
/**
* @brief Set rf mode
* @param uint8_t - mode
*
* @retval void
*/
void set_rf_mode(uint8_t mode)
{
#if (XINCX_RF_TRANS_RATE == RATE_2M)
XC_RF_2_4G->CFG_TOP = (XC_RF_2_4G->CFG_TOP & (~0x1ffff3)) | (mode & 0x01) | 0x1b8672;
#else
XC_RF_2_4G->CFG_TOP = (XC_RF_2_4G->CFG_TOP & (~0x1ffff3)) | (mode & 0x01) | 0x0b8272;
#endif
}
/**
* @brief Set rf crc
* @param uint8_t - enable
* uint8_t - crc_bit
* @retval void
*/
void set_rf_crc(uint8_t enable, uint8_t crc_bit)
{
uint32_t val = 0x0c;
if (enable) {
if (crc_bit == CRC_1BIT) {
XC_RF_2_4G->CFG_TOP |= ~val;
XC_RF_2_4G->CFG_TOP |= 0x08;
} else {
XC_RF_2_4G->CFG_TOP |= val;
}
} else {
val = 0x08;
XC_RF_2_4G->CFG_TOP &= ~val;
}
}
/**
* @brief Set rf pipe rx payload len
* @param uint8_t - p0_len
* uint8_t - p1_len
* uint8_t - p2_len
* uint8_t - p3_len
* uint8_t - p4_len
* uint8_t - p5_len
* @retval void
*/
void set_rf_pipe_rx_payLen(uint8_t p0_len, uint8_t p1_len, uint8_t p2_len, uint8_t p3_len, uint8_t p4_len,
uint8_t p5_len)
{
XC_RF_2_4G->RX_PW_Px_L = p0_len | (p1_len << 8) | (p2_len << 16) | (p3_len << 24);
XC_RF_2_4G->RX_PW_Px_H = p4_len | (p5_len << 8);
}
/**
* @brief Set rf retry parameters
* @param uint8_t - cnt
* uint8_t - delay
* @retval void
*/
void set_rf_retr(uint8_t cnt, uint8_t delay) { XC_RF_2_4G->SETUP_RETR = cnt | (delay << 4); }
/**
* @brief Set rf pipe en_aa
* @param uint8_t - pipe0_enaa
* uint8_t - pipe1_enaa
* uint8_t - pipe2_enaa
* uint8_t - pipe3_enaa
* uint8_t - pipe4_enaa
* uint8_t - pipe5_enaa
* @retval void
*/
void set_rf_enaa(uint8_t pipe0_enaa, uint8_t pipe1_enaa, uint8_t pipe2_enaa, uint8_t pipe3_enaa, uint8_t pipe4_enaa,
uint8_t pipe5_enaa)
{
XC_RF_2_4G->EN_AA = (pipe0_enaa << 0) | (pipe1_enaa << 1) | (pipe2_enaa << 2) | (pipe3_enaa << 3) |
(pipe4_enaa << 4) | (pipe5_enaa << 5);
}
/**
* @brief Rf tx packet
* @param uint8_t * - data
* uint8_t - len
* @retval uint8_t - ret = 0 or 1
*/
__RAM_CODE uint8_t rf_tx_packet(uint8_t *data, uint8_t len)
{
uint8_t ret;
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
XC_RF_2_4G->STATUS = MASK_TX_DS | MASK_MAX_RT;
if (!((XC_RF_2_4G->STATUS_FIFO & STAT_TX_FULL) == STAT_TX_FULL)) {
for (uint8_t i = 0; i < RF_SEND_CMD_CNT; i++)
XC_RF_2_4G->CMD_CFG = CMD_DONE | W_TX_PLOAD;
for (uint8_t i = 0; i < len; i++)
XC_RF_2_4G->TX_FIFO_DATA = data[i];
CE_CTL_HIGH;
delay_us(100); // 100
CE_CTL_LOW;
ret = false;
} else {
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
ret = true;
}
return ret;
}
/**
* @brief Rf rx packet
* @param uint8_t * - buff
*
* @retval uint8_t - len
*/
__RAM_CODE uint8_t rf_rx_packet(uint8_t *buff)
{
uint8_t len = 0;
if ((XC_RF_2_4G->STATUS & MASK_RX_DR) == MASK_RX_DR) {
CE_CTL_LOW;
XC_RF_2_4G->CMD_CFG = CMD_DONE | R_RX_PL_WID;
len = XC_RF_2_4G->RX_FIFO_LEN & 0xff;
if (len) {
for (uint8_t i = 0; i < RF_RECV_CMD_CNT; i++) {
nop_cnt(16);
XC_RF_2_4G->CMD_CFG = CMD_DONE | R_RX_PLOAD;
nop_cnt(16);
}
for (uint8_t i = 0; i < len; i++) {
buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
}
}
XC_RF_2_4G->CMD_CFG = FLUSH_RX | CMD_DONE;
XC_RF_2_4G->STATUS = MASK_RX_DR;
}
return len;
}
/**
* @brief Rf set channel
* @param uint16_t - channel
*
* @retval void
*/
void rf_set_channel(uint16_t channel)
{
set_rf_channel(channel);
#if XINCX_RF_MODE
#if (XINCX_RF_NVIC_MODE)
NVIC_EnableIRQ(RF24G_IRQn);
#endif // XINCX_RF_NVIC_MODE
#endif // XINCX_RF_MODE
}
/**
* @brief Rf 2.4g Initialization
* @param void
*
* @retval void
*/
void rf24g_init(void)
{
/* Rf modem init*/
rf24g_modem_init();
/* Set up 2.4G RF modem*/
rf24g_config();
/* Set up crystal oscillator capacitor array */
freq_ctune(XINCX_2_4G_CRY_CPT_ARRAY);
/* Set up dynamic load */
set_rf_dynpd(XINCX_2_4G_DYNPD);
/* Set retransmission delay and retransmission frequency */
set_rf_retr(XINCX_2_4G_RETRANS_CNT, XINCX_2_4G_RETRANS_DELAY);
/* Set address width */
set_rf_tx_addr_width(XINCX_RF_TX_ADDR_WIDTH);
/* Set PTX address */
set_rf_txaddr(TX_ADDR_L_VAL, TX_ADDR_H_VAL);
/* Set PRX address */
set_rf_pipe0_rxaddr(RX_ADDR_L_VAL, RX_ADDR_H_VAL);
/* Set transfer rate */
set_rf_DR(XINCX_RF_TRANS_RATE);
/* Set CRC */
set_rf_crc(XINCX_RF_CRC_ENABLE, XINCX_2_4G_CRC_BYTE);
/* Set data frame format */
set_rf_feature(XINCX_2_4G_LONG_PLD, XINCX_2_4G_FEC, XINCX_2_4G_WHITEN, XINCX_2_4G_DPL, XINCX_2_4G_ACK_PAY,
XINCX_2_4G_DYN_ACK);
set_rf_compatility_featue(XINCX_2_4G_GUARD_CFG, XINCX_2_4G_LONG_PLD_TYPE, XINCX_2_4G_PREAMBLE_NUM,
XINCX_2_4G_PREAMBLE_TYPE, XINCX_2_4G_CRC_SCOPE_HEADER, XINCX_2_4G_CRC_SCOPE_ADDR);
/* Set the leading code */
set_rf_preamble(XINCX_2_4G_PREAMBLE);
/* Set guard field */
set_rf_guard_woard(XINCX_2_4G_GUARD);
/* Set Payload */
set_rf_pipe_rx_payLen(PIPE0_LEN, PIPE1_LEN, PIPE2_LEN, PIPE3_LEN, PIPE4_LEN, PIPE5_LEN);
/* Set mode */
set_rf_mode(XINCX_RF_MODE);
/* Set transmission power */
set_rf_power(XINCX_POWER);
/*Set ack pipe*/
set_rf_enaa(XINCX_2_4G_PIPE0_ENAA, XINCX_2_4G_PIPE1_ENAA, XINCX_2_4G_PIPE2_ENAA, XINCX_2_4G_PIPE3_ENAA,
XINCX_2_4G_PIPE4_ENAA, XINCX_2_4G_PIPE5_ENAA);
/* RC filtering calibration */
rf_rc_calib();
}
/**
* @brief Rf 2.4g tx event
* @param uint8_t - buff
* uint8_t - len
* @retval eRF_Tx_Status - ret
*/
__RAM_CODE eRF_Tx_Status rf_tx_event(uint8_t *buff, uint8_t len)
{
eRF_Tx_Status ret = TX_DATA_INVALID;
static uint32_t send_cnt = 0;
if (len == 0) {
return ret;
}
while (rf_tx_packet(buff, len))
;
do {
if ((XC_RF_2_4G->STATUS & MASK_TX_DS) == MASK_TX_DS) {
XC_RF_2_4G->STATUS |= MASK_ALL_INTER;
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
ret = TX_DATA_OK;
break;
} else if ((XC_RF_2_4G->STATUS & MASK_MAX_RT) == MASK_MAX_RT) {
XC_RF_2_4G->STATUS |= MASK_ALL_INTER;
XC_RF_2_4G->CMD_CFG = CMD_DONE | FLUSH_TX;
ret = TX_RETRANS_MAX;
break;
}
} while (1);
send_cnt++;
return ret;
}
/**
* @brief Rf 2.4g rx event
* @param uint8_t * - buff
*
* @retval uint8_t - len
*/
__RAM_CODE uint8_t rf_rx_event(uint8_t *buff) { return rf_rx_packet(buff); }
/**
* @brief Rf 2.4g rx handler
* @param void
*
* @retval void
*/
__RAM_CODE void RF24G_Handler(void)
{
CE_CTL_LOW;
rf24g_handler_flag = true;
#if (1 == XINCX_RF_ADV_NVIC_MODE)
recv_len = rf_rx_event(recv_adv_buf);
#endif // XINCX_RF_ADV_NVIC_MODE
#if (1 == XINCX_RF_NVIC_MODE)
recv_len = rf_rx_event(recv_buf);
#endif // XINCX_RF_NVIC_MODE
XC_RF_2_4G->CMD_CFG = FLUSH_TX | CMD_DONE;
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
rf_24g_callback(NULL);
/* The stable time of receiving dynamic ACK is interrupted */
nop_cnt(4);
}
__WEAK void rf_24g_callback(void *context) {}
/**
* @brief rf_2M_config
* @param void
* @return void
*/
void rf_2M_config(void)
{
XC_BT_RF->BT.rf_ctrl1_l |= (1 << 12) | (1 << 13);
/* 2M Frequency select */
XC_RF_2_4G->CFG_TOP = (XC_RF_2_4G->CFG_TOP & 0xFFFFFFFF) | (1 << 10) | (1 << 20);
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | 0x158); // 0x158
XC_BT_RF->ana5_reg_l &= ~(0x1f);
XC_BT_RF->ana5_reg_l |= 0x06;
XC_BT_RF->ana19_reg_l &= ~((0x7 << 11) | (0xf << 4));
XC_BT_RF->ana19_reg_l |= (3 << 11);
uint8_t agc_buff[5] = {0};
for (uint8_t i = 0; i < 5; i++) {
agc_buff[i] = 0x42 - 10 * i;
if (i == 4) {
agc_buff[i] = agc_buff[i - 1] - 12;
}
}
XC_RF_2_4G->PGA_SETTING = (agc_buff[0] << 0) | (agc_buff[1] << 8) | (agc_buff[2] << 16) | (agc_buff[3] << 24);
XC_RF_2_4G->TX_ADDR_H = (XC_RF_2_4G->TX_ADDR_H & ~(0xff << 8)) | (agc_buff[4] << 8);
XC_BT_RF->ana24_reg_l &= ~(0x7);
XC_BT_RF->ana24_reg_l |= (0x2);
XC_BT_RF->ana19_reg_l &= ~(0xf);
XC_BT_RF->ana19_reg_l |= 0x4;
XC_BT_RF->ana8_reg_l &= ~(0x3 << 2);
XC_BT_RF->ana11_reg_l &= ~(0x1f << 6);
XC_BT_RF->ana11_reg_l |= (0x7 << 6);
}
component/rf24/Drivers/xc6xxx_rf_2_4g/xc6xxx_rf_2_4g.h
+173
View File
@@ -0,0 +1,173 @@
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RF_2_4G_H__
#define __RF_2_4G_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_config.h"
#include "xc6xxx.h"
#include "xc_rf_24g_register.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* RF Command Code */
#define R_REG 0x00
#define W_REG 0x20
#define R_RX_PL_WID 0x60
#define R_RX_PLOAD 0x61
#define W_TX_PLOAD 0xA0
#define W_TX_PLOAD_NOACK 0xB0
#define W_ACK_PLOAD 0xA8
#define FLUSH_TX 0xE1
#define FLUSH_RX 0xE2
#define REUSE_TX_PL 0xE3
#define CMD_NOP 0xFF
#define CMD_DONE 0x100
/* FIFO status */
#define STAT_TX_REUSE (0x1 << 6)
#define STAT_TX_FULL (0x1 << 5)
#define STAT_TX_EMPTY (0x1 << 4)
#define STAT_RX_FULL (0x02)
#define STAT_RX_EMPTY (0x01)
/* STATUS Interrupt status */
#define MASK_RX_DR (0x1 << 6)
#define MASK_TX_DS (0x1 << 5)
#define MASK_MAX_RT (0x1 << 4)
#define MASK_ALL_INTER (MASK_RX_DR | MASK_TX_DS| MASK_MAX_RT)
#define CRC_1BIT 1U
#define CRC_2BIT 2U
#define DR_1M 0x02
#define DR_2M 0x0A
#define DR_250K 0x22
#define DR_125K 0x2A
#define TX_MODE 0
#define RX_MODE 1
#define CE_CTL_HIGH XC_RF_2_4G->CFG_TOP |= 0x4000
#define CE_CTL_LOW XC_RF_2_4G->CFG_TOP &= ~0x4000
#define DELAY_CNT 0U
#define RATE_1M 0x02
#define RATE_2M 0x0A
#define RATE_250K 0x22
#define RATE_125K 0x2A
#define LOGI(...) printf(__VA_ARGS__)
#ifdef RF_DEMO
#define FAIL 0U
#define SUCCESS 1U
#define ASSERT while(1)
#endif
#define RF_SEND_CMD_CNT 6U
#define RF_RECV_CMD_CNT 4U
#define BUFF_LEN XINCX_2_4G_PIPE0_LEN
/* RF Tx Status Typedef */
typedef enum
{
TX_DATA_OK = 0,
TX_DATA_INVALID = 1,
TX_RETRANS_MAX = 2
}eRF_Tx_Status;
typedef struct
{
uint8_t buff[BUFF_LEN];
uint32_t cnt;
uint32_t temp;
uint8_t data_length;
} rf_data_typedef_t;
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern uint8_t recv_len;
extern uint8_t recv_buf[BUFF_LEN];
extern bool rf24g_send_timer_flag;
extern bool rf24g_handler_flag;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void nop_cnt(uint32_t cnt);
uint8_t reverseBits(uint8_t input);
uint8_t bleWhitenStart(uint16_t Fre);
void ble_whiten(uint8_t *data, uint8_t len, uint8_t whitenCoeff);
void ble_crc(uint8_t *data, uint8_t len, uint8_t *dst);
void rf_rc_calib(void);
void reset_rf2_4g(void);
void freq_ctune(uint8_t val);
void rf24g_modem_init(void);
void rf24g_config(void);
void rf24g_init(void);
void set_rf_dynpd(uint8_t dynpd);
void set_rf_power(uint8_t tx_pwr);
void rf_set_channel(uint16_t channel);
void set_rf_txaddr(uint32_t addr_l, uint32_t addr_h);
void set_rf_pipe0_rxaddr(uint32_t addr_l, uint32_t addr_h);
void set_rf_tx_addr_width(uint8_t bytes);
void set_rf_DR(uint8_t rate);
void set_rf_feature(uint8_t long_pld, uint8_t fec, uint8_t whiten, uint8_t dpl, uint8_t ack_pay, uint8_t dyn_ack);
void set_rf_compatility_featue(uint8_t guard_cfg, uint8_t long_pld_type, uint8_t preamble_num,
uint8_t preamble_type, uint8_t crc_scope_header, uint8_t crc_scope_addr);
uint8_t set_rf_preamble(uint32_t preamble_word);
void set_rf_guard_woard(uint16_t guard_word);
void set_rf_mode(uint8_t mode);
void set_rf_crc(uint8_t enable, uint8_t crc_bit);
void set_rf_pipe_rx_payLen(uint8_t p0_len, uint8_t p1_len, uint8_t p2_len, uint8_t p3_len, uint8_t p4_len,
uint8_t p5_len);
void set_rf_retr(uint8_t cnt, uint8_t delay);
void set_rf_enaa(uint8_t pipe0_enaa, uint8_t pipe1_enaa, uint8_t pipe2_enaa, uint8_t pipe3_enaa, uint8_t pipe4_enaa,
uint8_t pipe5_enaa);
void rf_24g_callback(void *context);
void rf_2M_config(void);
uint8_t rf_tx_packet(uint8_t *data, uint8_t len);
uint8_t rf_rx_packet(uint8_t *buff);
eRF_Tx_Status rf_tx_event(uint8_t *buff, uint8_t len);
uint8_t rf_rx_event(uint8_t *buff);
#define INFO_BUFF(buff, len) rf_buff_info(buff, len)
#ifdef __cplusplus
}
#endif
#endif /* __RF_2_4G__ */