hpw421初始版本

2026-06-06 16:49:48 +08:00
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+/*
+ * @Descripttion:
+ * @version:
+ * @Author: sueRimn
+ * @Date: 2023-12-12 14:24:01
+ * @LastEditors: sueRimn
+ * @LastEditTime: 2023-12-13 13:56:02
+ */
+/*!
+ * \file      rf_2_4g.h
+ *
+ * \brief     The head file of rf_2_4g.c
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *
+ *            _  __ _       ________    _
+ *           | |/ /(_)___  / ____/ /_  (_)___
+ *           |   // / __ \/ /   / __ \/ / __ \
+ *          /   |/ / / / / /___/ / / / / /_/ /
+ *         /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
+ *                                   /_/
+ *           (C) 2022-2025 XinChip
+ *
+ * \endcode
+ *
+ * \author     ( XinChip ) Alex-J
+ *
+ * \author     ( XinChip )
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __XC6XXX_RF_ADV_H__
+#define __XC6XXX_RF_ADV_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*-----------------------------------------------------------------------------------
+                                       INCLUDE HEADE FILES
+ ------------------------------------------------------------------------------------*/
+#include "rf_adv_config.h"
+#include "xc6xxx.h"
+#include "xc6xxx_rf_2_4g.h"
+
+/*------------------------------------------------------------------------------------
+                                         Macros
+ -------------------------------------------------------------------------------------*/
+#define PIPE0_LEN     XINCX_ADV_PIPE0_LEN
+#define PIPE1_LEN     XINCX_ADV_PIPE1_LEN
+#define PIPE2_LEN     XINCX_ADV_PIPE2_LEN
+#define PIPE3_LEN     XINCX_ADV_PIPE3_LEN
+#define PIPE4_LEN     XINCX_ADV_PIPE4_LEN
+#define PIPE5_LEN     XINCX_ADV_PIPE5_LEN
+
+#define MAC_ADDR_0    XINC_ADV_MAC_ADDR_0
+#define MAC_ADDR_1    XINC_ADV_MAC_ADDR_1
+#define MAC_ADDR_2    XINC_ADV_MAC_ADDR_2
+#define MAC_ADDR_3    XINC_ADV_MAC_ADDR_3
+#define MAC_ADDR_4    XINC_ADV_MAC_ADDR_4
+#define MAC_ADDR_5    XINC_ADV_MAC_ADDR_5
+
+#define TX_ADDR_L_VAL XINCX_ADV_ADDR_L
+#define TX_ADDR_H_VAL XINCX_ADV_ADDR_H
+#define RX_ADDR_L_VAL TX_ADDR_L_VAL
+#define RX_ADDR_H_VAL TX_ADDR_H_VAL
+
+#define ADV_LENGTH    XINCX_ADV_PIPE0_LEN
+/*------------------------------------------------------------------------------------
+                                     Exported Functions
+-------------------------------------------------------------------------------------*/
+typedef enum
+{
+    CRC_ERROR = 0,
+    CRC_OK,
+    CRC_IDLE
+} rf_adv_crc_stat;
+
+void rf24g_adv_init(void);
+uint32_t rf_adv_packet_whiten(uint8_t *len);
+uint8_t rf_adv_crc(uint8_t *adv_buff, uint8_t *len, uint32_t blecrc);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XC6XXX_RF_ADV_H__ */