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hpw421初始版本

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xushaoxiang
2026-06-06 16:49:48 +08:00
commit 2339bbfd1f
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc60xx.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc6xxx.h
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/*!
* \file xc6xxx.h
*
* \brief CMSIS xc6xxx Device Peripheral Access Layer Header File.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6xxx_H
#define __XC6xxx_H
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
/** @addtogroup Device_Included
* @{
*/
#if defined(XC60XX)
#include "xc60xx.h"
#elif defined(XC_LORA_XX)
#include "xc_lora_xx.h"
#else
#error \
"Please select first the target XC6xxx device used in your application (in xc6xxx.h file)"
#endif
/**
* @}
*/
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
XR_OK = 0,
XR_ERROR,
XR_TIMEOUT,
XR_UNKNOWN = 0xFF,
} eXC_RESULT;
/**
* @}
*/
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/** @addtogroup Exported_macro
* @{
*/
#define GD_FlASH_RDID 0x1364c8
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define REG_BIT_VAL_GET(REG, MSK, POS) ((REG & MSK) >> POS)
#define BIT_BUILD(VAL, POS, MSK) ((uint32_t)(((VAL) << POS) & MSK))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) < (b) ? (b) : (a))
// power of 2 macro
#define POW2(pow) (1 << (pow))
// Is A greater than or equal to B macro ?
#define A_MAXEQ_B(a, b) ((a) >= (b))
#define ALIGN_DOWN_ADDR(a, size) (a & (~(size - 1)))
#define ALIGN_UP_ADDR(a, size) ((a + size - 1) & (~(size - 1)))
#ifdef DEBUG_ENABLE
#define DEBUG(fmt, ...) printf(fmt, ##__VA_ARGS__)//printf("[DEBUG] " fmt, ##__VA_ARGS__)
#define PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
#if(_DEBUG_==0)
//#define printf
#endif
#else
#define DEBUG(fmt, ...)
#define PRINT(fmt, ...)
#endif
#define RSTN_VALID (0UL)
#define RSTN_INVALID (1UL)
#ifndef ENABLE
#define ENABLE 0x01
#endif
#ifndef DISABLE
#define DISABLE 0x00
#endif
#ifndef RSTCTL_ENABLE
#define RSTCTL_ENABLE 0x00
#endif
#ifndef RSTCTL_DISABLE
#define RSTCTL_DISABLE 0x01
#endif
#ifndef ASSERT_ERR
#define ASSERT_ERR(cond) \
{ \
}
#endif
/** @brief Enable interrupts globally in the system.
* This macro must be used when the initialization phase is over and the interrupts
* can start being handled by the system.
*/
#define GLOBAL_INT_START() ; \
do { \
__enable_irq(); \
} while(0);
#define GLOBAL_INT_STOP() ; \
do { \
__disable_irq(); \
} while(0);
#define GLOBAL_INT_DISABLE() ; \
do { \
uint32_t irq_temp; \
irq_temp = __disable_irq();
#define GLOBAL_INT_RESTORE() ; \
if(!irq_temp) \
{ \
__enable_irq(); \
} \
} while(0);
/**
* @}
*/
#include "xc_drv_conf.h"
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_Delay delay_ms
void HAL_Delay(unsigned int Delay);
void Error_Handler(void);
#define __HAL_LOCK(__HANDLE__) \
do { \
if ((__HANDLE__)->Lock == HAL_LOCKED) { \
return HAL_BUSY; \
} else { \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
} while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do { \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
} while (0U)
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive
* "#pragma data_alignment=4" must be used instead */
#if defined(__ARMCC_VERSION) && \
(__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif
#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined(__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* __XC6xxx_H */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_lora_xx.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_adc.h
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#ifndef _XC_REG_ADC_H_
#define _XC_REG_ADC_H_
#include <stdint.h>
#define XC_REG_ADC_BASE_ADDR 0x40018000
#define XC_REG_ADC_DECODING_MASK 0x0000003F
/**
* @brief ADC_MAIN_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:12 EXT_SAMPLE_NUM 0x0
* 11 EXT_DATA_MODE 0
* 10:08 EXT_TRIGGER_SEL 0x0
* 05:04 EXT_EDGE_SEL 0x0
* 03 EDGE_SEL 0
* 02 AUTO_SW 0
* 01 DMAS_ON 0
* 00 ADC_EN 0
* </pre>
*/
#define ADC_MAIN_CTL_REG (*(volatile uint32_t *)(0x40018000))
#define ADC_MAIN_CTL_ADDR 0x40018000
#define ADC_MAIN_CTL_OFFSET 0x00000000
__INLINE uint32_t adc_main_ctl_get(void)
{
return ADC_MAIN_CTL_REG;
}
__INLINE void adc_main_ctl_set(uint32_t value)
{
ADC_MAIN_CTL_REG = value;
}
// field definitions
#define EXT_SAMPLE_NUM_MASK 0x0000F000
#define EXT_SAMPLE_NUM_LSB 12
#define EXT_SAMPLE_NUM_WIDTH 0x00000004
#define EXT_DATA_MODE_BIT 0x00000800
#define EXT_DATA_MODE_POS 11
#define EXT_TRIGGER_SEL_MASK 0x00000700
#define EXT_TRIGGER_SEL_LSB 8
#define EXT_TRIGGER_SEL_WIDTH 0x00000003
#define EXT_EDGE_SEL_MASK 0x00000030
#define EXT_EDGE_SEL_LSB 4
#define EXT_EDGE_SEL_WIDTH 0x00000002
#define EDGE_SEL_BIT 0x00000008
#define EDGE_SEL_POS 3
#define AUTO_SW_BIT 0x00000004
#define AUTO_SW_POS 2
#define DMAS_ON_BIT 0x00000002
#define DMAS_ON_POS 1
#define ADC_EN_BIT 0x00000001
#define ADC_EN_POS 0
#define EXT_SAMPLE_NUM_RST 0x0
#define EXT_DATA_MODE_RST 0x0
#define EXT_TRIGGER_SEL_RST 0x0
#define EXT_EDGE_SEL_RST 0x0
#define EDGE_SEL_RST 0x0
#define AUTO_SW_RST 0x0
#define DMAS_ON_RST 0x0
#define ADC_EN_RST 0x0
__INLINE void adc_main_ctl_pack(uint8_t ext_sample_num, uint8_t ext_data_mode, uint8_t ext_trigger_sel, uint8_t ext_edge_sel, uint8_t edge_sel, uint8_t auto_sw, uint8_t dmas_on, uint8_t adc_en)
{
ASSERT_ERR(((ext_sample_num << 12) & ~0x0000F000) == 0);
ASSERT_ERR(((ext_data_mode << 11) & ~0x00000800) == 0);
ASSERT_ERR(((ext_trigger_sel << 8) & ~0x00000700) == 0);
ASSERT_ERR(((ext_edge_sel << 4) & ~0x00000030) == 0);
ASSERT_ERR(((edge_sel << 3) & ~0x00000008) == 0);
ASSERT_ERR(((auto_sw << 2) & ~0x00000004) == 0);
ASSERT_ERR(((dmas_on << 1) & ~0x00000002) == 0);
ASSERT_ERR(((adc_en << 0) & ~0x00000001) == 0);
ADC_MAIN_CTL_REG = (ext_sample_num << 12) | (ext_data_mode << 11) | (ext_trigger_sel << 8) | (ext_edge_sel << 4) | (edge_sel << 3) | (auto_sw << 2) | (dmas_on << 1) | (adc_en << 0);
}
__INLINE void adc_main_ctl_unpack(uint8_t* ext_sample_num, uint8_t* ext_data_mode, uint8_t* ext_trigger_sel, uint8_t* ext_edge_sel, uint8_t* edge_sel, uint8_t* auto_sw, uint8_t* dmas_on, uint8_t* adc_en)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
*ext_sample_num = (localVal & 0x0000F000) >> 12;
*ext_data_mode = (localVal & 0x00000800) >> 11;
*ext_trigger_sel = (localVal & 0x00000700) >> 8;
*ext_edge_sel = (localVal & 0x00000030) >> 4;
*edge_sel = (localVal & 0x00000008) >> 3;
*auto_sw = (localVal & 0x00000004) >> 2;
*dmas_on = (localVal & 0x00000002) >> 1;
*adc_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t adc_main_ctl__ext_sample_num__getf(void)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
return ((localVal & 0x0000F000) >> 12);
}
__INLINE void adc_main_ctl__ext_sample_num__setf(uint8_t ext_sample_num)
{
ASSERT_ERR(((ext_sample_num << 12) & ~0x0000F000) == 0);
ADC_MAIN_CTL_REG = (ADC_MAIN_CTL_REG & ~0x0000F000) | (ext_sample_num << 12);
}
__INLINE uint8_t adc_main_ctl__ext_data_mode__getf(void)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
return ((localVal & 0x00000800) >> 11);
}
__INLINE void adc_main_ctl__ext_data_mode__setf(uint8_t ext_data_mode)
{
ASSERT_ERR(((ext_data_mode << 11) & ~0x00000800) == 0);
ADC_MAIN_CTL_REG = (ADC_MAIN_CTL_REG & ~0x00000800) | (ext_data_mode << 11);
}
__INLINE uint8_t adc_main_ctl__ext_trigger_sel__getf(void)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
return ((localVal & 0x00000700) >> 8);
}
__INLINE void adc_main_ctl__ext_trigger_sel__setf(uint8_t ext_trigger_sel)
{
ASSERT_ERR(((ext_trigger_sel << 8) & ~0x00000700) == 0);
ADC_MAIN_CTL_REG = (ADC_MAIN_CTL_REG & ~0x00000700) | (ext_trigger_sel << 8);
}
__INLINE uint8_t adc_main_ctl__ext_edge_sel__getf(void)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
return ((localVal & 0x00000030) >> 4);
}
__INLINE void adc_main_ctl__ext_edge_sel__setf(uint8_t ext_edge_sel)
{
ASSERT_ERR(((ext_edge_sel << 4) & ~0x00000030) == 0);
ADC_MAIN_CTL_REG = (ADC_MAIN_CTL_REG & ~0x00000030) | (ext_edge_sel << 4);
}
__INLINE uint8_t adc_main_ctl__edge_sel__getf(void)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void adc_main_ctl__edge_sel__setf(uint8_t edge_sel)
{
ASSERT_ERR(((edge_sel << 3) & ~0x00000008) == 0);
ADC_MAIN_CTL_REG = (ADC_MAIN_CTL_REG & ~0x00000008) | (edge_sel << 3);
}
__INLINE uint8_t adc_main_ctl__auto_sw__getf(void)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void adc_main_ctl__auto_sw__setf(uint8_t auto_sw)
{
ASSERT_ERR(((auto_sw << 2) & ~0x00000004) == 0);
ADC_MAIN_CTL_REG = (ADC_MAIN_CTL_REG & ~0x00000004) | (auto_sw << 2);
}
__INLINE uint8_t adc_main_ctl__dmas_on__getf(void)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void adc_main_ctl__dmas_on__setf(uint8_t dmas_on)
{
ASSERT_ERR(((dmas_on << 1) & ~0x00000002) == 0);
ADC_MAIN_CTL_REG = (ADC_MAIN_CTL_REG & ~0x00000002) | (dmas_on << 1);
}
__INLINE uint8_t adc_main_ctl__adc_en__getf(void)
{
uint32_t localVal = ADC_MAIN_CTL_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void adc_main_ctl__adc_en__setf(uint8_t adc_en)
{
ASSERT_ERR(((adc_en << 0) & ~0x00000001) == 0);
ADC_MAIN_CTL_REG = (ADC_MAIN_CTL_REG & ~0x00000001) | (adc_en << 0);
}
/**
* @brief ADC_CHAN_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 11:08 CHAN_AUTO 0x0
* 05:04 VCM_CHAN_AUTO 0x0
* 03:00 SELECT_CHAN 0x0
* </pre>
*/
#define ADC_CHAN_CTL_REG (*(volatile uint32_t *)(0x40018004))
#define ADC_CHAN_CTL_ADDR 0x40018004
#define ADC_CHAN_CTL_OFFSET 0x00000004
__INLINE uint32_t adc_chan_ctl_get(void)
{
return ADC_CHAN_CTL_REG;
}
__INLINE void adc_chan_ctl_set(uint32_t value)
{
ADC_CHAN_CTL_REG = value;
}
// field definitions
#define CHAN_AUTO_MASK 0x00000F00
#define CHAN_AUTO_LSB 8
#define CHAN_AUTO_WIDTH 0x00000004
#define VCM_CHAN_AUTO_MASK 0x00000030
#define VCM_CHAN_AUTO_LSB 4
#define VCM_CHAN_AUTO_WIDTH 0x00000002
#define SELECT_CHAN_MASK 0x0000000F
#define SELECT_CHAN_LSB 0
#define SELECT_CHAN_WIDTH 0x00000004
#define CHAN_AUTO_RST 0x0
#define VCM_CHAN_AUTO_RST 0x0
#define SELECT_CHAN_RST 0x0
__INLINE void adc_chan_ctl_pack(uint8_t chan_auto, uint8_t vcm_chan_auto, uint8_t select_chan)
{
ASSERT_ERR(((chan_auto << 8) & ~0x00000F00) == 0);
ASSERT_ERR(((vcm_chan_auto << 4) & ~0x00000030) == 0);
ASSERT_ERR(((select_chan << 0) & ~0x0000000F) == 0);
ADC_CHAN_CTL_REG = (chan_auto << 8) | (vcm_chan_auto << 4) | (select_chan << 0);
}
__INLINE void adc_chan_ctl_unpack(uint8_t* chan_auto, uint8_t* vcm_chan_auto, uint8_t* select_chan)
{
uint32_t localVal = ADC_CHAN_CTL_REG;
*chan_auto = (localVal & 0x00000F00) >> 8;
*vcm_chan_auto = (localVal & 0x00000030) >> 4;
*select_chan = (localVal & 0x0000000F) >> 0;
}
__INLINE uint8_t adc_chan_ctl__chan_auto__getf(void)
{
uint32_t localVal = ADC_CHAN_CTL_REG;
return ((localVal & 0x00000F00) >> 8);
}
__INLINE void adc_chan_ctl__chan_auto__setf(uint8_t chan_auto)
{
ASSERT_ERR(((chan_auto << 8) & ~0x00000F00) == 0);
ADC_CHAN_CTL_REG = (ADC_CHAN_CTL_REG & ~0x00000F00) | (chan_auto << 8);
}
__INLINE uint8_t adc_chan_ctl__vcm_chan_auto__getf(void)
{
uint32_t localVal = ADC_CHAN_CTL_REG;
return ((localVal & 0x00000030) >> 4);
}
__INLINE void adc_chan_ctl__vcm_chan_auto__setf(uint8_t vcm_chan_auto)
{
ASSERT_ERR(((vcm_chan_auto << 4) & ~0x00000030) == 0);
ADC_CHAN_CTL_REG = (ADC_CHAN_CTL_REG & ~0x00000030) | (vcm_chan_auto << 4);
}
__INLINE uint8_t adc_chan_ctl__select_chan__getf(void)
{
uint32_t localVal = ADC_CHAN_CTL_REG;
return ((localVal & 0x0000000F) >> 0);
}
__INLINE void adc_chan_ctl__select_chan__setf(uint8_t select_chan)
{
ASSERT_ERR(((select_chan << 0) & ~0x0000000F) == 0);
ADC_CHAN_CTL_REG = (ADC_CHAN_CTL_REG & ~0x0000000F) | (select_chan << 0);
}
/**
* @brief ADC_FIFO_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 FIFO_FLUSH 0
* 03:00 READ_REQ_THRESH 0x0
* </pre>
*/
#define ADC_FIFO_CTL_REG (*(volatile uint32_t *)(0x40018008))
#define ADC_FIFO_CTL_ADDR 0x40018008
#define ADC_FIFO_CTL_OFFSET 0x00000008
__INLINE uint32_t adc_fifo_ctl_get(void)
{
return ADC_FIFO_CTL_REG;
}
__INLINE void adc_fifo_ctl_set(uint32_t value)
{
ADC_FIFO_CTL_REG = value;
}
// field definitions
#define FIFO_FLUSH_BIT 0x00000010
#define FIFO_FLUSH_POS 4
#define READ_REQ_THRESH_MASK 0x0000000F
#define READ_REQ_THRESH_LSB 0
#define READ_REQ_THRESH_WIDTH 0x00000004
#define FIFO_FLUSH_RST 0x0
#define READ_REQ_THRESH_RST 0x0
__INLINE void adc_fifo_ctl_pack(uint8_t fifo_flush, uint8_t read_req_thresh)
{
ASSERT_ERR(((fifo_flush << 4) & ~0x00000010) == 0);
ASSERT_ERR(((read_req_thresh << 0) & ~0x0000000F) == 0);
ADC_FIFO_CTL_REG = (fifo_flush << 4) | (read_req_thresh << 0);
}
__INLINE void adc_fifo_ctl_unpack(uint8_t* fifo_flush, uint8_t* read_req_thresh)
{
uint32_t localVal = ADC_FIFO_CTL_REG;
*fifo_flush = (localVal & 0x00000010) >> 4;
*read_req_thresh = (localVal & 0x0000000F) >> 0;
}
__INLINE uint8_t adc_fifo_ctl__fifo_flush__getf(void)
{
uint32_t localVal = ADC_FIFO_CTL_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE void adc_fifo_ctl__fifo_flush__setf(uint8_t fifo_flush)
{
ASSERT_ERR(((fifo_flush << 4) & ~0x00000010) == 0);
ADC_FIFO_CTL_REG = (ADC_FIFO_CTL_REG & ~0x00000010) | (fifo_flush << 4);
}
__INLINE uint8_t adc_fifo_ctl__read_req_thresh__getf(void)
{
uint32_t localVal = ADC_FIFO_CTL_REG;
return ((localVal & 0x0000000F) >> 0);
}
__INLINE void adc_fifo_ctl__read_req_thresh__setf(uint8_t read_req_thresh)
{
ASSERT_ERR(((read_req_thresh << 0) & ~0x0000000F) == 0);
ADC_FIFO_CTL_REG = (ADC_FIFO_CTL_REG & ~0x0000000F) | (read_req_thresh << 0);
}
/**
* @brief ADC_TIMER0 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 SW_WAIT_CNT 0x0
* </pre>
*/
#define ADC_TIMER0_REG (*(volatile uint32_t *)(0x4001800C))
#define ADC_TIMER0_ADDR 0x4001800C
#define ADC_TIMER0_OFFSET 0x0000000C
__INLINE uint32_t adc_timer0_get(void)
{
return ADC_TIMER0_REG;
}
__INLINE void adc_timer0_set(uint32_t value)
{
ADC_TIMER0_REG = value;
}
// field definitions
#define SW_WAIT_CNT_MASK 0x000000FF
#define SW_WAIT_CNT_LSB 0
#define SW_WAIT_CNT_WIDTH 0x00000008
#define SW_WAIT_CNT_RST 0x0
__INLINE uint8_t adc_timer0__sw_wait_cnt__getf(void)
{
uint32_t localVal = ADC_TIMER0_REG;
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
__INLINE void adc_timer0__sw_wait_cnt__setf(uint8_t sw_wait_cnt)
{
ASSERT_ERR(((sw_wait_cnt << 0) & ~0x000000FF) == 0);
ADC_TIMER0_REG = sw_wait_cnt << 0;
}
/**
* @brief ADC_TIMER1 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 AUTO_SW_CNT 0x0
* </pre>
*/
#define ADC_TIMER1_REG (*(volatile uint32_t *)(0x40018010))
#define ADC_TIMER1_ADDR 0x40018010
#define ADC_TIMER1_OFFSET 0x00000010
__INLINE uint32_t adc_timer1_get(void)
{
return ADC_TIMER1_REG;
}
__INLINE void adc_timer1_set(uint32_t value)
{
ADC_TIMER1_REG = value;
}
// field definitions
#define AUTO_SW_CNT_MASK 0x0000FFFF
#define AUTO_SW_CNT_LSB 0
#define AUTO_SW_CNT_WIDTH 0x00000010
#define AUTO_SW_CNT_RST 0x0
__INLINE uint16_t adc_timer1__auto_sw_cnt__getf(void)
{
uint32_t localVal = ADC_TIMER1_REG;
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
__INLINE void adc_timer1__auto_sw_cnt__setf(uint16_t auto_sw_cnt)
{
ASSERT_ERR(((auto_sw_cnt << 0) & ~0x0000FFFF) == 0);
ADC_TIMER1_REG = auto_sw_cnt << 0;
}
/**
* @brief ADC_INT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01 FIFO_ERROR_INT 0
* 00 READ_REQ_INT 0
* </pre>
*/
#define ADC_INT_REG (*(volatile uint32_t *)(0x40018014))
#define ADC_INT_ADDR 0x40018014
#define ADC_INT_OFFSET 0x00000014
__INLINE uint32_t adc_int_get(void)
{
return ADC_INT_REG;
}
__INLINE void adc_int_set(uint32_t value)
{
ADC_INT_REG = value;
}
// field definitions
#define FIFO_ERROR_INT_BIT 0x00000002
#define FIFO_ERROR_INT_POS 1
#define READ_REQ_INT_BIT 0x00000001
#define READ_REQ_INT_POS 0
#define FIFO_ERROR_INT_RST 0x0
#define READ_REQ_INT_RST 0x0
__INLINE void adc_int_pack(uint8_t fifo_error_int, uint8_t read_req_int)
{
ASSERT_ERR(((fifo_error_int << 1) & ~0x00000002) == 0);
ASSERT_ERR(((read_req_int << 0) & ~0x00000001) == 0);
ADC_INT_REG = (fifo_error_int << 1) | (read_req_int << 0);
}
__INLINE void adc_int_unpack(uint8_t* fifo_error_int, uint8_t* read_req_int)
{
uint32_t localVal = ADC_INT_REG;
*fifo_error_int = (localVal & 0x00000002) >> 1;
*read_req_int = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t adc_int__fifo_error_int__getf(void)
{
uint32_t localVal = ADC_INT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void adc_int__fifo_error_int__setf(uint8_t fifo_error_int)
{
ASSERT_ERR(((fifo_error_int << 1) & ~0x00000002) == 0);
ADC_INT_REG = (ADC_INT_REG & ~0x00000002) | (fifo_error_int << 1);
}
__INLINE uint8_t adc_int__read_req_int__getf(void)
{
uint32_t localVal = ADC_INT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void adc_int__read_req_int__setf(uint8_t read_req_int)
{
ASSERT_ERR(((read_req_int << 0) & ~0x00000001) == 0);
ADC_INT_REG = (ADC_INT_REG & ~0x00000001) | (read_req_int << 0);
}
/**
* @brief ADC_INT_RAW register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01 FIFO_ERROR_RAW 0
* 00 READ_REQ_RAW 0
* </pre>
*/
#define ADC_INT_RAW_REG (*(volatile uint32_t *)(0x40018018))
#define ADC_INT_RAW_ADDR 0x40018018
#define ADC_INT_RAW_OFFSET 0x00000018
__INLINE uint32_t adc_int_raw_get(void)
{
return ADC_INT_RAW_REG;
}
// field definitions
#define FIFO_ERROR_RAW_BIT 0x00000002
#define FIFO_ERROR_RAW_POS 1
#define READ_REQ_RAW_BIT 0x00000001
#define READ_REQ_RAW_POS 0
#define FIFO_ERROR_RAW_RST 0x0
#define READ_REQ_RAW_RST 0x0
__INLINE void adc_int_raw_unpack(uint8_t* fifo_error_raw, uint8_t* read_req_raw)
{
uint32_t localVal = ADC_INT_RAW_REG;
*fifo_error_raw = (localVal & 0x00000002) >> 1;
*read_req_raw = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t adc_int_raw__fifo_error_raw__getf(void)
{
uint32_t localVal = ADC_INT_RAW_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE uint8_t adc_int_raw__read_req_raw__getf(void)
{
uint32_t localVal = ADC_INT_RAW_REG;
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief ADC_INT_EN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01 FIFO_ERROR_EN 0
* 00 READ_REQ_EN 0
* </pre>
*/
#define ADC_INT_EN_REG (*(volatile uint32_t *)(0x4001801C))
#define ADC_INT_EN_ADDR 0x4001801C
#define ADC_INT_EN_OFFSET 0x0000001C
__INLINE uint32_t adc_int_en_get(void)
{
return ADC_INT_EN_REG;
}
__INLINE void adc_int_en_set(uint32_t value)
{
ADC_INT_EN_REG = value;
}
// field definitions
#define FIFO_ERROR_EN_BIT 0x00000002
#define FIFO_ERROR_EN_POS 1
#define READ_REQ_EN_BIT 0x00000001
#define READ_REQ_EN_POS 0
#define FIFO_ERROR_EN_RST 0x0
#define READ_REQ_EN_RST 0x0
__INLINE void adc_int_en_pack(uint8_t fifo_error_en, uint8_t read_req_en)
{
ASSERT_ERR(((fifo_error_en << 1) & ~0x00000002) == 0);
ASSERT_ERR(((read_req_en << 0) & ~0x00000001) == 0);
ADC_INT_EN_REG = (fifo_error_en << 1) | (read_req_en << 0);
}
__INLINE void adc_int_en_unpack(uint8_t* fifo_error_en, uint8_t* read_req_en)
{
uint32_t localVal = ADC_INT_EN_REG;
*fifo_error_en = (localVal & 0x00000002) >> 1;
*read_req_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t adc_int_en__fifo_error_en__getf(void)
{
uint32_t localVal = ADC_INT_EN_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void adc_int_en__fifo_error_en__setf(uint8_t fifo_error_en)
{
ASSERT_ERR(((fifo_error_en << 1) & ~0x00000002) == 0);
ADC_INT_EN_REG = (ADC_INT_EN_REG & ~0x00000002) | (fifo_error_en << 1);
}
__INLINE uint8_t adc_int_en__read_req_en__getf(void)
{
uint32_t localVal = ADC_INT_EN_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void adc_int_en__read_req_en__setf(uint8_t read_req_en)
{
ASSERT_ERR(((read_req_en << 0) & ~0x00000001) == 0);
ADC_INT_EN_REG = (ADC_INT_EN_REG & ~0x00000001) | (read_req_en << 0);
}
/**
* @brief ADC_FIFO register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 FIFO_DOUT 0x0
* </pre>
*/
#define ADC_FIFO_REG (*(volatile uint32_t *)(0x40018020))
#define ADC_FIFO_ADDR 0x40018020
#define ADC_FIFO_OFFSET 0x00000020
__INLINE uint32_t adc_fifo_get(void)
{
return ADC_FIFO_REG;
}
// field definitions
#define FIFO_DOUT_MASK 0xFFFFFFFF
#define FIFO_DOUT_LSB 0
#define FIFO_DOUT_WIDTH 0x00000020
#define FIFO_DOUT_RST 0x0
__INLINE uint32_t adc_fifo__fifo_dout__getf(void)
{
uint32_t localVal = ADC_FIFO_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief ADC_RF_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:08 adc_clkdiv 0x0
* 04 ADC_ctl_mux 0
* 03 rst_ADC 0
* 02 diffsel_ADC 0
* 01 gadc_vref_sel 0
* 00 pd_ADC 0
* </pre>
*/
#define ADC_RF_CTL_REG (*(volatile uint32_t *)(0x40018024))
#define ADC_RF_CTL_ADDR 0x40018024
#define ADC_RF_CTL_OFFSET 0x00000024
__INLINE uint32_t adc_rf_ctl_get(void)
{
return ADC_RF_CTL_REG;
}
__INLINE void adc_rf_ctl_set(uint32_t value)
{
ADC_RF_CTL_REG = value;
}
// field definitions
#define ADC_CLKDIV_MASK 0x0000FF00
#define ADC_CLKDIV_LSB 8
#define ADC_CLKDIV_WIDTH 0x00000008
#define ADC_CTL_MUX_BIT 0x00000010
#define ADC_CTL_MUX_POS 4
#define RST_ADC_BIT 0x00000008
#define RST_ADC_POS 3
#define DIFFSEL_ADC_BIT 0x00000004
#define DIFFSEL_ADC_POS 2
#define GADC_VREF_SEL_BIT 0x00000002
#define GADC_VREF_SEL_POS 1
#define PD_ADC_BIT 0x00000001
#define PD_ADC_POS 0
#define ADC_CLKDIV_RST 0x0
#define ADC_CTL_MUX_RST 0x0
#define RST_ADC_RST 0x0
#define DIFFSEL_ADC_RST 0x0
#define GADC_VREF_SEL_RST 0x0
#define PD_ADC_RST 0x0
__INLINE void adc_rf_ctl_pack(uint8_t adc_clkdiv, uint8_t adc_ctl_mux, uint8_t rst_adc, uint8_t diffsel_adc, uint8_t gadc_vref_sel, uint8_t pd_adc)
{
ASSERT_ERR(((adc_clkdiv << 8) & ~0x0000FF00) == 0);
ASSERT_ERR(((adc_ctl_mux << 4) & ~0x00000010) == 0);
ASSERT_ERR(((rst_adc << 3) & ~0x00000008) == 0);
ASSERT_ERR(((diffsel_adc << 2) & ~0x00000004) == 0);
ASSERT_ERR(((gadc_vref_sel << 1) & ~0x00000002) == 0);
ASSERT_ERR(((pd_adc << 0) & ~0x00000001) == 0);
ADC_RF_CTL_REG = (adc_clkdiv << 8) | (adc_ctl_mux << 4) | (rst_adc << 3) | (diffsel_adc << 2) | (gadc_vref_sel << 1) | (pd_adc << 0);
}
__INLINE void adc_rf_ctl_unpack(uint8_t* adc_clkdiv, uint8_t* adc_ctl_mux, uint8_t* rst_adc, uint8_t* diffsel_adc, uint8_t* gadc_vref_sel, uint8_t* pd_adc)
{
uint32_t localVal = ADC_RF_CTL_REG;
*adc_clkdiv = (localVal & 0x0000FF00) >> 8;
*adc_ctl_mux = (localVal & 0x00000010) >> 4;
*rst_adc = (localVal & 0x00000008) >> 3;
*diffsel_adc = (localVal & 0x00000004) >> 2;
*gadc_vref_sel = (localVal & 0x00000002) >> 1;
*pd_adc = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t adc_rf_ctl__adc_clkdiv__getf(void)
{
uint32_t localVal = ADC_RF_CTL_REG;
return ((localVal & 0x0000FF00) >> 8);
}
__INLINE void adc_rf_ctl__adc_clkdiv__setf(uint8_t adc_clkdiv)
{
ASSERT_ERR(((adc_clkdiv << 8) & ~0x0000FF00) == 0);
ADC_RF_CTL_REG = (ADC_RF_CTL_REG & ~0x0000FF00) | (adc_clkdiv << 8);
}
__INLINE uint8_t adc_rf_ctl__adc_ctl_mux__getf(void)
{
uint32_t localVal = ADC_RF_CTL_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE void adc_rf_ctl__adc_ctl_mux__setf(uint8_t adc_ctl_mux)
{
ASSERT_ERR(((adc_ctl_mux << 4) & ~0x00000010) == 0);
ADC_RF_CTL_REG = (ADC_RF_CTL_REG & ~0x00000010) | (adc_ctl_mux << 4);
}
__INLINE uint8_t adc_rf_ctl__rst_adc__getf(void)
{
uint32_t localVal = ADC_RF_CTL_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void adc_rf_ctl__rst_adc__setf(uint8_t rst_adc)
{
ASSERT_ERR(((rst_adc << 3) & ~0x00000008) == 0);
ADC_RF_CTL_REG = (ADC_RF_CTL_REG & ~0x00000008) | (rst_adc << 3);
}
__INLINE uint8_t adc_rf_ctl__diffsel_adc__getf(void)
{
uint32_t localVal = ADC_RF_CTL_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void adc_rf_ctl__diffsel_adc__setf(uint8_t diffsel_adc)
{
ASSERT_ERR(((diffsel_adc << 2) & ~0x00000004) == 0);
ADC_RF_CTL_REG = (ADC_RF_CTL_REG & ~0x00000004) | (diffsel_adc << 2);
}
__INLINE uint8_t adc_rf_ctl__gadc_vref_sel__getf(void)
{
uint32_t localVal = ADC_RF_CTL_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void adc_rf_ctl__gadc_vref_sel__setf(uint8_t gadc_vref_sel)
{
ASSERT_ERR(((gadc_vref_sel << 1) & ~0x00000002) == 0);
ADC_RF_CTL_REG = (ADC_RF_CTL_REG & ~0x00000002) | (gadc_vref_sel << 1);
}
__INLINE uint8_t adc_rf_ctl__pd_adc__getf(void)
{
uint32_t localVal = ADC_RF_CTL_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void adc_rf_ctl__pd_adc__setf(uint8_t pd_adc)
{
ASSERT_ERR(((pd_adc << 0) & ~0x00000001) == 0);
ADC_RF_CTL_REG = (ADC_RF_CTL_REG & ~0x00000001) | (pd_adc << 0);
}
#endif // _XC_REG_ADC_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_aotimer.h
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#ifndef _XC_REG_AOTIMER_H_
#define _XC_REG_AOTIMER_H_
#include <stdint.h>
#include "xc6xxx.h"
#define XC_REG_AOTIMER_BASE_ADDR 0x40002800
#define XC_REG_AOTIMER_DECODING_MASK 0x0000001F
/**
* @brief AOTIMER_TLC register definition
*/
#define AOTIMER_TLC_REG(i) (*(volatile uint32_t *)(0x40002800 + aotimer_offset[i]))
#define AOTIMER_TLC_ADDR(i) (0x40002800 + aotimer_offset[i])
#define AOTIMER_TLC_OFFSET 0x00000000
__INLINE uint32_t aotimer_tlc_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TLC_REG(reg_idx);
}
__INLINE void aotimer_tlc_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
AOTIMER_TLC_REG(reg_idx) = value;
}
/**
* @brief AOTIMER_TCV register definition
*/
#define AOTIMER_TCV_REG(i) (*(volatile uint32_t *)(0x40002804 + aotimer_offset[i]))
#define AOTIMER_TCV_ADDR(i) (0x40002804 + aotimer_offset[i])
#define AOTIMER_TCV_OFFSET 0x00000004
__INLINE uint32_t aotimer_tcv_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TCV_REG(reg_idx);
}
/**
* @brief AOTIMER_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 TIM 0
* 01 TMS 0
* 00 TES 0
* </pre>
*/
#define AOTIMER_TCR_REG(i) (*(volatile uint32_t *)(0x40002808 + aotimer_offset[i]))
#define AOTIMER_TCR_ADDR(i) (0x40002808 + aotimer_offset[i])
#define AOTIMER_TCR_OFFSET 0x00000008
__INLINE uint32_t aotimer_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TCR_REG(reg_idx);
}
__INLINE void aotimer_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
AOTIMER_TCR_REG(reg_idx) = value;
}
// field definitions
#define TIM_BIT 0x00000004
#define TIM_POS 2
#define TMS_BIT 0x00000002
#define TMS_POS 1
#define TES_BIT 0x00000001
#define TES_POS 0
#define TIM_RST 0x0
#define TMS_RST 0x0
#define TES_RST 0x0
__INLINE void aotimer_tcr_pack(uint32_t reg_idx, uint8_t tim, uint8_t tms, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
AOTIMER_TCR_REG(reg_idx) = (tim << 2) | (tms << 1) | (tes << 0);
}
__INLINE void aotimer_tcr_unpack(uint32_t reg_idx, uint8_t* tim, uint8_t* tms, uint8_t* tes)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
*tim = (localVal & 0x00000004) >> 2;
*tms = (localVal & 0x00000002) >> 1;
*tes = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t aotimer_tcr__tim__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void aotimer_tcr__tim__setf(uint32_t reg_idx, uint8_t tim)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000004) | (tim << 2);
}
__INLINE uint8_t aotimer_tcr__tms__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void aotimer_tcr__tms__setf(uint32_t reg_idx, uint8_t tms)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000002) | (tms << 1);
}
__INLINE uint8_t aotimer_tcr__tes__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void aotimer_tcr__tes__setf(uint32_t reg_idx, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000001) | (tes << 0);
}
/**
* @brief AOTIMER_TIC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 TIC 0
* </pre>
*/
#define AOTIMER_TIC_REG(i) (*(volatile uint32_t *)(0x4000280C + aotimer_offset[i]))
#define AOTIMER_TIC_ADDR(i) (0x4000280C + aotimer_offset[i])
#define AOTIMER_TIC_OFFSET 0x0000000C
__INLINE uint32_t aotimer_tic_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TIC_REG(reg_idx);
}
// field definitions
#define TIC_BIT 0x00000001
#define TIC_POS 0
#define TIC_RST 0x0
__INLINE uint8_t aotimer_tic__tic__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TIC_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief AOTIMER_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 TIS 0
* </pre>
*/
#define AOTIMER_TIS_REG(i) (*(volatile uint32_t *)(0x40002810 + aotimer_offset[i]))
#define AOTIMER_TIS_ADDR(i) (0x40002810 + aotimer_offset[i])
#define AOTIMER_TIS_OFFSET 0x00000010
__INLINE uint32_t aotimer_tis_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TIS_REG(reg_idx);
}
// field definitions
#define TIS_BIT 0x00000001
#define TIS_POS 0
#define TIS_RST 0x0
__INLINE uint8_t aotimer_tis__tis__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TIS_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_AOTIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_cpr.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_cprao.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_dma.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_fmc.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_fmc_cache.h
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#ifndef _XC_REG_FMC_CACHE_H_
#define _XC_REG_FMC_CACHE_H_
#include <stdint.h>
#define XC_REG_FMC_CACHE_BASE_ADDR 0x52000000
#define XC_REG_FMC_CACHE_DECODING_MASK 0x0000001F
/**
* @brief FMC_CACHE_CCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 06 STATISTIC_EN 0
* 05 SET_PREFETCH 0
* 04 SET_MAN_INV 0
* 03 SET_MAN_POW 0
* 02 POW_REQ 0
* 01 INV_REQ 0
* 00 EN 0
* </pre>
*/
#define FMC_CACHE_CCR_REG (*(volatile uint32_t *)(0x52000000))
#define FMC_CACHE_CCR_ADDR 0x52000000
#define FMC_CACHE_CCR_OFFSET 0x00000000
__INLINE uint32_t fmc_cache_ccr_get(void)
{
return FMC_CACHE_CCR_REG;
}
__INLINE void fmc_cache_ccr_set(uint32_t value)
{
FMC_CACHE_CCR_REG = value;
}
// field definitions
#define STATISTIC_EN_BIT 0x00000040
#define STATISTIC_EN_POS 6
#define SET_PREFETCH_BIT 0x00000020
#define SET_PREFETCH_POS 5
#define SET_MAN_INV_BIT 0x00000010
#define SET_MAN_INV_POS 4
#define SET_MAN_POW_BIT 0x00000008
#define SET_MAN_POW_POS 3
#define POW_REQ_BIT 0x00000004
#define POW_REQ_POS 2
#define INV_REQ_BIT 0x00000002
#define INV_REQ_POS 1
#define EN_BIT 0x00000001
#define EN_POS 0
#define STATISTIC_EN_RST 0x0
#define SET_PREFETCH_RST 0x0
#define SET_MAN_INV_RST 0x0
#define SET_MAN_POW_RST 0x0
#define POW_REQ_RST 0x0
#define INV_REQ_RST 0x0
#define EN_RST 0x0
__INLINE void fmc_cache_ccr_pack(uint8_t statistic_en, uint8_t set_prefetch, uint8_t set_man_inv, uint8_t set_man_pow, uint8_t pow_req, uint8_t inv_req, uint8_t en)
{
ASSERT_ERR(((statistic_en << 6) & ~0x00000040) == 0);
ASSERT_ERR(((set_prefetch << 5) & ~0x00000020) == 0);
ASSERT_ERR(((set_man_inv << 4) & ~0x00000010) == 0);
ASSERT_ERR(((set_man_pow << 3) & ~0x00000008) == 0);
ASSERT_ERR(((pow_req << 2) & ~0x00000004) == 0);
ASSERT_ERR(((inv_req << 1) & ~0x00000002) == 0);
ASSERT_ERR(((en << 0) & ~0x00000001) == 0);
FMC_CACHE_CCR_REG = (statistic_en << 6) | (set_prefetch << 5) | (set_man_inv << 4) | (set_man_pow << 3) | (pow_req << 2) | (inv_req << 1) | (en << 0);
}
__INLINE void fmc_cache_ccr_unpack(uint8_t* statistic_en, uint8_t* set_prefetch, uint8_t* set_man_inv, uint8_t* set_man_pow, uint8_t* pow_req, uint8_t* inv_req, uint8_t* en)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
*statistic_en = (localVal & 0x00000040) >> 6;
*set_prefetch = (localVal & 0x00000020) >> 5;
*set_man_inv = (localVal & 0x00000010) >> 4;
*set_man_pow = (localVal & 0x00000008) >> 3;
*pow_req = (localVal & 0x00000004) >> 2;
*inv_req = (localVal & 0x00000002) >> 1;
*en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t fmc_cache_ccr__statistic_en__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000040) >> 6);
}
__INLINE void fmc_cache_ccr__statistic_en__setf(uint8_t statistic_en)
{
ASSERT_ERR(((statistic_en << 6) & ~0x00000040) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000040) | (statistic_en << 6);
}
__INLINE uint8_t fmc_cache_ccr__set_prefetch__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000020) >> 5);
}
__INLINE void fmc_cache_ccr__set_prefetch__setf(uint8_t set_prefetch)
{
ASSERT_ERR(((set_prefetch << 5) & ~0x00000020) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000020) | (set_prefetch << 5);
}
__INLINE uint8_t fmc_cache_ccr__set_man_inv__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE void fmc_cache_ccr__set_man_inv__setf(uint8_t set_man_inv)
{
ASSERT_ERR(((set_man_inv << 4) & ~0x00000010) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000010) | (set_man_inv << 4);
}
__INLINE uint8_t fmc_cache_ccr__set_man_pow__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void fmc_cache_ccr__set_man_pow__setf(uint8_t set_man_pow)
{
ASSERT_ERR(((set_man_pow << 3) & ~0x00000008) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000008) | (set_man_pow << 3);
}
__INLINE uint8_t fmc_cache_ccr__pow_req__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void fmc_cache_ccr__pow_req__setf(uint8_t pow_req)
{
ASSERT_ERR(((pow_req << 2) & ~0x00000004) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000004) | (pow_req << 2);
}
__INLINE uint8_t fmc_cache_ccr__inv_req__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void fmc_cache_ccr__inv_req__setf(uint8_t inv_req)
{
ASSERT_ERR(((inv_req << 1) & ~0x00000002) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000002) | (inv_req << 1);
}
__INLINE uint8_t fmc_cache_ccr__en__getf(void)
{
uint32_t localVal = FMC_CACHE_CCR_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void fmc_cache_ccr__en__setf(uint8_t en)
{
ASSERT_ERR(((en << 0) & ~0x00000001) == 0);
FMC_CACHE_CCR_REG = (FMC_CACHE_CCR_REG & ~0x00000001) | (en << 0);
}
/**
* @brief FMC_CACHE_SR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 POW_STAT 0
* 02 INV_STAT 0
* 01:00 CS 0x0
* </pre>
*/
#define FMC_CACHE_SR_REG (*(volatile uint32_t *)(0x52000004))
#define FMC_CACHE_SR_ADDR 0x52000004
#define FMC_CACHE_SR_OFFSET 0x00000004
__INLINE uint32_t fmc_cache_sr_get(void)
{
return FMC_CACHE_SR_REG;
}
// field definitions
#define POW_STAT_BIT 0x00000010
#define POW_STAT_POS 4
#define INV_STAT_BIT 0x00000004
#define INV_STAT_POS 2
#define CS_MASK 0x00000003
#define CS_LSB 0
#define CS_WIDTH 0x00000002
#define POW_STAT_RST 0x0
#define INV_STAT_RST 0x0
#define CS_RST 0x0
__INLINE void fmc_cache_sr_unpack(uint8_t* pow_stat, uint8_t* inv_stat, uint8_t* cs)
{
uint32_t localVal = FMC_CACHE_SR_REG;
*pow_stat = (localVal & 0x00000010) >> 4;
*inv_stat = (localVal & 0x00000004) >> 2;
*cs = (localVal & 0x00000003) >> 0;
}
__INLINE uint8_t fmc_cache_sr__pow_stat__getf(void)
{
uint32_t localVal = FMC_CACHE_SR_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t fmc_cache_sr__inv_stat__getf(void)
{
uint32_t localVal = FMC_CACHE_SR_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE uint8_t fmc_cache_sr__cs__getf(void)
{
uint32_t localVal = FMC_CACHE_SR_REG;
return ((localVal & 0x00000003) >> 0);
}
/**
* @brief FMC_CACHE_IRQMASK register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01 MAN_INV_ERR0 0
* 00 POW_ERR0 0
* </pre>
*/
#define FMC_CACHE_IRQMASK_REG (*(volatile uint32_t *)(0x52000008))
#define FMC_CACHE_IRQMASK_ADDR 0x52000008
#define FMC_CACHE_IRQMASK_OFFSET 0x00000008
__INLINE uint32_t fmc_cache_irqmask_get(void)
{
return FMC_CACHE_IRQMASK_REG;
}
__INLINE void fmc_cache_irqmask_set(uint32_t value)
{
FMC_CACHE_IRQMASK_REG = value;
}
// field definitions
#define MAN_INV_ERR0_BIT 0x00000002
#define MAN_INV_ERR0_POS 1
#define POW_ERR0_BIT 0x00000001
#define POW_ERR0_POS 0
#define MAN_INV_ERR0_RST 0x0
#define POW_ERR0_RST 0x0
__INLINE void fmc_cache_irqmask_pack(uint8_t man_inv_err0, uint8_t pow_err0)
{
ASSERT_ERR(((man_inv_err0 << 1) & ~0x00000002) == 0);
ASSERT_ERR(((pow_err0 << 0) & ~0x00000001) == 0);
FMC_CACHE_IRQMASK_REG = (man_inv_err0 << 1) | (pow_err0 << 0);
}
__INLINE void fmc_cache_irqmask_unpack(uint8_t* man_inv_err0, uint8_t* pow_err0)
{
uint32_t localVal = FMC_CACHE_IRQMASK_REG;
*man_inv_err0 = (localVal & 0x00000002) >> 1;
*pow_err0 = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t fmc_cache_irqmask__man_inv_err0__getf(void)
{
uint32_t localVal = FMC_CACHE_IRQMASK_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void fmc_cache_irqmask__man_inv_err0__setf(uint8_t man_inv_err0)
{
ASSERT_ERR(((man_inv_err0 << 1) & ~0x00000002) == 0);
FMC_CACHE_IRQMASK_REG = (FMC_CACHE_IRQMASK_REG & ~0x00000002) | (man_inv_err0 << 1);
}
__INLINE uint8_t fmc_cache_irqmask__pow_err0__getf(void)
{
uint32_t localVal = FMC_CACHE_IRQMASK_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void fmc_cache_irqmask__pow_err0__setf(uint8_t pow_err0)
{
ASSERT_ERR(((pow_err0 << 0) & ~0x00000001) == 0);
FMC_CACHE_IRQMASK_REG = (FMC_CACHE_IRQMASK_REG & ~0x00000001) | (pow_err0 << 0);
}
/**
* @brief FMC_CACHE_IRQSTAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01 MAN_INV_ERR1 0
* 00 POW_ERR1 0
* </pre>
*/
#define FMC_CACHE_IRQSTAT_REG (*(volatile uint32_t *)(0x5200000C))
#define FMC_CACHE_IRQSTAT_ADDR 0x5200000C
#define FMC_CACHE_IRQSTAT_OFFSET 0x0000000C
__INLINE uint32_t fmc_cache_irqstat_get(void)
{
return FMC_CACHE_IRQSTAT_REG;
}
__INLINE void fmc_cache_irqstat_set(uint32_t value)
{
FMC_CACHE_IRQSTAT_REG = value;
}
// field definitions
#define MAN_INV_ERR1_BIT 0x00000002
#define MAN_INV_ERR1_POS 1
#define POW_ERR1_BIT 0x00000001
#define POW_ERR1_POS 0
#define MAN_INV_ERR1_RST 0x0
#define POW_ERR1_RST 0x0
__INLINE void fmc_cache_irqstat_pack(uint8_t man_inv_err1, uint8_t pow_err1)
{
ASSERT_ERR(((man_inv_err1 << 1) & ~0x00000002) == 0);
ASSERT_ERR(((pow_err1 << 0) & ~0x00000001) == 0);
FMC_CACHE_IRQSTAT_REG = (man_inv_err1 << 1) | (pow_err1 << 0);
}
__INLINE void fmc_cache_irqstat_unpack(uint8_t* man_inv_err1, uint8_t* pow_err1)
{
uint32_t localVal = FMC_CACHE_IRQSTAT_REG;
*man_inv_err1 = (localVal & 0x00000002) >> 1;
*pow_err1 = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t fmc_cache_irqstat__man_inv_err1__getf(void)
{
uint32_t localVal = FMC_CACHE_IRQSTAT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void fmc_cache_irqstat__man_inv_err1__setf(uint8_t man_inv_err1)
{
ASSERT_ERR(((man_inv_err1 << 1) & ~0x00000002) == 0);
FMC_CACHE_IRQSTAT_REG = (FMC_CACHE_IRQSTAT_REG & ~0x00000002) | (man_inv_err1 << 1);
}
__INLINE uint8_t fmc_cache_irqstat__pow_err1__getf(void)
{
uint32_t localVal = FMC_CACHE_IRQSTAT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void fmc_cache_irqstat__pow_err1__setf(uint8_t pow_err1)
{
ASSERT_ERR(((pow_err1 << 0) & ~0x00000001) == 0);
FMC_CACHE_IRQSTAT_REG = (FMC_CACHE_IRQSTAT_REG & ~0x00000001) | (pow_err1 << 0);
}
/**
* @brief FMC_CACHE_HWPARAMS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 13 GEN_STAT_LOGIC 0
* 12 RESET_ALL_REGS 0
* 11:10 CACHE_WAY 0x0
* 09:05 CW 0x0
* 04:00 AW 0x0
* </pre>
*/
#define FMC_CACHE_HWPARAMS_REG (*(volatile uint32_t *)(0x52000010))
#define FMC_CACHE_HWPARAMS_ADDR 0x52000010
#define FMC_CACHE_HWPARAMS_OFFSET 0x00000010
__INLINE uint32_t fmc_cache_hwparams_get(void)
{
return FMC_CACHE_HWPARAMS_REG;
}
// field definitions
#define GEN_STAT_LOGIC_BIT 0x00002000
#define GEN_STAT_LOGIC_POS 13
#define RESET_ALL_REGS_BIT 0x00001000
#define RESET_ALL_REGS_POS 12
#define CACHE_WAY_MASK 0x00000C00
#define CACHE_WAY_LSB 10
#define CACHE_WAY_WIDTH 0x00000002
#define CW_MASK 0x000003E0
#define CW_LSB 5
#define CW_WIDTH 0x00000005
#define AW_MASK 0x0000001F
#define AW_LSB 0
#define AW_WIDTH 0x00000005
#define GEN_STAT_LOGIC_RST 0x0
#define RESET_ALL_REGS_RST 0x0
#define CACHE_WAY_RST 0x0
#define CW_RST 0x0
#define AW_RST 0x0
__INLINE void fmc_cache_hwparams_unpack(uint8_t* gen_stat_logic, uint8_t* reset_all_regs, uint8_t* cache_way, uint8_t* cw, uint8_t* aw)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
*gen_stat_logic = (localVal & 0x00002000) >> 13;
*reset_all_regs = (localVal & 0x00001000) >> 12;
*cache_way = (localVal & 0x00000C00) >> 10;
*cw = (localVal & 0x000003E0) >> 5;
*aw = (localVal & 0x0000001F) >> 0;
}
__INLINE uint8_t fmc_cache_hwparams__gen_stat_logic__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x00002000) >> 13);
}
__INLINE uint8_t fmc_cache_hwparams__reset_all_regs__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x00001000) >> 12);
}
__INLINE uint8_t fmc_cache_hwparams__cache_way__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x00000C00) >> 10);
}
__INLINE uint8_t fmc_cache_hwparams__cw__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x000003E0) >> 5);
}
__INLINE uint8_t fmc_cache_hwparams__aw__getf(void)
{
uint32_t localVal = FMC_CACHE_HWPARAMS_REG;
return ((localVal & 0x0000001F) >> 0);
}
/**
* @brief FMC_CACHE_CSHR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 CSHR 0x0
* </pre>
*/
#define FMC_CACHE_CSHR_REG (*(volatile uint32_t *)(0x52000014))
#define FMC_CACHE_CSHR_ADDR 0x52000014
#define FMC_CACHE_CSHR_OFFSET 0x00000014
__INLINE uint32_t fmc_cache_cshr_get(void)
{
return FMC_CACHE_CSHR_REG;
}
__INLINE void fmc_cache_cshr_set(uint32_t value)
{
FMC_CACHE_CSHR_REG = value;
}
// field definitions
#define CSHR_MASK 0xFFFFFFFF
#define CSHR_LSB 0
#define CSHR_WIDTH 0x00000020
#define CSHR_RST 0x0
__INLINE uint32_t fmc_cache_cshr__cshr__getf(void)
{
uint32_t localVal = FMC_CACHE_CSHR_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
__INLINE void fmc_cache_cshr__cshr__setf(uint32_t cshr)
{
ASSERT_ERR(((cshr << 0) & ~0xFFFFFFFF) == 0);
FMC_CACHE_CSHR_REG = cshr << 0;
}
/**
* @brief FMC_CACHE_CSMR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 CSMR 0x0
* </pre>
*/
#define FMC_CACHE_CSMR_REG (*(volatile uint32_t *)(0x52000018))
#define FMC_CACHE_CSMR_ADDR 0x52000018
#define FMC_CACHE_CSMR_OFFSET 0x00000018
__INLINE uint32_t fmc_cache_csmr_get(void)
{
return FMC_CACHE_CSMR_REG;
}
__INLINE void fmc_cache_csmr_set(uint32_t value)
{
FMC_CACHE_CSMR_REG = value;
}
// field definitions
#define CSMR_MASK 0xFFFFFFFF
#define CSMR_LSB 0
#define CSMR_WIDTH 0x00000020
#define CSMR_RST 0x0
__INLINE uint32_t fmc_cache_csmr__csmr__getf(void)
{
uint32_t localVal = FMC_CACHE_CSMR_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
__INLINE void fmc_cache_csmr__csmr__setf(uint32_t csmr)
{
ASSERT_ERR(((csmr << 0) & ~0xFFFFFFFF) == 0);
FMC_CACHE_CSMR_REG = csmr << 0;
}
#endif // _XC_REG_FMC_CACHE_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_gpio.h
+655
View File
@@ -0,0 +1,655 @@
#ifndef _XC_REG_GPIO_H_
#define _XC_REG_GPIO_H_
#include <stdint.h>
#define XC_REG_GPIO_BASE_ADDR 0x40001000
#define XC_REG_GPIO_DECODING_MASK 0x000003FF
#define GPIO_REG_SIZE 0x04
/**
* @brief GPIO_PORT_DR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 DR_WE 0x0
* 15:00 DR 0x0
* </pre>
*/
#define GPIO_PORT_DR_REG(i) (*(volatile uint32_t *)(0x40001000 + i*GPIO_REG_SIZE))
#define GPIO_PORT_DR_ADDR(i) (0x40001000 + i*GPIO_REG_SIZE)
#define GPIO_PORT_DR_OFFSET 0x00000000
__INLINE uint32_t gpio_port_dr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_PORT_DR_REG(reg_idx);
}
__INLINE void gpio_port_dr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_PORT_DR_REG(reg_idx) = value;
}
// field definitions
#define DR_WE_MASK 0xFFFF0000
#define DR_WE_LSB 16
#define DR_WE_WIDTH 0x00000010
#define DR_MASK 0x0000FFFF
#define DR_LSB 0
#define DR_WIDTH 0x00000010
#define DR_WE_RST 0x0
#define DR_RST 0x0
__INLINE void gpio_port_dr_pack(uint32_t reg_idx, uint16_t drwe, uint16_t dr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((drwe << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((dr << 0) & ~0x0000FFFF) == 0);
GPIO_PORT_DR_REG(reg_idx) = (drwe << 16) | (dr << 0);
}
__INLINE void gpio_port_dr_unpack(uint32_t reg_idx, uint16_t* drwe, uint16_t* dr)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_PORT_DR_REG(reg_idx);
*drwe = (localVal & 0xFFFF0000) >> 16;
*dr = (localVal & 0x0000FFFF) >> 0;
}
__INLINE void gpio_port_dr__dr_we__setf(uint32_t reg_idx, uint16_t drwe)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((drwe << 16) & ~0xFFFF0000) == 0);
GPIO_PORT_DR_REG(reg_idx) = (GPIO_PORT_DR_REG(reg_idx) & ~0xFFFF0000) | (drwe << 16);
}
__INLINE uint16_t gpio_port_dr__dr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_PORT_DR_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void gpio_port_dr__dr__setf(uint32_t reg_idx, uint16_t dr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((dr << 0) & ~0x0000FFFF) == 0);
GPIO_PORT_DR_REG(reg_idx) = (GPIO_PORT_DR_REG(reg_idx) & ~0x0000FFFF) | (dr << 0);
}
/**
* @brief GPIO_PORT_DDR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 DDR_WE 0x0
* 15:00 DDR 0x0
* </pre>
*/
#define GPIO_PORT_DDR_REG(i) (*(volatile uint32_t *)(0x40001020 + i*GPIO_REG_SIZE))
#define GPIO_PORT_DDR_ADDR(i) (0x40001020 + i*GPIO_REG_SIZE)
#define GPIO_PORT_DDR_OFFSET 0x00000020
__INLINE uint32_t gpio_port_ddr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_PORT_DDR_REG(reg_idx);
}
__INLINE void gpio_port_ddr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_PORT_DDR_REG(reg_idx) = value;
}
// field definitions
#define DDR_WE_MASK 0xFFFF0000
#define DDR_WE_LSB 16
#define DDR_WE_WIDTH 0x00000010
#define DDR_MASK 0x0000FFFF
#define DDR_LSB 0
#define DDR_WIDTH 0x00000010
#define DDR_WE_RST 0x0
#define DDR_RST 0x0
__INLINE void gpio_port_ddr_pack(uint32_t reg_idx, uint16_t ddrwe, uint16_t ddr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((ddrwe << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((ddr << 0) & ~0x0000FFFF) == 0);
GPIO_PORT_DDR_REG(reg_idx) = (ddrwe << 16) | (ddr << 0);
}
__INLINE void gpio_port_ddr_unpack(uint32_t reg_idx, uint16_t* ddrwe, uint16_t* ddr)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_PORT_DDR_REG(reg_idx);
*ddrwe = (localVal & 0xFFFF0000) >> 16;
*ddr = (localVal & 0x0000FFFF) >> 0;
}
__INLINE void gpio_port_ddr__ddr_we__setf(uint32_t reg_idx, uint16_t ddrwe)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((ddrwe << 16) & ~0xFFFF0000) == 0);
GPIO_PORT_DDR_REG(reg_idx) = (GPIO_PORT_DDR_REG(reg_idx) & ~0xFFFF0000) | (ddrwe << 16);
}
__INLINE uint16_t gpio_port_ddr__ddr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_PORT_DDR_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void gpio_port_ddr__ddr__setf(uint32_t reg_idx, uint16_t ddr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((ddr << 0) & ~0x0000FFFF) == 0);
GPIO_PORT_DDR_REG(reg_idx) = (GPIO_PORT_DDR_REG(reg_idx) & ~0x0000FFFF) | (ddr << 0);
}
/**
* @brief GPIO_EXT_PORT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 DIN 0x0
* </pre>
*/
#define GPIO_EXT_PORT_REG(i) (*(volatile uint32_t *)(0x40001040 + i*GPIO_REG_SIZE))
#define GPIO_EXT_PORT_ADDR(i) (0x40001040 + i*GPIO_REG_SIZE)
#define GPIO_EXT_PORT_OFFSET 0x00000040
__INLINE uint32_t gpio_ext_port_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_EXT_PORT_REG(reg_idx);
}
// field definitions
#define DIN_MASK 0xFFFFFFFF
#define DIN_LSB 0
#define DIN_WIDTH 0x00000020
#define DIN_RST 0x0
__INLINE uint32_t gpio_ext_port__din__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_EXT_PORT_REG(reg_idx);
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief GPIO_INTR_CTRL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 19:16 MODE_WE 0x0
* 15:13 MODE3 0x0
* 12 MODE_EN3 0
* 11:09 MODE2 0x0
* 08 MODE_EN2 0
* 07:05 MODE1 0x0
* 04 MODE_EN1 0
* 03:01 MODE0 0x0
* 00 MODE_EN0 0
* </pre>
*/
#define GPIO_INTR_CTRL_REG(i) (*(volatile uint32_t *)(0x40001100 + i*GPIO_REG_SIZE))
#define GPIO_INTR_CTRL_ADDR(i) (0x40001100 + i*GPIO_REG_SIZE)
#define GPIO_INTR_CTRL_OFFSET 0x00000100
__INLINE uint32_t gpio_intr_ctrl_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
return GPIO_INTR_CTRL_REG(reg_idx);
}
__INLINE void gpio_intr_ctrl_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 7);
GPIO_INTR_CTRL_REG(reg_idx) = value;
}
// field definitions
#define MODE_WE_MASK 0x000F0000
#define MODE_WE_LSB 16
#define MODE_WE_WIDTH 0x00000004
#define MODE3_MASK 0x0000E000
#define MODE3_LSB 13
#define MODE3_WIDTH 0x00000003
#define MODE_EN3_BIT 0x00001000
#define MODE_EN3_POS 12
#define MODE2_MASK 0x00000E00
#define MODE2_LSB 9
#define MODE2_WIDTH 0x00000003
#define MODE_EN2_BIT 0x00000100
#define MODE_EN2_POS 8
#define MODE1_MASK 0x000000E0
#define MODE1_LSB 5
#define MODE1_WIDTH 0x00000003
#define MODE_EN1_BIT 0x00000010
#define MODE_EN1_POS 4
#define MODE0_MASK 0x0000000E
#define MODE0_LSB 1
#define MODE0_WIDTH 0x00000003
#define MODE_EN0_BIT 0x00000001
#define MODE_EN0_POS 0
#define MODE_WE_RST 0x0
#define MODE3_RST 0x0
#define MODE_EN3_RST 0x0
#define MODE2_RST 0x0
#define MODE_EN2_RST 0x0
#define MODE1_RST 0x0
#define MODE_EN1_RST 0x0
#define MODE0_RST 0x0
#define MODE_EN0_RST 0x0
__INLINE void gpio_intr_ctrl_pack(uint32_t reg_idx, uint8_t modewe, uint8_t mode3, uint8_t modeen3, uint8_t mode2, uint8_t modeen2, uint8_t mode1, uint8_t modeen1, uint8_t mode0, uint8_t modeen0)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modewe << 16) & ~0x000F0000) == 0);
ASSERT_ERR(((mode3 << 13) & ~0x0000E000) == 0);
ASSERT_ERR(((modeen3 << 12) & ~0x00001000) == 0);
ASSERT_ERR(((mode2 << 9) & ~0x00000E00) == 0);
ASSERT_ERR(((modeen2 << 8) & ~0x00000100) == 0);
ASSERT_ERR(((mode1 << 5) & ~0x000000E0) == 0);
ASSERT_ERR(((modeen1 << 4) & ~0x00000010) == 0);
ASSERT_ERR(((mode0 << 1) & ~0x0000000E) == 0);
ASSERT_ERR(((modeen0 << 0) & ~0x00000001) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (modewe << 16) | (mode3 << 13) | (modeen3 << 12) | (mode2 << 9) | (modeen2 << 8) | (mode1 << 5) | (modeen1 << 4) | (mode0 << 1) | (modeen0 << 0);
}
__INLINE void gpio_intr_ctrl_unpack(uint32_t reg_idx, uint8_t* modewe, uint8_t* mode3, uint8_t* modeen3, uint8_t* mode2, uint8_t* modeen2, uint8_t* mode1, uint8_t* modeen1, uint8_t* mode0, uint8_t* modeen0)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
*modewe = (localVal & 0x000F0000) >> 16;
*mode3 = (localVal & 0x0000E000) >> 13;
*modeen3 = (localVal & 0x00001000) >> 12;
*mode2 = (localVal & 0x00000E00) >> 9;
*modeen2 = (localVal & 0x00000100) >> 8;
*mode1 = (localVal & 0x000000E0) >> 5;
*modeen1 = (localVal & 0x00000010) >> 4;
*mode0 = (localVal & 0x0000000E) >> 1;
*modeen0 = (localVal & 0x00000001) >> 0;
}
__INLINE void gpio_intr_ctrl__mode_we__setf(uint32_t reg_idx, uint8_t modewe)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modewe << 16) & ~0x000F0000) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x000F0000) | (modewe << 16);
}
__INLINE uint8_t gpio_intr_ctrl__mode3__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x0000E000) >> 13);
}
__INLINE void gpio_intr_ctrl__mode3__setf(uint32_t reg_idx, uint8_t mode3)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((mode3 << 13) & ~0x0000E000) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x0000E000) | (mode3 << 13);
}
__INLINE uint8_t gpio_intr_ctrl__mode_en3__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00001000) >> 12);
}
__INLINE void gpio_intr_ctrl__mode_en3__setf(uint32_t reg_idx, uint8_t modeen3)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modeen3 << 12) & ~0x00001000) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00001000) | (modeen3 << 12);
}
__INLINE uint8_t gpio_intr_ctrl__mode2__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00000E00) >> 9);
}
__INLINE void gpio_intr_ctrl__mode2__setf(uint32_t reg_idx, uint8_t mode2)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((mode2 << 9) & ~0x00000E00) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00000E00) | (mode2 << 9);
}
__INLINE uint8_t gpio_intr_ctrl__mode_en2__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00000100) >> 8);
}
__INLINE void gpio_intr_ctrl__mode_en2__setf(uint32_t reg_idx, uint8_t modeen2)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modeen2 << 8) & ~0x00000100) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00000100) | (modeen2 << 8);
}
__INLINE uint8_t gpio_intr_ctrl__mode1__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x000000E0) >> 5);
}
__INLINE void gpio_intr_ctrl__mode1__setf(uint32_t reg_idx, uint8_t mode1)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((mode1 << 5) & ~0x000000E0) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x000000E0) | (mode1 << 5);
}
__INLINE uint8_t gpio_intr_ctrl__mode_en1__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE void gpio_intr_ctrl__mode_en1__setf(uint32_t reg_idx, uint8_t modeen1)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modeen1 << 4) & ~0x00000010) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00000010) | (modeen1 << 4);
}
__INLINE uint8_t gpio_intr_ctrl__mode0__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x0000000E) >> 1);
}
__INLINE void gpio_intr_ctrl__mode0__setf(uint32_t reg_idx, uint8_t mode0)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((mode0 << 1) & ~0x0000000E) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x0000000E) | (mode0 << 1);
}
__INLINE uint8_t gpio_intr_ctrl__mode_en0__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 7);
uint32_t localVal = GPIO_INTR_CTRL_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void gpio_intr_ctrl__mode_en0__setf(uint32_t reg_idx, uint8_t modeen0)
{
ASSERT_ERR(reg_idx <= 7);
ASSERT_ERR(((modeen0 << 0) & ~0x00000001) == 0);
GPIO_INTR_CTRL_REG(reg_idx) = (GPIO_INTR_CTRL_REG(reg_idx) & ~0x00000001) | (modeen0 << 0);
}
/**
* @brief GPIO_DEBOUNCE register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 DEBEN_WE 0x0
* 15:00 DEBEN 0x0
* </pre>
*/
#define GPIO_DEBOUNCE_REG(i) (*(volatile uint32_t *)(0x40001180 + i*GPIO_REG_SIZE))
#define GPIO_DEBOUNCE_ADDR(i) (0x40001180 + i*GPIO_REG_SIZE)
#define GPIO_DEBOUNCE_OFFSET 0x00000180
__INLINE uint32_t gpio_debounce_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_DEBOUNCE_REG(reg_idx);
}
__INLINE void gpio_debounce_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_DEBOUNCE_REG(reg_idx) = value;
}
// field definitions
#define DEBEN_WE_MASK 0xFFFF0000
#define DEBEN_WE_LSB 16
#define DEBEN_WE_WIDTH 0x00000010
#define DEBEN_MASK 0x0000FFFF
#define DEBEN_LSB 0
#define DEBEN_WIDTH 0x00000010
#define DEBEN_WE_RST 0x0
#define DEBEN_RST 0x0
__INLINE void gpio_debounce_pack(uint32_t reg_idx, uint16_t debenwe, uint16_t deben)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((debenwe << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((deben << 0) & ~0x0000FFFF) == 0);
GPIO_DEBOUNCE_REG(reg_idx) = (debenwe << 16) | (deben << 0);
}
__INLINE void gpio_debounce_unpack(uint32_t reg_idx, uint16_t* debenwe, uint16_t* deben)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_DEBOUNCE_REG(reg_idx);
*debenwe = (localVal & 0xFFFF0000) >> 16;
*deben = (localVal & 0x0000FFFF) >> 0;
}
__INLINE void gpio_debounce__deben_we__setf(uint32_t reg_idx, uint16_t debenwe)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((debenwe << 16) & ~0xFFFF0000) == 0);
GPIO_DEBOUNCE_REG(reg_idx) = (GPIO_DEBOUNCE_REG(reg_idx) & ~0xFFFF0000) | (debenwe << 16);
}
__INLINE uint16_t gpio_debounce__deben__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_DEBOUNCE_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void gpio_debounce__deben__setf(uint32_t reg_idx, uint16_t deben)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((deben << 0) & ~0x0000FFFF) == 0);
GPIO_DEBOUNCE_REG(reg_idx) = (GPIO_DEBOUNCE_REG(reg_idx) & ~0x0000FFFF) | (deben << 0);
}
/**
* @brief GPIO_INTR_RAW register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 RAW 0x0
* </pre>
*/
#define GPIO_INTR_RAW_REG (*(volatile uint32_t *)(0x400011A0))
#define GPIO_INTR_RAW_ADDR 0x400011A0
#define GPIO_INTR_RAW_OFFSET 0x000001A0
__INLINE uint32_t gpio_intr_raw_get(void)
{
return GPIO_INTR_RAW_REG;
}
// field definitions
#define RAW_MASK 0xFFFFFFFF
#define RAW_LSB 0
#define RAW_WIDTH 0x00000020
#define RAW_RST 0x0
__INLINE uint32_t gpio_intr_raw__raw__getf(void)
{
uint32_t localVal = GPIO_INTR_RAW_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief GPIO_INTR_CLR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 CLR 0x0
* </pre>
*/
#define GPIO_INTR_CLR_REG(i) (*(volatile uint32_t *)(0x400011B0 + i*GPIO_REG_SIZE))
#define GPIO_INTR_CLR_ADDR(i) (0x400011B0 + i*GPIO_REG_SIZE)
#define GPIO_INTR_CLR_OFFSET 0x000001B0
__INLINE void gpio_intr_clr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_INTR_CLR_REG(reg_idx) = value;
}
// field definitions
#define CLR_MASK 0xFFFFFFFF
#define CLR_LSB 0
#define CLR_WIDTH 0x00000020
#define CLR_RST 0x0
__INLINE void gpio_intr_clr__clr__setf(uint32_t reg_idx, uint32_t clr)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((clr << 0) & ~0xFFFFFFFF) == 0);
GPIO_INTR_CLR_REG(reg_idx) = clr << 0;
}
/**
* @brief GPIO_INTR_MASK_C register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 MASK_WE 0x0
* 15:00 MASK 0x0
* </pre>
*/
#define GPIO_INTR_MASK_C_REG(i) (*(volatile uint32_t *)(0x40001200 + i*GPIO_REG_SIZE))
#define GPIO_INTR_MASK_C_ADDR(i) (0x40001200 + i*GPIO_REG_SIZE)
#define GPIO_INTR_MASK_C_OFFSET 0x00000200
__INLINE uint32_t gpio_intr_mask_c_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_INTR_MASK_C_REG(reg_idx);
}
__INLINE void gpio_intr_mask_c_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
GPIO_INTR_MASK_C_REG(reg_idx) = value;
}
// field definitions
#define MASK_WE_MASK 0xFFFF0000
#define MASK_WE_LSB 16
#define MASK_WE_WIDTH 0x00000010
#define MASK_MASK 0x0000FFFF
#define MASK_LSB 0
#define MASK_WIDTH 0x00000010
#define MASK_WE_RST 0x0
#define MASK_RST 0x0
__INLINE void gpio_intr_mask_c_pack(uint32_t reg_idx, uint16_t maskwe, uint16_t mask)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((maskwe << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((mask << 0) & ~0x0000FFFF) == 0);
GPIO_INTR_MASK_C_REG(reg_idx) = (maskwe << 16) | (mask << 0);
}
__INLINE void gpio_intr_mask_c_unpack(uint32_t reg_idx, uint16_t* maskwe, uint16_t* mask)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_INTR_MASK_C_REG(reg_idx);
*maskwe = (localVal & 0xFFFF0000) >> 16;
*mask = (localVal & 0x0000FFFF) >> 0;
}
__INLINE void gpio_intr_mask_c__mask_we__setf(uint32_t reg_idx, uint16_t maskwe)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((maskwe << 16) & ~0xFFFF0000) == 0);
GPIO_INTR_MASK_C_REG(reg_idx) = (GPIO_INTR_MASK_C_REG(reg_idx) & ~0xFFFF0000) | (maskwe << 16);
}
__INLINE uint16_t gpio_intr_mask_c__mask__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_INTR_MASK_C_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void gpio_intr_mask_c__mask__setf(uint32_t reg_idx, uint16_t mask)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((mask << 0) & ~0x0000FFFF) == 0);
GPIO_INTR_MASK_C_REG(reg_idx) = (GPIO_INTR_MASK_C_REG(reg_idx) & ~0x0000FFFF) | (mask << 0);
}
/**
* @brief GPIO_INTR_STATUS_C register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 STATUS 0x0
* </pre>
*/
#define GPIO_INTR_STATUS_C_REG(i) (*(volatile uint32_t *)(0x40001220 + i*GPIO_REG_SIZE))
#define GPIO_INTR_STATUS_C_ADDR(i) (0x40001220 + i*GPIO_REG_SIZE)
#define GPIO_INTR_STATUS_C_OFFSET 0x00000220
__INLINE uint32_t gpio_intr_status_c_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return GPIO_INTR_STATUS_C_REG(reg_idx);
}
// field definitions
#define STATUS_MASK 0xFFFFFFFF
#define STATUS_LSB 0
#define STATUS_WIDTH 0x00000020
#define STATUS_RST 0x0
__INLINE uint32_t gpio_intr_status_c__status__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = GPIO_INTR_STATUS_C_REG(reg_idx);
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_GPIO_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_i2c.h
+2000
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File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_offset.h
+67
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@@ -0,0 +1,67 @@
/*!
* \file xc_reg_offset.h
*
* \brief The header of xc registers offset index
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
#ifndef _XC_REG_OFFSET_H_
#define _XC_REG_OFFSET_H_
#define AOTIMER0_IDX 0U
#define AOTIMER1_IDX 1U
// #define AOTIMER_OFFSET {0x00, 0x14}
#define TIMER0_IDX 0U
#define TIMER1_IDX 1U
#define TIMER2_IDX 2U
#define TIMER3_IDX 3U
#define PWM0_IDX 0U
#define PWM1_IDX 1U
#define PWM2_IDX 2U
#define PWM3_IDX 3U
#define PWM4_IDX 4U
#define PWM5_IDX 5U
#define UART0_IDX (uint8_t)0U
#define UART1_IDX (uint8_t)1U
#define UART2_IDX (uint8_t)2U
#define PWM_TIMER0_IDX 0U
#define PWM_TIMER1_IDX 1U
#define PWM_TIMER2_IDX 2U
#define PWM_TIMER3_IDX 3U
#define PWM_TIMER4_IDX 4U
#define PWM_TIMER5_IDX 5U
#if (USE_XIP == 0)
#define SPI0_IDX 0U
#endif
#define SPI1_IDX 1U
#define SPI2_IDX 2U
const static unsigned char aotimer_offset[2] = {0x00, 0x14};
const static unsigned char timer_offset[4] = {0x00, 0x14, 0x28, 0x3C};
const static unsigned short pwm_offset[6] = {0x00, 0x40, 0x400, 0x440, 0x800, 0x840};
const static unsigned short uart_offset[3] ={0x00, 0x1000, 0x1400};
const static unsigned short spi_offset[3] ={0x00, 0x1000, 0x1800};
//#include "xc6xxx.h"
#endif // _XC_REG_OFFSET_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm.h
+675
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#ifndef _XC_REG_PWM_H_
#define _XC_REG_PWM_H_
#include <stdint.h>
#define XC_REG_PWM_BASE_ADDR 0x40017000
#define XC_REG_PWM_DECODING_MASK 0x0000003F
/**
* @brief PWM_EN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 06 pwm_en_all 0
* 05 sleep_en 0
* 04 sleep_incr 0
* 03 EN_SEL 0
* 02:01 MODE 0x0
* 00 EN 0
* </pre>
*/
#define PWM_EN_REG(i) (* ((volatile uint32_t *)(0x40017000 + pwm_offset[i])) )
#define PWM_EN_ADDR(i) (0x40017000 + pwm_offset[i])
#define PWM_EN_OFFSET 0x00000000
__INLINE uint32_t pwm_en_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_EN_REG(reg_idx);
}
__INLINE void pwm_en_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_EN_REG(reg_idx) = value;
}
// field definitions
#define PWM_EN_ALL_BIT 0x00000040
#define PWM_EN_ALL_POS 6
#define SLEEP_EN_BIT 0x00000020
#define SLEEP_EN_POS 5
#define SLEEP_INCR_BIT 0x00000010
#define SLEEP_INCR_POS 4
#define EN_SEL_BIT 0x00000008
#define EN_SEL_POS 3
#define MODE_MASK 0x00000006
#define MODE_LSB 1
#define MODE_WIDTH 0x00000002
#define EN_BIT 0x00000001
#define EN_POS 0
#define PWM_EN_ALL_RST 0x0
#define SLEEP_EN_RST 0x0
#define SLEEP_INCR_RST 0x0
#define EN_SEL_RST 0x0
#define MODE_RST 0x0
#define EN_RST 0x0
__INLINE void pwm_en_pack(uint32_t reg_idx, uint8_t pwm_en_all, uint8_t sleep_en, uint8_t sleep_incr, uint8_t en_sel, uint8_t mode, uint8_t en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_en_all << 6) & ~0x00000040) == 0);
ASSERT_ERR(((sleep_en << 5) & ~0x00000020) == 0);
ASSERT_ERR(((sleep_incr << 4) & ~0x00000010) == 0);
ASSERT_ERR(((en_sel << 3) & ~0x00000008) == 0);
ASSERT_ERR(((mode << 1) & ~0x00000006) == 0);
ASSERT_ERR(((en << 0) & ~0x00000001) == 0);
PWM_EN_REG(reg_idx) = (pwm_en_all << 6) | (sleep_en << 5) | (sleep_incr << 4) | (en_sel << 3) | (mode << 1) | (en << 0);
}
__INLINE void pwm_en_unpack(uint32_t reg_idx, uint8_t* pwm_en_all, uint8_t* sleep_en, uint8_t* sleep_incr, uint8_t* en_sel, uint8_t* mode, uint8_t* en)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
*pwm_en_all = (localVal & 0x00000040) >> 6;
*sleep_en = (localVal & 0x00000020) >> 5;
*sleep_incr = (localVal & 0x00000010) >> 4;
*en_sel = (localVal & 0x00000008) >> 3;
*mode = (localVal & 0x00000006) >> 1;
*en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_en__pwm_en_all__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000040) >> 6);
}
__INLINE void pwm_en__pwm_en_all__setf(uint32_t reg_idx, uint8_t pwm_en_all)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_en_all << 6) & ~0x00000040) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000040) | (pwm_en_all << 6);
}
__INLINE uint8_t pwm_en__sleep_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000020) >> 5);
}
__INLINE void pwm_en__sleep_en__setf(uint32_t reg_idx, uint8_t sleep_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((sleep_en << 5) & ~0x00000020) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000020) | (sleep_en << 5);
}
__INLINE uint8_t pwm_en__sleep_incr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE void pwm_en__sleep_incr__setf(uint32_t reg_idx, uint8_t sleep_incr)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((sleep_incr << 4) & ~0x00000010) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000010) | (sleep_incr << 4);
}
__INLINE uint8_t pwm_en__en_sel__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE void pwm_en__en_sel__setf(uint32_t reg_idx, uint8_t en_sel)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((en_sel << 3) & ~0x00000008) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000008) | (en_sel << 3);
}
__INLINE uint8_t pwm_en__mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000006) >> 1);
}
__INLINE void pwm_en__mode__setf(uint32_t reg_idx, uint8_t mode)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((mode << 1) & ~0x00000006) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000006) | (mode << 1);
}
__INLINE uint8_t pwm_en__en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_EN_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_en__en__setf(uint32_t reg_idx, uint8_t en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((en << 0) & ~0x00000001) == 0);
PWM_EN_REG(reg_idx) = (PWM_EN_REG(reg_idx) & ~0x00000001) | (en << 0);
}
/**
* @brief PWM_UP register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 UPDATE 0
* </pre>
*/
#define PWM_UP_REG(i) (* ((volatile uint32_t *)(0x40017004 + pwm_offset[i])) )
#define PWM_UP_ADDR(i) (0x40017004 + pwm_offset[i])
#define PWM_UP_OFFSET 0x00000004
__INLINE uint32_t pwm_up_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_UP_REG(reg_idx);
}
__INLINE void pwm_up_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_UP_REG(reg_idx) = value;
}
// field definitions
#define UPDATE_BIT 0x00000001
#define UPDATE_POS 0
#define UPDATE_RST 0x0
__INLINE uint8_t pwm_up__update__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_UP_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
__INLINE void pwm_up__update__setf(uint32_t reg_idx, uint8_t update)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((update << 0) & ~0x00000001) == 0);
PWM_UP_REG(reg_idx) = update << 0;
}
/**
* @brief PWM_RST register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 RESET 0
* </pre>
*/
#define PWM_RST_REG(i) (* ((volatile uint32_t *)(0x40017008 + pwm_offset[i])) )
#define PWM_RST_ADDR(i) (0x40017008 + pwm_offset[i])
#define PWM_RST_OFFSET 0x00000008
__INLINE uint32_t pwm_rst_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_RST_REG(reg_idx);
}
__INLINE void pwm_rst_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_RST_REG(reg_idx) = value;
}
// field definitions
#define RESET_BIT 0x00000001
#define RESET_POS 0
#define RESET_RST 0x0
__INLINE uint8_t pwm_rst__reset__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_RST_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
__INLINE void pwm_rst__reset__setf(uint32_t reg_idx, uint8_t reset)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((reset << 0) & ~0x00000001) == 0);
PWM_RST_REG(reg_idx) = reset << 0;
}
/**
* @brief PWM_PERIOD register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 PERIOD 0x0
* </pre>
*/
#define PWM_PERIOD_REG(i) (* ((volatile uint32_t *)(0x4001700C + pwm_offset[i])) )
#define PWM_PERIOD_ADDR(i) (0x4001700C + pwm_offset[i])
#define PWM_PERIOD_OFFSET 0x0000000C
__INLINE uint32_t pwm_period_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_PERIOD_REG(reg_idx);
}
__INLINE void pwm_period_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_PERIOD_REG(reg_idx) = value;
}
// field definitions
#define PERIOD_MASK 0x000000FF
#define PERIOD_LSB 0
#define PERIOD_WIDTH 0x00000008
#define PERIOD_RST 0x0
__INLINE uint8_t pwm_period__period__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_PERIOD_REG(reg_idx);
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_period__period__setf(uint32_t reg_idx, uint8_t period)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((period << 0) & ~0x000000FF) == 0);
PWM_PERIOD_REG(reg_idx) = period << 0;
}
/**
* @brief PWM_OCPY register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 OCPY_RATIO_CONFIG 0x0
* 15:00 OCPY_RATIO 0x0
* </pre>
*/
#define PWM_OCPY_REG(i) (* ((volatile uint32_t *)(0x40017010 + pwm_offset[i])) )
#define PWM_OCPY_ADDR(i) (0x40017010 + pwm_offset[i])
#define PWM_OCPY_OFFSET 0x00000010
__INLINE uint32_t pwm_ocpy_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_OCPY_REG(reg_idx);
}
__INLINE void pwm_ocpy_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_OCPY_REG(reg_idx) = value;
}
// field definitions
#define OCPY_RATIO_CONFIG_MASK 0xFFFF0000
#define OCPY_RATIO_CONFIG_LSB 16
#define OCPY_RATIO_CONFIG_WIDTH 0x00000010
#define OCPY_RATIO_MASK 0x0000FFFF
#define OCPY_RATIO_LSB 0
#define OCPY_RATIO_WIDTH 0x00000010
#define OCPY_RATIO_CONFIG_RST 0x0
#define OCPY_RATIO_RST 0x0
__INLINE void pwm_ocpy_pack(uint32_t reg_idx, uint16_t ocpy_ratio_config, uint16_t ocpy_ratio)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((ocpy_ratio_config << 16) & ~0xFFFF0000) == 0);
ASSERT_ERR(((ocpy_ratio << 0) & ~0x0000FFFF) == 0);
PWM_OCPY_REG(reg_idx) = (ocpy_ratio_config << 16) | (ocpy_ratio << 0);
}
__INLINE void pwm_ocpy_unpack(uint32_t reg_idx, uint16_t* ocpy_ratio_config, uint16_t* ocpy_ratio)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_OCPY_REG(reg_idx);
*ocpy_ratio_config = (localVal & 0xFFFF0000) >> 16;
*ocpy_ratio = (localVal & 0x0000FFFF) >> 0;
}
__INLINE uint16_t pwm_ocpy__ocpy_ratio_config__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_OCPY_REG(reg_idx);
return ((localVal & 0xFFFF0000) >> 16);
}
__INLINE void pwm_ocpy__ocpy_ratio_config__setf(uint32_t reg_idx, uint16_t ocpy_ratio_config)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((ocpy_ratio_config << 16) & ~0xFFFF0000) == 0);
PWM_OCPY_REG(reg_idx) = (PWM_OCPY_REG(reg_idx) & ~0xFFFF0000) | (ocpy_ratio_config << 16);
}
__INLINE uint16_t pwm_ocpy__ocpy_ratio__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_OCPY_REG(reg_idx);
return ((localVal & 0x0000FFFF) >> 0);
}
__INLINE void pwm_ocpy__ocpy_ratio__setf(uint32_t reg_idx, uint16_t ocpy_ratio)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((ocpy_ratio << 0) & ~0x0000FFFF) == 0);
PWM_OCPY_REG(reg_idx) = (PWM_OCPY_REG(reg_idx) & ~0x0000FFFF) | (ocpy_ratio << 0);
}
/**
* @brief PWM_COMPEN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 PWMCOMPEN 0
* </pre>
*/
#define PWM_COMPEN_REG(i) (* ((volatile uint32_t *)(0x40017014 + pwm_offset[i])) )
#define PWM_COMPEN_ADDR(i) (0x40017014 + pwm_offset[i])
#define PWM_COMPEN_OFFSET 0x00000014
__INLINE uint32_t pwm_compen_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_COMPEN_REG(reg_idx);
}
__INLINE void pwm_compen_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_COMPEN_REG(reg_idx) = value;
}
// field definitions
#define PWMCOMPEN_BIT 0x00000001
#define PWMCOMPEN_POS 0
#define PWMCOMPEN_RST 0x0
__INLINE uint8_t pwm_compen__pwmcompen__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_COMPEN_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
__INLINE void pwm_compen__pwmcompen__setf(uint32_t reg_idx, uint8_t pwmcompen)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwmcompen << 0) & ~0x00000001) == 0);
PWM_COMPEN_REG(reg_idx) = pwmcompen << 0;
}
/**
* @brief PWM_COMPTIME register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02:00 COMPTIME 0x0
* </pre>
*/
#define PWM_COMPTIME_REG(i) (* ((volatile uint32_t *)(0x40017018 + pwm_offset[i])) )
#define PWM_COMPTIME_ADDR(i) (0x40017018 + pwm_offset[i])
#define PWM_COMPTIME_OFFSET 0x00000018
__INLINE uint32_t pwm_comptime_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_COMPTIME_REG(reg_idx);
}
__INLINE void pwm_comptime_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_COMPTIME_REG(reg_idx) = value;
}
// field definitions
#define COMPTIME_MASK 0x00000007
#define COMPTIME_LSB 0
#define COMPTIME_WIDTH 0x00000003
#define COMPTIME_RST 0x0
__INLINE uint8_t pwm_comptime__comptime__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_COMPTIME_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
__INLINE void pwm_comptime__comptime__setf(uint32_t reg_idx, uint8_t comptime)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((comptime << 0) & ~0x0000003F) == 0);
PWM_COMPTIME_REG(reg_idx) = comptime << 0;
}
/**
* @brief PWM_BREAK_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 19:17 PWM_BRK_ENABLE 0x0
* 16 PWM_BRK_SYNC 0
* 14:12 PWM_BRK_MASK 0x0
* 11:09 PWM_BRK_INV 0x0
* 08 BRK_MODE 0
* 07 BRK_DBC_EN 0
* 06:01 BRK_DBC_STEP 0x0
* 00 CLEAR 0
* </pre>
*/
#define PWM_BREAK_CTL_REG(i) (* ((volatile uint32_t *)(0x40017020 + pwm_offset[i])) )
#define PWM_BREAK_CTL_ADDR(i) (0x40017020 + pwm_offset[i])
#define PWM_BREAK_CTL_OFFSET 0x00000020
__INLINE uint32_t pwm_break_ctl_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_BREAK_CTL_REG(reg_idx);
}
__INLINE void pwm_break_ctl_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_BREAK_CTL_REG(reg_idx) = value;
}
// field definitions
#define PWM_BRK_ENABLE_MASK 0x000E0000
#define PWM_BRK_ENABLE_LSB 17
#define PWM_BRK_ENABLE_WIDTH 0x00000003
#define PWM_BRK_SYNC_BIT 0x00010000
#define PWM_BRK_SYNC_POS 16
#define PWM_BRK_MASK_MASK 0x00007000
#define PWM_BRK_MASK_LSB 12
#define PWM_BRK_MASK_WIDTH 0x00000003
#define PWM_BRK_INV_MASK 0x00000E00
#define PWM_BRK_INV_LSB 9
#define PWM_BRK_INV_WIDTH 0x00000003
#define BRK_MODE_BIT 0x00000100
#define BRK_MODE_POS 8
#define BRK_DBC_EN_BIT 0x00000080
#define BRK_DBC_EN_POS 7
#define BRK_DBC_STEP_MASK 0x0000007E
#define BRK_DBC_STEP_LSB 1
#define BRK_DBC_STEP_WIDTH 0x00000006
#define BRK_CLEAR_BIT 0x00000001
#define BRK_CLEAR_POS 0
#define PWM_BRK_ENABLE_RST 0x0
#define PWM_BRK_SYNC_RST 0x0
#define PWM_BRK_MASK_RST 0x0
#define PWM_BRK_INV_RST 0x0
#define BRK_MODE_RST 0x0
#define BRK_DBC_EN_RST 0x0
#define BRK_DBC_STEP_RST 0x0
#define CLEAR_RST 0x0
__INLINE void pwm_break_ctl_pack(uint32_t reg_idx, uint8_t pwm_brk_enable, uint8_t pwm_brk_mask, uint8_t pwm_brk_inv, uint8_t brk_mode, uint8_t brk_dbc_en, uint8_t brk_dbc_step, uint8_t clear)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_brk_enable << 17) & ~0x000E0000) == 0);
ASSERT_ERR(((pwm_brk_mask << 12) & ~0x00007000) == 0);
ASSERT_ERR(((pwm_brk_inv << 9) & ~0x00000E00) == 0);
ASSERT_ERR(((brk_mode << 8) & ~0x00000100) == 0);
ASSERT_ERR(((brk_dbc_en << 7) & ~0x00000080) == 0);
ASSERT_ERR(((brk_dbc_step << 1) & ~0x0000007E) == 0);
ASSERT_ERR(((clear << 0) & ~0x00000001) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (pwm_brk_enable << 17) | (pwm_brk_mask << 12) | (pwm_brk_inv << 9) | (brk_mode << 8) | (brk_dbc_en << 7) | (brk_dbc_step << 1) | (clear << 0);
}
__INLINE void pwm_break_ctl_unpack(uint32_t reg_idx, uint8_t* pwm_brk_enable, uint8_t* pwm_brk_sync, uint8_t* pwm_brk_mask, uint8_t* pwm_brk_inv, uint8_t* brk_mode, uint8_t* brk_dbc_en, uint8_t* brk_dbc_step, uint8_t* clear)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
*pwm_brk_enable = (localVal & 0x000E0000) >> 17;
*pwm_brk_sync = (localVal & 0x00010000) >> 16;
*pwm_brk_mask = (localVal & 0x00007000) >> 12;
*pwm_brk_inv = (localVal & 0x00000E00) >> 9;
*brk_mode = (localVal & 0x00000100) >> 8;
*brk_dbc_en = (localVal & 0x00000080) >> 7;
*brk_dbc_step = (localVal & 0x0000007E) >> 1;
*clear = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_break_ctl__pwm_brk_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x000E0000) >> 17);
}
__INLINE void pwm_break_ctl__pwm_brk_enable__setf(uint32_t reg_idx, uint8_t pwm_brk_enable)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_brk_enable << 17) & ~0x000E0000) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x000E0000) | (pwm_brk_enable << 17);
}
__INLINE uint8_t pwm_break_ctl__pwm_brk_sync__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00010000) >> 16);
}
__INLINE uint8_t pwm_break_ctl__pwm_brk_mask__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00007000) >> 12);
}
__INLINE void pwm_break_ctl__pwm_brk_mask__setf(uint32_t reg_idx, uint8_t pwm_brk_mask)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_brk_mask << 12) & ~0x00007000) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00007000) | (pwm_brk_mask << 12);
}
__INLINE uint8_t pwm_break_ctl__pwm_brk_inv__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00000E00) >> 9);
}
__INLINE void pwm_break_ctl__pwm_brk_inv__setf(uint32_t reg_idx, uint8_t pwm_brk_inv)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((pwm_brk_inv << 9) & ~0x00000E00) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00000E00) | (pwm_brk_inv << 9);
}
__INLINE uint8_t pwm_break_ctl__brk_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00000100) >> 8);
}
__INLINE void pwm_break_ctl__brk_mode__setf(uint32_t reg_idx, uint8_t brk_mode)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((brk_mode << 8) & ~0x00000100) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00000100) | (brk_mode << 8);
}
__INLINE uint8_t pwm_break_ctl__brk_dbc_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00000080) >> 7);
}
__INLINE void pwm_break_ctl__brk_dbc_en__setf(uint32_t reg_idx, uint8_t brk_dbc_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((brk_dbc_en << 7) & ~0x00000080) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00000080) | (brk_dbc_en << 7);
}
__INLINE uint8_t pwm_break_ctl__brk_dbc_step__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x0000007E) >> 1);
}
__INLINE void pwm_break_ctl__brk_dbc_step__setf(uint32_t reg_idx, uint8_t brk_dbc_step)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((brk_dbc_step << 1) & ~0x0000007E) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x0000007E) | (brk_dbc_step << 1);
}
__INLINE uint8_t pwm_break_ctl__clear__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_BREAK_CTL_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_break_ctl__clear__setf(uint32_t reg_idx, uint8_t clear)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((clear << 0) & ~0x00000001) == 0);
PWM_BREAK_CTL_REG(reg_idx) = (PWM_BREAK_CTL_REG(reg_idx) & ~0x00000001) | (clear << 0);
}
#endif // _XC_REG_PWM_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm_comn.h
+487
View File
@@ -0,0 +1,487 @@
#ifndef _XC_REG_PWM_COMN_H_
#define _XC_REG_PWM_COMN_H_
#include <stdint.h>
#define XC_REG_PWM_COMN_BASE_ADDR 0x40017C00
#define XC_REG_PWM_COMN_DECODING_MASK 0x0000003F
#define PWM_COMMON_REG_SIZE 0x04
/**
* @brief CAP_TIM_VAL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 CAPTURE_VALUE 0x0
* </pre>
*/
#define CAP_TIM_VAL_REG(i) (* ((volatile uint32_t *)(0x40017C00 + i*PWM_COMMON_REG_SIZE)) )
#define CAP_TIM_VAL_ADDR(i) (0x40017C00 + i*PWM_COMMON_REG_SIZE)
#define CAP_TIM_VAL_OFFSET 0x00000000
__INLINE uint32_t cap_tim_val_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return CAP_TIM_VAL_REG(reg_idx);
}
// field definitions
#define CAPTURE_VALUE_MASK 0x0000FFFF
#define CAPTURE_VALUE_LSB 0
#define CAPTURE_VALUE_WIDTH 0x00000010
#define CAPTURE_VALUE_RST 0x0
__INLINE uint16_t cap_tim_val__capture_value__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_VAL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_CAP_TIM_INT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 CAPTURE_UPD2 0
* 01 CAPTURE_UPD1 0
* 00 CAPTURE_UPD0 0
* </pre>
*/
#define PWM_CAP_TIM_INT_REG (*(volatile uint32_t *)(0x40017C0C))
#define PWM_CAP_TIM_INT_ADDR 0x40017C0C
#define PWM_CAP_TIM_INT_OFFSET 0x0000000C
__INLINE uint32_t pwm_cap_tim_int_get(void)
{
return PWM_CAP_TIM_INT_REG;
}
__INLINE void pwm_cap_tim_int_set(uint32_t value)
{
PWM_CAP_TIM_INT_REG = value;
}
// field definitions
#define CAPTURE_UPD2_BIT 0x00000004
#define CAPTURE_UPD2_POS 2
#define CAPTURE_UPD1_BIT 0x00000002
#define CAPTURE_UPD1_POS 1
#define CAPTURE_UPD0_BIT 0x00000001
#define CAPTURE_UPD0_POS 0
#define CAPTURE_UPD2_RST 0x0
#define CAPTURE_UPD1_RST 0x0
#define CAPTURE_UPD0_RST 0x0
__INLINE void pwm_cap_tim_int_pack(uint8_t capture_upd2, uint8_t capture_upd1, uint8_t capture_upd0)
{
ASSERT_ERR(((capture_upd2 << 2) & ~0x00000004) == 0);
ASSERT_ERR(((capture_upd1 << 1) & ~0x00000002) == 0);
ASSERT_ERR(((capture_upd0 << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_REG = (capture_upd2 << 2) | (capture_upd1 << 1) | (capture_upd0 << 0);
}
__INLINE void pwm_cap_tim_int_unpack(uint8_t* capture_upd2, uint8_t* capture_upd1, uint8_t* capture_upd0)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
*capture_upd2 = (localVal & 0x00000004) >> 2;
*capture_upd1 = (localVal & 0x00000002) >> 1;
*capture_upd0 = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd2__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_cap_tim_int__capture_upd2__setf(uint8_t capture_upd2)
{
ASSERT_ERR(((capture_upd2 << 2) & ~0x00000004) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000004) | (capture_upd2 << 2);
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd1__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_cap_tim_int__capture_upd1__setf(uint8_t capture_upd1)
{
ASSERT_ERR(((capture_upd1 << 1) & ~0x00000002) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000002) | (capture_upd1 << 1);
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd0__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_cap_tim_int__capture_upd0__setf(uint8_t capture_upd0)
{
ASSERT_ERR(((capture_upd0 << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000001) | (capture_upd0 << 0);
}
/**
* @brief PWM_CAP_TIM_INT_EN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 capture_upd2_en 0
* 01 capture_upd1_en 0
* 00 capture_upd0_en 0
* </pre>
*/
#define PWM_CAP_TIM_INT_EN_REG (*(volatile uint32_t *)(0x40017C10))
#define PWM_CAP_TIM_INT_EN_ADDR 0x40017C10
#define PWM_CAP_TIM_INT_EN_OFFSET 0x00000010
__INLINE uint32_t pwm_cap_tim_int_en_get(void)
{
return PWM_CAP_TIM_INT_EN_REG;
}
__INLINE void pwm_cap_tim_int_en_set(uint32_t value)
{
PWM_CAP_TIM_INT_EN_REG = value;
}
// field definitions
#define CAPTURE_UPD_2_EN_BIT 0x00000004
#define CAPTURE_UPD_2_EN_POS 2
#define CAPTURE_UPD_1_EN_BIT 0x00000002
#define CAPTURE_UPD_1_EN_POS 1
#define CAPTURE_UPD_0_EN_BIT 0x00000001
#define CAPTURE_UPD_0_EN_POS 0
#define CAPTURE_UPD_2_EN_RST 0x0
#define CAPTURE_UPD_1_EN_RST 0x0
#define CAPTURE_UPD_0_EN_RST 0x0
__INLINE void pwm_cap_tim_int_en_pack(uint8_t capture_upd2_en, uint8_t capture_upd1_en, uint8_t capture_upd0_en)
{
ASSERT_ERR(((capture_upd2_en << 2) & ~0x00000004) == 0);
ASSERT_ERR(((capture_upd1_en << 1) & ~0x00000002) == 0);
ASSERT_ERR(((capture_upd0_en << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_EN_REG = (capture_upd2_en << 2) | (capture_upd1_en << 1) | (capture_upd0_en << 0);
}
__INLINE void pwm_cap_tim_int_en_unpack(uint8_t* capture_upd2_en, uint8_t* capture_upd1_en, uint8_t* capture_upd0_en)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
*capture_upd2_en = (localVal & 0x00000004) >> 2;
*capture_upd1_en = (localVal & 0x00000002) >> 1;
*capture_upd0_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_2_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_2_en__setf(uint8_t capture_upd2_en)
{
ASSERT_ERR(((capture_upd2_en << 2) & ~0x00000004) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000004) | (capture_upd2_en << 2);
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_1_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_1_en__setf(uint8_t capture_upd1_en)
{
ASSERT_ERR(((capture_upd1_en << 1) & ~0x00000002) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000002) | (capture_upd1_en << 1);
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_0_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_0_en__setf(uint8_t capture_upd0_en)
{
ASSERT_ERR(((capture_upd0_en << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000001) | (capture_upd0_en << 0);
}
/**
* @brief PWM_CAP_TIM_INT_RAW register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 capture_upd2_raw 0
* 01 capture_upd1_raw 0
* 00 capture_upd0_raw 0
* </pre>
*/
#define PWM_CAP_TIM_INT_RAW_REG (*(volatile uint32_t *)(0x40017C14))
#define PWM_CAP_TIM_INT_RAW_ADDR 0x40017C14
#define PWM_CAP_TIM_INT_RAW_OFFSET 0x00000014
__INLINE uint32_t pwm_cap_tim_int_raw_get(void)
{
return PWM_CAP_TIM_INT_RAW_REG;
}
// field definitions
#define CAPTURE_UPD_2_RAW_BIT 0x00000004
#define CAPTURE_UPD_2_RAW_POS 2
#define CAPTURE_UPD_1_RAW_BIT 0x00000002
#define CAPTURE_UPD_1_RAW_POS 1
#define CAPTURE_UPD_0_RAW_BIT 0x00000001
#define CAPTURE_UPD_0_RAW_POS 0
#define CAPTURE_UPD_2_RAW_RST 0x0
#define CAPTURE_UPD_1_RAW_RST 0x0
#define CAPTURE_UPD_0_RAW_RST 0x0
__INLINE void pwm_cap_tim_int_raw_unpack(uint8_t* capture_upd2_raw, uint8_t* capture_upd1_raw, uint8_t* capture_upd0_raw)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
*capture_upd2_raw = (localVal & 0x00000004) >> 2;
*capture_upd1_raw = (localVal & 0x00000002) >> 1;
*capture_upd0_raw = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_2_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_1_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_0_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief CAP_TIM_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:19 CLK_DIV_VAL 0x0
* 18:16 CAPTURE_SIG_SEL 0x0
* 14 DBC_EN 0
* 13:08 DBC_STEP 0x0
* 05:04 CAPTURE_MODE 0x0
* 03:02 CAPTURE_PSC 0x0
* 01 capture_enable 0
* 00 COMMON_CNT_ENABLE 0
* </pre>
*/
#define CAP_TIM_CTL_REG(i) (* ((volatile uint32_t *)(0x40017C18 + i*PWM_COMMON_REG_SIZE)) )
#define CAP_TIM_CTL_ADDR(i) (0x40017C18 + i*PWM_COMMON_REG_SIZE)
#define CAP_TIM_CTL_OFFSET 0x00000018
__INLINE uint32_t cap_tim_ctl_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return CAP_TIM_CTL_REG(reg_idx);
}
__INLINE void cap_tim_ctl_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
CAP_TIM_CTL_REG(reg_idx) = value;
}
// field definitions
#define CLK_DIV_VAL_MASK 0x00F80000
#define CLK_DIV_VAL_LSB 19
#define CLK_DIV_VAL_WIDTH 0x00000005
#define CAPTURE_SIG_SEL_MASK 0x00070000
#define CAPTURE_SIG_SEL_LSB 16
#define CAPTURE_SIG_SEL_WIDTH 0x00000003
#define DBC_EN_BIT 0x00004000
#define DBC_EN_POS 14
#define DBC_STEP_MASK 0x00003F00
#define DBC_STEP_LSB 8
#define DBC_STEP_WIDTH 0x00000006
#define CAPTURE_MODE_MASK 0x00000030
#define CAPTURE_MODE_LSB 4
#define CAPTURE_MODE_WIDTH 0x00000002
#define CAPTURE_PSC_MASK 0x0000000C
#define CAPTURE_PSC_LSB 2
#define CAPTURE_PSC_WIDTH 0x00000002
#define CAPTURE_ENABLE_BIT 0x00000002
#define CAPTURE_ENABLE_POS 1
#define COMMON_CNT_ENABLE_BIT 0x00000001
#define COMMON_CNT_ENABLE_POS 0
#define CLK_DIV_VAL_RST 0x0
#define CAPTURE_SIG_SEL_RST 0x0
#define DBC_EN_RST 0x0
#define DBC_STEP_RST 0x0
#define CAPTURE_MODE_RST 0x0
#define CAPTURE_PSC_RST 0x0
#define CAPTURE_ENABLE_RST 0x0
#define COMMON_CNT_ENABLE_RST 0x0
__INLINE void cap_tim_ctl_pack(uint32_t reg_idx, uint8_t clk_div_val, uint8_t capture_sig_sel, uint8_t dbc_en, uint8_t dbc_step, uint8_t capture_mode, uint8_t capture_psc, uint8_t capture_enable, uint8_t common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((clk_div_val << 19) & ~0x00F80000) == 0);
ASSERT_ERR(((capture_sig_sel << 16) & ~0x00070000) == 0);
ASSERT_ERR(((dbc_en << 14) & ~0x00004000) == 0);
ASSERT_ERR(((dbc_step << 8) & ~0x00003F00) == 0);
ASSERT_ERR(((capture_mode << 4) & ~0x00000030) == 0);
ASSERT_ERR(((capture_psc << 2) & ~0x0000000C) == 0);
ASSERT_ERR(((capture_enable << 1) & ~0x00000002) == 0);
ASSERT_ERR(((common_cnt_enable << 0) & ~0x00000001) == 0);
CAP_TIM_CTL_REG(reg_idx) = (clk_div_val << 19) | (capture_sig_sel << 16) | (dbc_en << 14) | (dbc_step << 8) | (capture_mode << 4) | (capture_psc << 2) | (capture_enable << 1) | (common_cnt_enable << 0);
}
__INLINE void cap_tim_ctl_unpack(uint32_t reg_idx, uint8_t* clk_div_val, uint8_t* capture_sig_sel, uint8_t* dbc_en, uint8_t* dbc_step, uint8_t* capture_mode, uint8_t* capture_psc, uint8_t* capture_enable, uint8_t* common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
*clk_div_val = (localVal & 0x00F80000) >> 19;
*capture_sig_sel = (localVal & 0x00070000) >> 16;
*dbc_en = (localVal & 0x00004000) >> 14;
*dbc_step = (localVal & 0x00003F00) >> 8;
*capture_mode = (localVal & 0x00000030) >> 4;
*capture_psc = (localVal & 0x0000000C) >> 2;
*capture_enable = (localVal & 0x00000002) >> 1;
*common_cnt_enable = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t cap_tim_ctl__clk_div_val__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00F80000) >> 19);
}
__INLINE void cap_tim_ctl__clk_div_val__setf(uint32_t reg_idx, uint8_t clk_div_val)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((clk_div_val << 19) & ~0x00F80000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00F80000) | (clk_div_val << 19);
}
__INLINE uint8_t cap_tim_ctl__capture_sig_sel__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00070000) >> 16);
}
__INLINE void cap_tim_ctl__capture_sig_sel__setf(uint32_t reg_idx, uint8_t capture_sig_sel)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_sig_sel << 16) & ~0x00070000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00070000) | (capture_sig_sel << 16);
}
__INLINE uint8_t cap_tim_ctl__dbc_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00004000) >> 14);
}
__INLINE void cap_tim_ctl__dbc_en__setf(uint32_t reg_idx, uint8_t dbc_en)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dbc_en << 14) & ~0x00004000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00004000) | (dbc_en << 14);
}
__INLINE uint8_t cap_tim_ctl__dbc_step__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00003F00) >> 8);
}
__INLINE void cap_tim_ctl__dbc_step__setf(uint32_t reg_idx, uint8_t dbc_step)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dbc_step << 8) & ~0x00003F00) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00003F00) | (dbc_step << 8);
}
__INLINE uint8_t cap_tim_ctl__capture_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000030) >> 4);
}
__INLINE void cap_tim_ctl__capture_mode__setf(uint32_t reg_idx, uint8_t capture_mode)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_mode << 4) & ~0x00000030) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000030) | (capture_mode << 4);
}
__INLINE uint8_t cap_tim_ctl__capture_psc__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x0000000C) >> 2);
}
__INLINE void cap_tim_ctl__capture_psc__setf(uint32_t reg_idx, uint8_t capture_psc)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_psc << 2) & ~0x0000000C) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x0000000C) | (capture_psc << 2);
}
__INLINE uint8_t cap_tim_ctl__capture_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void cap_tim_ctl__capture_enable__setf(uint32_t reg_idx, uint8_t capture_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_enable << 1) & ~0x00000002) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000002) | (capture_enable << 1);
}
__INLINE uint8_t cap_tim_ctl__common_cnt_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void cap_tim_ctl__common_cnt_enable__setf(uint32_t reg_idx, uint8_t common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((common_cnt_enable << 0) & ~0x00000001) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000001) | (common_cnt_enable << 0);
}
#endif // _XC_REG_PWM_COMN_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm_timer.h
+453
View File
@@ -0,0 +1,453 @@
#ifndef _XC_REG_PWM_TIMER_H_
#define _XC_REG_PWM_TIMER_H_
#include <stdint.h>
#include "xc_reg_offset.h"
#define XC_REG_PWM_TIMER_BASE_ADDR 0x40017D00
#define XC_REG_PWM_TIMER_DECODING_MASK 0x000000FF
#define PWM_TIMER_REG_SIZE 0x14
#define PWM_LOAD_CNT2_REG_SIZE 0x04
/**
* @brief PWM_TIMER_LOADCOUNT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 TIMER_LC 0x0
* </pre>
*/
#define PWM_TIMER_LOADCOUNT_REG(i) (* ((volatile uint32_t *)(0x40017D00 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_LOADCOUNT_ADDR(i) (0x40017D00 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_LOADCOUNT_OFFSET 0x00000000
__INLINE uint32_t pwm_timer_loadcount_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_LOADCOUNT_REG(reg_idx);
}
__INLINE void pwm_timer_loadcount_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_LOADCOUNT_REG(reg_idx) = value;
}
// field definitions
#define TIMER_LC_MASK 0x0000FFFF
#define TIMER_LC_LSB 0
#define TIMER_LC_WIDTH 0x00000010
#define TIMER_LC_RST 0x0
__INLINE uint16_t pwm_timer_loadcount__timer_lc__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_LOADCOUNT_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_timer_loadcount__timer_lc__setf(uint32_t reg_idx, uint16_t timer_lc)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_lc << 0) & ~0x0000FFFF) == 0);
PWM_TIMER_LOADCOUNT_REG(reg_idx) = timer_lc << 0;
}
/**
* @brief PWM_TIMER_CURRENTVAL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 TIMER_CV 0x0
* </pre>
*/
#define PWM_TIMER_CURRENTVAL_REG(i) (* ((volatile uint32_t *)(0x40017D04 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_CURRENTVAL_ADDR(i) (0x40017D04 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_CURRENTVAL_OFFSET 0x00000004
__INLINE uint32_t pwm_timer_currentval_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_CURRENTVAL_REG(reg_idx);
}
// field definitions
#define TIMER_CV_MASK 0x0000FFFF
#define TIMER_CV_LSB 0
#define TIMER_CV_WIDTH 0x00000010
#define TIMER_CV_RST 0x0
__INLINE uint16_t pwm_timer_currentval__timer_cv__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CURRENTVAL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_CONTROLREG register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 TIMER_ON10OPWM_EN 0
* 03 TIMER_PWM 0
* 02 TIMER_INT_MASK 0
* 01 TIMER_MODE 0
* 00 TIMER_EN 0
* </pre>
*/
#define PWM_TIMER_CONTROLREG_REG(i) (* ((volatile uint32_t *)(0x40017D08 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_CONTROLREG_ADDR(i) (0x40017D08 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_CONTROLREG_OFFSET 0x00000008
__INLINE uint32_t pwm_timer_controlreg_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_CONTROLREG_REG(reg_idx);
}
__INLINE void pwm_timer_controlreg_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_CONTROLREG_REG(reg_idx) = value;
}
// field definitions
#define TIMER_ON10OPWM_EN_BIT 0x00000010
#define TIMER_ON10OPWM_EN_POS 4
#define TIMER_PWM_BIT 0x00000008
#define TIMER_PWM_POS 3
#define TIMER_INT_MASK_BIT 0x00000004
#define TIMER_INT_MASK_POS 2
#define TIMER_MODE_BIT 0x00000002
#define TIMER_MODE_POS 1
#define TIMER_EN_BIT 0x00000001
#define TIMER_EN_POS 0
#define TIMER_ON10OPWM_EN_RST 0x0
#define TIMER_PWM_RST 0x0
#define TIMER_INT_MASK_RST 0x0
#define TIMER_MODE_RST 0x0
#define TIMER_EN_RST 0x0
__INLINE void pwm_timer_controlreg_pack(uint32_t reg_idx, uint8_t timer_int_mask, uint8_t timer_mode, uint8_t timer_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_int_mask << 2) & ~0x00000004) == 0);
ASSERT_ERR(((timer_mode << 1) & ~0x00000002) == 0);
ASSERT_ERR(((timer_en << 0) & ~0x00000001) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (timer_int_mask << 2) | (timer_mode << 1) | (timer_en << 0);
}
__INLINE void pwm_timer_controlreg_unpack(uint32_t reg_idx, uint8_t* timer_on10opwm_en, uint8_t* timer_pwm, uint8_t* timer_int_mask, uint8_t* timer_mode, uint8_t* timer_en)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
*timer_on10opwm_en = (localVal & 0x00000010) >> 4;
*timer_pwm = (localVal & 0x00000008) >> 3;
*timer_int_mask = (localVal & 0x00000004) >> 2;
*timer_mode = (localVal & 0x00000002) >> 1;
*timer_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_timer_controlreg__timer_on10opwm_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t pwm_timer_controlreg__timer_pwm__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE uint8_t pwm_timer_controlreg__timer_int_mask__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_timer_controlreg__timer_int_mask__setf(uint32_t reg_idx, uint8_t timer_int_mask)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_int_mask << 2) & ~0x00000004) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000004) | (timer_int_mask << 2);
}
__INLINE uint8_t pwm_timer_controlreg__timer_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_timer_controlreg__timer_mode__setf(uint32_t reg_idx, uint8_t timer_mode)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_mode << 1) & ~0x00000002) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000002) | (timer_mode << 1);
}
__INLINE uint8_t pwm_timer_controlreg__timer_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_timer_controlreg__timer_en__setf(uint32_t reg_idx, uint8_t timer_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_en << 0) & ~0x00000001) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000001) | (timer_en << 0);
}
/**
* @brief PWM_TIMER_EOI register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 Timer_EOI 0
* </pre>
*/
#define PWM_TIMER_EOI_REG(i) (* ((volatile uint32_t *)(0x40017D0C + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_EOI_ADDR(i) (0x40017D0C + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_EOI_OFFSET 0x0000000C
__INLINE uint32_t pwm_timer_eoi_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_EOI_REG(reg_idx);
}
// field definitions
#define TIMER_EOI_BIT 0x00000001
#define TIMER_EOI_POS 0
#define TIMER_EOI_RST 0x0
__INLINE uint8_t pwm_timer_eoi__timer_eoi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_EOI_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_INTSTAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 Timer_IS 0
* </pre>
*/
#define PWM_TIMER_INTSTAT_REG(i) (* ((volatile uint32_t *)(0x40017D10 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_INTSTAT_ADDR(i) (0x40017D10 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_INTSTAT_OFFSET 0x00000010
__INLINE uint32_t pwm_timer_intstat_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_INTSTAT_REG(reg_idx);
}
// field definitions
#define TIMER_IS_BIT 0x00000001
#define TIMER_IS_POS 0
#define TIMER_IS_RST 0x0
__INLINE uint8_t pwm_timer_intstat__timer_is__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_INTSTAT_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 Timers_IS 0x0
* </pre>
*/
#define PWM_TIMER_A_TIS_REG (*(volatile uint32_t *)(0x40017DA0))
#define PWM_TIMER_A_TIS_ADDR 0x40017DA0
#define PWM_TIMER_A_TIS_OFFSET 0x000000A0
__INLINE uint32_t pwm_timer_a_tis_get(void)
{
return PWM_TIMER_A_TIS_REG;
}
// field definitions
#define TIMERS_IS_MASK 0x0000003F
#define TIMERS_IS_LSB 0
#define TIMERS_IS_WIDTH 0x00000006
#define TIMERS_IS_RST 0x0
__INLINE uint8_t pwm_timer_a_tis__timers_is__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TIS_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TEOI register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 TIMERS_EOI 0x0
* </pre>
*/
#define PWM_TIMER_A_TEOI_REG (*(volatile uint32_t *)(0x40017DA4))
#define PWM_TIMER_A_TEOI_ADDR 0x40017DA4
#define PWM_TIMER_A_TEOI_OFFSET 0x000000A4
__INLINE uint32_t pwm_timer_a_teoi_get(void)
{
return PWM_TIMER_A_TEOI_REG;
}
// field definitions
#define TIMERS_EOI_MASK 0x0000003F
#define TIMERS_EOI_LSB 0
#define TIMERS_EOI_WIDTH 0x00000006
#define TIMERS_EOI_RST 0x0
__INLINE uint8_t pwm_timer_a_teoi__timers_eoi__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TEOI_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TRIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 TIMERS_RIS 0x0
* </pre>
*/
#define PWM_TIMER_A_TRIS_REG (*(volatile uint32_t *)(0x40017DA8))
#define PWM_TIMER_A_TRIS_ADDR 0x40017DA8
#define PWM_TIMER_A_TRIS_OFFSET 0x000000A8
__INLINE uint32_t pwm_timer_a_tris_get(void)
{
return PWM_TIMER_A_TRIS_REG;
}
// field definitions
#define TIMERS_RIS_MASK 0x0000003F
#define TIMERS_RIS_LSB 0
#define TIMERS_RIS_WIDTH 0x00000006
#define TIMERS_RIS_RST 0x0
__INLINE uint8_t pwm_timer_a_tris__timers_ris__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TRIS_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_TCOMP register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 TIMERS_COMP 0x0
* </pre>
*/
#define PWM_TIMER_TCOMP_REG (*(volatile uint32_t *)(0x40017DAC))
#define PWM_TIMER_TCOMP_ADDR 0x40017DAC
#define PWM_TIMER_TCOMP_OFFSET 0x000000AC
__INLINE uint32_t pwm_timer_tcomp_get(void)
{
return PWM_TIMER_TCOMP_REG;
}
// field definitions
#define TIMERS_COMP_MASK 0xFFFFFFFF
#define TIMERS_COMP_LSB 0
#define TIMERS_COMP_WIDTH 0x00000020
#define TIMERS_COMP_RST 0x0
__INLINE uint32_t pwm_timer_tcomp__timers_comp__getf(void)
{
uint32_t localVal = PWM_TIMER_TCOMP_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_LOADCOUNT2 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 11:00 TIMER_LC2 0x0
* </pre>
*/
#define PWM_TIMER_LOADCOUNT2_REG(i) (* ((volatile uint32_t *)(0x40017DB0 + i*PWM_LOAD_CNT2_REG_SIZE)) )
#define PWM_TIMER_LOADCOUNT2_ADDR(i) (0x40017DB0 + i*PWM_LOAD_CNT2_REG_SIZE)
#define PWM_TIMER_LOADCOUNT2_OFFSET 0x000000B0
__INLINE uint32_t pwm_timer_loadcount2_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_LOADCOUNT2_REG(reg_idx);
}
__INLINE void pwm_timer_loadcount2_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_LOADCOUNT2_REG(reg_idx) = value;
}
// field definitions
#define TIMER_LC2_MASK 0x00000FFF
#define TIMER_LC2_LSB 0
#define TIMER_LC2_WIDTH 0x0000000C
#define TIMER_LC2_RST 0x0
__INLINE uint16_t pwm_timer_loadcount2__timer_lc2__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_LOADCOUNT2_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000FFF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_timer_loadcount2__timer_lc2__setf(uint32_t reg_idx, uint16_t timer_lc2)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_lc2 << 0) & ~0x00000FFF) == 0);
PWM_TIMER_LOADCOUNT2_REG(reg_idx) = timer_lc2 << 0;
}
#endif // _XC_REG_PWM_TIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_qdec.h
+665
View File
@@ -0,0 +1,665 @@
#ifndef _XC_REG_QDEC_H_
#define _XC_REG_QDEC_H_
#include <stdint.h>
#include "xc_reg_offset.h"
#define XC_REG_QDEC_BASE_ADDR 0x40016000
#define XC_REG_QDEC_DECODING_MASK 0x0000003F
/**
* @brief QDEC_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 06 DB_FILTER_EN 0
* 05 SINGLE_SAMPLE_RST_EN 0
* 04 AUTO_CLR_EN 0
* 03 SOFT_CLR 0
* 02 SOFT_RST 0
* 01 QDEC_START 0
* 00 QDEC_EN 0
* </pre>
*/
#define QDEC_CTL_REG (*(volatile uint32_t *)(0x40016000))
#define QDEC_CTL_ADDR 0x40016000
#define QDEC_CTL_OFFSET 0x00000000
__INLINE uint32_t qdec_ctl_get(void)
{
return QDEC_CTL_REG;
}
__INLINE void qdec_ctl_set(uint32_t value)
{
QDEC_CTL_REG = value;
}
// field definitions
#define DB_FILTER_EN_BIT 0x00000040
#define DB_FILTER_EN_POS 6
#define SINGLE_SAMPLE_RST_EN_BIT 0x00000020
#define SINGLE_SAMPLE_RST_EN_POS 5
#define AUTO_CLR_EN_BIT 0x00000010
#define AUTO_CLR_EN_POS 4
#define SOFT_CLR_BIT 0x00000008
#define SOFT_CLR_POS 3
#define SOFT_RST_BIT 0x00000004
#define SOFT_RST_POS 2
#define QDEC_START_BIT 0x00000002
#define QDEC_START_POS 1
#define QDEC_EN_BIT 0x00000001
#define QDEC_EN_POS 0
#define DB_FILTER_EN_RST 0x0
#define SINGLE_SAMPLE_RST_EN_RST 0x0
#define AUTO_CLR_EN_RST 0x0
#define SOFT_CLR_RST 0x0
#define SOFT_RST_RST 0x0
#define QDEC_START_RST 0x0
#define QDEC_EN_RST 0x0
__INLINE void qdec_ctl_pack(uint8_t db_filter_en, uint8_t single_sample_rst_en, uint8_t auto_clr_en, uint8_t soft_clr, uint8_t soft_rst, uint8_t qdec_start, uint8_t qdec_en)
{
ASSERT_ERR(((db_filter_en << 6) & ~0x00000040) == 0);
ASSERT_ERR(((single_sample_rst_en << 5) & ~0x00000020) == 0);
ASSERT_ERR(((auto_clr_en << 4) & ~0x00000010) == 0);
ASSERT_ERR(((soft_clr << 3) & ~0x00000008) == 0);
ASSERT_ERR(((soft_rst << 2) & ~0x00000004) == 0);
ASSERT_ERR(((qdec_start << 1) & ~0x00000002) == 0);
ASSERT_ERR(((qdec_en << 0) & ~0x00000001) == 0);
QDEC_CTL_REG = (db_filter_en << 6) | (single_sample_rst_en << 5) | (auto_clr_en << 4) | (soft_clr << 3) | (soft_rst << 2) | (qdec_start << 1) | (qdec_en << 0);
}
__INLINE void qdec_ctl_unpack(uint8_t* db_filter_en, uint8_t* single_sample_rst_en, uint8_t* auto_clr_en, uint8_t* soft_clr, uint8_t* soft_rst, uint8_t* qdec_start, uint8_t* qdec_en)
{
uint32_t localVal = QDEC_CTL_REG;
*db_filter_en = (localVal & 0x00000040) >> 6;
*single_sample_rst_en = (localVal & 0x00000020) >> 5;
*auto_clr_en = (localVal & 0x00000010) >> 4;
*soft_clr = (localVal & 0x00000008) >> 3;
*soft_rst = (localVal & 0x00000004) >> 2;
*qdec_start = (localVal & 0x00000002) >> 1;
*qdec_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t qdec_ctl__db_filter_en__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000040) >> 6);
}
__INLINE void qdec_ctl__db_filter_en__setf(uint8_t db_filter_en)
{
ASSERT_ERR(((db_filter_en << 6) & ~0x00000040) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000040) | (db_filter_en << 6);
}
__INLINE uint8_t qdec_ctl__single_sample_rst_en__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000020) >> 5);
}
__INLINE void qdec_ctl__single_sample_rst_en__setf(uint8_t single_sample_rst_en)
{
ASSERT_ERR(((single_sample_rst_en << 5) & ~0x00000020) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000020) | (single_sample_rst_en << 5);
}
__INLINE uint8_t qdec_ctl__auto_clr_en__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE void qdec_ctl__auto_clr_en__setf(uint8_t auto_clr_en)
{
ASSERT_ERR(((auto_clr_en << 4) & ~0x00000010) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000010) | (auto_clr_en << 4);
}
__INLINE uint8_t qdec_ctl__soft_clr__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void qdec_ctl__soft_clr__setf(uint8_t soft_clr)
{
ASSERT_ERR(((soft_clr << 3) & ~0x00000008) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000008) | (soft_clr << 3);
}
__INLINE uint8_t qdec_ctl__soft_rst__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void qdec_ctl__soft_rst__setf(uint8_t soft_rst)
{
ASSERT_ERR(((soft_rst << 2) & ~0x00000004) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000004) | (soft_rst << 2);
}
__INLINE uint8_t qdec_ctl__qdec_start__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void qdec_ctl__qdec_start__setf(uint8_t qdec_start)
{
ASSERT_ERR(((qdec_start << 1) & ~0x00000002) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000002) | (qdec_start << 1);
}
__INLINE uint8_t qdec_ctl__qdec_en__getf(void)
{
uint32_t localVal = QDEC_CTL_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void qdec_ctl__qdec_en__setf(uint8_t qdec_en)
{
ASSERT_ERR(((qdec_en << 0) & ~0x00000001) == 0);
QDEC_CTL_REG = (QDEC_CTL_REG & ~0x00000001) | (qdec_en << 0);
}
/**
* @brief QDEC_SAMP_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 19:16 DB_SAMP_DIV 0x0
* 11:08 QDEC_PTS 0x0
* 04:00 QDEC_DIVIDE 0x0
* </pre>
*/
#define QDEC_SAMP_CTL_REG (*(volatile uint32_t *)(0x40016004))
#define QDEC_SAMP_CTL_ADDR 0x40016004
#define QDEC_SAMP_CTL_OFFSET 0x00000004
__INLINE uint32_t qdec_samp_ctl_get(void)
{
return QDEC_SAMP_CTL_REG;
}
__INLINE void qdec_samp_ctl_set(uint32_t value)
{
QDEC_SAMP_CTL_REG = value;
}
// field definitions
#define DB_SAMP_DIV_MASK 0x000F0000
#define DB_SAMP_DIV_LSB 16
#define DB_SAMP_DIV_WIDTH 0x00000004
#define QDEC_PTS_MASK 0x00000F00
#define QDEC_PTS_LSB 8
#define QDEC_PTS_WIDTH 0x00000004
#define QDEC_DIVIDE_MASK 0x0000001F
#define QDEC_DIVIDE_LSB 0
#define QDEC_DIVIDE_WIDTH 0x00000005
#define DB_SAMP_DIV_RST 0x0
#define QDEC_PTS_RST 0x0
#define QDEC_DIVIDE_RST 0x0
__INLINE void qdec_samp_ctl_pack(uint8_t db_samp_div, uint8_t qdec_pts, uint8_t qdec_divide)
{
ASSERT_ERR(((db_samp_div << 16) & ~0x000F0000) == 0);
ASSERT_ERR(((qdec_pts << 8) & ~0x00000F00) == 0);
ASSERT_ERR(((qdec_divide << 0) & ~0x0000001F) == 0);
QDEC_SAMP_CTL_REG = (db_samp_div << 16) | (qdec_pts << 8) | (qdec_divide << 0);
}
__INLINE void qdec_samp_ctl_unpack(uint8_t* db_samp_div, uint8_t* qdec_pts, uint8_t* qdec_divide)
{
uint32_t localVal = QDEC_SAMP_CTL_REG;
*db_samp_div = (localVal & 0x000F0000) >> 16;
*qdec_pts = (localVal & 0x00000F00) >> 8;
*qdec_divide = (localVal & 0x0000001F) >> 0;
}
__INLINE uint8_t qdec_samp_ctl__db_samp_div__getf(void)
{
uint32_t localVal = QDEC_SAMP_CTL_REG;
return ((localVal & 0x000F0000) >> 16);
}
__INLINE void qdec_samp_ctl__db_samp_div__setf(uint8_t db_samp_div)
{
ASSERT_ERR(((db_samp_div << 16) & ~0x000F0000) == 0);
QDEC_SAMP_CTL_REG = (QDEC_SAMP_CTL_REG & ~0x000F0000) | (db_samp_div << 16);
}
__INLINE uint8_t qdec_samp_ctl__qdec_pts__getf(void)
{
uint32_t localVal = QDEC_SAMP_CTL_REG;
return ((localVal & 0x00000F00) >> 8);
}
__INLINE void qdec_samp_ctl__qdec_pts__setf(uint8_t qdec_pts)
{
ASSERT_ERR(((qdec_pts << 8) & ~0x00000F00) == 0);
QDEC_SAMP_CTL_REG = (QDEC_SAMP_CTL_REG & ~0x00000F00) | (qdec_pts << 8);
}
__INLINE uint8_t qdec_samp_ctl__qdec_divide__getf(void)
{
uint32_t localVal = QDEC_SAMP_CTL_REG;
return ((localVal & 0x0000001F) >> 0);
}
__INLINE void qdec_samp_ctl__qdec_divide__setf(uint8_t qdec_divide)
{
ASSERT_ERR(((qdec_divide << 0) & ~0x0000001F) == 0);
QDEC_SAMP_CTL_REG = (QDEC_SAMP_CTL_REG & ~0x0000001F) | (qdec_divide << 0);
}
/**
* @brief QDEC_SAMPLE register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 01:00 QDEC_SAMPLE 0x0
* </pre>
*/
#define QDEC_SAMPLE_REG (*(volatile uint32_t *)(0x40016008))
#define QDEC_SAMPLE_ADDR 0x40016008
#define QDEC_SAMPLE_OFFSET 0x00000008
__INLINE uint32_t qdec_sample_get(void)
{
return QDEC_SAMPLE_REG;
}
// field definitions
#define QDEC_SAMPLE_MASK 0x00000003
#define QDEC_SAMPLE_LSB 0
#define QDEC_SAMPLE_WIDTH 0x00000002
#define QDEC_SAMPLE_RST 0x0
__INLINE uint8_t qdec_sample__getf(void)
{
uint32_t localVal = QDEC_SAMPLE_REG;
ASSERT_ERR((localVal & ~0x00000003) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_ACC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 10:00 ACC 0x0
* </pre>
*/
#define QDEC_ACC_REG (*(volatile uint32_t *)(0x4001600C))
#define QDEC_ACC_ADDR 0x4001600C
#define QDEC_ACC_OFFSET 0x0000000C
__INLINE uint32_t qdec_acc_get(void)
{
return QDEC_ACC_REG;
}
// field definitions
#define ACC_MASK 0x000007FF
#define ACC_LSB 0
#define ACC_WIDTH 0x0000000B
#define ACC_RST 0x0
__INLINE uint16_t qdec_acc__acc__getf(void)
{
uint32_t localVal = QDEC_ACC_REG;
ASSERT_ERR((localVal & ~0x000007FF) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_ACC_R register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 10:00 ACC_R 0x0
* </pre>
*/
#define QDEC_ACC_R_REG (*(volatile uint32_t *)(0x40016010))
#define QDEC_ACC_R_ADDR 0x40016010
#define QDEC_ACC_R_OFFSET 0x00000010
__INLINE uint32_t qdec_acc_r_get(void)
{
return QDEC_ACC_R_REG;
}
// field definitions
#define ACC_R_MASK 0x000007FF
#define ACC_R_LSB 0
#define ACC_R_WIDTH 0x0000000B
#define ACC_R_RST 0x0
__INLINE uint16_t qdec_acc_r__acc_r__getf(void)
{
uint32_t localVal = QDEC_ACC_R_REG;
ASSERT_ERR((localVal & ~0x000007FF) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_DB register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03:00 DB 0x0
* </pre>
*/
#define QDEC_DB_REG (*(volatile uint32_t *)(0x40016014))
#define QDEC_DB_ADDR 0x40016014
#define QDEC_DB_OFFSET 0x00000014
__INLINE uint32_t qdec_db_get(void)
{
return QDEC_DB_REG;
}
// field definitions
#define DB_MASK 0x0000000F
#define DB_LSB 0
#define DB_WIDTH 0x00000004
#define DB_RST 0x0
__INLINE uint8_t qdec_db__db__getf(void)
{
uint32_t localVal = QDEC_DB_REG;
ASSERT_ERR((localVal & ~0x0000000F) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_DB_R register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03:00 DB_R 0x0
* </pre>
*/
#define QDEC_DB_R_REG (*(volatile uint32_t *)(0x40016018))
#define QDEC_DB_R_ADDR 0x40016018
#define QDEC_DB_R_OFFSET 0x00000018
__INLINE uint32_t qdec_db_r_get(void)
{
return QDEC_DB_R_REG;
}
// field definitions
#define DB_R_MASK 0x0000000F
#define DB_R_LSB 0
#define DB_R_WIDTH 0x00000004
#define DB_R_RST 0x0
__INLINE uint8_t qdec_db_r__db_r__getf(void)
{
uint32_t localVal = QDEC_DB_R_REG;
ASSERT_ERR((localVal & ~0x0000000F) == 0);
return (localVal >> 0);
}
/**
* @brief QDEC_INT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03 DB_OF_RAW 0
* 02 ACC_OF_RAW 0
* 01 SAMPLE_END_RAW 0
* 00 SINGLE_SAMPLE_RAW 0
* </pre>
*/
#define QDEC_INT_REG (*(volatile uint32_t *)(0x4001601C))
#define QDEC_INT_ADDR 0x4001601C
#define QDEC_INT_OFFSET 0x0000001C
__INLINE uint32_t qdec_int_get(void)
{
return QDEC_INT_REG;
}
__INLINE void qdec_int_set(uint32_t value)
{
QDEC_INT_REG = value;
}
// field definitions
#define DB_OF_RAW_BIT 0x00000008
#define DB_OF_RAW_POS 3
#define ACC_OF_RAW_BIT 0x00000004
#define ACC_OF_RAW_POS 2
#define SAMPLE_END_RAW_BIT 0x00000002
#define SAMPLE_END_RAW_POS 1
#define SINGLE_SAMPLE_RAW_BIT 0x00000001
#define SINGLE_SAMPLE_RAW_POS 0
#define DB_OF_RAW_RST 0x0
#define ACC_OF_RAW_RST 0x0
#define SAMPLE_END_RAW_RST 0x0
#define SINGLE_SAMPLE_RAW_RST 0x0
__INLINE void qdec_int_pack(uint8_t db_of_raw, uint8_t acc_of_raw, uint8_t sample_end_raw, uint8_t single_sample_raw)
{
ASSERT_ERR(((db_of_raw << 3) & ~0x00000008) == 0);
ASSERT_ERR(((acc_of_raw << 2) & ~0x00000004) == 0);
ASSERT_ERR(((sample_end_raw << 1) & ~0x00000002) == 0);
ASSERT_ERR(((single_sample_raw << 0) & ~0x00000001) == 0);
QDEC_INT_REG = (db_of_raw << 3) | (acc_of_raw << 2) | (sample_end_raw << 1) | (single_sample_raw << 0);
}
__INLINE void qdec_int_unpack(uint8_t* db_of_raw, uint8_t* acc_of_raw, uint8_t* sample_end_raw, uint8_t* single_sample_raw)
{
uint32_t localVal = QDEC_INT_REG;
*db_of_raw = (localVal & 0x00000008) >> 3;
*acc_of_raw = (localVal & 0x00000004) >> 2;
*sample_end_raw = (localVal & 0x00000002) >> 1;
*single_sample_raw = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t qdec_int__db_of_raw__getf(void)
{
uint32_t localVal = QDEC_INT_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void qdec_int__db_of_raw__setf(uint8_t db_of_raw)
{
ASSERT_ERR(((db_of_raw << 3) & ~0x00000008) == 0);
QDEC_INT_REG = (QDEC_INT_REG & ~0x00000008) | (db_of_raw << 3);
}
__INLINE uint8_t qdec_int__acc_of_raw__getf(void)
{
uint32_t localVal = QDEC_INT_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void qdec_int__acc_of_raw__setf(uint8_t acc_of_raw)
{
ASSERT_ERR(((acc_of_raw << 2) & ~0x00000004) == 0);
QDEC_INT_REG = (QDEC_INT_REG & ~0x00000004) | (acc_of_raw << 2);
}
__INLINE uint8_t qdec_int__sample_end_raw__getf(void)
{
uint32_t localVal = QDEC_INT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void qdec_int__sample_end_raw__setf(uint8_t sample_end_raw)
{
ASSERT_ERR(((sample_end_raw << 1) & ~0x00000002) == 0);
QDEC_INT_REG = (QDEC_INT_REG & ~0x00000002) | (sample_end_raw << 1);
}
__INLINE uint8_t qdec_int__single_sample_raw__getf(void)
{
uint32_t localVal = QDEC_INT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void qdec_int__single_sample_raw__setf(uint8_t single_sample_raw)
{
ASSERT_ERR(((single_sample_raw << 0) & ~0x00000001) == 0);
QDEC_INT_REG = (QDEC_INT_REG & ~0x00000001) | (single_sample_raw << 0);
}
/**
* @brief QDEC_INT_MSK register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03 DB_OF_MSK 0
* 02 ACC_OF_MSK 0
* 01 SAMPLE_END_MSK 0
* 00 SINGLE_SAMPLE_MSK 0
* </pre>
*/
#define QDEC_INT_MSK_REG (*(volatile uint32_t *)(0x40016020))
#define QDEC_INT_MSK_ADDR 0x40016020
#define QDEC_INT_MSK_OFFSET 0x00000020
__INLINE uint32_t qdec_int_msk_get(void)
{
return QDEC_INT_MSK_REG;
}
__INLINE void qdec_int_msk_set(uint32_t value)
{
QDEC_INT_MSK_REG = value;
}
// field definitions
#define DB_OF_MSK_BIT 0x00000008
#define DB_OF_MSK_POS 3
#define ACC_OF_MSK_BIT 0x00000004
#define ACC_OF_MSK_POS 2
#define SAMPLE_END_MSK_BIT 0x00000002
#define SAMPLE_END_MSK_POS 1
#define SINGLE_SAMPLE_MSK_BIT 0x00000001
#define SINGLE_SAMPLE_MSK_POS 0
#define DB_OF_MSK_RST 0x0
#define ACC_OF_MSK_RST 0x0
#define SAMPLE_END_MSK_RST 0x0
#define SINGLE_SAMPLE_MSK_RST 0x0
__INLINE void qdec_int_msk_pack(uint8_t db_of_msk, uint8_t acc_of_msk, uint8_t sample_end_msk, uint8_t single_sample_msk)
{
ASSERT_ERR(((db_of_msk << 3) & ~0x00000008) == 0);
ASSERT_ERR(((acc_of_msk << 2) & ~0x00000004) == 0);
ASSERT_ERR(((sample_end_msk << 1) & ~0x00000002) == 0);
ASSERT_ERR(((single_sample_msk << 0) & ~0x00000001) == 0);
QDEC_INT_MSK_REG = (db_of_msk << 3) | (acc_of_msk << 2) | (sample_end_msk << 1) | (single_sample_msk << 0);
}
__INLINE void qdec_int_msk_unpack(uint8_t* db_of_msk, uint8_t* acc_of_msk, uint8_t* sample_end_msk, uint8_t* single_sample_msk)
{
uint32_t localVal = QDEC_INT_MSK_REG;
*db_of_msk = (localVal & 0x00000008) >> 3;
*acc_of_msk = (localVal & 0x00000004) >> 2;
*sample_end_msk = (localVal & 0x00000002) >> 1;
*single_sample_msk = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t qdec_int_msk__db_of_msk__getf(void)
{
uint32_t localVal = QDEC_INT_MSK_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void qdec_int_msk__db_of_msk__setf(uint8_t db_of_msk)
{
ASSERT_ERR(((db_of_msk << 3) & ~0x00000008) == 0);
QDEC_INT_MSK_REG = (QDEC_INT_MSK_REG & ~0x00000008) | (db_of_msk << 3);
}
__INLINE uint8_t qdec_int_msk__acc_of_msk__getf(void)
{
uint32_t localVal = QDEC_INT_MSK_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void qdec_int_msk__acc_of_msk__setf(uint8_t acc_of_msk)
{
ASSERT_ERR(((acc_of_msk << 2) & ~0x00000004) == 0);
QDEC_INT_MSK_REG = (QDEC_INT_MSK_REG & ~0x00000004) | (acc_of_msk << 2);
}
__INLINE uint8_t qdec_int_msk__sample_end_msk__getf(void)
{
uint32_t localVal = QDEC_INT_MSK_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void qdec_int_msk__sample_end_msk__setf(uint8_t sample_end_msk)
{
ASSERT_ERR(((sample_end_msk << 1) & ~0x00000002) == 0);
QDEC_INT_MSK_REG = (QDEC_INT_MSK_REG & ~0x00000002) | (sample_end_msk << 1);
}
__INLINE uint8_t qdec_int_msk__single_sample_msk__getf(void)
{
uint32_t localVal = QDEC_INT_MSK_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void qdec_int_msk__single_sample_msk__setf(uint8_t single_sample_msk)
{
ASSERT_ERR(((single_sample_msk << 0) & ~0x00000001) == 0);
QDEC_INT_MSK_REG = (QDEC_INT_MSK_REG & ~0x00000001) | (single_sample_msk << 0);
}
/**
* @brief QDEC_STAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 QDEC_BUSY 0
* </pre>
*/
#define QDEC_STAT_REG (*(volatile uint32_t *)(0x40016024))
#define QDEC_STAT_ADDR 0x40016024
#define QDEC_STAT_OFFSET 0x00000024
__INLINE uint32_t qdec_stat_get(void)
{
return QDEC_STAT_REG;
}
// field definitions
#define QDEC_BUSY_BIT 0x00000001
#define QDEC_BUSY_POS 0
#define QDEC_BUSY_RST 0x0
__INLINE uint8_t qdec_stat__qdec_busy__getf(void)
{
uint32_t localVal = QDEC_STAT_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_QDEC_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_rf.h
+483
View File
@@ -0,0 +1,483 @@
#ifndef _XC_REG_RF_H_
#define _XC_REG_RF_H_
#include <stdint.h>
#define XC_REG_RF_BASE_ADDR 0x53021000
#define XC_REG_RF_DECODING_MASK 0x000000FF
/**
* @brief RF_ANA26 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15 clk_bbpll_en 0
* 14 clk_bbpll_rstn 0
* 13 bbpll_en 0
* 12 bbpll_core64m_en 0
* 11 bbpll_rc16m_sel 0
* 10:09 bbpll_bufmsel 0x1
* 08:06 bbpll_res 0x2
* 05:00 bbpll_loopdiv 0x4
* </pre>
*/
#define RF_ANA26_REG (*(volatile uint32_t *)(0x53021068))
#define RF_ANA26_ADDR 0x53021068
#define RF_ANA26_OFFSET 0x00000068
__INLINE uint16_t rf_ana26_get(void)
{
return RF_ANA26_REG;
}
__INLINE void rf_ana26_set(uint16_t value)
{
RF_ANA26_REG = value;
}
// field definitions
#define CLK_BBPLL_EN_BIT 0x00008000
#define CLK_BBPLL_EN_POS 15
#define CLK_BBPLL_RSTN_BIT 0x00004000
#define CLK_BBPLL_RSTN_POS 14
#define BBPLL_EN_BIT 0x00002000
#define BBPLL_EN_POS 13
#define BBPLL_CORE_64M_EN_BIT 0x00001000
#define BBPLL_CORE_64M_EN_POS 12
#define BBPLL_RC_16M_SEL_BIT 0x00000800
#define BBPLL_RC_16M_SEL_POS 11
#define BBPLL_BUFMSEL_MASK 0x00000600
#define BBPLL_BUFMSEL_LSB 9
#define BBPLL_BUFMSEL_WIDTH 0x00000002
#define BBPLL_RES_MASK 0x000001C0
#define BBPLL_RES_LSB 6
#define BBPLL_RES_WIDTH 0x00000003
#define BBPLL_LOOPDIV_MASK 0x0000003F
#define BBPLL_LOOPDIV_LSB 0
#define BBPLL_LOOPDIV_WIDTH 0x00000006
#define CLK_BBPLL_EN_RST 0x0
#define CLK_BBPLL_RSTN_RST 0x0
#define BBPLL_EN_RST 0x0
#define BBPLL_CORE_64M_EN_RST 0x0
#define BBPLL_RC_16M_SEL_RST 0x0
#define BBPLL_BUFMSEL_RST 0x1
#define BBPLL_RES_RST 0x2
#define BBPLL_LOOPDIV_RST 0x4
__INLINE void rf_ana26_pack(uint8_t clk_bbpll_en, uint8_t clk_bbpll_rstn, uint8_t bbpll_en, uint8_t bbpll_core64m_en, uint8_t bbpll_rc16m_sel, uint8_t bbpll_bufmsel, uint8_t bbpll_res, uint8_t bbpll_loopdiv)
{
ASSERT_ERR(((clk_bbpll_en << 15) & ~0x00008000) == 0);
ASSERT_ERR(((clk_bbpll_rstn << 14) & ~0x00004000) == 0);
ASSERT_ERR(((bbpll_en << 13) & ~0x00002000) == 0);
ASSERT_ERR(((bbpll_core64m_en << 12) & ~0x00001000) == 0);
ASSERT_ERR(((bbpll_rc16m_sel << 11) & ~0x00000800) == 0);
ASSERT_ERR(((bbpll_bufmsel << 9) & ~0x00000600) == 0);
ASSERT_ERR(((bbpll_res << 6) & ~0x000001C0) == 0);
ASSERT_ERR(((bbpll_loopdiv << 0) & ~0x0000003F) == 0);
RF_ANA26_REG = (clk_bbpll_en << 15) | (clk_bbpll_rstn << 14) | (bbpll_en << 13) | (bbpll_core64m_en << 12) | (bbpll_rc16m_sel << 11) | (bbpll_bufmsel << 9) | (bbpll_res << 6) | (bbpll_loopdiv << 0);
}
__INLINE void rf_ana26_unpack(uint8_t* clk_bbpll_en, uint8_t* clk_bbpll_rstn, uint8_t* bbpll_en, uint8_t* bbpll_core64m_en, uint8_t* bbpll_rc16m_sel, uint8_t* bbpll_bufmsel, uint8_t* bbpll_res, uint8_t* bbpll_loopdiv)
{
uint32_t localVal = RF_ANA26_REG;
*clk_bbpll_en = (localVal & 0x00008000) >> 15;
*clk_bbpll_rstn = (localVal & 0x00004000) >> 14;
*bbpll_en = (localVal & 0x00002000) >> 13;
*bbpll_core64m_en = (localVal & 0x00001000) >> 12;
*bbpll_rc16m_sel = (localVal & 0x00000800) >> 11;
*bbpll_bufmsel = (localVal & 0x00000600) >> 9;
*bbpll_res = (localVal & 0x000001C0) >> 6;
*bbpll_loopdiv = (localVal & 0x0000003F) >> 0;
}
__INLINE uint8_t rf_ana26__clk_bbpll_en__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00008000) >> 15);
}
__INLINE void rf_ana26__clk_bbpll_en__setf(uint8_t clk_bbpll_en)
{
ASSERT_ERR(((clk_bbpll_en << 15) & ~0x00008000) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00008000) | (clk_bbpll_en << 15);
}
__INLINE uint8_t rf_ana26__clk_bbpll_rstn__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00004000) >> 14);
}
__INLINE void rf_ana26__clk_bbpll_rstn__setf(uint8_t clk_bbpll_rstn)
{
ASSERT_ERR(((clk_bbpll_rstn << 14) & ~0x00004000) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00004000) | (clk_bbpll_rstn << 14);
}
__INLINE uint8_t rf_ana26__bbpll_en__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00002000) >> 13);
}
__INLINE void rf_ana26__bbpll_en__setf(uint8_t bbpll_en)
{
ASSERT_ERR(((bbpll_en << 13) & ~0x00002000) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00002000) | (bbpll_en << 13);
}
__INLINE uint8_t rf_ana26__bbpll_core_64m_en__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00001000) >> 12);
}
__INLINE void rf_ana26__bbpll_core_64m_en__setf(uint8_t bbpll_core64m_en)
{
ASSERT_ERR(((bbpll_core64m_en << 12) & ~0x00001000) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00001000) | (bbpll_core64m_en << 12);
}
__INLINE uint8_t rf_ana26__bbpll_rc_16m_sel__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00000800) >> 11);
}
__INLINE void rf_ana26__bbpll_rc_16m_sel__setf(uint8_t bbpll_rc16m_sel)
{
ASSERT_ERR(((bbpll_rc16m_sel << 11) & ~0x00000800) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00000800) | (bbpll_rc16m_sel << 11);
}
__INLINE uint8_t rf_ana26__bbpll_bufmsel__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x00000600) >> 9);
}
__INLINE void rf_ana26__bbpll_bufmsel__setf(uint8_t bbpll_bufmsel)
{
ASSERT_ERR(((bbpll_bufmsel << 9) & ~0x00000600) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x00000600) | (bbpll_bufmsel << 9);
}
__INLINE uint8_t rf_ana26__bbpll_res__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x000001C0) >> 6);
}
__INLINE void rf_ana26__bbpll_res__setf(uint8_t bbpll_res)
{
ASSERT_ERR(((bbpll_res << 6) & ~0x000001C0) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x000001C0) | (bbpll_res << 6);
}
__INLINE uint8_t rf_ana26__bbpll_loopdiv__getf(void)
{
uint32_t localVal = RF_ANA26_REG;
return ((localVal & 0x0000003F) >> 0);
}
__INLINE void rf_ana26__bbpll_loopdiv__setf(uint8_t bbpll_loopdiv)
{
ASSERT_ERR(((bbpll_loopdiv << 0) & ~0x0000003F) == 0);
RF_ANA26_REG = (RF_ANA26_REG & ~0x0000003F) | (bbpll_loopdiv << 0);
}
/**
* @brief RF_ANA27 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:13 bbpll_dvddres 0x4
* 12:10 bbpll_icp 0x3
* 07 bbpll16m_sel 0
* 01 bbpll_core96m_en 0
* 00 spi_sx_afc_rstn 0
* </pre>
*/
#define RF_ANA27_REG (*(volatile uint32_t *)(0x5302106C))
#define RF_ANA27_ADDR 0x5302106C
#define RF_ANA27_OFFSET 0x0000006C
__INLINE uint16_t rf_ana27_get(void)
{
return RF_ANA27_REG;
}
__INLINE void rf_ana27_set(uint16_t value)
{
RF_ANA27_REG = value;
}
// field definitions
#define BBPLL_DVDDRES_MASK 0x0000E000
#define BBPLL_DVDDRES_LSB 13
#define BBPLL_DVDDRES_WIDTH 0x00000003
#define BBPLL_ICP_MASK 0x00001C00
#define BBPLL_ICP_LSB 10
#define BBPLL_ICP_WIDTH 0x00000003
#define BBPLL_16M_SEL_BIT 0x00000080
#define BBPLL_16M_SEL_POS 7
#define BBPLL_CORE_96M_EN_BIT 0x00000002
#define BBPLL_CORE_96M_EN_POS 1
#define SPI_SX_AFC_RSTN_BIT 0x00000001
#define SPI_SX_AFC_RSTN_POS 0
#define BBPLL_DVDDRES_RST 0x4
#define BBPLL_ICP_RST 0x3
#define BBPLL_16M_SEL_RST 0x0
#define BBPLL_CORE_96M_EN_RST 0x0
#define SPI_SX_AFC_RSTN_RST 0x0
__INLINE void rf_ana27_pack(uint8_t bbpll_dvddres, uint8_t bbpll_icp, uint8_t bbpll16m_sel, uint8_t bbpll_core96m_en, uint8_t spi_sx_afc_rstn)
{
ASSERT_ERR(((bbpll_dvddres << 13) & ~0x0000E000) == 0);
ASSERT_ERR(((bbpll_icp << 10) & ~0x00001C00) == 0);
ASSERT_ERR(((bbpll16m_sel << 7) & ~0x00000080) == 0);
ASSERT_ERR(((bbpll_core96m_en << 1) & ~0x00000002) == 0);
ASSERT_ERR(((spi_sx_afc_rstn << 0) & ~0x00000001) == 0);
RF_ANA27_REG = (bbpll_dvddres << 13) | (bbpll_icp << 10) | (bbpll16m_sel << 7) | (bbpll_core96m_en << 1) | (spi_sx_afc_rstn << 0);
}
__INLINE void rf_ana27_unpack(uint8_t* bbpll_dvddres, uint8_t* bbpll_icp, uint8_t* bbpll16m_sel, uint8_t* bbpll_core96m_en, uint8_t* spi_sx_afc_rstn)
{
uint32_t localVal = RF_ANA27_REG;
*bbpll_dvddres = (localVal & 0x0000E000) >> 13;
*bbpll_icp = (localVal & 0x00001C00) >> 10;
*bbpll16m_sel = (localVal & 0x00000080) >> 7;
*bbpll_core96m_en = (localVal & 0x00000002) >> 1;
*spi_sx_afc_rstn = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t rf_ana27__bbpll_dvddres__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x0000E000) >> 13);
}
__INLINE void rf_ana27__bbpll_dvddres__setf(uint8_t bbpll_dvddres)
{
ASSERT_ERR(((bbpll_dvddres << 13) & ~0x0000E000) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x0000E000) | (bbpll_dvddres << 13);
}
__INLINE uint8_t rf_ana27__bbpll_icp__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x00001C00) >> 10);
}
__INLINE void rf_ana27__bbpll_icp__setf(uint8_t bbpll_icp)
{
ASSERT_ERR(((bbpll_icp << 10) & ~0x00001C00) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00001C00) | (bbpll_icp << 10);
}
__INLINE uint8_t rf_ana27__bbpll_16m_sel__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x00000080) >> 7);
}
__INLINE void rf_ana27__bbpll_16m_sel__setf(uint8_t bbpll16m_sel)
{
ASSERT_ERR(((bbpll16m_sel << 7) & ~0x00000080) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00000080) | (bbpll16m_sel << 7);
}
__INLINE uint8_t rf_ana27__bbpll_core_96m_en__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void rf_ana27__bbpll_core_96m_en__setf(uint8_t bbpll_core96m_en)
{
ASSERT_ERR(((bbpll_core96m_en << 1) & ~0x00000002) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00000002) | (bbpll_core96m_en << 1);
}
__INLINE uint8_t rf_ana27__spi_sx_afc_rstn__getf(void)
{
uint32_t localVal = RF_ANA27_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void rf_ana27__spi_sx_afc_rstn__setf(uint8_t spi_sx_afc_rstn)
{
ASSERT_ERR(((spi_sx_afc_rstn << 0) & ~0x00000001) == 0);
RF_ANA27_REG = (RF_ANA27_REG & ~0x00000001) | (spi_sx_afc_rstn << 0);
}
/**
* @brief BT_RF_PM_REG register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15 bt_en_pm_fc_soft 0
* 14 bt_en_pm 0
* 13:06 ch_cnt_delay 0x80
* 05 da_ism_rstn_soften 0
* 04 da_ism_dac_rstn_soft 0
* 03 da_ism_sx_dsm_resetn_soft 0
* 02 da_ism_sx_afc_resetn_soft 0
* </pre>
*/
#define BT_RF_PM_REG_REG (*(volatile uint32_t *)(0x530210B0))
#define BT_RF_PM_REG_ADDR 0x530210B0
#define BT_RF_PM_REG_OFFSET 0x000000B0
__INLINE uint16_t bt_rf_pm_reg_get(void)
{
return BT_RF_PM_REG_REG;
}
__INLINE void bt_rf_pm_reg_set(uint16_t value)
{
BT_RF_PM_REG_REG = value;
}
// field definitions
#define BT_EN_PM_FC_SOFT_BIT 0x00008000
#define BT_EN_PM_FC_SOFT_POS 15
#define BT_EN_PM_BIT 0x00004000
#define BT_EN_PM_POS 14
#define CH_CNT_DELAY_MASK 0x00003FC0
#define CH_CNT_DELAY_LSB 6
#define CH_CNT_DELAY_WIDTH 0x00000008
#define DA_ISM_RSTN_SOFTEN_BIT 0x00000020
#define DA_ISM_RSTN_SOFTEN_POS 5
#define DA_ISM_DAC_RSTN_SOFT_BIT 0x00000010
#define DA_ISM_DAC_RSTN_SOFT_POS 4
#define DA_ISM_SX_DSM_RESETN_SOFT_BIT 0x00000008
#define DA_ISM_SX_DSM_RESETN_SOFT_POS 3
#define DA_ISM_SX_AFC_RESETN_SOFT_BIT 0x00000004
#define DA_ISM_SX_AFC_RESETN_SOFT_POS 2
#define BT_EN_PM_FC_SOFT_RST 0x0
#define BT_EN_PM_RST 0x0
#define CH_CNT_DELAY_RST 0x80
#define DA_ISM_RSTN_SOFTEN_RST 0x0
#define DA_ISM_DAC_RSTN_SOFT_RST 0x0
#define DA_ISM_SX_DSM_RESETN_SOFT_RST 0x0
#define DA_ISM_SX_AFC_RESETN_SOFT_RST 0x0
__INLINE void bt_rf_pm_reg_pack(uint8_t bt_en_pm_fc_soft, uint8_t bt_en_pm, uint8_t ch_cnt_delay, uint8_t da_ism_rstn_soften, uint8_t da_ism_dac_rstn_soft, uint8_t da_ism_sx_dsm_resetn_soft, uint8_t da_ism_sx_afc_resetn_soft)
{
ASSERT_ERR(((bt_en_pm_fc_soft << 15) & ~0x00008000) == 0);
ASSERT_ERR(((bt_en_pm << 14) & ~0x00004000) == 0);
ASSERT_ERR(((ch_cnt_delay << 6) & ~0x00003FC0) == 0);
ASSERT_ERR(((da_ism_rstn_soften << 5) & ~0x00000020) == 0);
ASSERT_ERR(((da_ism_dac_rstn_soft << 4) & ~0x00000010) == 0);
ASSERT_ERR(((da_ism_sx_dsm_resetn_soft << 3) & ~0x00000008) == 0);
ASSERT_ERR(((da_ism_sx_afc_resetn_soft << 2) & ~0x00000004) == 0);
BT_RF_PM_REG_REG = (bt_en_pm_fc_soft << 15) | (bt_en_pm << 14) | (ch_cnt_delay << 6) | (da_ism_rstn_soften << 5) | (da_ism_dac_rstn_soft << 4) | (da_ism_sx_dsm_resetn_soft << 3) | (da_ism_sx_afc_resetn_soft << 2);
}
__INLINE void bt_rf_pm_reg_unpack(uint8_t* bt_en_pm_fc_soft, uint8_t* bt_en_pm, uint8_t* ch_cnt_delay, uint8_t* da_ism_rstn_soften, uint8_t* da_ism_dac_rstn_soft, uint8_t* da_ism_sx_dsm_resetn_soft, uint8_t* da_ism_sx_afc_resetn_soft)
{
uint32_t localVal = BT_RF_PM_REG_REG;
*bt_en_pm_fc_soft = (localVal & 0x00008000) >> 15;
*bt_en_pm = (localVal & 0x00004000) >> 14;
*ch_cnt_delay = (localVal & 0x00003FC0) >> 6;
*da_ism_rstn_soften = (localVal & 0x00000020) >> 5;
*da_ism_dac_rstn_soft = (localVal & 0x00000010) >> 4;
*da_ism_sx_dsm_resetn_soft = (localVal & 0x00000008) >> 3;
*da_ism_sx_afc_resetn_soft = (localVal & 0x00000004) >> 2;
}
__INLINE uint8_t bt_rf_pm_reg__bt_en_pm_fc_soft__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00008000) >> 15);
}
__INLINE void bt_rf_pm_reg__bt_en_pm_fc_soft__setf(uint8_t bt_en_pm_fc_soft)
{
ASSERT_ERR(((bt_en_pm_fc_soft << 15) & ~0x00008000) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00008000) | (bt_en_pm_fc_soft << 15);
}
__INLINE uint8_t bt_rf_pm_reg__bt_en_pm__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00004000) >> 14);
}
__INLINE void bt_rf_pm_reg__bt_en_pm__setf(uint8_t bt_en_pm)
{
ASSERT_ERR(((bt_en_pm << 14) & ~0x00004000) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00004000) | (bt_en_pm << 14);
}
__INLINE uint8_t bt_rf_pm_reg__ch_cnt_delay__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00003FC0) >> 6);
}
__INLINE void bt_rf_pm_reg__ch_cnt_delay__setf(uint8_t ch_cnt_delay)
{
ASSERT_ERR(((ch_cnt_delay << 6) & ~0x00003FC0) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00003FC0) | (ch_cnt_delay << 6);
}
__INLINE uint8_t bt_rf_pm_reg__da_ism_rstn_soften__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00000020) >> 5);
}
__INLINE void bt_rf_pm_reg__da_ism_rstn_soften__setf(uint8_t da_ism_rstn_soften)
{
ASSERT_ERR(((da_ism_rstn_soften << 5) & ~0x00000020) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00000020) | (da_ism_rstn_soften << 5);
}
__INLINE uint8_t bt_rf_pm_reg__da_ism_dac_rstn_soft__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00000010) >> 4);
}
__INLINE void bt_rf_pm_reg__da_ism_dac_rstn_soft__setf(uint8_t da_ism_dac_rstn_soft)
{
ASSERT_ERR(((da_ism_dac_rstn_soft << 4) & ~0x00000010) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00000010) | (da_ism_dac_rstn_soft << 4);
}
__INLINE uint8_t bt_rf_pm_reg__da_ism_sx_dsm_resetn_soft__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00000008) >> 3);
}
__INLINE void bt_rf_pm_reg__da_ism_sx_dsm_resetn_soft__setf(uint8_t da_ism_sx_dsm_resetn_soft)
{
ASSERT_ERR(((da_ism_sx_dsm_resetn_soft << 3) & ~0x00000008) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00000008) | (da_ism_sx_dsm_resetn_soft << 3);
}
__INLINE uint8_t bt_rf_pm_reg__da_ism_sx_afc_resetn_soft__getf(void)
{
uint32_t localVal = BT_RF_PM_REG_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void bt_rf_pm_reg__da_ism_sx_afc_resetn_soft__setf(uint8_t da_ism_sx_afc_resetn_soft)
{
ASSERT_ERR(((da_ism_sx_afc_resetn_soft << 2) & ~0x00000004) == 0);
BT_RF_PM_REG_REG = (BT_RF_PM_REG_REG & ~0x00000004) | (da_ism_sx_afc_resetn_soft << 2);
}
#endif // _XC_REG_RF_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_rtc.h
+3059
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_spi.h
+1376
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_timer.h
+209
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#ifndef _XC_REG_TIMER_H_
#define _XC_REG_TIMER_H_
#include <stdint.h>
#define XC_REG_TIMER_BASE_ADDR 0x40003000
#define XC_REG_TIMER_DECODING_MASK 0x0000001F
/**
* @brief TIMER_TLC register definition
*/
#define TIMER_TLC_REG(i) (*(volatile uint32_t *)(0x40003000 + timer_offset[i]))
#define TIMER_TLC_ADDR(i) (0x40003000 + timer_offset[i])
#define TIMER_TLC_OFFSET 0x00000000
__INLINE uint32_t timer_tlc_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TLC_REG(reg_idx);
}
__INLINE void timer_tlc_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 3);
TIMER_TLC_REG(reg_idx) = value;
}
/**
* @brief TIMER_TCV register definition
*/
#define TIMER_TCV_REG(i) (*(volatile uint32_t *)(0x40003004 + timer_offset[i]))
#define TIMER_TCV_ADDR(i) (0x40003004 + timer_offset[i])
#define TIMER_TCV_OFFSET 0x00000004
__INLINE uint32_t timer_tcv_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TCV_REG(reg_idx);
}
/**
* @brief TIMER_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 TIM 0
* 01 TMS 0
* 00 TES 0
* </pre>
*/
#define TIMER_TCR_REG(i) (*(volatile uint32_t *)(0x40003008 + timer_offset[i]))
#define TIMER_TCR_ADDR(i) (0x40003008 + timer_offset[i])
#define TIMER_TCR_OFFSET 0x00000008
__INLINE uint32_t timer_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TCR_REG(reg_idx);
}
__INLINE void timer_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 3);
TIMER_TCR_REG(reg_idx) = value;
}
// field definitions
#define TIM_BIT 0x00000004
#define TIM_POS 2
#define TMS_BIT 0x00000002
#define TMS_POS 1
#define TES_BIT 0x00000001
#define TES_POS 0
#define TIM_RST 0x0
#define TMS_RST 0x0
#define TES_RST 0x0
__INLINE void timer_tcr_pack(uint32_t reg_idx, uint8_t tim, uint8_t tms, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
TIMER_TCR_REG(reg_idx) = (tim << 2) | (tms << 1) | (tes << 0);
}
__INLINE void timer_tcr_unpack(uint32_t reg_idx, uint8_t* tim, uint8_t* tms, uint8_t* tes)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
*tim = (localVal & 0x00000004) >> 2;
*tms = (localVal & 0x00000002) >> 1;
*tes = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t timer_tcr__tim__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void timer_tcr__tim__setf(uint32_t reg_idx, uint8_t tim)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000004) | (tim << 2);
}
__INLINE uint8_t timer_tcr__tms__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void timer_tcr__tms__setf(uint32_t reg_idx, uint8_t tms)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000002) | (tms << 1);
}
__INLINE uint8_t timer_tcr__tes__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void timer_tcr__tes__setf(uint32_t reg_idx, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000001) | (tes << 0);
}
/**
* @brief TIMER_TIC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 INTR 0
* </pre>
*/
#define TIMER_TIC_REG(i) (*(volatile uint32_t *)(0x4000300C + timer_offset[i]))
#define TIMER_TIC_ADDR(i) (0x4000300C + timer_offset[i])
#define TIMER_TIC_OFFSET 0x0000000C
__INLINE uint32_t timer_tic_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TIC_REG(reg_idx);
}
// field definitions
#define INTR_BIT 0x00000001
#define INTR_POS 0
#define INTR_RST 0x0
__INLINE uint8_t timer_tic__intr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TIC_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief TIMER_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 STAT 0
* </pre>
*/
#define TIMER_TIS_REG(i) (*(volatile uint32_t *)(0x40003010 + timer_offset[i]))
#define TIMER_TIS_ADDR(i) (0x40003010 + timer_offset[i])
#define TIMER_TIS_OFFSET 0x00000010
__INLINE uint32_t timer_tis_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TIS_REG(reg_idx);
}
// field definitions
#define STAT_BIT 0x00000001
#define STAT_POS 0
#define STAT_RST 0x0
__INLINE uint8_t timer_tis__stat__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TIS_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_TIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_uart.h
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#ifndef _XC_REG_UART_H_
#define _XC_REG_UART_H_
#include <stdint.h>
#include "xc_reg_offset.h"
#define XC_REG_UART_BASE_ADDR 0x40010000
#define XC_REG_UART_DECODING_MASK 0x000000FF
/**
* @brief UART_RBR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 RBR 0x0
* </pre>
*/
#define UART_RBR_REG(i) (* ((volatile uint32_t *)(0x40010000 + uart_offset[i])) )
#define UART_RBR_ADDR(i) (0x40010000 + uart_offset[i])
#define UART_RBR_OFFSET 0x00000000
__INLINE uint32_t uart_rbr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_RBR_REG(reg_idx);
}
// field definitions
#define RBR_MASK 0x000000FF
#define RBR_LSB 0
#define RBR_WIDTH 0x00000008
#define RBR_RST 0x0
__INLINE uint8_t uart_rbr__rbr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_RBR_REG(reg_idx);
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
/**
* @brief UART_THR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 THR 0x0
* </pre>
*/
#define UART_THR_REG(i) (* ((volatile uint32_t *)(0x40010000 + uart_offset[i])) )
#define UART_THR_ADDR(i) (0x40010000 + uart_offset[i])
#define UART_THR_OFFSET 0x00000000
__INLINE void uart_thr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_THR_REG(reg_idx) = value;
}
// field definitions
#define THR_MASK 0x000000FF
#define THR_LSB 0
#define THR_WIDTH 0x00000008
#define THR_RST 0x0
__INLINE void uart_thr__thr__setf(uint32_t reg_idx, uint8_t thr)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((thr << 0) & ~0x000000FF) == 0);
UART_THR_REG(reg_idx) = thr << 0;
}
/**
* @brief UART_DLL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 DLL 0x0
* </pre>
*/
#define UART_DLL_REG(i) (* ((volatile uint32_t *)(0x40010000 + uart_offset[i])) )
#define UART_DLL_ADDR(i) (0x40010000 + uart_offset[i])
#define UART_DLL_OFFSET 0x00000000
__INLINE uint32_t uart_dll_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_DLL_REG(reg_idx);
}
__INLINE void uart_dll_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_DLL_REG(reg_idx) = value;
}
// field definitions
#define DLL_MASK 0x000000FF
#define DLL_LSB 0
#define DLL_WIDTH 0x00000008
#define DLL_RST 0x0
__INLINE uint8_t uart_dll__dll__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_DLL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
__INLINE void uart_dll__dll__setf(uint32_t reg_idx, uint8_t dll)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dll << 0) & ~0x000000FF) == 0);
UART_DLL_REG(reg_idx) = dll << 0;
}
/**
* @brief UART_IER register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07 PTIME 0
* 03 EMSI 0
* 02 ETSI 0
* 01 ETHEI 0
* 00 ERDAI 0
* </pre>
*/
#define UART_IER_REG(i) (* ((volatile uint32_t *)(0x40010004 + uart_offset[i])) )
#define UART_IER_ADDR(i) (0x40010004 + uart_offset[i])
#define UART_IER_OFFSET 0x00000004
__INLINE uint32_t uart_ier_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_IER_REG(reg_idx);
}
__INLINE void uart_ier_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_IER_REG(reg_idx) = value;
}
// field definitions
#define PTIME_BIT 0x00000080
#define PTIME_POS 7
#define EMSI_BIT 0x00000008
#define EMSI_POS 3
#define ETSI_BIT 0x00000004
#define ETSI_POS 2
#define ETHEI_BIT 0x00000002
#define ETHEI_POS 1
#define ERDAI_BIT 0x00000001
#define ERDAI_POS 0
#define PTIME_RST 0x0
#define EMSI_RST 0x0
#define ETSI_RST 0x0
#define ETHEI_RST 0x0
#define ERDAI_RST 0x0
__INLINE void uart_ier_pack(uint32_t reg_idx, uint8_t ptime, uint8_t emsi, uint8_t etsi, uint8_t ethei, uint8_t erdai)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((ptime << 7) & ~0x00000080) == 0);
ASSERT_ERR(((emsi << 3) & ~0x00000008) == 0);
ASSERT_ERR(((etsi << 2) & ~0x00000004) == 0);
ASSERT_ERR(((ethei << 1) & ~0x00000002) == 0);
ASSERT_ERR(((erdai << 0) & ~0x00000001) == 0);
UART_IER_REG(reg_idx) = (ptime << 7) | (emsi << 3) | (etsi << 2) | (ethei << 1) | (erdai << 0);
}
__INLINE void uart_ier_unpack(uint32_t reg_idx, uint8_t* ptime, uint8_t* emsi, uint8_t* etsi, uint8_t* ethei, uint8_t* erdai)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
*ptime = (localVal & 0x00000080) >> 7;
*emsi = (localVal & 0x00000008) >> 3;
*etsi = (localVal & 0x00000004) >> 2;
*ethei = (localVal & 0x00000002) >> 1;
*erdai = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t uart_ier__ptime__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000080) >> 7);
}
__INLINE void uart_ier__ptime__setf(uint32_t reg_idx, uint8_t ptime)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((ptime << 7) & ~0x00000080) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000080) | (ptime << 7);
}
__INLINE uint8_t uart_ier__emsi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE void uart_ier__emsi__setf(uint32_t reg_idx, uint8_t emsi)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((emsi << 3) & ~0x00000008) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000008) | (emsi << 3);
}
__INLINE uint8_t uart_ier__etsi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void uart_ier__etsi__setf(uint32_t reg_idx, uint8_t etsi)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((etsi << 2) & ~0x00000004) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000004) | (etsi << 2);
}
__INLINE uint8_t uart_ier__ethei__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void uart_ier__ethei__setf(uint32_t reg_idx, uint8_t ethei)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((ethei << 1) & ~0x00000002) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000002) | (ethei << 1);
}
__INLINE uint8_t uart_ier__erdai__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IER_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void uart_ier__erdai__setf(uint32_t reg_idx, uint8_t erdai)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((erdai << 0) & ~0x00000001) == 0);
UART_IER_REG(reg_idx) = (UART_IER_REG(reg_idx) & ~0x00000001) | (erdai << 0);
}
/**
* @brief UART_DLH register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 DLH 0x0
* </pre>
*/
#define UART_DLH_REG(i) (* ((volatile uint32_t *)(0x40010004 + uart_offset[i])) )
#define UART_DLH_ADDR(i) (0x40010004 + uart_offset[i])
#define UART_DLH_OFFSET 0x00000004
__INLINE uint32_t uart_dlh_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_DLH_REG(reg_idx);
}
__INLINE void uart_dlh_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_DLH_REG(reg_idx) = value;
}
// field definitions
#define DLH_MASK 0x000000FF
#define DLH_LSB 0
#define DLH_WIDTH 0x00000008
#define DLH_RST 0x0
__INLINE uint8_t uart_dlh__dlh__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_DLH_REG(reg_idx);
ASSERT_ERR((localVal & ~0x000000FF) == 0);
return (localVal >> 0);
}
__INLINE void uart_dlh__dlh__setf(uint32_t reg_idx, uint8_t dlh)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dlh << 0) & ~0x000000FF) == 0);
UART_DLH_REG(reg_idx) = dlh << 0;
}
/**
* @brief UART_IIR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:06 FS 0x0
* 03:00 IID 0x0
* </pre>
*/
#define UART_IIR_REG(i) (* ((volatile uint32_t *)(0x40010008 + uart_offset[i])) )
#define UART_IIR_ADDR(i) (0x40010008 + uart_offset[i])
#define UART_IIR_OFFSET 0x00000008
__INLINE uint32_t uart_iir_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_IIR_REG(reg_idx);
}
// field definitions
#define FS_MASK 0x000000C0
#define FS_LSB 6
#define FS_WIDTH 0x00000002
#define IID_MASK 0x0000000F
#define IID_LSB 0
#define IID_WIDTH 0x00000004
#define FS_RST 0x0
#define IID_RST 0x0
__INLINE void uart_iir_unpack(uint32_t reg_idx, uint8_t* fs, uint8_t* iid)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IIR_REG(reg_idx);
*fs = (localVal & 0x000000C0) >> 6;
*iid = (localVal & 0x0000000F) >> 0;
}
__INLINE uint8_t uart_iir__fs__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IIR_REG(reg_idx);
return ((localVal & 0x000000C0) >> 6);
}
__INLINE uint8_t uart_iir__iid__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_IIR_REG(reg_idx);
return ((localVal & 0x0000000F) >> 0);
}
/**
* @brief UART_FCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:06 RCVR_Trigger 0x0
* 05:04 TX_Empty_Trigger 0x0
* 02 XMIT_FIFO_Reset 0
* 01 RCVR_FIFO_Reset 0
* 00 FIFO_ENABLE 0
* </pre>
*/
#define UART_FCR_REG(i) (* ((volatile uint32_t *)(0x40010008 + uart_offset[i])) )
#define UART_FCR_ADDR(i) (0x40010008 + uart_offset[i])
#define UART_FCR_OFFSET 0x00000008
__INLINE void uart_fcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_FCR_REG(reg_idx) = value;
}
// field definitions
#define RCVR__TRIGGER_MASK 0x000000C0
#define RCVR__TRIGGER_LSB 6
#define RCVR__TRIGGER_WIDTH 0x00000002
#define TX__EMPTY__TRIGGER_MASK 0x00000030
#define TX__EMPTY__TRIGGER_LSB 4
#define TX__EMPTY__TRIGGER_WIDTH 0x00000002
#define XMIT_FIFO__RESET_BIT 0x00000004
#define XMIT_FIFO__RESET_POS 2
#define RCVR_FIFO__RESET_BIT 0x00000002
#define RCVR_FIFO__RESET_POS 1
#define FIFO_ENABLE_BIT 0x00000001
#define FIFO_ENABLE_POS 0
#define RCVR__TRIGGER_RST 0x0
#define TX__EMPTY__TRIGGER_RST 0x0
#define XMIT_FIFO__RESET_RST 0x0
#define RCVR_FIFO__RESET_RST 0x0
#define FIFO_ENABLE_RST 0x0
__INLINE void uart_fcr_pack(uint32_t reg_idx, uint8_t rcvr_trigger, uint8_t tx_empty_trigger, uint8_t xmit_fifo_reset, uint8_t rcvr_fifo_reset, uint8_t fifo_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((rcvr_trigger << 6) & ~0x000000C0) == 0);
ASSERT_ERR(((tx_empty_trigger << 4) & ~0x00000030) == 0);
ASSERT_ERR(((xmit_fifo_reset << 2) & ~0x00000004) == 0);
ASSERT_ERR(((rcvr_fifo_reset << 1) & ~0x00000002) == 0);
ASSERT_ERR(((fifo_enable << 0) & ~0x00000001) == 0);
UART_FCR_REG(reg_idx) = (rcvr_trigger << 6) | (tx_empty_trigger << 4) | (xmit_fifo_reset << 2) | (rcvr_fifo_reset << 1) | (fifo_enable << 0);
}
__INLINE void uart_fcr__rcvr__trigger__setf(uint32_t reg_idx, uint8_t rcvr_trigger)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((rcvr_trigger << 6) & ~0x000000C0) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x000000C0) | (rcvr_trigger << 6);
}
__INLINE void uart_fcr__tx__empty__trigger__setf(uint32_t reg_idx, uint8_t tx_empty_trigger)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((tx_empty_trigger << 4) & ~0x00000030) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x00000030) | (tx_empty_trigger << 4);
}
__INLINE void uart_fcr__xmit_fifo__reset__setf(uint32_t reg_idx, uint8_t xmit_fifo_reset)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((xmit_fifo_reset << 2) & ~0x00000004) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x00000004) | (xmit_fifo_reset << 2);
}
__INLINE void uart_fcr__rcvr_fifo__reset__setf(uint32_t reg_idx, uint8_t rcvr_fifo_reset)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((rcvr_fifo_reset << 1) & ~0x00000002) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x00000002) | (rcvr_fifo_reset << 1);
}
__INLINE void uart_fcr__fifo_enable__setf(uint32_t reg_idx, uint8_t fifo_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((fifo_enable << 0) & ~0x00000001) == 0);
UART_FCR_REG(reg_idx) = (UART_FCR_REG(reg_idx) & ~0x00000001) | (fifo_enable << 0);
}
/**
* @brief UART_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07 DLAB 0
* 06 Brk 0
* 04 EPS 0
* 03 PEN 0
* 02 STOP 0
* 01:00 CLS 0x0
* </pre>
*/
#define UART_TCR_REG(i) (* ((volatile uint32_t *)(0x4001000C + uart_offset[i])) )
#define UART_TCR_ADDR(i) (0x4001000C + uart_offset[i])
#define UART_TCR_OFFSET 0x0000000C
__INLINE uint32_t uart_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_TCR_REG(reg_idx);
}
__INLINE void uart_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_TCR_REG(reg_idx) = value;
}
// field definitions
#define DLAB_BIT 0x00000080
#define DLAB_POS 7
#define BRK_BIT 0x00000040
#define BRK_POS 6
#define EPS_BIT 0x00000010
#define EPS_POS 4
#define PEN_BIT 0x00000008
#define PEN_POS 3
#define STOP_BIT 0x00000004
#define STOP_POS 2
#define CLS_MASK 0x00000003
#define CLS_LSB 0
#define CLS_WIDTH 0x00000002
#define DLAB_RST 0x0
#define BRK_RST 0x0
#define EPS_RST 0x0
#define PEN_RST 0x0
#define STOP_RST 0x0
#define CLS_RST 0x0
__INLINE void uart_tcr_pack(uint32_t reg_idx, uint8_t dlab, uint8_t brk, uint8_t eps, uint8_t pen, uint8_t stop, uint8_t cls)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dlab << 7) & ~0x00000080) == 0);
ASSERT_ERR(((brk << 6) & ~0x00000040) == 0);
ASSERT_ERR(((eps << 4) & ~0x00000010) == 0);
ASSERT_ERR(((pen << 3) & ~0x00000008) == 0);
ASSERT_ERR(((stop << 2) & ~0x00000004) == 0);
ASSERT_ERR(((cls << 0) & ~0x00000003) == 0);
UART_TCR_REG(reg_idx) = (dlab << 7) | (brk << 6) | (eps << 4) | (pen << 3) | (stop << 2) | (cls << 0);
}
__INLINE void uart_tcr_unpack(uint32_t reg_idx, uint8_t* dlab, uint8_t* brk, uint8_t* eps, uint8_t* pen, uint8_t* stop, uint8_t* cls)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
*dlab = (localVal & 0x00000080) >> 7;
*brk = (localVal & 0x00000040) >> 6;
*eps = (localVal & 0x00000010) >> 4;
*pen = (localVal & 0x00000008) >> 3;
*stop = (localVal & 0x00000004) >> 2;
*cls = (localVal & 0x00000003) >> 0;
}
__INLINE uint8_t uart_tcr__dlab__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000080) >> 7);
}
__INLINE void uart_tcr__dlab__setf(uint32_t reg_idx, uint8_t dlab)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dlab << 7) & ~0x00000080) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000080) | (dlab << 7);
}
__INLINE uint8_t uart_tcr__brk__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000040) >> 6);
}
__INLINE void uart_tcr__brk__setf(uint32_t reg_idx, uint8_t brk)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((brk << 6) & ~0x00000040) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000040) | (brk << 6);
}
__INLINE uint8_t uart_tcr__eps__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE void uart_tcr__eps__setf(uint32_t reg_idx, uint8_t eps)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((eps << 4) & ~0x00000010) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000010) | (eps << 4);
}
__INLINE uint8_t uart_tcr__pen__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE void uart_tcr__pen__setf(uint32_t reg_idx, uint8_t pen)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((pen << 3) & ~0x00000008) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000008) | (pen << 3);
}
__INLINE uint8_t uart_tcr__stop__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void uart_tcr__stop__setf(uint32_t reg_idx, uint8_t stop)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((stop << 2) & ~0x00000004) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000004) | (stop << 2);
}
__INLINE uint8_t uart_tcr__cls__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TCR_REG(reg_idx);
return ((localVal & 0x00000003) >> 0);
}
__INLINE void uart_tcr__cls__setf(uint32_t reg_idx, uint8_t cls)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((cls << 0) & ~0x00000003) == 0);
UART_TCR_REG(reg_idx) = (UART_TCR_REG(reg_idx) & ~0x00000003) | (cls << 0);
}
/**
* @brief UART_MCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05 AFCE 0
* 00 RTS 0
* </pre>
*/
#define UART_MCR_REG(i) (* ((volatile uint32_t *)(0x40010010 + uart_offset[i])) )
#define UART_MCR_ADDR(i) (0x40010010 + uart_offset[i])
#define UART_MCR_OFFSET 0x00000010
__INLINE uint32_t uart_mcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_MCR_REG(reg_idx);
}
__INLINE void uart_mcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
UART_MCR_REG(reg_idx) = value;
}
// field definitions
#define AFCE_BIT 0x00000020
#define AFCE_POS 5
#define RTS_BIT 0x00000001
#define RTS_POS 0
#define AFCE_RST 0x0
#define RTS_RST 0x0
__INLINE void uart_mcr_pack(uint32_t reg_idx, uint8_t afce, uint8_t rts)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((afce << 5) & ~0x00000020) == 0);
ASSERT_ERR(((rts << 0) & ~0x00000001) == 0);
UART_MCR_REG(reg_idx) = (afce << 5) | (rts << 0);
}
__INLINE void uart_mcr_unpack(uint32_t reg_idx, uint8_t* afce, uint8_t* rts)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MCR_REG(reg_idx);
*afce = (localVal & 0x00000020) >> 5;
*rts = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t uart_mcr__afce__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MCR_REG(reg_idx);
return ((localVal & 0x00000020) >> 5);
}
__INLINE void uart_mcr__afce__setf(uint32_t reg_idx, uint8_t afce)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((afce << 5) & ~0x00000020) == 0);
UART_MCR_REG(reg_idx) = (UART_MCR_REG(reg_idx) & ~0x00000020) | (afce << 5);
}
__INLINE uint8_t uart_mcr__rts__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void uart_mcr__rts__setf(uint32_t reg_idx, uint8_t rts)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((rts << 0) & ~0x00000001) == 0);
UART_MCR_REG(reg_idx) = (UART_MCR_REG(reg_idx) & ~0x00000001) | (rts << 0);
}
/**
* @brief UART_TSR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07 RX_FIFO_ERROR 0
* 05 THRE 0
* 04 BI 0
* 03 FE 0
* 02 PE 0
* 01 OE 0
* 00 DR 0
* </pre>
*/
#define UART_TSR_REG(i) (* ((volatile uint32_t *)(0x40010014 + uart_offset[i])) )
#define UART_TSR_ADDR(i) (0x40010014 + uart_offset[i])
#define UART_TSR_OFFSET 0x00000014
__INLINE uint32_t uart_tsr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_TSR_REG(reg_idx);
}
// field definitions
#define RX_FIFO_ERROR_BIT 0x00000080
#define RX_FIFO_ERROR_POS 7
#define THRE_BIT 0x00000020
#define THRE_POS 5
#define BI_BIT 0x00000010
#define BI_POS 4
#define FE_BIT 0x00000008
#define FE_POS 3
#define PE_BIT 0x00000004
#define PE_POS 2
#define OE_BIT 0x00000002
#define OE_POS 1
#define DR_BIT 0x00000001
#define DR_POS 0
#define RX_FIFO_ERROR_RST 0x0
#define THRE_RST 0x0
#define BI_RST 0x0
#define FE_RST 0x0
#define PE_RST 0x0
#define OE_RST 0x0
#define DR_RST 0x0
__INLINE void uart_tsr_unpack(uint32_t reg_idx, uint8_t* rx_fifo_error, uint8_t* thre, uint8_t* bi, uint8_t* fe, uint8_t* pe, uint8_t* oe, uint8_t* dr)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
*rx_fifo_error = (localVal & 0x00000080) >> 7;
*thre = (localVal & 0x00000020) >> 5;
*bi = (localVal & 0x00000010) >> 4;
*fe = (localVal & 0x00000008) >> 3;
*pe = (localVal & 0x00000004) >> 2;
*oe = (localVal & 0x00000002) >> 1;
*dr = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t uart_tsr__rx_fifo_error__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000080) >> 7);
}
__INLINE uint8_t uart_tsr__thre__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000020) >> 5);
}
__INLINE uint8_t uart_tsr__bi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t uart_tsr__fe__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE uint8_t uart_tsr__pe__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE uint8_t uart_tsr__oe__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE uint8_t uart_tsr__dr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_TSR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief UART_MSR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 CTS 0
* 00 DCTS 0
* </pre>
*/
#define UART_MSR_REG(i) (* ((volatile uint32_t *)(0x40010018 + uart_offset[i])) )
#define UART_MSR_ADDR(i) (0x40010018 + uart_offset[i])
#define UART_MSR_OFFSET 0x00000018
__INLINE uint32_t uart_msr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_MSR_REG(reg_idx);
}
// field definitions
#define CTS_BIT 0x00000010
#define CTS_POS 4
#define DCTS_BIT 0x00000001
#define DCTS_POS 0
#define CTS_RST 0x0
#define DCTS_RST 0x0
__INLINE void uart_msr_unpack(uint32_t reg_idx, uint8_t* cts, uint8_t* dcts)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MSR_REG(reg_idx);
*cts = (localVal & 0x00000010) >> 4;
*dcts = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t uart_msr__cts__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MSR_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t uart_msr__dcts__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_MSR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief UART_USR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 BUSY 0
* </pre>
*/
#define UART_USR_REG(i) (* ((volatile uint32_t *)(0x4001007C + uart_offset[i])) )
#define UART_USR_ADDR(i) (0x4001007C + uart_offset[i])
#define UART_USR_OFFSET 0x0000007C
__INLINE uint32_t uart_usr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return UART_USR_REG(reg_idx);
}
// field definitions
#define BUSY_BIT 0x00000001
#define BUSY_POS 0
#define BUSY_RST 0x0
__INLINE uint8_t uart_usr__busy__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = UART_USR_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_UART_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_wdt.h
+270
View File
@@ -0,0 +1,270 @@
#ifndef _XC_REG_WDT_H_
#define _XC_REG_WDT_H_
#include <stdint.h>
#define XC_REG_WDT_BASE_ADDR 0x40004000
#define XC_REG_WDT_DECODING_MASK 0x0000001F
/**
* @brief WDT_CR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04:02 WDT_RPL 0x0
* 01 WDT_RMOD 0
* 00 WDT_EN 0
* </pre>
*/
#define WDT_CR_REG (*(volatile uint32_t *)(0x40004000))
#define WDT_CR_ADDR 0x40004000
#define WDT_CR_OFFSET 0x00000000
__INLINE uint32_t wdt_cr_get(void)
{
return WDT_CR_REG;
}
__INLINE void wdt_cr_set(uint32_t value)
{
WDT_CR_REG = value;
}
// field definitions
#define WDT_RPL_MASK 0x0000001C
#define WDT_RPL_LSB 2
#define WDT_RPL_WIDTH 0x00000003
#define WDT_RMOD_BIT 0x00000002
#define WDT_RMOD_POS 1
#define WDT_EN_BIT 0x00000001
#define WDT_EN_POS 0
#define WDT_RPL_RST 0x0
#define WDT_RMOD_RST 0x0
#define WDT_EN_RST 0x0
__INLINE void wdt_cr_pack(uint8_t wdt_rpl, uint8_t wdt_rmod, uint8_t wdt_en)
{
ASSERT_ERR(((wdt_rpl << 2) & ~0x0000001C) == 0);
ASSERT_ERR(((wdt_rmod << 1) & ~0x00000002) == 0);
ASSERT_ERR(((wdt_en << 0) & ~0x00000001) == 0);
WDT_CR_REG = (wdt_rpl << 2) | (wdt_rmod << 1) | (wdt_en << 0);
}
__INLINE void wdt_cr_unpack(uint8_t* wdt_rpl, uint8_t* wdt_rmod, uint8_t* wdt_en)
{
uint32_t localVal = WDT_CR_REG;
*wdt_rpl = (localVal & 0x0000001C) >> 2;
*wdt_rmod = (localVal & 0x00000002) >> 1;
*wdt_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t wdt_cr__wdt_rpl__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x0000001C) >> 2);
}
__INLINE void wdt_cr__wdt_rpl__setf(uint8_t wdt_rpl)
{
ASSERT_ERR(((wdt_rpl << 2) & ~0x0000001C) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x0000001C) | (wdt_rpl << 2);
}
__INLINE uint8_t wdt_cr__wdt_rmod__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void wdt_cr__wdt_rmod__setf(uint8_t wdt_rmod)
{
ASSERT_ERR(((wdt_rmod << 1) & ~0x00000002) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x00000002) | (wdt_rmod << 1);
}
__INLINE uint8_t wdt_cr__wdt_en__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void wdt_cr__wdt_en__setf(uint8_t wdt_en)
{
ASSERT_ERR(((wdt_en << 0) & ~0x00000001) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x00000001) | (wdt_en << 0);
}
/**
* @brief WDT_TORR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03:00 WDT_TOP 0x0
* </pre>
*/
#define WDT_TORR_REG (*(volatile uint32_t *)(0x40004004))
#define WDT_TORR_ADDR 0x40004004
#define WDT_TORR_OFFSET 0x00000004
__INLINE uint32_t wdt_torr_get(void)
{
return WDT_TORR_REG;
}
__INLINE void wdt_torr_set(uint32_t value)
{
WDT_TORR_REG = value;
}
// field definitions
#define WDT_TOP_MASK 0x0000000F
#define WDT_TOP_LSB 0
#define WDT_TOP_WIDTH 0x00000004
#define WDT_TOP_RST 0x0
__INLINE uint8_t wdt_torr__wdt_top__getf(void)
{
uint32_t localVal = WDT_TORR_REG;
ASSERT_ERR((localVal & ~0x0000000F) == 0);
return (localVal >> 0);
}
__INLINE void wdt_torr__wdt_top__setf(uint8_t wdt_top)
{
ASSERT_ERR(((wdt_top << 0) & ~0x0000000F) == 0);
WDT_TORR_REG = wdt_top << 0;
}
/**
* @brief WDT_CCVR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 WDT_CCVR 0x0
* </pre>
*/
#define WDT_CCVR_REG (*(volatile uint32_t *)(0x40004008))
#define WDT_CCVR_ADDR 0x40004008
#define WDT_CCVR_OFFSET 0x00000008
__INLINE uint32_t wdt_ccvr_get(void)
{
return WDT_CCVR_REG;
}
__INLINE void wdt_ccvr_set(uint32_t value)
{
WDT_CCVR_REG = value;
}
// field definitions
#define WDT_CCVR_MASK 0xFFFFFFFF
#define WDT_CCVR_LSB 0
#define WDT_CCVR_WIDTH 0x00000020
#define WDT_CCVR_RST 0x0
__INLINE uint32_t wdt_ccvr__getf(void)
{
uint32_t localVal = WDT_CCVR_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief WDT_CRR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 WDT_CRR 0x0
* </pre>
*/
#define WDT_CRR_REG (*(volatile uint32_t *)(0x4000400C))
#define WDT_CRR_ADDR 0x4000400C
#define WDT_CRR_OFFSET 0x0000000C
__INLINE void wdt_crr_set(uint32_t value)
{
WDT_CRR_REG = value;
}
// field definitions
#define WDT_CRR_MASK 0x000000FF
#define WDT_CRR_LSB 0
#define WDT_CRR_WIDTH 0x00000008
#define WDT_CRR_RST 0x0
__INLINE void wdt_crr__setf(uint8_t wdt_crr)
{
ASSERT_ERR(((wdt_crr << 0) & ~0x000000FF) == 0);
WDT_CRR_REG = wdt_crr << 0;
}
/**
* @brief WDT_STAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 WDT_STAT 0
* </pre>
*/
#define WDT_STAT_REG (*(volatile uint32_t *)(0x40004010))
#define WDT_STAT_ADDR 0x40004010
#define WDT_STAT_OFFSET 0x00000010
__INLINE uint32_t wdt_stat_get(void)
{
return WDT_STAT_REG;
}
// field definitions
#define WDT_STAT_BIT 0x00000001
#define WDT_STAT_POS 0
#define WDT_STAT_RST 0x0
__INLINE uint8_t wdt_stat__getf(void)
{
uint32_t localVal = WDT_STAT_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief WDT_ICR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 WDT_ICR 0
* </pre>
*/
#define WDT_ICR_REG (*(volatile uint32_t *)(0x40004014))
#define WDT_ICR_ADDR 0x40004014
#define WDT_ICR_OFFSET 0x00000014
__INLINE uint32_t wdt_icr_get(void)
{
return WDT_ICR_REG;
}
// field definitions
#define WDT_ICR_BIT 0x00000001
#define WDT_ICR_POS 0
#define WDT_ICR_RST 0x0
__INLINE uint8_t wdt_icr__getf(void)
{
uint32_t localVal = WDT_ICR_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_WDT_H_