hpw421初始版本
This commit is contained in:
xushaoxiang
@@ -0,0 +1,234 @@
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;/*****************************************************************************
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; * @file: startup_xinc.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
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; * Device xinc.
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; *****************************************************************************/
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Stack_Size EQU 0x00000600
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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; ToDo: Add here the vectors for the device specific external interrupts handler
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DCD 0 ; 0 BLE Handler
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DCD DMAS_Handler ; 1
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DCD CPR_Handler ; 2
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DCD GPIO_Handler ; 3
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DCD RTC_Handler ; 4
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DCD TIMER0_Handler ; 5
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DCD TIMER1_Handler
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DCD TIMER2_Handler
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DCD TIMER3_Handler
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DCD WDT_Handler
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DCD I2C_Handler
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DCD UART0_Handler
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DCD UART1_Handler
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DCD SPI0_Handler
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DCD SPI1_Handler
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DCD 0
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DCD 0
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DCD GADC_Handler ; 17
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DCD 0 ; 18
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DCD 0 ; 19
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DCD 0 ; 20
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DCD 0 ; 21
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DCD RF24G_Handler ; 22
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DCD PWM_Handler ; 23
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DCD BOR_Handler ; 24
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DCD 0 ; 25
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DCD 0 ; 26
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DCD AOTIMER0_Handler ; 27
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DCD AOTIMER1_Handler ; 28
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DCD CMP_Handler ; 29
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DCD FMC_Handler ; 30
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DCD CAN_Handler ; 31
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR r0, =0x4000013C ; remap
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LDR r1, =0x10000001
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STR r1, [r0]
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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;EXPORT BLE_Handler [WEAK]
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EXPORT DMAS_Handler [WEAK]
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EXPORT CPR_Handler [WEAK]
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EXPORT GPIO_Handler [WEAK]
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EXPORT RTC_Handler [WEAK]
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EXPORT TIMER0_Handler [WEAK]
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EXPORT TIMER1_Handler [WEAK]
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EXPORT TIMER2_Handler [WEAK]
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EXPORT TIMER3_Handler [WEAK]
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EXPORT WDT_Handler [WEAK]
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EXPORT I2C_Handler [WEAK]
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EXPORT UART0_Handler [WEAK]
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EXPORT UART1_Handler [WEAK]
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EXPORT SPI0_Handler [WEAK]
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EXPORT SPI1_Handler [WEAK]
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;EXPORT KBS_Handler [WEAK]
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;EXPORT QDEC_Handler [WEAK]
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EXPORT GADC_Handler [WEAK]
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EXPORT AOTIMER0_Handler [WEAK]
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EXPORT AOTIMER1_Handler [WEAK]
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EXPORT CMP_Handler [WEAK]
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EXPORT FMC_Handler [WEAK]
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EXPORT CAN_Handler [WEAK]
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;EXPORT SIM_Handler [WEAK]
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;EXPORT AES_Handler [WEAK]
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EXPORT PendSV_Handler [WEAK]
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EXPORT SysTick_Handler [WEAK]
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EXPORT RF24G_Handler [WEAK]
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EXPORT PWM_Handler [WEAK]
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EXPORT BOR_Handler [WEAK]
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PendSV_Handler
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SysTick_Handler
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;BLE_Handler
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DMAS_Handler
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CPR_Handler
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GPIO_Handler
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RTC_Handler
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TIMER0_Handler
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TIMER1_Handler
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TIMER2_Handler
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TIMER3_Handler
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WDT_Handler
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I2C_Handler
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UART0_Handler
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UART1_Handler
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SPI0_Handler
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SPI1_Handler
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;KBS_Handler
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;QDEC_Handler
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GADC_Handler
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;SIM_Handler
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;AES_Handler
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AOTIMER0_Handler
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AOTIMER1_Handler
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CMP_Handler
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FMC_Handler
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CAN_Handler
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RF24G_Handler
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PWM_Handler
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BOR_Handler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, = (Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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END
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@@ -0,0 +1,232 @@
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/*!
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* \file system_it_xinc.c
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*
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* \brief Target system interruption implementation
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "system_it_xinc.h"
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/*------------------------------------------------------------------------------------
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Func Prototype
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Functions
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-------------------------------------------------------------------------------------*/
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/**
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****************************************************************************************
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* @brief This function handles NMI exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void NMI_Handler(void)
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{
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/* USER CODE BEGIN NonMaskableInt_IRQn */
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DEBUG("%s\n", __func__);
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/* USER CODE END NonMaskableInt_IRQn */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Hard Fault exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void HardFault_Handler(void)
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{
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/* USER CODE BEGIN HardFault_IRQn */
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DEBUG("%s\n", __func__);
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/* USER CODE END HardFault_IRQn */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Memory Manage exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void MemManage_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Bus Fault exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void BusFault_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Usage Fault exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void UsageFault_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
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||||
while (1)
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{
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}
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}
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/**
|
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****************************************************************************************
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* @brief This function handles SVCall exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void SVC_Handler(void)
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{
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/* USER CODE BEGIN SVCall_IRQn */
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DEBUG("%s\n", __func__);
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/* USER CODE END SVCall_IRQn */
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while (1)
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{
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||||
|
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}
|
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}
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|
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/**
|
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****************************************************************************************
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* @brief This function handles Debug Monitor exception.
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*
|
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* @param[in]
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* @param[in]
|
||||
****************************************************************************************
|
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*/
|
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void DebugMon_Handler(void)
|
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{
|
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
|
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/* USER CODE END */
|
||||
while (1)
|
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{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************
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||||
* @brief This function handles PendSVC exception.
|
||||
*
|
||||
* @param[in]
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||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
||||
void PendSV_Handler(void)
|
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{
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/* USER CODE BEGIN PendSV_IRQn */
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DEBUG("%s\n", __func__);
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||||
/* USER CODE END PendSV_IRQn */
|
||||
while (1)
|
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{
|
||||
|
||||
}
|
||||
}
|
||||
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||||
/****************************** Hard Fault Handler Functions *******************************/
|
||||
/*------------------------------------------------------------------------------------
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Private Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
void HardFault_Handler_c(unsigned int * HardFault_args)
|
||||
{
|
||||
/*栈帧里面内容：*/
|
||||
unsigned int stack_r0; //压栈的 R0
|
||||
unsigned int stack_r1; //压栈的 R1
|
||||
unsigned int stack_r2; //压栈的 R2
|
||||
unsigned int stack_r3; //压栈的 R3
|
||||
unsigned int stack_r12; //压栈的 R12
|
||||
unsigned int stack_lr; //压栈的 lr
|
||||
unsigned int stack_pc; //压栈的 pc
|
||||
unsigned int stack_psr; //压栈的 psr
|
||||
|
||||
stack_r0 = ((unsigned int)HardFault_args[0]);
|
||||
stack_r1 = ((unsigned int)HardFault_args[1]);
|
||||
stack_r2 = ((unsigned int)HardFault_args[2]);
|
||||
stack_r3 = ((unsigned int)HardFault_args[3]);
|
||||
stack_r12 = ((unsigned int)HardFault_args[4]);
|
||||
stack_lr = ((unsigned int)HardFault_args[5]);
|
||||
stack_pc = ((unsigned int)HardFault_args[6]);
|
||||
stack_psr = ((unsigned int)HardFault_args[7]);
|
||||
|
||||
DEBUG("----%s----\n", __func__);
|
||||
DEBUG("R0=%x\n",stack_r0);
|
||||
DEBUG("R1=%x\n",stack_r1);
|
||||
DEBUG("R2=%x\n",stack_r2);
|
||||
DEBUG("R3=%x\n",stack_r3);
|
||||
DEBUG("R12=%x\n",stack_r12);
|
||||
DEBUG("LR[R14]=%x\n",stack_lr);
|
||||
DEBUG("PC[R15]=%x\n",stack_pc);
|
||||
DEBUG("PSR=%x\n",stack_psr);
|
||||
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
|
||||
DEBUG("---------------------------\n");
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*******************************************************************************************/
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
/*!
|
||||
* \file system_it_xinc.h
|
||||
*
|
||||
* \brief The header of system_it_xinc.c
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __SYSTEM_IT_XINC_H__
|
||||
#define __SYSTEM_IT_XINC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "xc6xxx.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
void NMI_Handler( void );
|
||||
void HardFault_Handler( void );
|
||||
void MemManage_Handler( void );
|
||||
void BusFault_Handler( void );
|
||||
void UsageFault_Handler( void );
|
||||
void SVC_Handler( void );
|
||||
void DebugMon_Handler( void );
|
||||
void PendSV_Handler( void );
|
||||
|
||||
void HardFault_Handler_c(unsigned int * HardFault_args);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_IT_XINC_H__ */
|
||||
|
||||
@@ -0,0 +1,113 @@
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system
|
||||
*
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include <stdio.h>
|
||||
|
||||
#include "xc6xxx.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
#define __DEBUG_OUT_PORT 0
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
#define VECTOR_NUM 48
|
||||
|
||||
void set_vector(void)
|
||||
{
|
||||
#if (USE_XIP == 1)
|
||||
__disable_irq();
|
||||
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
|
||||
*_vector_table = (uint32_t *)(0x10000000);
|
||||
i < VECTOR_NUM; i++) // copy vertor table
|
||||
{
|
||||
_vector_table[i] = *Pvector++;
|
||||
}
|
||||
|
||||
*((volatile unsigned int *)(0x4000013C)) = 0x10000001; // inter vertor table remap
|
||||
__enable_irq();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void WDT_ResetInit(void)
|
||||
{
|
||||
cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
|
||||
|
||||
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
|
||||
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
|
||||
|
||||
cpr_rstctl_wdtrst_mask_set((WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
|
||||
|
||||
cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
|
||||
wdt_cr__wdt_en__setf(DISABLE);
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
|
||||
WDT_ResetInit();
|
||||
|
||||
#if (USE_XIP == 1)
|
||||
|
||||
set_vector();
|
||||
#endif
|
||||
}
|
||||
|
||||
__RAM_CODE int sendchar(int c)
|
||||
{
|
||||
unsigned int status;
|
||||
#if (__DEBUG_OUT_PORT == 1)
|
||||
for (;;) {
|
||||
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
|
||||
status &= 0x20;
|
||||
if (status == 0x20)
|
||||
break;
|
||||
}
|
||||
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
|
||||
return (1);
|
||||
#else
|
||||
for (;;) {
|
||||
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
|
||||
status &= 0x20;
|
||||
if (status == 0x20)
|
||||
break;
|
||||
}
|
||||
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
|
||||
return (1);
|
||||
#endif
|
||||
}
|
||||
|
||||
struct __FILE
|
||||
{
|
||||
int handle; /* Add whatever you need here */
|
||||
};
|
||||
|
||||
FILE __stdout;
|
||||
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
|
||||
|
||||
int ferror(FILE *f)
|
||||
{
|
||||
/* Your implementation of ferror */
|
||||
return EOF;
|
||||
}
|
||||
|
||||
void _ttywrch(int ch) { sendchar(ch); }
|
||||
|
||||
void _sys_exit(int return_code)
|
||||
{
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
@@ -0,0 +1,256 @@
|
||||
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_xinc.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
|
||||
; * Device xinc.
|
||||
; *****************************************************************************/
|
||||
|
||||
Stack_Size EQU 0x00001800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; ToDo: Add here the vectors for the device specific external interrupts handler
|
||||
DCD BLE_Handler ; 0
|
||||
DCD DMA_Handler ; 1
|
||||
DCD CPR_Handler ; 2
|
||||
DCD GPIO_Handler ; 3
|
||||
DCD RTC_Handler ; 4
|
||||
DCD TIMER0_Handler ; 5
|
||||
DCD TIMER1_Handler ; 6
|
||||
DCD TIMER2_Handler ; 7
|
||||
DCD TIMER3_Handler ; 8
|
||||
DCD WDT_Handler ; 9
|
||||
DCD I2C_Handler ; 10
|
||||
DCD UART0_Handler ; 11
|
||||
DCD UART1_Handler ; 12
|
||||
DCD SPI0_Handler ; 13
|
||||
DCD SPI1_Handler ; 14
|
||||
DCD 0 ; 15
|
||||
DCD 0 ; 16
|
||||
DCD GADC_Handler ; 17
|
||||
DCD PWM_Handler ; 18
|
||||
DCD AES_Handler ; 19
|
||||
DCD USB_Handler ; 20
|
||||
DCD AUDIO_Handler ; 21
|
||||
DCD RF24G_Handler ; 22
|
||||
DCD SPI2_Handler ; 23
|
||||
DCD 0 ; 24
|
||||
DCD UART2_Handler ; 25
|
||||
DCD I2S_Handler ; 26
|
||||
DCD AOTIMER0_Handler ; 27
|
||||
DCD AOTIMER1_Handler ; 28
|
||||
DCD CMP_Handler ; 29
|
||||
DCD FMC_Handler ; 30
|
||||
DCD CAN_Handler ; 31
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR r0, =0x4000013C ; remap
|
||||
LDR r1, =0x10000001
|
||||
STR r1, [r0]
|
||||
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
IMPORT HardFault_Handler_c ;函数声明
|
||||
movs r0, #4 ;判断主栈指针还是进程栈指针
|
||||
mov r1, lr
|
||||
tst r0, r1
|
||||
beq hf_used_msp ;如果是主栈指针
|
||||
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
|
||||
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
|
||||
bx r1
|
||||
hf_used_msp
|
||||
mrs r0, msp ;把主栈指针地址赋给 R0
|
||||
ldr r1, =HardFault_Handler_c
|
||||
bx r1
|
||||
;EXPORT HardFault_Handler [WEAK]
|
||||
;B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT BLE_Handler [WEAK]
|
||||
EXPORT DMA_Handler [WEAK]
|
||||
EXPORT CPR_Handler [WEAK]
|
||||
EXPORT GPIO_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT TIMER0_Handler [WEAK]
|
||||
EXPORT TIMER1_Handler [WEAK]
|
||||
EXPORT TIMER2_Handler [WEAK]
|
||||
EXPORT TIMER3_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT I2C_Handler [WEAK]
|
||||
EXPORT UART0_Handler [WEAK]
|
||||
EXPORT UART1_Handler [WEAK]
|
||||
EXPORT SPI0_Handler [WEAK]
|
||||
EXPORT SPI1_Handler [WEAK]
|
||||
;EXPORT KBS_Handler [WEAK]
|
||||
;EXPORT QDEC_Handler [WEAK]
|
||||
EXPORT GADC_Handler [WEAK]
|
||||
EXPORT PWM_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
|
||||
EXPORT USB_Handler [WEAK];20
|
||||
EXPORT AUDIO_Handler [WEAK];21
|
||||
EXPORT RF24G_Handler [WEAK];22
|
||||
EXPORT SPI2_Handler [WEAK];23
|
||||
;EXPORT MPU_Handler [WEAK];24
|
||||
EXPORT UART2_Handler [WEAK];25
|
||||
EXPORT I2S_Handler [WEAK];26
|
||||
EXPORT AOTIMER0_Handler [WEAK];27
|
||||
EXPORT AOTIMER1_Handler [WEAK];28
|
||||
EXPORT CMP_Handler [WEAK];29
|
||||
EXPORT FMC_Handler [WEAK];30
|
||||
EXPORT CAN_Handler [WEAK];31
|
||||
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
BLE_Handler
|
||||
RF24G_Handler
|
||||
DMA_Handler
|
||||
CPR_Handler
|
||||
GPIO_Handler
|
||||
RTC_Handler
|
||||
TIMER0_Handler
|
||||
TIMER1_Handler
|
||||
TIMER2_Handler
|
||||
TIMER3_Handler
|
||||
WDT_Handler
|
||||
I2C_Handler
|
||||
I2S_Handler
|
||||
UART0_Handler
|
||||
UART1_Handler
|
||||
UART2_Handler
|
||||
SPI0_Handler
|
||||
SPI1_Handler
|
||||
SPI2_Handler
|
||||
;KBS_Handler
|
||||
;QDEC_Handler
|
||||
GADC_Handler
|
||||
PWM_Handler
|
||||
AUDIO_Handler
|
||||
;SIM_Handler
|
||||
AES_Handler
|
||||
AOTIMER0_Handler
|
||||
AOTIMER1_Handler
|
||||
CMP_Handler
|
||||
FMC_Handler
|
||||
CAN_Handler
|
||||
USB_Handler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
@@ -0,0 +1,81 @@
|
||||
/*!
|
||||
* \file main.h
|
||||
*
|
||||
* \brief The head file of main.c
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MAIN_H__
|
||||
#define __MAIN_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "xc6xxx.h"
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
#include "rf_config.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
#define DEBUG_LOG
|
||||
|
||||
#define RECV_TIMERMS_OUT 1000
|
||||
#define SEND_TIMERMS_CNT 50
|
||||
//#define XC_SEND_NUM 1000U
|
||||
|
||||
#define RF_TX_TIMERx TIMER0_IDX
|
||||
#define RF_RX_TIMERx TIMER0_IDX
|
||||
|
||||
|
||||
#define RF_CONFIRMED_VALUE 5
|
||||
|
||||
#define RF_SPI_BASR_ADDR 0x3f000 //A multiple of 4096
|
||||
/*------------------------------------------------------------------------------------
|
||||
TypeDef
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Global Variables
|
||||
-------------------------------------------------------------------------------------*/
|
||||
extern uint8_t recv_len;
|
||||
extern uint8_t recv_buf[XINCX_2_4G_PIPE0_LEN];
|
||||
extern bool rf_send_timer_flag;
|
||||
extern bool rf24g_handler_flag;
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
uint32_t rf_2_4g_tx_manage(rf_data_typedef_t *rf_data);
|
||||
uint32_t rf_2_4g_rx_manage(rf_data_typedef_t *rf_data);
|
||||
void rf_2_4g_dump_log(void);
|
||||
uint8_t rf_2_4g_data_config(uint8_t *buff, uint8_t len);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MAIN_H__ */
|
||||
|
||||
@@ -0,0 +1,286 @@
|
||||
|
||||
#ifndef SDK_CONFIG_H
|
||||
#define SDK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>\n
|
||||
|
||||
// <h> Xinc_RF
|
||||
|
||||
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
|
||||
// <0=> TX Mode
|
||||
// <1=> RX Mode
|
||||
#ifndef XINCX_RF_MODE
|
||||
#define XINCX_RF_MODE 0
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_ADDR_L - rf Address Set
|
||||
#ifndef XINCX_2_4G_ADDR_L
|
||||
#define XINCX_2_4G_ADDR_L 0xE7E7E7E6
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_ADDR_H - rf Address Set
|
||||
#ifndef XINCX_2_4G_ADDR_H
|
||||
#define XINCX_2_4G_ADDR_H 0xEA
|
||||
#endif
|
||||
// <h> XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
|
||||
//==========================================================
|
||||
// <o> XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_2_4G_PIPE0_ENAA
|
||||
#define XINCX_2_4G_PIPE0_ENAA 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_2_4G_PIPE1_ENAA
|
||||
#define XINCX_2_4G_PIPE1_ENAA 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_2_4G_PIPE2_ENAA
|
||||
#define XINCX_2_4G_PIPE2_ENAA 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_2_4G_PIPE3_ENAA
|
||||
#define XINCX_2_4G_PIPE3_ENAA 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_2_4G_PIPE4_ENAA
|
||||
#define XINCX_2_4G_PIPE4_ENAA 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_2_4G_PIPE5_ENAA
|
||||
#define XINCX_2_4G_PIPE5_ENAA 1
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <o> XINCX_RF_POWER - rf Power Set
|
||||
#ifndef XINCX_POWER
|
||||
#define XINCX_POWER 0x00008
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
|
||||
#ifndef XINCX_2_4G_CHANNEL
|
||||
#define XINCX_2_4G_CHANNEL 2410
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
|
||||
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_RF_NVIC_MODE
|
||||
#define XINCX_RF_NVIC_MODE 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
|
||||
|
||||
// <3=> 3 Bytes
|
||||
// <4=> 4 Bytes
|
||||
// <5=> 5 Bytes
|
||||
#ifndef XINCX_RF_TX_ADDR_WIDTH
|
||||
#define XINCX_RF_TX_ADDR_WIDTH 5
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
|
||||
|
||||
// <0x02=> 1M
|
||||
// <0x0A=> 2M
|
||||
// <0x22=> 250k
|
||||
// <0x2A=> 125k
|
||||
#ifndef XINCX_RF_TRANS_RATE
|
||||
#define XINCX_RF_TRANS_RATE 0x02
|
||||
#endif
|
||||
|
||||
// <e> XINCX_RF_CRC_ENABLE - RF CRC Enable
|
||||
//==========================================================
|
||||
#ifndef XINCX_RF_CRC_ENABLE
|
||||
#define XINCX_RF_CRC_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
|
||||
|
||||
// <1=> 1 Byte
|
||||
// <2=> 2 Bytes
|
||||
#ifndef XINCX_2_4G_CRC_BYTE
|
||||
#define XINCX_2_4G_CRC_BYTE 2
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <h> XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
|
||||
//==========================================================
|
||||
|
||||
// <q> XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
|
||||
#ifndef XINCX_2_4G_GUARD_CFG
|
||||
#define XINCX_2_4G_GUARD_CFG 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
|
||||
#ifndef XINCX_2_4G_LONG_PLD_TYPE
|
||||
#define XINCX_2_4G_LONG_PLD_TYPE 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
|
||||
// <o> XINCX_2_4G_PREAMBLE_NUM
|
||||
// <0=> 1 Byte
|
||||
// <1=> 2 Bytes
|
||||
// <2=> 3 Bytes
|
||||
// <3=> 4 Bytes
|
||||
#ifndef XINCX_2_4G_PREAMBLE_NUM
|
||||
#define XINCX_2_4G_PREAMBLE_NUM 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
|
||||
#ifndef XINCX_2_4G_PREAMBLE_TYPE
|
||||
#define XINCX_2_4G_PREAMBLE_TYPE 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
|
||||
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
|
||||
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
|
||||
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
|
||||
#ifndef XINCX_2_4G_LONG_PLD
|
||||
#define XINCX_2_4G_LONG_PLD 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
|
||||
#ifndef XINCX_2_4G_FEC
|
||||
#define XINCX_2_4G_FEC 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
|
||||
#ifndef XINCX_2_4G_WHITEN
|
||||
#define XINCX_2_4G_WHITEN 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
|
||||
#ifndef XINCX_2_4G_DPL
|
||||
#define XINCX_2_4G_DPL 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
|
||||
#ifndef XINCX_2_4G_ACK_PAY
|
||||
#define XINCX_2_4G_ACK_PAY 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
|
||||
#ifndef XINCX_2_4G_DYN_ACK
|
||||
#define XINCX_2_4G_DYN_ACK 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <h> XINCX_2_4G_PREAMBLE - 2.4g preamble
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_2_4G_PREAMBLE - 2.4g preamble
|
||||
#ifndef XINCX_2_4G_PREAMBLE
|
||||
#define XINCX_2_4G_PREAMBLE 0x710f5555
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> XINCX_2_4G_GUARD - 2.4g guard
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_2_4G_GUARD - 2.4g guard
|
||||
#ifndef XINCX_2_4G_GUARD
|
||||
#define XINCX_2_4G_GUARD 0x8fc9
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> XINCX_2_4G_DYNPD - 2.4g dynpd
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_2_4G_DYNPD - 2.4g dynpd
|
||||
#ifndef XINCX_2_4G_DYNPD
|
||||
#define XINCX_2_4G_DYNPD 0x3f
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
|
||||
// <h> XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
|
||||
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
|
||||
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
|
||||
#endif
|
||||
// </h>
|
||||
|
||||
// <h> XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
|
||||
#ifndef XINCX_2_4G_RETRANS_CNT
|
||||
#define XINCX_2_4G_RETRANS_CNT 0
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
|
||||
#ifndef XINCX_2_4G_RETRANS_DELAY
|
||||
#define XINCX_2_4G_RETRANS_DELAY 3
|
||||
#endif
|
||||
|
||||
// <h> XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
|
||||
//==========================================================
|
||||
// <o> - 2.4g Pipe0 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE0_LEN
|
||||
#define XINCX_2_4G_PIPE0_LEN 32
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE1_LEN
|
||||
#define XINCX_2_4G_PIPE1_LEN 32
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE2_LEN
|
||||
#define XINCX_2_4G_PIPE2_LEN 32
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE3_LEN
|
||||
#define XINCX_2_4G_PIPE3_LEN 32
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE4_LEN
|
||||
#define XINCX_2_4G_PIPE4_LEN 32
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE5_LEN
|
||||
#define XINCX_2_4G_PIPE5_LEN 32
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,579 @@
|
||||
/*!
|
||||
* \file main.c
|
||||
*
|
||||
* \brief Target main implementation
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Global Variables
|
||||
-------------------------------------------------------------------------------------*/
|
||||
#if !USE_XIP
|
||||
uint8_t spi_idx = SPI0_IDX;
|
||||
#else
|
||||
uint8_t spi_idx = SPI1_IDX;
|
||||
#endif
|
||||
uint8_t rx_flash_buff[BUFF_LEN] = {0};
|
||||
uint8_t rx_timerout_flag = false;
|
||||
uint32_t recv_count = 0;
|
||||
uint32_t recv_err_cnt = 0;
|
||||
uint8_t send_spi_buff[BUFF_LEN] = {0};
|
||||
|
||||
bool rf_send_timer_flag = false;
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Func Prototype
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @brief
|
||||
*
|
||||
* @param[in]
|
||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @brief Clock Initialization
|
||||
*
|
||||
* @param[in]
|
||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
||||
void clock_init(void)
|
||||
{
|
||||
CLOCK_InitCfg_t clock_cfg;
|
||||
|
||||
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
|
||||
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
|
||||
#if (RC_32K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
|
||||
#endif //(RC_32K)
|
||||
|
||||
#if (XTAL_32K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
|
||||
#endif // (XTAL_32K)
|
||||
|
||||
#if (XTAL_32768K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
|
||||
#endif // (XTAL_32768K)
|
||||
|
||||
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
|
||||
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
|
||||
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
|
||||
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
|
||||
}
|
||||
|
||||
xc_clock_init_cfg(&clock_cfg);
|
||||
|
||||
SysTick_Config(xc_clock_hfclk_in_get() / 100);
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Timer0_Callback
|
||||
* @param void * - context
|
||||
*
|
||||
* @retval void
|
||||
*/
|
||||
void timer0_callback(void *context)
|
||||
{
|
||||
#if !(XINCX_RF_MODE)
|
||||
rf_send_timer_flag = true;
|
||||
#else
|
||||
rx_timerout_flag = true;
|
||||
#endif //!(XINCX_RF_MODE)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief timer init
|
||||
* @param TIMER_TypeDef * - timer_id
|
||||
* @param uint32_t - timer_cnt
|
||||
* @retval void
|
||||
*/
|
||||
void timer_init(uint8_t timer_id, uint32_t timer_cnt)
|
||||
{
|
||||
Timer_InitCfg_t timer_cfg;
|
||||
|
||||
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32M_DIV;
|
||||
timer_cfg.timer_div_clk = TIMER_DIV_CLK_16MHzOr16K;
|
||||
timer_cfg.timer_mode = TIMER_MODE_CYCLE;
|
||||
|
||||
xc_timer_init(timer_id, &timer_cfg);
|
||||
#if !(XINCX_RF_MODE)
|
||||
uint32_t Us = timer_cnt * 1000;
|
||||
xc_timer_set_value(timer_id, Us);
|
||||
xc_timer_start(timer_id);
|
||||
#endif //!(XINCX_RF_MODE)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g dump log
|
||||
* @param void
|
||||
*
|
||||
* @retval void
|
||||
*/
|
||||
#ifdef DEBUG_LOG
|
||||
void rf_dump_log(void)
|
||||
{
|
||||
LOGI("***************** 2.4G Param ******************\n");
|
||||
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
|
||||
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
|
||||
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
|
||||
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
|
||||
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
|
||||
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
|
||||
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
|
||||
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
|
||||
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
|
||||
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
|
||||
LOGI("RX_ADDR_P0: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
|
||||
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
|
||||
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
|
||||
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
|
||||
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
|
||||
LOGI("PGA_SETTING: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
|
||||
LOGI("TX_ADDR: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
|
||||
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
|
||||
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
|
||||
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
|
||||
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
|
||||
LOGI("RXPROC_CFG: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
|
||||
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
|
||||
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
|
||||
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
|
||||
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
|
||||
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
|
||||
LOGI("***********************************************\n");
|
||||
LOGI("\r\n");
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* @brief RF 2.4g data config
|
||||
* @param uint8_t * - buff
|
||||
* uint8 - len
|
||||
* @retval uint8_t - 0
|
||||
*/
|
||||
uint8_t rf_data_config(uint8_t *buff, uint8_t len)
|
||||
{
|
||||
if (len == 0) {
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
for (uint8_t i = 0; i < len; i++) {
|
||||
buff[i] = i;
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Spi init
|
||||
* @param void
|
||||
* @retval void
|
||||
*/
|
||||
void rf_spi_init(void)
|
||||
{
|
||||
|
||||
#if (!USE_XIP)
|
||||
SPI_InitCfg_t spi_cfg = {0};
|
||||
|
||||
if (spi_idx == SPI1_IDX) {
|
||||
GPIO_InitCfg_t gpio_cfg = {0};
|
||||
|
||||
gpio_cfg.Mux = GPIO_Mux0;
|
||||
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
|
||||
gpio_cfg.FunSel = SSI1_CLK;
|
||||
gpio_cfg.Int = NOT_INT;
|
||||
gpio_cfg.Pull = GPIO_PULLDOWN;
|
||||
gpio_cfg.Pin = GPIO_14;
|
||||
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.FunSel = SSI1_SSN;
|
||||
gpio_cfg.Pin = GPIO_15;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.FunSel = SSI1_TX;
|
||||
gpio_cfg.Pin = GPIO_16;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.FunSel = SSI1_RX;
|
||||
gpio_cfg.Pin = GPIO_17;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
} else if (spi_idx == SPI2_IDX) {
|
||||
GPIO_InitCfg_t gpio_cfg = {0};
|
||||
|
||||
gpio_cfg.Mux = GPIO_Mux2;
|
||||
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
|
||||
gpio_cfg.FunSel = GPIO_Dx;
|
||||
gpio_cfg.Int = NOT_INT;
|
||||
gpio_cfg.Pull = GPIO_PULLDOWN;
|
||||
gpio_cfg.Pin = GPIO_14; // clk
|
||||
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.FunSel = GPIO_Dx;
|
||||
gpio_cfg.Pin = GPIO_15; // ssn
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.FunSel = GPIO_Dx;
|
||||
gpio_cfg.Pin = GPIO_16;
|
||||
xc_gpio_init(&gpio_cfg); // mosi
|
||||
|
||||
gpio_cfg.FunSel = GPIO_Dx;
|
||||
gpio_cfg.Pin = GPIO_17;
|
||||
xc_gpio_init(&gpio_cfg); // miso
|
||||
}
|
||||
|
||||
spi_cfg.Mode = SPI_MODE_MASTER;
|
||||
spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
|
||||
spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
|
||||
spi_cfg.BaudRatePrescaler = SSI_BAUD_DIV_2;
|
||||
spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
|
||||
spi_cfg.CLKPhase = SSI_CTRL0_SCPHA_LEAD;
|
||||
spi_cfg.FirstBit = SPI_FirstBit_MSB;
|
||||
|
||||
xc_spi_init(spi_idx, &spi_cfg);
|
||||
|
||||
xc_spi_flash_wake_up(spi_idx);
|
||||
uint32_t mid = 0;
|
||||
xc_spi_flash_rdid(spi_idx, (uint8_t *)&mid);
|
||||
PRINT("Flash RDID: 0x%08x\n", mid);
|
||||
|
||||
uint8_t ruid[16];
|
||||
xc_spi_flash_read_128bit_uid(spi_idx, ruid);
|
||||
#else
|
||||
xc_fmc_spi_init_oprt();
|
||||
|
||||
xc_fmc_spi_flash_wake_up();
|
||||
uint32_t mid = 0;
|
||||
xc_fmc_spi_flash_rdid((uint8_t *)&mid);
|
||||
PRINT("Flash RDID: 0x%08x\n", mid);
|
||||
|
||||
uint8_t ruid[16];
|
||||
xc_fmc_spi_flash_ruid(ruid);
|
||||
#endif //(!USE_XIP)
|
||||
PRINT("Flash RUID: ");
|
||||
for (int i = 0; i < 16; i++) {
|
||||
LOGI("%02x ", ruid[i]);
|
||||
}
|
||||
LOGI("\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g tx manage
|
||||
* @param rf_data_typedef_t * - rf_data
|
||||
* @retval uint8_t - cnt
|
||||
*/
|
||||
uint32_t rf_tx_manage(rf_data_typedef_t *rf_data)
|
||||
{
|
||||
#ifdef XC_SEND_NUM // Limited number of transmissions
|
||||
if (rf_data->cnt == XC_SEND_NUM) {
|
||||
rf_data->cnt += 1;
|
||||
LOGI("SEND END\r\n");
|
||||
|
||||
/* Turn off the send timer */
|
||||
xc_timer_stop(RF_TX_TIMERx);
|
||||
}
|
||||
if ((rf_data->cnt < XC_SEND_NUM) && (rf_send_timer_flag)) {
|
||||
#else // Timed transmission
|
||||
if (rf_send_timer_flag) {
|
||||
#endif // XC_SEND_NUM
|
||||
rf_send_timer_flag = false;
|
||||
GLOBAL_INT_DISABLE();
|
||||
#if (!USE_XIP)
|
||||
xc_spi_flash_read(spi_idx, RF_SPI_BASR_ADDR, rf_data->buff, sizeof(rf_data->buff));
|
||||
#else
|
||||
xc_fmc_spi_flash_read(RF_SPI_BASR_ADDR, rf_data->buff, sizeof(rf_data->buff));
|
||||
#endif //(!USE_XIP)
|
||||
|
||||
GLOBAL_INT_RESTORE();
|
||||
rf_data_config(rf_data->buff, sizeof(rf_data->buff));
|
||||
/* Filling in software frame number */
|
||||
rf_data->cnt += 1;
|
||||
rf_data->buff[0] = rf_data->cnt;
|
||||
LOGI("send_cnt:%d\r\n", rf_data->cnt);
|
||||
|
||||
/* Data transmission */
|
||||
for (uint8_t i = 0; i < sizeof(rf_data->buff); i++)
|
||||
LOGI("%02x ", rf_data->buff[i]);
|
||||
LOGI("\r\n");
|
||||
rf_tx_event(rf_data->buff, BUFF_LEN);
|
||||
memcpy(send_spi_buff, rf_data->buff, sizeof(rf_data->buff));
|
||||
|
||||
/* Operating Flash*/
|
||||
GLOBAL_INT_DISABLE();
|
||||
#if (!USE_XIP)
|
||||
xc_spi_flash_erase_sector(spi_idx, RF_SPI_BASR_ADDR);
|
||||
xc_spi_flash_write(spi_idx, RF_SPI_BASR_ADDR, send_spi_buff, sizeof(send_spi_buff));
|
||||
xc_spi_flash_read(spi_idx, RF_SPI_BASR_ADDR, rf_data->buff, sizeof(rf_data->buff));
|
||||
#else
|
||||
xc_fmc_spi_flash_erase_sector(RF_SPI_BASR_ADDR);
|
||||
xc_fmc_spi_flash_write(RF_SPI_BASR_ADDR, send_spi_buff, sizeof(send_spi_buff));
|
||||
xc_fmc_spi_flash_read(RF_SPI_BASR_ADDR, rf_data->buff, sizeof(rf_data->buff));
|
||||
#endif //(!USE_XIP)
|
||||
GLOBAL_INT_RESTORE();
|
||||
}
|
||||
return rf_data->cnt;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g rx manage
|
||||
* @param rf_data_typedef_t * - rf_data
|
||||
* @retval uint32_t - 0
|
||||
*/
|
||||
#if !(XINCX_RF_NVIC_MODE)
|
||||
uint32_t rf_rx_manage(rf_data_typedef_t *rf_data)
|
||||
{
|
||||
static uint32_t conut = 0;
|
||||
|
||||
/* Receive event processing */
|
||||
uint8_t len = rf_rx_event(rf_data->buff);
|
||||
|
||||
/* Receiving end polling data processing */
|
||||
if (len != 0) {
|
||||
/* Receive Count */
|
||||
CE_CTL_LOW;
|
||||
|
||||
/* Receive Count */
|
||||
conut += 1;
|
||||
|
||||
/* Receiving data processing */
|
||||
if (rf_data->buff[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE) {
|
||||
PRINT("%d\r\n", conut);
|
||||
GLOBAL_INT_DISABLE();
|
||||
#if (!USE_XIP)
|
||||
xc_spi_flash_erase_sector(spi_idx, RF_SPI_BASR_ADDR);
|
||||
xc_spi_flash_write(spi_idx, RF_SPI_BASR_ADDR, rf_data->buff, sizeof(rf_data->buff));
|
||||
xc_spi_flash_read(spi_idx, RF_SPI_BASR_ADDR, rx_flash_buff, sizeof(rx_flash_buff));
|
||||
#else
|
||||
xc_fmc_spi_flash_erase_sector(RF_SPI_BASR_ADDR);
|
||||
xc_fmc_spi_flash_write(RF_SPI_BASR_ADDR, rf_data->buff, sizeof(recv_buf));
|
||||
xc_fmc_spi_flash_read(RF_SPI_BASR_ADDR, rx_flash_buff, sizeof(rx_flash_buff));
|
||||
#endif //(USE_XIP)
|
||||
GLOBAL_INT_RESTORE();
|
||||
|
||||
recv_count += 1;
|
||||
} else {
|
||||
recv_err_cnt += 1;
|
||||
}
|
||||
|
||||
LOGI("read flash:");
|
||||
for (uint8_t i = 0; i < len; i++) {
|
||||
LOGI("%02x ", rx_flash_buff[i]);
|
||||
}
|
||||
LOGI("\r\n");
|
||||
xc_timer_set_value(RF_RX_TIMERx, 1000 * 1000);
|
||||
xc_timer_start(RF_RX_TIMERx);
|
||||
|
||||
/* Receive read data buffer reset */
|
||||
memset(rf_data->buff, 0, len);
|
||||
memset(rx_flash_buff, 0, sizeof(rx_flash_buff));
|
||||
len = 0;
|
||||
|
||||
/* Entering the receiver */
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
|
||||
if (rx_timerout_flag) {
|
||||
rx_timerout_flag = false;
|
||||
LOGI("recv_count:%d,recv_err_cnt:%d\r\n", recv_count, recv_err_cnt);
|
||||
xc_timer_stop(RF_RX_TIMERx);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
uint32_t rf_rx_manage(rf_data_typedef_t *rf_data)
|
||||
{
|
||||
static uint32_t conut = 0;
|
||||
|
||||
uint8_t len = recv_len;
|
||||
if (rf24g_handler_flag) {
|
||||
rf24g_handler_flag = false;
|
||||
|
||||
/* Entering standby mode */
|
||||
CE_CTL_LOW;
|
||||
if ((len != 0) && (recv_buf[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE)) {
|
||||
recv_count += 1;
|
||||
LOGI("%d\r\n", recv_buf[0]);
|
||||
GLOBAL_INT_DISABLE();
|
||||
#if (!USE_XIP)
|
||||
xc_spi_flash_erase_sector(spi_idx, RF_SPI_BASR_ADDR);
|
||||
xc_spi_flash_write(spi_idx, RF_SPI_BASR_ADDR, recv_buf, sizeof(recv_buf));
|
||||
xc_spi_flash_read(spi_idx, RF_SPI_BASR_ADDR, rx_flash_buff, sizeof(rx_flash_buff));
|
||||
#else
|
||||
xc_fmc_spi_flash_erase_sector(RF_SPI_BASR_ADDR);
|
||||
xc_fmc_spi_flash_write(RF_SPI_BASR_ADDR, recv_buf, sizeof(recv_buf));
|
||||
xc_fmc_spi_flash_read(RF_SPI_BASR_ADDR, rx_flash_buff, sizeof(rx_flash_buff));
|
||||
#endif
|
||||
GLOBAL_INT_RESTORE();
|
||||
|
||||
} else {
|
||||
recv_err_cnt += 1;
|
||||
}
|
||||
LOGI("read flash:");
|
||||
for (uint8_t i = 0; i < len; i++) {
|
||||
LOGI("%02x ", rx_flash_buff[i]);
|
||||
}
|
||||
LOGI("\r\n");
|
||||
xc_timer_set_value(RF_RX_TIMERx, 1000 * 1000);
|
||||
xc_timer_start(RF_RX_TIMERx);
|
||||
|
||||
/* Receive Count */
|
||||
conut += 1;
|
||||
|
||||
/* Receive read data buffer reset */
|
||||
memset(recv_buf, 0, len);
|
||||
memset(rx_flash_buff, 0, sizeof(rx_flash_buff));
|
||||
|
||||
/* Entering the receiver */
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
|
||||
if (rx_timerout_flag) {
|
||||
rx_timerout_flag = false;
|
||||
LOGI("recv_count:%d,recv_err_cnt:%d\r\n", recv_count, recv_err_cnt);
|
||||
xc_timer_stop(RF_RX_TIMERx);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif //!(XINCX_RF_NVIC_MODE)
|
||||
|
||||
void app_uart_init(void)
|
||||
{
|
||||
GPIO_InitCfg_t gpio_cfg = {0};
|
||||
|
||||
gpio_cfg.Mux = GPIO_Mux0;
|
||||
gpio_cfg.Pull = GPIO_PULLUP;
|
||||
gpio_cfg.Int = NOT_INT;
|
||||
gpio_cfg.FunSel = UART0_TX;
|
||||
|
||||
gpio_cfg.Pin = GPIO_18;
|
||||
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.FunSel = UART0_RX;
|
||||
gpio_cfg.Pin = GPIO_19;
|
||||
gpio_cfg.Dir = GPIO_DIR_INPUT;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
UART_InitCfg_t uart_cfg = {0};
|
||||
|
||||
uart_cfg.Parity = UART_PARITY_DISABLE;
|
||||
uart_cfg.StopBits = UART_STOP_1_BITS;
|
||||
uart_cfg.WordLength = UART_DATA_8_BITS;
|
||||
uart_cfg.BaudRate = UART_BAUDRATE_115200;
|
||||
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
|
||||
|
||||
xc_uart_init(UART0_IDX, &uart_cfg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief main
|
||||
* @details
|
||||
* @param[in] void
|
||||
* @param[out] void
|
||||
* @retval int - 0
|
||||
* @retval void
|
||||
* @par identifier
|
||||
* reserve
|
||||
* @par other
|
||||
* void
|
||||
* @par change log
|
||||
* Alex created on 2023-05-31
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
rf_data_typedef_t rf_data;
|
||||
rf_data_config(rf_data.buff, sizeof(rf_data.buff));
|
||||
rf_data.cnt = 0;
|
||||
rf_data.temp = SEND_TIMERMS_CNT;
|
||||
|
||||
/* Clock initialization */
|
||||
clock_init();
|
||||
|
||||
/* Serial port initialization */
|
||||
app_uart_init();
|
||||
|
||||
/* SPI initialization */
|
||||
rf_spi_init();
|
||||
|
||||
/* rf 2.4g initialization configuration */
|
||||
rf24g_init();
|
||||
|
||||
/* Set testing frequency points */
|
||||
rf_set_channel(XINCX_2_4G_CHANNEL);
|
||||
|
||||
#if (XINCX_RF_TRANS_RATE == RATE_2M)
|
||||
/* Set 2M mode register configuration */
|
||||
/* Don't move this function interface */
|
||||
rf_2M_config();
|
||||
#endif //(XINCX_RF_TRANS_RATE == RATE_2M)
|
||||
|
||||
#ifdef DEBUG_LOG
|
||||
/* Register information printing */
|
||||
rf_dump_log();
|
||||
#endif
|
||||
|
||||
#if XINCX_RF_MODE
|
||||
/* Receive timeout setting */
|
||||
timer_init(RF_RX_TIMERx, RECV_TIMERMS_OUT);
|
||||
|
||||
/* Enter receiver mode */
|
||||
CE_CTL_HIGH;
|
||||
#else
|
||||
/* Launch data packaging filling */
|
||||
rf_data_config(rf_data.buff, sizeof(rf_data.buff));
|
||||
#if (!USE_XIP)
|
||||
xc_spi_flash_erase_sector(spi_idx, RF_SPI_BASR_ADDR);
|
||||
xc_spi_flash_write(spi_idx, RF_SPI_BASR_ADDR, rf_data.buff, sizeof(rf_data.buff));
|
||||
#else
|
||||
xc_fmc_spi_flash_erase_sector(RF_SPI_BASR_ADDR);
|
||||
xc_fmc_spi_flash_write(RF_SPI_BASR_ADDR, rf_data.buff, sizeof(rf_data.buff));
|
||||
#endif //(!USE_XIP)
|
||||
/* Set emission interval */
|
||||
timer_init(RF_TX_TIMERx, SEND_TIMERMS_CNT);
|
||||
#endif // XINCX_RF_MODE
|
||||
|
||||
for (;;) {
|
||||
|
||||
#if XINCX_RF_MODE
|
||||
/* receive */
|
||||
rf_rx_manage(&rf_data);
|
||||
#else
|
||||
/* sending */
|
||||
rf_data.cnt = rf_tx_manage(&rf_data);
|
||||
#endif // XINCX_RF_MODE
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
|
||||
FUNC void Initialization(void)
|
||||
{
|
||||
SP = _RDWORD(0x10000000);
|
||||
PC = _RDWORD(0x10000004);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
LOAD %L INCREMENTAL
|
||||
Initialization();
|
||||
@@ -0,0 +1,84 @@
|
||||
|
||||
|
||||
|
||||
FUNC void InitGpio(void)
|
||||
{
|
||||
// Config IOMUX
|
||||
/*
|
||||
gpio_mux_ctl_u(33,1);//d2
|
||||
gpio_mux_ctl_u(34,1);//d3
|
||||
gpio_mux_ctl_u(35,2);//clk
|
||||
gpio_mux_ctl_u(36,2);//cs
|
||||
gpio_mux_ctl_u(37,2);//d0 rx
|
||||
gpio_mux_ctl_u(38,2);//d1 tx
|
||||
*/
|
||||
_WDWORD(0x4000019c, 0x00002A94);
|
||||
}
|
||||
FUNC void InitFlash(void)
|
||||
{
|
||||
|
||||
}
|
||||
FUNC void InitXIP(void)
|
||||
{
|
||||
|
||||
_WDWORD(0x40000104,0x040000);//reset ssi0
|
||||
_WDWORD(0x40000104,0x040004);//reset ssi0
|
||||
_WDWORD(0x40000050,0x110000);//close spi0 mclk
|
||||
_WDWORD(0x40000070,0x1000000);//close spi0 pclk
|
||||
|
||||
|
||||
//config fmc
|
||||
_WDWORD(0x40000270, 0x0503);
|
||||
_Sleep_(1);// delay about 400us
|
||||
_WDWORD(0x40000270, 0x3503);
|
||||
//config cache
|
||||
_Sleep_(1);// delay about 400us
|
||||
_WDWORD(0x52000000, 0x0);
|
||||
_Sleep_(1);// delay about 400us
|
||||
_WDWORD(0x52000000, 0x21);
|
||||
_Sleep_(1);// delay about 400us
|
||||
_Sleep_(1);// delay about 400us
|
||||
_Sleep_(1);// delay about 400us
|
||||
_Sleep_(1);// delay about 400us
|
||||
|
||||
|
||||
//config xip spi
|
||||
_WDWORD(0x51000008, 0); //disable spi
|
||||
|
||||
_WDWORD(0x5100002c,0); //close IE
|
||||
_WDWORD(0x51000000,0x1F); //32bit SPI data
|
||||
_WDWORD(0x51000010,0x01); //enable select slave -- SE
|
||||
_WDWORD(0x51000018,0x0); //TXFTL be set 0
|
||||
_WDWORD(0x5100001c,0x0); //RXFTL be set 0
|
||||
|
||||
_WDWORD(0x5100010c, 0x01);//enable select slave
|
||||
_WDWORD(0x51000114, 0xFF);//XIP time out
|
||||
|
||||
_WDWORD(0x51000014, 0x2);//div 2
|
||||
|
||||
//quad
|
||||
_WDWORD(0x51000108, (2)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0<<24)|(8<<13));
|
||||
_WDWORD(0x51000100, 0x6b);//quad read cmd
|
||||
_WDWORD(0x51000104, 0x6b);//quad read cmd
|
||||
|
||||
|
||||
// //dual
|
||||
// _WDWORD(0x51000108, (1)|(6<<4)|(2<<9)|(1<<22)|(1<<29)|(1<<23)|(0)|(8<<13));
|
||||
// _WDWORD(0x51000100, 0x3b);//dual read cmd
|
||||
// _WDWORD(0x51000104, 0x3b);//dual read cmd
|
||||
|
||||
|
||||
_WDWORD(0x51000008, 1); //enable spi
|
||||
}
|
||||
|
||||
FUNC void Initialization(void)
|
||||
{
|
||||
InitGpio();
|
||||
InitFlash();
|
||||
InitXIP();
|
||||
SP = _RDWORD(0x11001000);
|
||||
PC = _RDWORD(0x11001004);
|
||||
_WDWORD(0x4000013C, 0x11001001);
|
||||
}
|
||||
LOAD %L INCREMENTAL
|
||||
Initialization();
|
||||
@@ -0,0 +1,18 @@
|
||||
|
||||
LOAD 0x10000000
|
||||
{
|
||||
EXE 0x10000000
|
||||
{
|
||||
startup_xinc.o (RESET, +FIRST)
|
||||
* (+RO)
|
||||
|
||||
}
|
||||
|
||||
RW +0000
|
||||
{
|
||||
* (+RW,+ZI)
|
||||
}
|
||||
|
||||
ScatterAssert(ImageLength(RW) < 1024 * 28)
|
||||
}
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
|
||||
|
||||
LOAD 0x11001000
|
||||
{
|
||||
EXE 0x11001000
|
||||
{
|
||||
startup_xinc.o (RESET, +FIRST)
|
||||
* (+RO)
|
||||
|
||||
}
|
||||
|
||||
RW 0x10002000
|
||||
{
|
||||
* (+RW,+ZI)
|
||||
*(ram_code)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1 @@
|
||||
Xincboot_tool.exe 0_ram.bin 1_ram_download.bin 0 0 0 0 1
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
.\Tools\xinchip_xip_tool.exe .\Output\0_ram.bin .\Output\xip_dual .\Output\rf24_ack_flash_xip.bin
|
||||
Binary file not shown.
@@ -0,0 +1,59 @@
|
||||
#!/usr/bin/env python
|
||||
#-*- coding:UTF-8 -*-
|
||||
import socket
|
||||
from select import select
|
||||
import time
|
||||
import os
|
||||
import sys
|
||||
import threading
|
||||
import json
|
||||
import struct
|
||||
import binascii
|
||||
import time
|
||||
import re
|
||||
import fileinput
|
||||
|
||||
|
||||
|
||||
def dump_addr(addr):
|
||||
file_asm = "./Xinc_ble_sdk_asm"
|
||||
cur_func = ""
|
||||
with open(file_asm, 'r') as fd:
|
||||
for line in fd:
|
||||
if re.match(r" \w+", line) != None:
|
||||
cur_func = line.strip()
|
||||
#
|
||||
if re.search("^ 0x", line) != None and re.search(addr, line) != None:
|
||||
print(addr, cur_func)
|
||||
break
|
||||
fd.close()
|
||||
|
||||
if __name__ == "__main__":
|
||||
file_in = "./dump.txt"
|
||||
|
||||
for line in fileinput.input(file_in):
|
||||
# 处理 PC 指针信息
|
||||
if re.search("PC = ", line) != None:
|
||||
pc_addr = line.split("PC = ")[1].split(",")[0]
|
||||
#print(hex(int(pc_addr, 16)))
|
||||
dump_addr(hex(int(pc_addr, 16)))
|
||||
|
||||
# 处理 栈信息
|
||||
if re.search("^[0-9]",line) != None:
|
||||
#print(line)
|
||||
stack = line.split('=')[1].replace('\n', '').split(' ')
|
||||
for addr in stack:
|
||||
if addr == ' ' or re.search("^1", addr) == None:
|
||||
continue
|
||||
#print(addr, hex(int(addr,16)-1))
|
||||
dump_addr(hex(int(addr,16)-1))
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,564 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rf24_ack_flash</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>0</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>0</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Target>
|
||||
<TargetName>rf24_ack_flash_xip_demo</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>0</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Startup</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\CMSIS\core_cm0.h</PathWithFileName>
|
||||
<FilenameWithoutPath>core_cm0.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\app\Startup\xc60xx\startup_xinc.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_xinc.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\app\Startup\system_xinc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_xinc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
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<PathWithFileName>..\app\Startup\system_it_xinc.c</PathWithFileName>
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</Group>
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<Group>
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<GroupName>Application</GroupName>
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<PathWithFileName>..\app\src\main.c</PathWithFileName>
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</Group>
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<Group>
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<tvExp>1</tvExp>
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<tvExp>0</tvExp>
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<bDave2>0</bDave2>
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<tvExp>1</tvExp>
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<bDave2>0</bDave2>
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<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_clock.c</PathWithFileName>
|
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<RteFlg>0</RteFlg>
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<tvExp>0</tvExp>
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<bDave2>0</bDave2>
|
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<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_gpio.c</PathWithFileName>
|
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<FilenameWithoutPath>xc_drv_gpio.c</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
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<bShared>0</bShared>
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<tvExp>0</tvExp>
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<bDave2>0</bDave2>
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|
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<FilenameWithoutPath>xc_drv_pwr.c</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
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<bShared>0</bShared>
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<tvExp>0</tvExp>
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<bDave2>0</bDave2>
|
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<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_spi.c</PathWithFileName>
|
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<FilenameWithoutPath>xc_drv_spi.c</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
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<FileType>1</FileType>
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<tvExp>0</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<bDave2>0</bDave2>
|
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<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_uart.c</PathWithFileName>
|
||||
<FilenameWithoutPath>xc_drv_uart.c</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
|
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<bShared>0</bShared>
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</File>
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<File>
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<GroupNumber>5</GroupNumber>
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|
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<FileType>1</FileType>
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<tvExp>0</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<bDave2>0</bDave2>
|
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<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_timer.c</PathWithFileName>
|
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<FilenameWithoutPath>xc_drv_timer.c</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
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<bShared>0</bShared>
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</File>
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<File>
|
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<FileNumber>14</FileNumber>
|
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<FileType>1</FileType>
|
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<tvExp>0</tvExp>
|
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<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_systick.c</PathWithFileName>
|
||||
<FilenameWithoutPath>xc_drv_systick.c</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
|
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<bShared>0</bShared>
|
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</File>
|
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<File>
|
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<GroupNumber>5</GroupNumber>
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<FileNumber>15</FileNumber>
|
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<FileType>1</FileType>
|
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<tvExp>0</tvExp>
|
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<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\ringbuffer.c</PathWithFileName>
|
||||
<FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
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<bShared>0</bShared>
|
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</File>
|
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<File>
|
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<GroupNumber>5</GroupNumber>
|
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<FileNumber>16</FileNumber>
|
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<FileType>1</FileType>
|
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<tvExp>0</tvExp>
|
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<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_dma.c</PathWithFileName>
|
||||
<FilenameWithoutPath>xc_drv_dma.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
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<bShared>0</bShared>
|
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</File>
|
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<File>
|
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<GroupNumber>5</GroupNumber>
|
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<FileNumber>17</FileNumber>
|
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<FileType>1</FileType>
|
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<tvExp>0</tvExp>
|
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<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\..\component\xc6xx_drivers\Drivers\xc_driver\xc_drv_fmc_spi.c</PathWithFileName>
|
||||
<FilenameWithoutPath>xc_drv_fmc_spi.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user