hpw421初始版本

2026-06-06 16:49:48 +08:00
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+
+#ifndef SDK_CONFIG_H
+#define SDK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>\n
+
+// <h> Xinc_RF
+
+// <o> XINCX_RF_MODE  - RF Tx or Rx Mode
+// <0=> TX Mode
+// <1=> RX Mode
+#ifndef XINCX_RF_MODE
+#define XINCX_RF_MODE 0
+#endif
+
+// <o> XINCX_2_4G_ADDR_L  - rf Address Set
+#ifndef XINCX_2_4G_ADDR_L
+#define XINCX_2_4G_ADDR_L 0xE7E7E7E6
+#endif
+
+// <o> XINCX_2_4G_ADDR_H  - rf Address Set
+#ifndef XINCX_2_4G_ADDR_H
+#define XINCX_2_4G_ADDR_H 0xEA
+#endif
+// <h> XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
+//==========================================================
+// <o> XINCX_2_4G_PIPE0_ENAA  - 2.4g Pipe0 Auto Ack
+// <0=> Disable
+// <1=> Enable
+#ifndef XINCX_2_4G_PIPE0_ENAA
+#define XINCX_2_4G_PIPE0_ENAA 1
+#endif
+
+// <o> XINCX_2_4G_PIPE1_ENAA  - 2.4g Pipe1 Auto Ack
+// <0=> Disable
+// <1=> Enable
+#ifndef XINCX_2_4G_PIPE1_ENAA
+#define XINCX_2_4G_PIPE1_ENAA 1
+#endif
+
+// <o> XINCX_2_4G_PIPE2_ENAA  - 2.4g Pipe2 Auto Ack
+// <0=> Disable
+// <1=> Enable
+#ifndef XINCX_2_4G_PIPE2_ENAA
+#define XINCX_2_4G_PIPE2_ENAA 1
+#endif
+
+// <o> XINCX_2_4G_PIPE3_ENAA  - 2.4g Pipe3 Auto Ack
+// <0=> Disable
+// <1=> Enable
+#ifndef XINCX_2_4G_PIPE3_ENAA
+#define XINCX_2_4G_PIPE3_ENAA 1
+#endif
+
+// <o> XINCX_2_4G_PIPE4_ENAA  - 2.4g Pipe4 Auto Ack
+// <0=> Disable
+// <1=> Enable
+#ifndef XINCX_2_4G_PIPE4_ENAA
+#define XINCX_2_4G_PIPE4_ENAA 1
+#endif
+
+// <o> XINCX_2_4G_PIPE5_ENAA  - 2.4g Pipe5 Auto Ack
+// <0=> Disable
+// <1=> Enable
+#ifndef XINCX_2_4G_PIPE5_ENAA
+#define XINCX_2_4G_PIPE5_ENAA 1
+#endif
+// </h>
+
+// <o> XINCX_RF_POWER  - rf Power Set
+#ifndef XINCX_POWER
+#define XINCX_POWER 0x00008
+#endif
+
+// <o> XINCX_2_4G_CHANNEL  - 2.4g Channel Set
+#ifndef XINCX_2_4G_CHANNEL
+#define XINCX_2_4G_CHANNEL 2410
+#endif
+
+// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
+
+// <0=> Disable
+// <1=> Enable
+#ifndef XINCX_RF_NVIC_MODE
+#define XINCX_RF_NVIC_MODE 1
+#endif
+
+// <o> XINCX_RF_TX_ADDR_WIDTH  - RF Tx Addr Width
+
+// <3=> 3 Bytes
+// <4=> 4 Bytes
+// <5=> 5 Bytes
+#ifndef XINCX_RF_TX_ADDR_WIDTH
+#define XINCX_RF_TX_ADDR_WIDTH 5
+#endif
+
+// <o> XINCX_RF_TRANS_RATE  - RF Transmission Rate Config
+
+// <0x02=> 1M
+// <0x0A=> 2M
+// <0x22=> 250k
+// <0x2A=> 125k
+#ifndef XINCX_RF_TRANS_RATE
+#define XINCX_RF_TRANS_RATE 0x02
+#endif
+
+// <e> XINCX_RF_CRC_ENABLE  - RF CRC Enable
+//==========================================================
+#ifndef XINCX_RF_CRC_ENABLE
+#define XINCX_RF_CRC_ENABLE 1
+#endif
+
+// <o> XINCX_2_4G_CRC_BYTE  - 2.4g CRC Bytes Set
+
+// <1=> 1 Byte
+// <2=> 2 Bytes
+#ifndef XINCX_2_4G_CRC_BYTE
+#define XINCX_2_4G_CRC_BYTE 2
+#endif
+
+// </e>
+
+// <h> XINCX_2_4G_FEATURE_PARAM  - 2.4g Feature Parameters
+//==========================================================
+
+// <q> XINCX_2_4G_GUARD_CFG  - 2.4g Long Payload Feature
+#ifndef XINCX_2_4G_GUARD_CFG
+#define XINCX_2_4G_GUARD_CFG 0
+#endif
+
+// <q> XINCX_2_4G_LONG_PLD_TYPE   - 2.4g Long Pld Type
+#ifndef XINCX_2_4G_LONG_PLD_TYPE
+#define XINCX_2_4G_LONG_PLD_TYPE 0
+#endif
+
+// <q> XINCX_2_4G_PREAMBLE_NUM   - 2.4g Preamble 
+// <o> XINCX_2_4G_PREAMBLE_NUM
+// <0=> 1 Byte
+// <1=> 2 Bytes
+// <2=> 3 Bytes
+// <3=> 4 Bytes
+#ifndef XINCX_2_4G_PREAMBLE_NUM
+#define XINCX_2_4G_PREAMBLE_NUM 0
+#endif
+
+// <q> XINCX_2_4G_PREAMBLE_TYPE   - 2.4g Preamble Type
+#ifndef XINCX_2_4G_PREAMBLE_TYPE
+#define XINCX_2_4G_PREAMBLE_TYPE 0
+#endif
+
+// <q> XINCX_2_4G_CRC_SCOPE_GUARD   - 2.4g CRC Scope Guard
+#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
+#define XINCX_2_4G_CRC_SCOPE_GUARD 0
+#endif
+
+// <q> XINCX_2_4G_CRC_SCOPE_HEADER   - 2.4g CRC Scope Header
+#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
+#define XINCX_2_4G_CRC_SCOPE_HEADER 1
+#endif
+
+// <q> XINCX_2_4G_CRC_SCOPE_ADDR   - 2.4g CRC Scope Addr
+#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
+#define XINCX_2_4G_CRC_SCOPE_ADDR 1
+#endif
+
+// <q> XINCX_2_4G_LONG_PLD  - 2.4g Long Payload Feature
+#ifndef XINCX_2_4G_LONG_PLD
+#define XINCX_2_4G_LONG_PLD 0
+#endif
+
+// <q> XINCX_2_4G_FEC  - 2.4g FEC&Interleave Feature
+#ifndef XINCX_2_4G_FEC
+#define XINCX_2_4G_FEC 1
+#endif
+
+// <q> XINCX_2_4G_WHITEN  - 2.4g Whiten Feature
+#ifndef XINCX_2_4G_WHITEN
+#define XINCX_2_4G_WHITEN 1
+#endif
+
+// <q> XINCX_2_4G_DPL  - 2.4g Dynamic Payload Length Feature
+#ifndef XINCX_2_4G_DPL
+#define XINCX_2_4G_DPL 1
+#endif
+
+// <q> XINCX_2_4G_ACK_PAY  - 2.4g  Payload  on ACK
+#ifndef XINCX_2_4G_ACK_PAY
+#define XINCX_2_4G_ACK_PAY 0
+#endif
+
+// <q> XINCX_2_4G_DYN_ACK  - 2.4g  W_TX_PAYLOAD_NOACK Command
+#ifndef XINCX_2_4G_DYN_ACK
+#define XINCX_2_4G_DYN_ACK 0
+#endif
+
+// </h>
+// </h>
+
+// <h> XINCX_2_4G_PREAMBLE - 2.4g preamble
+//==========================================================
+
+// <o> XINCX_2_4G_PREAMBLE  - 2.4g preamble
+#ifndef XINCX_2_4G_PREAMBLE
+#define XINCX_2_4G_PREAMBLE 0x710f5555
+#endif
+// </h>
+
+// <h> XINCX_2_4G_GUARD - 2.4g guard
+//==========================================================
+
+// <o> XINCX_2_4G_GUARD  - 2.4g guard
+#ifndef XINCX_2_4G_GUARD
+#define XINCX_2_4G_GUARD 0x8fc9
+#endif
+// </h>
+
+// <h> XINCX_2_4G_DYNPD - 2.4g dynpd
+//==========================================================
+
+// <o> XINCX_2_4G_DYNPD  - 2.4g dynpd
+#ifndef XINCX_2_4G_DYNPD
+#define XINCX_2_4G_DYNPD 0x3f
+#endif
+// </h>
+
+
+// <h> XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
+//==========================================================
+
+// <o> XINCX_2_4G_CRY_CPT_ARRAY  - 2.4g Crystal capacitor array
+#ifndef XINCX_2_4G_CRY_CPT_ARRAY
+#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
+#endif
+// </h>
+
+// <h> XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
+//==========================================================
+
+// <o> XINCX_2_4G_RETRANS_CNT  - 2.4g Retransmit Count
+#ifndef XINCX_2_4G_RETRANS_CNT
+#define XINCX_2_4G_RETRANS_CNT 0
+#endif
+
+// <o> XINCX_2_4G_RETRANS_DELAY  - 2.4g Retransmission Delay
+#ifndef XINCX_2_4G_RETRANS_DELAY
+#define XINCX_2_4G_RETRANS_DELAY 3
+#endif
+
+// <h> XINCX_2_4G_PIPE_RX_PAYLEN  - 2.4g Pipe Rx Payload Len
+//==========================================================
+// <o>   - 2.4g Pipe0 Rx Payload Len
+#ifndef XINCX_2_4G_PIPE0_LEN
+#define XINCX_2_4G_PIPE0_LEN 32
+#endif
+
+// <o> XINCX_2_4G_PIPE1_LEN  - 2.4g Pipe1 Rx Payload Len
+#ifndef XINCX_2_4G_PIPE1_LEN
+#define XINCX_2_4G_PIPE1_LEN 32
+#endif
+
+// <o> XINCX_2_4G_PIPE2_LEN  - 2.4g Pipe2 Rx Payload Len
+#ifndef XINCX_2_4G_PIPE2_LEN
+#define XINCX_2_4G_PIPE2_LEN 32
+#endif
+
+// <o> XINCX_2_4G_PIPE3_LEN  - 2.4g Pipe3 Rx Payload Len
+#ifndef XINCX_2_4G_PIPE3_LEN
+#define XINCX_2_4G_PIPE3_LEN 32
+#endif
+
+// <o> XINCX_2_4G_PIPE4_LEN  - 2.4g Pipe4 Rx Payload Len
+#ifndef XINCX_2_4G_PIPE4_LEN
+#define XINCX_2_4G_PIPE4_LEN 32
+#endif
+
+// <o> XINCX_2_4G_PIPE5_LEN  - 2.4g Pipe5 Rx Payload Len
+#ifndef XINCX_2_4G_PIPE5_LEN
+#define XINCX_2_4G_PIPE5_LEN 32
+#endif
+
+// </h>
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif