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hpw422移植新的sdk

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xushaoxiang
2026-07-03 18:08:25 +08:00
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component/ble/plf/refip/src/arch/arch.h
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/**
****************************************************************************************
*
* @file arch.h
*
* @brief This file contains the definitions of the macros and functions that are
* architecture dependent. The implementation of those is implemented in the
* appropriate architecture directory.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef _ARCH_H_
#define _ARCH_H_
/**
****************************************************************************************
* @defgroup REFIP
* @brief Reference IP Platform
*
* This module contains reference platform components - REFIP.
*
*
* @{
****************************************************************************************
*/
/**
****************************************************************************************
* @defgroup DRIVERS
* @ingroup REFIP
* @brief Reference IP Platform Drivers
*
* This module contains the necessary drivers to run the platform with the
* RW BT SW protocol stack.
*
* This has the declaration of the platform architecture API.
*
*
* @{
****************************************************************************************
*/
/*
* INCLUDE FILES
****************************************************************************************
*/
#include "rwip_config.h" // SW configuration
#include <stdint.h> // standard integer definition
#include <stdbool.h> // standard boolean definition
#include "compiler.h" // inline functions
/*
* CPU WORD SIZE
****************************************************************************************
*/
/// ARM is a 32-bit CPU
#define CPU_WORD_SIZE 4
/*
* CPU Endianness
****************************************************************************************
*/
/// ARM is little endian
#define CPU_LE 1
/*
* DEBUG configuration
****************************************************************************************
*/
#if defined(CFG_DBG)
#define PLF_DEBUG 1
#else //CFG_DBG
#define PLF_DEBUG 0
#endif //CFG_DBG
#if defined(CFG_PROFILING)
#define PLF_PROFILING 1
#else //CFG_DBG
#define PLF_PROFILING 0
#endif //CFG_PROFILING
#if defined(CFG_MEM_PROTECTION)
#define PLF_MEM_PROTECTION 1
#else //CFG_DBG
#define PLF_MEM_PROTECTION 0
#endif //CFG_PROFILING
/*
* NVDS
****************************************************************************************
*/
/// NVDS
#ifdef CFG_NVDS
#define PLF_NVDS 1
#else // CFG_NVDS
#define PLF_NVDS 0
#endif // CFG_NVDS
/*
* DMA
****************************************************************************************
*/
/// UART
#define PLF_DMA (BLE_EMB_PRESENT && BLE_ISO_PRESENT)
/*
* DEFINES
****************************************************************************************
*/
/// Possible errors detected by FW
#define RESET_NO_ERROR 0x00000000
#define RESET_MEM_ALLOC_FAIL 0xF2F2F2F2
/// Reset platform and stay in ROM
#define RESET_TO_ROM 0xA5A5A5A5
/// Reset platform and reload FW
#define RESET_AND_LOAD_FW 0xC3C3C3C3
/// Exchange memory size limit
#if (BT_DUAL_MODE)
#define EM_SIZE_LIMIT 0x10000
#else
#define EM_SIZE_LIMIT 0x4000
#endif
/*
* EXPORTED FUNCTION DECLARATION
****************************************************************************************
*/
#if (RW_DEBUG_STACK_PROF)
/**
****************************************************************************************
* @brief Initialise stack memory area.
*
* This function initialises the stack memory with pattern for use in stack profiling.
****************************************************************************************
*/
void stack_init(void);
/**
****************************************************************************************
* @brief Compute size of SW stack used.
*
* This function is compute the maximum size stack used by SW.
*
* @return Size of stack used (in bytes)
****************************************************************************************
*/
uint16_t get_stack_usage(void);
#endif //(RW_DEBUG_STACK_PROF)
/**
****************************************************************************************
* @brief Re-boot FW.
*
* This function is used to re-boot the FW when error has been detected, it is the end of
* the current FW execution.
* After waiting transfers on UART to be finished, and storing the information that
* FW has re-booted by itself in a non-loaded area, the FW restart by branching at FW
* entry point.
*
* Note: when calling this function, the code after it will not be executed.
*
* @param[in] error Error detected by FW
****************************************************************************************
*/
void platform_reset(uint32_t error);
#if PLF_DEBUG
/**
****************************************************************************************
* @brief Print the assertion error reason and loop forever.
*
* @param condition C string containing the condition.
* @param file C string containing file where the assertion is located.
* @param line Line number in the file where the assertion is located.
****************************************************************************************
*/
void assert_err(const char *condition, const char * file, int line);
/**
****************************************************************************************
* @brief Print the assertion error reason and loop forever.
* The parameter value that is causing the assertion will also be disclosed.
*
* @param param0 parameter value 0.
* @param param1 parameter value 1.
* @param file C string containing file where the assertion is located.
* @param line Line number in the file where the assertion is located.
****************************************************************************************
*/
void assert_param(int param0, int param1, const char * file, int line);
/**
****************************************************************************************
* @brief Print the assertion warning reason.
*
* @param param0 parameter value 0.
* @param param1 parameter value 1.
* @param file C string containing file where the assertion is located.
* @param line Line number in the file where the assertion is located.
****************************************************************************************
*/
void assert_warn(int param0, int param1, const char * file, int line);
/**
****************************************************************************************
* @brief Dump data value into FW.
*
* @param data start pointer of the data.
* @param length data size to dump
****************************************************************************************
*/
void dump_data(uint8_t* data, uint16_t length);
#endif //PLF_DEBUG
#if (PLF_PROFILING)
/**
****************************************************************************************
* @brief Trace enter into a function
*
* @param[in] p_func_ptr Pointer of the function
* @param[in] p_func_name_ptr Pointer of the function name
****************************************************************************************
*/
void func_enter(const void* p_func_ptr, const void* p_func_name_ptr);
/**
****************************************************************************************
* @brief Trace exit of a function
*
* @param[in] p_func_ptr Pointer of the function
* @param[in] p_func_name_ptr Pointer of the function name
****************************************************************************************
*/
void func_exit(const void* p_func_ptr, const void* p_func_name_ptr);
/**
****************************************************************************************
* @brief Trace data pointer allocation
*
* @param[in] p_ptr Data pointer address
****************************************************************************************
*/
void data_trace_alloc(const void* p_ptr);
/**
****************************************************************************************
* @brief Trace data pointer free
*
* @param[in] p_ptr Data pointer address
****************************************************************************************
*/
void data_trace_free(const void* p_ptr);
/**
****************************************************************************************
* @brief Trace data into a VCD
*
* @param[in] p_ptr Data pointer address
* @param[in] p_name_ptr Data variable name pointer address
* @param[in] data_size Size of data to trace in bytes (8, 16 or 32 only)
****************************************************************************************
*/
void data_trace(const void* p_ptr, const void* p_name_ptr, uint8_t data_size);
#endif // (PLF_PROFILING)
#if (PLF_MEM_PROTECTION)
/**
****************************************************************************************
* @brief Control memory access
*
* @param[in] p_mem_ptr Pointer to memory block
* @param[in] enable True to grant complete access on memory block, False to flow memory permissions
****************************************************************************************
*/
void mem_grant_access_ctrl(const void* p_mem_ptr, bool enable);
/**
****************************************************************************************
* @brief Set permission onto a specific memory block
*
* @param[in] p_mem_ptr Pointer to memory block
* @param[in] size Size of the memory block
* @param[in] write_en True to enable write permission, False to disable write
* @param[in] read_en True to enable read permission, False to disable read
* @param[in] init_clr True to mark memory block not initialized, False: no action
****************************************************************************************
*/
void mem_perm_set(const void* p_mem_ptr, uint16_t size, bool write_en, bool read_en, bool init_clr);
/**
****************************************************************************************
* @brief Mark memory block initialized - without modifying memory data
*
* @param[in] p_mem_ptr Pointer to memory block
* @param[in] size Size of the memory block
****************************************************************************************
*/
void mem_init(const void* p_mem_ptr, uint16_t size);
#endif // (PLF_MEM_PROTECTION)
/*
* ASSERTION CHECK
****************************************************************************************
*/
#if PLF_DEBUG
/// Assertions showing a critical error that could require a full system reset
#define ASSERT_ERR(cond) \
do { \
if (!(cond)) { \
assert_err(#cond, __MODULE__, __LINE__); \
} \
} while(0)
/// Assertions showing a critical error that could require a full system reset
#define ASSERT_INFO(cond, param0, param1) \
do { \
if (!(cond)) { \
assert_param((int)param0, (int)param1, __MODULE__, __LINE__); \
} \
} while(0)
/// Assertions showing a non-critical problem that has to be fixed by the SW
#define ASSERT_WARN(cond, param0, param1) \
do { \
if (!(cond)) { \
assert_warn((int)param0, (int)param1, __MODULE__, __LINE__); \
} \
} while(0)
/// DUMP data array present in the SW.
#define DUMP_DATA(data, length) \
dump_data((uint8_t*)data, length)
#else
#ifndef ASSERT_ERR
/// Assertions showing a critical error that could require a full system reset
#define ASSERT_ERR(cond)
#endif
/// Assertions showing a critical error that could require a full system reset
#define ASSERT_INFO(cond, param0, param1)
/// Assertions showing a non-critical problem that has to be fixed by the SW
#define ASSERT_WARN(cond, param0, param1)
/// DUMP data array present in the SW.
#define DUMP_DATA(data, length)
#endif //PLF_DEBUG
#if (PLF_PROFILING)
/// Trace data into a VCD
#define DBG_DATA_TRACE(data, size) data_trace(&data, #data, size)
/// Trace data allocation
#define DBG_DATA_ALLOC(data) data_trace_alloc(&data)
/// Trace data free
#define DBG_DATA_FREE(data) data_trace_free(&data)
/// Trace Function Enter
#define DBG_FUNC_ENTER(func) func_enter(func, #func)
/// Trace Function Exit
#define DBG_FUNC_EXIT(func) func_exit(func, #func)
#else
/// Trace data into a VCD
#define DBG_DATA_TRACE(data, size)
/// Trace data allocation
#define DBG_DATA_ALLOC(data)
/// Trace data free
#define DBG_DATA_FREE(data)
/// Trace Function Enter
#define DBG_FUNC_ENTER(func)
/// Trace Function Exit
#define DBG_FUNC_EXIT(func)
#endif //PLF_PROFILING
#if (PLF_MEM_PROTECTION)
/// Control memory access
#define DBG_MEM_GRANT_CTRL(mem_ptr, enable) mem_grant_access_ctrl(mem_ptr, enable)
/// Set permission onto a specific memory block
#define DBG_MEM_PERM_SET(mem_ptr, size, write_en, read_en, init_clr) mem_perm_set(mem_ptr, size, write_en, read_en, init_clr)
/// Mark memory initialized
#define DBG_MEM_INIT(mem_ptr, size) mem_init(mem_ptr, size)
#else // !(PLF_MEM_PROTECTION)
/// Control memory access
#define DBG_MEM_GRANT_CTRL(mem_ptr, enable)
/// Set permission onto a specific memory block
#define DBG_MEM_PERM_SET(mem_ptr, size, write_en, read_en, init_clr)
/// Mark memory initialized
#define DBG_MEM_INIT(mem_ptr, size)
#endif // (PLF_MEM_PROTECTION)
/// Object allocated in shared memory - check linker script
#define __SHARED __attribute__ ((section("shram")))
// required to define GLOBAL_INT_** macros as inline assembly. This file is included after
// definition of ASSERT macros as they are used inside ll.h
#include "ll.h" // ll definitions
/// @} DRIVERS
#endif // _ARCH_H_
component/ble/plf/refip/src/arch/boot/armgcc/boot.h
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/**
****************************************************************************************
*
* @file boot.h
*
* @brief This file contains the declarations of the boot related variables.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef _BOOT_H_
#define _BOOT_H_
/// Address of beginning of the CODE
extern char code_base;
#define CODE_BASE (&(code_base))
/// Address of the end of the CODE
extern char code_end;
#define CODE_END (&(code_end))
/// Length of the code
#define CODE_LENGTH ((CODE_END) - (CODE_BASE))
/// Address of beginning of the DATA
extern char data_base;
#define DATA_BASE (&(data_base))
/// Address of the end of the DATA
extern char data_end;
#define DATA_END (&(data_end))
/// Length of the DATA
#define DATA_LENGTH ((DATA_END) - (DATA_BASE))
/// Unloaded RAM area base address
extern char unloaded_area_start;
#define RAM_UNLOADED_BASE (&(unloaded_area_start))
/// Stack base address
extern char stack_base_unused;
#define STACK_BASE_UNUSED (&(stack_base_unused))
extern char stack_len_unused;
#define STACK_LEN_UNUSED (&(stack_len_unused))
extern char stack_base_svc ;
#define STACK_BASE_SVC (&(stack_base_svc))
extern char stack_len_svc;
#define STACK_LEN_SVC (&(stack_len_svc))
extern char stack_base_irq;
#define STACK_BASE_IRQ (&(stack_base_irq))
extern char stack_len_irq;
#define STACK_LEN_IRQ (&(stack_len_irq))
extern char stack_base_fiq;
#define STACK_BASE_FIQ (&(stack_base_fiq))
extern char stack_len_fiq;
#define STACK_LEN_FIQ (&(stack_len_fiq))
#define BOOT_PATTERN_UNUSED 0xAA // Pattern to fill UNUSED stack
#define BOOT_PATTERN_SVC 0xBB // Pattern to fill SVC stack
#define BOOT_PATTERN_IRQ 0xCC // Pattern to fill IRQ stack
#define BOOT_PATTERN_FIQ 0xDD // Pattern to fill FIQ stack
#endif // _BOOT_H_
component/ble/plf/refip/src/arch/boot/armgcc/boot_handlers.s
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#/**
# ****************************************************************************************
# *
# * @file boot_handlers.s
# *
# * @brief ARM Exception Vector handler functions.
# *
# * Copyright (C) RivieraWaves 2009-2015
# *
# * $Rev: $
# *
# ****************************************************************************************
# */
.text
.align 4
.global boot_reset
.type boot_reset, function
.global boot_undefined
.type boot_undefined, function
.global boot_swi
.type boot_swi, function
.global boot_pabort
.type boot_pabort, function
.global boot_dabort
.type boot_dabort, function
.global boot_reserved
.type boot_reserved, function
#/* ========================================================================
# * Constants
# * ======================================================================== */
.set BOOT_MODE_MASK, 0x1F
.set BOOT_MODE_USR, 0x10
.set BOOT_MODE_FIQ, 0x11
.set BOOT_MODE_IRQ, 0x12
.set BOOT_MODE_SVC, 0x13
.set BOOT_MODE_ABT, 0x17
.set BOOT_MODE_UND, 0x1B
.set BOOT_MODE_SYS, 0x1F
.set BOOT_FIQ_IRQ_MASK, 0xC0
.set BOOT_IRQ_MASK, 0x80
#/* ========================================================================
# * Macros
# * ======================================================================== */
#/* ========================================================================
#/**
# * Macro for switching ARM mode
# */
.macro BOOT_CHANGE_MODE newmode
MRS R0, CPSR
BIC R0, R0, #BOOT_MODE_MASK
ORR R0, R0, #BOOT_MODE_\newmode
MSR CPSR_c, R0
.endm
#/* ========================================================================
#/**
# * Macro for setting the stack
# */
.macro BOOT_SET_STACK stackname
LDR R0, boot_stack_base_\stackname
LDR R1, boot_stack_len_\stackname
ADD R0, R0, R1
MOV SP, R0
.endm
#/* ========================================================================
# * Globals
# * ======================================================================== */
#/* ========================================================================
#/**
# * CP15 DTCM Control Reg settings
# */
boot_Cp15DtcmReg:
.word 0x01010001
#/* ========================================================================
#/**
# * CP15 ITCM Control Reg settings
# */
boot_Cp15ItcmReg:
.word 0x01000001
#/* ========================================================================
#/**
# * RAM_BSS
# */
ram_bss_base:
.word bss_base
ram_bss_length:
.word bss_length
#/* ========================================================================
#/**
# * Unused (ABT, UNDEFINED, SYSUSR) Mode
# */
boot_stack_base_UNUSED:
.word stack_base_unused
boot_stack_len_UNUSED:
.word stack_len_unused
#/* ========================================================================
#/**
# * IRQ Mode
# */
boot_stack_base_IRQ:
.word stack_base_irq
boot_stack_len_IRQ:
.word stack_len_irq
#/* ========================================================================
#/**
# * Supervisor Mode
# */
boot_stack_base_SVC:
.word stack_base_svc
boot_stack_len_SVC:
.word stack_len_svc
#/* ========================================================================
#/**
# * FIQ Mode
# */
boot_stack_base_FIQ:
.word stack_base_fiq
boot_stack_len_FIQ:
.word stack_len_fiq
#/* ========================================================================
# * Functions
# * ========================================================================
#/* ========================================================================
#/**
# * Function to handle reset vector
# */
boot_reset:
# Disable IRQ and FIQ before starting anything
MRS R0, CPSR
ORR R0, R0, #0xC0
MSR CPSR_c, R0
# ==================
# Setup all stacks
# Note: Sys and Usr mode are not used
BOOT_CHANGE_MODE SYS
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE ABT
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE UND
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE IRQ
BOOT_SET_STACK IRQ
BOOT_CHANGE_MODE FIQ
BOOT_SET_STACK FIQ
# Clear FIQ banked registers while in FIQ mode
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
BOOT_CHANGE_MODE SVC
BOOT_SET_STACK SVC
# Stay in Supervisor Mode
# Init the BSS section
LDR R0, ram_bss_base
LDR R1, ram_bss_length
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
init_bss_loop:
SUBS R1, R1, #16
STMCSIA R0!, {R2, R3, R4, R5}
BHI init_bss_loop
MOVS R1, R1, LSL #29
STMCSIA R0!, {R4, R5}
STRMI R3, [R0]
# ==================
# Clear Registers
MOV R0, #0
MOV R1, #0
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
MOV R6, #0
MOV R7, #0
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
B rw_main
# undefined handler
boot_undefined:
B boot_undefined
# SWI handler
boot_swi:
B boot_swi
# Prefetch error handler
boot_pabort:
B boot_pabort
# abort handler
boot_dabort:
B boot_dabort
# reserved vector
boot_reserved:
B boot_reserved
SUBS PC, LR, #4
component/ble/plf/refip/src/arch/boot/armgcc/boot_vectors.s
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/**
****************************************************************************************
*
* @file boot_vectors.s
*
* @brief ARM Exception Vectors table.
*
* Copyright (C) RivieraWaves 2009-2015
*
* $Rev: $
*
****************************************************************************************
*/
.text
.align 4
.global vectors, boot_breakpoint
.type vectors, function
vectors:
# reset handler
B boot_reset
# undefined handler
B boot_undefined
# SWI handler
B boot_swi
# Prefetch error handler
B boot_pabort
# abort handler
B boot_dabort
# reserved vector
B boot_reserved
# irq
B intc_irq
# fiq
B intc_fiq
boot_breakpoint:
# If set to 0 by host before getting out of reset, the cpu
# will loop and light the leds indefinitely
.word 1
component/ble/plf/refip/src/arch/boot/armgcc_4_8/boot.h
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/**
****************************************************************************************
*
* @file boot.h
*
* @brief This file contains the declarations of the boot related variables.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef _BOOT_H_
#define _BOOT_H_
/// Address of beginning of the CODE
extern char code_base;
#define CODE_BASE (&(code_base))
/// Address of the end of the CODE
extern char code_end;
#define CODE_END (&(code_end))
/// Length of the code
#define CODE_LENGTH ((CODE_END) - (CODE_BASE))
/// Address of beginning of the DATA
extern char data_base;
#define DATA_BASE (&(data_base))
/// Address of the end of the DATA
extern char data_end;
#define DATA_END (&(data_end))
/// Length of the DATA
#define DATA_LENGTH ((DATA_END) - (DATA_BASE))
/// Unloaded RAM area base address
extern char unloaded_area_start;
#define RAM_UNLOADED_BASE (&(unloaded_area_start))
/// Stack base address
extern char stack_base_unused;
#define STACK_BASE_UNUSED (&(stack_base_unused))
extern char stack_len_unused;
#define STACK_LEN_UNUSED (&(stack_len_unused))
extern char stack_base_svc ;
#define STACK_BASE_SVC (&(stack_base_svc))
extern char stack_len_svc;
#define STACK_LEN_SVC (&(stack_len_svc))
extern char stack_base_irq;
#define STACK_BASE_IRQ (&(stack_base_irq))
extern char stack_len_irq;
#define STACK_LEN_IRQ (&(stack_len_irq))
extern char stack_base_fiq;
#define STACK_BASE_FIQ (&(stack_base_fiq))
extern char stack_len_fiq;
#define STACK_LEN_FIQ (&(stack_len_fiq))
#define BOOT_PATTERN_UNUSED 0xAA // Pattern to fill UNUSED stack
#define BOOT_PATTERN_SVC 0xBB // Pattern to fill SVC stack
#define BOOT_PATTERN_IRQ 0xCC // Pattern to fill IRQ stack
#define BOOT_PATTERN_FIQ 0xDD // Pattern to fill FIQ stack
#endif // _BOOT_H_
component/ble/plf/refip/src/arch/boot/armgcc_4_8/boot_handlers.s
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#/**
# ****************************************************************************************
# *
# * @file boot_handlers.s
# *
# * @brief ARM Exception Vector handler functions.
# *
# * Copyright (C) RivieraWaves 2009-2015
# *
# * $Rev: $
# *
# ****************************************************************************************
# */
.text
.align 4
.global boot_reset
.type boot_reset, function
.global boot_undefined
.type boot_undefined, function
.global boot_swi
.type boot_swi, function
.global boot_pabort
.type boot_pabort, function
.global boot_dabort
.type boot_dabort, function
.global boot_reserved
.type boot_reserved, function
#/* ========================================================================
# * Constants
# * ======================================================================== */
.set BOOT_MODE_MASK, 0x1F
.set BOOT_MODE_USR, 0x10
.set BOOT_MODE_FIQ, 0x11
.set BOOT_MODE_IRQ, 0x12
.set BOOT_MODE_SVC, 0x13
.set BOOT_MODE_ABT, 0x17
.set BOOT_MODE_UND, 0x1B
.set BOOT_MODE_SYS, 0x1F
.set BOOT_FIQ_IRQ_MASK, 0xC0
.set BOOT_IRQ_MASK, 0x80
#/* ========================================================================
# * Macros
# * ======================================================================== */
#/* ========================================================================
#/**
# * Macro for switching ARM mode
# */
.macro BOOT_CHANGE_MODE newmode
MRS R0, CPSR
BIC R0, R0, #BOOT_MODE_MASK
ORR R0, R0, #BOOT_MODE_\newmode
MSR CPSR_c, R0
.endm
#/* ========================================================================
#/**
# * Macro for setting the stack
# */
.macro BOOT_SET_STACK stackname
LDR R0, boot_stack_base_\stackname
LDR R1, boot_stack_len_\stackname
ADD R0, R0, R1
MOV SP, R0
.endm
#/* ========================================================================
# * Globals
# * ======================================================================== */
#/* ========================================================================
#/**
# * CP15 DTCM Control Reg settings
# */
boot_Cp15DtcmReg:
.word 0x01010001
#/* ========================================================================
#/**
# * CP15 ITCM Control Reg settings
# */
boot_Cp15ItcmReg:
.word 0x01000001
#/* ========================================================================
#/**
# * RAM_BSS
# */
ram_bss_base:
.word bss_base
ram_bss_length:
.word bss_length
#/* ========================================================================
#/**
# * Unused (ABT, UNDEFINED, SYSUSR) Mode
# */
boot_stack_base_UNUSED:
.word stack_base_unused
boot_stack_len_UNUSED:
.word stack_len_unused
#/* ========================================================================
#/**
# * IRQ Mode
# */
boot_stack_base_IRQ:
.word stack_base_irq
boot_stack_len_IRQ:
.word stack_len_irq
#/* ========================================================================
#/**
# * Supervisor Mode
# */
boot_stack_base_SVC:
.word stack_base_svc
boot_stack_len_SVC:
.word stack_len_svc
#/* ========================================================================
#/**
# * FIQ Mode
# */
boot_stack_base_FIQ:
.word stack_base_fiq
boot_stack_len_FIQ:
.word stack_len_fiq
#/* ========================================================================
# * Functions
# * ========================================================================
#/* ========================================================================
#/**
# * Function to handle reset vector
# */
boot_reset:
# Disable IRQ and FIQ before starting anything
MRS R0, CPSR
ORR R0, R0, #0xC0
MSR CPSR_c, R0
# ==================
# Setup all stacks
# Note: Sys and Usr mode are not used
BOOT_CHANGE_MODE SYS
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE ABT
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE UND
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE IRQ
BOOT_SET_STACK IRQ
BOOT_CHANGE_MODE FIQ
BOOT_SET_STACK FIQ
# Clear FIQ banked registers while in FIQ mode
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
BOOT_CHANGE_MODE SVC
BOOT_SET_STACK SVC
# Stay in Supervisor Mode
# Init the BSS section
LDR R0, ram_bss_base
LDR R1, ram_bss_length
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
init_bss_loop:
SUBS R1, R1, #16
STMCSIA R0!, {R2, R3, R4, R5}
BHI init_bss_loop
MOVS R1, R1, LSL #29
STMCSIA R0!, {R4, R5}
STRMI R3, [R0]
# ==================
# Clear Registers
MOV R0, #0
MOV R1, #0
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
MOV R6, #0
MOV R7, #0
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
B rw_main
# undefined handler
boot_undefined:
B boot_undefined
# SWI handler
boot_swi:
B boot_swi
# Prefetch error handler
boot_pabort:
B boot_pabort
# abort handler
boot_dabort:
B boot_dabort
# reserved vector
boot_reserved:
B boot_reserved
SUBS PC, LR, #4
component/ble/plf/refip/src/arch/boot/armgcc_4_8/boot_vectors.s
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/**
****************************************************************************************
*
* @file boot_vectors.s
*
* @brief ARM Exception Vectors table.
*
* Copyright (C) RivieraWaves 2009-2015
*
* $Rev: $
*
****************************************************************************************
*/
.text
.align 4
.global vectors, boot_breakpoint
.type vectors, function
vectors:
# reset handler
B boot_reset
# undefined handler
B boot_undefined
# SWI handler
B boot_swi
# Prefetch error handler
B boot_pabort
# abort handler
B boot_dabort
# reserved vector
B boot_reserved
# irq
B intc_irq
# fiq
B intc_fiq
boot_breakpoint:
# If set to 0 by host before getting out of reset, the cpu
# will loop and light the leds indefinitely
.word 1
component/ble/plf/refip/src/arch/boot/gnuarm/boot.h
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/**
****************************************************************************************
*
* @file boot.h
*
* @brief This file contains the declarations of the boot related variables.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef _BOOT_H_
#define _BOOT_H_
/// Address of beginning of the CODE
extern char code_base;
#define CODE_BASE (&(code_base))
/// Address of the end of the CODE
extern char code_end;
#define CODE_END (&(code_end))
/// Length of the code
#define CODE_LENGTH ((CODE_END) - (CODE_BASE))
/// Address of beginning of the DATA
extern char data_base;
#define DATA_BASE (&(data_base))
/// Address of the end of the DATA
extern char data_end;
#define DATA_END (&(data_end))
/// Length of the DATA
#define DATA_LENGTH ((DATA_END) - (DATA_BASE))
/// Unloaded RAM area base address
extern char unloaded_area_start;
#define RAM_UNLOADED_BASE (&(unloaded_area_start))
/// Stack base address
extern char stack_base_unused;
#define STACK_BASE_UNUSED (&(stack_base_unused))
extern char stack_len_unused;
#define STACK_LEN_UNUSED (&(stack_len_unused))
extern char stack_base_svc ;
#define STACK_BASE_SVC (&(stack_base_svc))
extern char stack_len_svc;
#define STACK_LEN_SVC (&(stack_len_svc))
extern char stack_base_irq;
#define STACK_BASE_IRQ (&(stack_base_irq))
extern char stack_len_irq;
#define STACK_LEN_IRQ (&(stack_len_irq))
extern char stack_base_fiq;
#define STACK_BASE_FIQ (&(stack_base_fiq))
extern char stack_len_fiq;
#define STACK_LEN_FIQ (&(stack_len_fiq))
#define BOOT_PATTERN_UNUSED 0xAA // Pattern to fill UNUSED stack
#define BOOT_PATTERN_SVC 0xBB // Pattern to fill SVC stack
#define BOOT_PATTERN_IRQ 0xCC // Pattern to fill IRQ stack
#define BOOT_PATTERN_FIQ 0xDD // Pattern to fill FIQ stack
#endif // _BOOT_H_
component/ble/plf/refip/src/arch/boot/gnuarm/boot_handlers.s
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#/**
# ****************************************************************************************
# *
# * @file boot_handlers.s
# *
# * @brief ARM Exception Vector handler functions.
# *
# * Copyright (C) RivieraWaves 2009-2015
# *
# * $Rev: $
# *
# ****************************************************************************************
# */
.text
.align 4
.global boot_reset
.type boot_reset, function
.global boot_undefined
.type boot_undefined, function
.global boot_swi
.type boot_swi, function
.global boot_pabort
.type boot_pabort, function
.global boot_dabort
.type boot_dabort, function
.global boot_reserved
.type boot_reserved, function
#/* ========================================================================
# * Constants
# * ======================================================================== */
.set BOOT_MODE_MASK, 0x1F
.set BOOT_MODE_USR, 0x10
.set BOOT_MODE_FIQ, 0x11
.set BOOT_MODE_IRQ, 0x12
.set BOOT_MODE_SVC, 0x13
.set BOOT_MODE_ABT, 0x17
.set BOOT_MODE_UND, 0x1B
.set BOOT_MODE_SYS, 0x1F
.set BOOT_FIQ_IRQ_MASK, 0xC0
.set BOOT_IRQ_MASK, 0x80
#/* ========================================================================
# * Macros
# * ======================================================================== */
#/* ========================================================================
#/**
# * Macro for switching ARM mode
# */
.macro BOOT_CHANGE_MODE newmode
MRS R0, CPSR
BIC R0, R0, #BOOT_MODE_MASK
ORR R0, R0, #BOOT_MODE_\newmode
MSR CPSR_c, R0
.endm
#/* ========================================================================
#/**
# * Macro for setting the stack
# */
.macro BOOT_SET_STACK stackname
LDR R0, boot_stack_base_\stackname
LDR R1, boot_stack_len_\stackname
ADD R0, R0, R1
MOV SP, R0
.endm
#/* ========================================================================
# * Globals
# * ======================================================================== */
#/* ========================================================================
#/**
# * CP15 DTCM Control Reg settings
# */
boot_Cp15DtcmReg:
.word 0x01010001
#/* ========================================================================
#/**
# * CP15 ITCM Control Reg settings
# */
boot_Cp15ItcmReg:
.word 0x01000001
#/* ========================================================================
#/**
# * RAM_BSS
# */
ram_bss_base:
.word bss_base
ram_bss_length:
.word bss_length
#/* ========================================================================
#/**
# * Unused (ABT, UNDEFINED, SYSUSR) Mode
# */
boot_stack_base_UNUSED:
.word stack_base_unused
boot_stack_len_UNUSED:
.word stack_len_unused
#/* ========================================================================
#/**
# * IRQ Mode
# */
boot_stack_base_IRQ:
.word stack_base_irq
boot_stack_len_IRQ:
.word stack_len_irq
#/* ========================================================================
#/**
# * Supervisor Mode
# */
boot_stack_base_SVC:
.word stack_base_svc
boot_stack_len_SVC:
.word stack_len_svc
#/* ========================================================================
#/**
# * FIQ Mode
# */
boot_stack_base_FIQ:
.word stack_base_fiq
boot_stack_len_FIQ:
.word stack_len_fiq
#/* ========================================================================
# * Functions
# * ========================================================================
#/* ========================================================================
#/**
# * Function to handle reset vector
# */
boot_reset:
# Disable IRQ and FIQ before starting anything
MRS R0, CPSR
ORR R0, R0, #0xC0
MSR CPSR_c, R0
# ==================
# Setup all stacks
# Note: Sys and Usr mode are not used
BOOT_CHANGE_MODE SYS
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE ABT
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE UND
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE IRQ
BOOT_SET_STACK IRQ
BOOT_CHANGE_MODE FIQ
BOOT_SET_STACK FIQ
# Clear FIQ banked registers while in FIQ mode
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
BOOT_CHANGE_MODE SVC
BOOT_SET_STACK SVC
# Stay in Supervisor Mode
# Init the BSS section
LDR R0, ram_bss_base
LDR R1, ram_bss_length
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
init_bss_loop:
SUBS R1, R1, #16
STMCSIA R0!, {R2, R3, R4, R5}
BHI init_bss_loop
MOVS R1, R1, LSL #29
STMCSIA R0!, {R4, R5}
STRMI R3, [R0]
# ==================
# Clear Registers
MOV R0, #0
MOV R1, #0
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
MOV R6, #0
MOV R7, #0
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
B rw_main
# undefined handler
boot_undefined:
B boot_undefined
# SWI handler
boot_swi:
B boot_swi
# Prefetch error handler
boot_pabort:
B boot_pabort
# abort handler
boot_dabort:
B boot_dabort
# reserved vector
boot_reserved:
B boot_reserved
SUBS PC, LR, #4
component/ble/plf/refip/src/arch/boot/gnuarm/boot_vectors.s
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/**
****************************************************************************************
*
* @file boot_vectors.s
*
* @brief ARM Exception Vectors table.
*
* Copyright (C) RivieraWaves 2009-2015
*
* $Rev: $
*
****************************************************************************************
*/
.text
.align 4
.global vectors, boot_breakpoint
.type vectors, function
vectors:
# reset handler
B boot_reset
# undefined handler
B boot_undefined
# SWI handler
B boot_swi
# Prefetch error handler
B boot_pabort
# abort handler
B boot_dabort
# reserved vector
B boot_reserved
# irq
B intc_irq
# fiq
B intc_fiq
boot_breakpoint:
# If set to 0 by host before getting out of reset, the cpu
# will loop and light the leds indefinitely
.word 1
component/ble/plf/refip/src/arch/boot/rvds/boot.h
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/**
****************************************************************************************
*
* @file boot.h
*
* @brief This file contains the declarations of the boot related variables.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef _BOOT_H_
#define _BOOT_H_
#if 0
/// Length of the code
extern const uint32_t Image$$EXEC_RAM_TEXT$$Length[];
#define CODE_LENGTH ((uint32_t)Image$$EXEC_RAM_TEXT$$Length)
/// Length of the RW data
extern const uint32_t Image$$RAM_DATA$$Length[];
#define DATA_LENGTH ((uint32_t)Image$$RAM_DATA$$Length)
/// Unloaded RAM area base address
extern const uint32_t Image$$RAM_UNLOADED$$Base[];
#define RAM_UNLOADED_BASE ((uint32_t)Image$$RAM_UNLOADED$$Base)
/// Stack base address
extern const uint32_t Image$$RAM_STACK_UNUSED$$Base[];
#define STACK_BASE_UNUSED ((uint32_t)Image$$RAM_STACK_UNUSED$$Base)
extern const uint32_t Image$$RAM_STACK_UNUSED$$ZI$$Length[];
#define STACK_LEN_UNUSED ((uint32_t)Image$$RAM_STACK_UNUSED$$ZI$$Length)
extern const uint32_t Image$$RAM_STACK_SVC$$Base[] ;
#define STACK_BASE_SVC ((uint32_t)Image$$RAM_STACK_SVC$$Base)
extern const uint32_t Image$$RAM_STACK_SVC$$ZI$$Length[];
#define STACK_LEN_SVC ((uint32_t)Image$$RAM_STACK_SVC$$ZI$$Length)
extern const uint32_t Image$$RAM_STACK_IRQ$$Base[];
#define STACK_BASE_IRQ ((uint32_t)Image$$RAM_STACK_IRQ$$Base)
extern const uint32_t Image$$RAM_STACK_IRQ$$ZI$$Length[];
#define STACK_LEN_IRQ ((uint32_t)Image$$RAM_STACK_IRQ$$ZI$$Length)
extern const uint32_t Image$$RAM_STACK_FIQ$$Base[];
#define STACK_BASE_FIQ ((uint32_t)Image$$RAM_STACK_FIQ$$Base)
extern const uint32_t Image$$RAM_STACK_FIQ$$ZI$$Length[];
#define STACK_LEN_FIQ ((uint32_t)Image$$RAM_STACK_FIQ$$ZI$$Length)
#endif
#define BOOT_PATTERN_UNUSED 0xAA // Pattern to fill UNUSED stack
#define BOOT_PATTERN_SVC 0xBB // Pattern to fill SVC stack
#define BOOT_PATTERN_IRQ 0xCC // Pattern to fill IRQ stack
#define BOOT_PATTERN_FIQ 0xDD // Pattern to fill FIQ stack
#endif // _BOOT_H_
component/ble/plf/refip/src/arch/boot/rvds/boot_handlers.s
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;/**
; ****************************************************************************************
; *
; * @file boot_handlers.s
; *
; * @brief ARM Exception Vector handler functions.
; *
; * Copyright (C) RivieraWaves 2009-2015
; *
; * $Rev: 7583 $
; *
; ****************************************************************************************
; */
IF {CPU} /= "Cortex-M3"
IF {CPU} /= "Cortex-M1"
IF {CPU} /= "Cortex-M0"
;Export pointers to the vector handlers.
EXPORT boot_reset
EXPORT boot_undefined
EXPORT boot_swi
EXPORT boot_pabort
EXPORT boot_dabort
EXPORT boot_reserved
IMPORT rw_main
;/* ========================================================================
; * Constants
; * ======================================================================== */
BOOT_MODE_MASK EQU 0x1F
BOOT_MODE_USR EQU 0x10
BOOT_MODE_FIQ EQU 0x11
BOOT_MODE_IRQ EQU 0x12
BOOT_MODE_SVC EQU 0x13
BOOT_MODE_ABT EQU 0x17
BOOT_MODE_UND EQU 0x1B
BOOT_MODE_SYS EQU 0x1F
I_BIT EQU 0x80
F_BIT EQU 0x40
BOOT_COLOR_UNUSED EQU 0xAAAAAAAA ; Pattern to fill UNUSED stack
BOOT_COLOR_SVC EQU 0xBBBBBBBB ; Pattern to fill SVC stack
BOOT_COLOR_IRQ EQU 0xCCCCCCCC ; Pattern to fill IRQ stack
BOOT_COLOR_FIQ EQU 0xDDDDDDDD ; Pattern to fill FIQ stack
;/* ========================================================================
; * Macros
; * ======================================================================== */
;/* ========================================================================
;/**
; * Macro for switching ARM mode
; */
MACRO
$x BOOT_CHANGE_MODE $newMode
MRS R0, CPSR
BIC R0, R0, #BOOT_MODE_MASK
ORR R0, R0, #BOOT_MODE_$newMode
MSR CPSR_c, R0
MEND
;/* ========================================================================
;/**
; * Macro for setting the stack
; */
MACRO
$x BOOT_SET_STACK $stackName
LDR R0, boot_stack_base_$stackName
LDR R2, boot_stack_len_$stackName
ADD R1, R0, R2
MOV SP, R1 ; Set stack pointer
LDR R2, =BOOT_COLOR_$stackName
90 CMP R0, R1 ; End of stack?
STRLT R2, [r0] ; Colorize stack word
ADDLT R0, R0, #4
BLT %B90 ; branch to previous local label
MEND
PRESERVE8
AREA ||.text||, CODE, READONLY
;/* ========================================================================
; * Globals
; * ======================================================================== */
;/* ========================================================================
;/**
; * CP15 DTCM Control Reg settings
; */
boot_Cp15DtcmReg
DCD 0x01010001
;/* ========================================================================
;/**
; * CP15 ITCM Control Reg settings
; */
boot_Cp15ItcmReg
DCD 0x01000001
;/* ========================================================================
;/**
; * ROM
; */
IMPORT |Load$$RAM_DATA$$Base| ; Base of ROM data
rom_base
DCD |Load$$RAM_DATA$$Base|
;/* ========================================================================
;/**
; * RAM to initialize with rom data
; */
IMPORT |Image$$RAM_DATA$$Base|
ram_base
DCD |Image$$RAM_DATA$$Base|
IMPORT |Image$$RAM_DATA$$Length|
ram_length
DCD |Image$$RAM_DATA$$Length|
;/* ========================================================================
;/**
; * RAM_BSS
; */
IMPORT |Image$$RAM_BSS$$ZI$$Base|
ram_bss_base
DCD |Image$$RAM_BSS$$ZI$$Base|
IMPORT |Image$$RAM_BSS$$ZI$$Length|
ram_bss_length
DCD |Image$$RAM_BSS$$ZI$$Length|
;/* ========================================================================
;/**
; * Unused (ABT, UNDEFINED, SYSUSR) Mode
; */
IMPORT |Image$$RAM_STACK_UNUSED$$Base|
boot_stack_base_UNUSED
DCD |Image$$RAM_STACK_UNUSED$$Base|
IMPORT |Image$$RAM_STACK_UNUSED$$ZI$$Length|
boot_stack_len_UNUSED
DCD |Image$$RAM_STACK_UNUSED$$ZI$$Length|
;/* ========================================================================
;/**
; * IRQ Mode
; */
IMPORT |Image$$RAM_STACK_IRQ$$Base|
boot_stack_base_IRQ
DCD |Image$$RAM_STACK_IRQ$$Base|
IMPORT |Image$$RAM_STACK_IRQ$$ZI$$Length|
boot_stack_len_IRQ
DCD |Image$$RAM_STACK_IRQ$$ZI$$Length|
;/* ========================================================================
;/**
; * Supervisor Mode
; */
IMPORT |Image$$RAM_STACK_SVC$$Base|
boot_stack_base_SVC
DCD |Image$$RAM_STACK_SVC$$Base|
IMPORT |Image$$RAM_STACK_SVC$$ZI$$Length|
boot_stack_len_SVC
DCD |Image$$RAM_STACK_SVC$$ZI$$Length|
;/* ========================================================================
;/**
; * FIQ Mode
; */
IMPORT |Image$$RAM_STACK_FIQ$$Base|
boot_stack_base_FIQ
DCD |Image$$RAM_STACK_FIQ$$Base|
IMPORT |Image$$RAM_STACK_FIQ$$ZI$$Length|
boot_stack_len_FIQ
DCD |Image$$RAM_STACK_FIQ$$ZI$$Length|
;/* ========================================================================
; * Functions
; * ======================================================================== */
;/* ========================================================================
;/**
; * Function to handle reset vector
; */
boot_reset
; * ==================
; Setup all stacks
; Note: Sys and Usr mode are not used
BOOT_CHANGE_MODE SYS
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE ABT
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE UND
BOOT_SET_STACK UNUSED
BOOT_CHANGE_MODE IRQ
BOOT_SET_STACK IRQ
BOOT_CHANGE_MODE FIQ
BOOT_SET_STACK FIQ
BOOT_CHANGE_MODE SVC
BOOT_SET_STACK SVC
; Stay in Supervisor Mode
; Recopy rom to ram
LDR R0, rom_base ; Get base of ROM data
LDR R1, ram_base ; Get base of RAM to initialise
LDR R3, ram_length ; Get length of RAM to initialise
copy_rom_ram
CMP R3, #0 ; Copy init data, init of RW area
LDRGT R2, [R0], #4 ; Load data
STRGT R2, [R1], #4 ; Store data
SUBGT R3, R3, #4 ; Decrement RW length
BGT copy_rom_ram ; For each word
; Init the BSS section
LDR R0, ram_bss_base
LDR R1, ram_bss_length
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
init_bss_loop
SUBS R1, R1, #16
STMCSIA R0!, {R2, R3, R4, R5}
BHI init_bss_loop
LSLS R1, R1, #29
STMCSIA R0!, {R4, R5}
STRMI R3, [R0]
; * ==================
; Clear Registers
MOV R0, #0
MOV R1, #0
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
MOV R6, #0
MOV R7, #0
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
; Now safe to enable interrupts, so do this and remain in SVC mode
MOV r0, #BOOT_MODE_SVC:OR:I_BIT:OR:F_BIT ; IRQ and FIQ still disabled
MSR CPSR_c, r0
BL rw_main
; If For some reason main returns (which it shouldn't)
; Just loop here and wait for the watchdog to reset
_boot_reset_loop
B _boot_reset_loop
;/* ========================================================================
;/**
; * Function to handle undefined vector
; */
boot_undefined
B boot_undefined
;/* ========================================================================
;/**
; * Function to handle software interrupt vector
; */
boot_swi
B boot_swi
;/* ========================================================================
;/**
; * Function to handle Prefetch Abort vector
; */
boot_pabort
B boot_pabort
;/* ========================================================================
;/**
; * Function to handle Data Abort vector
; */
boot_dabort
B boot_dabort
;/* ========================================================================
;/**
; * Function to handle Reserved vector
; */
boot_reserved
B boot_reserved
SUBS PC, LR, #4
ENDIF
ENDIF
ENDIF
END
component/ble/plf/refip/src/arch/boot/rvds/boot_vectors.s
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;/**
; ****************************************************************************************
; *
; * @file boot_vectors.s
; *
; * @brief ARM Exception Vectors table.
; *
; * Copyright (C) RivieraWaves 2009-2015
; *
; * $Rev: $
; *
; ****************************************************************************************
; */
IF {CPU} /= "Cortex-M3"
IF {CPU} /= "Cortex-M1"
IF {CPU} /= "Cortex-M0"
;Import pointers to the actual vector handlers.
IMPORT boot_reset
IMPORT boot_undefined
IMPORT boot_swi
IMPORT boot_pabort
IMPORT boot_dabort
IMPORT boot_reserved
IMPORT intc_irq
IMPORT intc_fiq
AREA |C$$zinit|,NOINIT ; Data in ZI area
AREA ||.boot_vectors||, CODE, READONLY
CODE32
;
; This is the entry point for the system and this vector table must be
; physically located or mapped to address 0.
;
ENTRY
EXPORT boot_vectors
boot_vectors
B boot_reset
B boot_undefined
B boot_swi
B boot_pabort
B boot_dabort
B boot_reserved
B intc_irq
B intc_fiq
EXPORT boot_breakpoint
boot_breakpoint
; If set to 0 by host before getting out of reset, the cpu
; will loop and light the leds indefinitely
DCD 1
ENDIF
ENDIF
ENDIF
END
component/ble/plf/refip/src/arch/compiler/gnuarm/compiler.h
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/**
****************************************************************************************
*
* @file gnuarm/compiler.h
*
* @brief Definitions of compiler specific directives.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#if 0
#ifndef _COMPILER_H_
#define _COMPILER_H_
/// define the static keyword for this compiler
#ifdef CFG_STATIC
#define __STATIC static
#else // CFG_STATIC
#define __STATIC
#endif // CFG_STATIC
/// define the force inlining attribute for this compiler
#define __INLINE static __attribute__((__always_inline__)) inline
/// define the IRQ handler attribute for this compiler
#define __IRQ __attribute__((__interrupt__("IRQ")))
/// define the BLE IRQ handler attribute for this compiler
#define __BTIRQ
/// define the BLE IRQ handler attribute for this compiler
#define __BLEIRQ
/// define the FIQ handler attribute for this compiler
#define __FIQ __attribute__((__interrupt__("FIQ")))
/// define size of an empty array (used to declare structure with an array size not defined)
#define __ARRAY_EMPTY
/// Function returns struct in registers (4 in rvds, var with gnuarm).
/// With Gnuarm, feature depends on command line options and
/// impacts ALL functions returning 2-words max structs
/// (check -freg-struct-return and -mabi=xxx)
#define __VIR
/// function has no side effect and return depends only on arguments
#define __PURE __attribute__((const))
/// Align instantiated lvalue or struct member on 4 bytes
#define __ALIGN4 __attribute__((aligned(4)))
/// __MODULE__ comes from the RVDS compiler that supports it
//#define __MODULE__ __BASE_FILE__
/// Pack a structure field
#define __PACKED __attribute__ ((__packed__))
/// Put a variable in a memory maintained during deep sleep
#define __LOWPOWER_SAVED
#endif // _COMPILER_H_
#endif
/**
****************************************************************************************
*
* @file rvds/compiler.h
*
* @brief Definitions of compiler specific directives.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef _COMPILER_H_
#define _COMPILER_H_
#include "xc6xxx.h"
#ifndef __ARMCC_VERSION
#error "File only included with RVDS!"
#endif // __ARMCC_VERSION
/// define the static keyword for this compiler
//#ifdef CFG_STATIC
//#define __STATIC static
//#else // CFG_STATIC
//#define __STATIC
//#endif // CFG_STATIC
#define __STATIC
/// define the force inlining attribute for this compiler
//#define __INLINE __forceinline static
/// define the IRQ handler attribute for this compiler
#define __IRQ __irq
/// define the BLE IRQ handler attribute for this compiler
#define __BTIRQ
/// define the BLE IRQ handler attribute for this compiler
#define __BLEIRQ
/// define the FIQ handler attribute for this compiler
#define __FIQ __irq
/// define size of an empty array (used to declare structure with an array size not defined)
#define __ARRAY_EMPTY
/// Put a variable in a memory maintained during deep sleep
#define __LOWPOWER_SAVED
#endif // _COMPILER_H_
component/ble/plf/refip/src/arch/ll/armgcc/ll.h
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/**
****************************************************************************************
*
* @file ll.h
*
* @brief Declaration of low level functions.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef LL_H_
#define LL_H_
#ifndef __GNUC__
#error "File only included with ARM GCC"
#endif // __GNUC__
#include <stdint.h>
/** @brief Enable interrupts globally in the system.
* This macro must be used when the initialization phase is over and the interrupts
* can start being handled by the system.
*/
#define GLOBAL_INT_START() \
do { \
uint32_t __l_cpsr_tmp; \
__asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp)); \
__asm volatile("BIC %0, %1, #0x80" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp)); \
} while(0)
/** @brief Disable interrupts globally in the system.
* This macro must be used when the system wants to disable all the interrupt
* it could handle.
*/
#define GLOBAL_INT_STOP() \
do { \
uint32_t __l_cpsr_tmp; \
__asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp)); \
__asm volatile("ORR %0, %1, #0x80" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp)); \
} while(0)
/** @brief Disable interrupts globally in the system.
* This macro must be used in conjunction with the @ref GLOBAL_INT_RESTORE macro since this
* last one will close the brace that the current macro opens. This means that both
* macros must be located at the same scope level.
*/
#define GLOBAL_INT_DISABLE(); \
do { \
uint32_t __l_cpsr_tmp; \
uint32_t __l_irq_rest; \
__asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp)); \
__asm volatile("AND %0, %1, #0x80" : "=r"(__l_irq_rest) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("ORR %0, %1, #0x80" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp)); \
/** @brief Restore interrupts from the previous global disable.
* @sa GLOBAL_INT_DISABLE
*/
#define GLOBAL_INT_RESTORE(); \
__asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp)); \
__asm volatile("BIC %0, %1, #0x80" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("ORR %0, %1, %2" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp), "r"(__l_irq_rest)); \
__asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp)); \
} while(0)
/** @brief Invoke the wait for interrupt procedure of the processor.
*
* @warning It is suggested that this macro is called while the interrupts are disabled
* to have performed the checks necessary to decide to move to sleep mode.
*
*/
#define WFI() \
do { \
uint32_t __l_rd; \
__asm volatile("MOV %0, #0" : "=r"(__l_rd)); \
__asm volatile("MCR p15, 0, %0, c7, c0, 4" : "=r"(__l_rd)); \
} while(0)
#endif // LL_H_
component/ble/plf/refip/src/arch/ll/armgcc/ll.s
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/**
****************************************************************************************
*
* @file ll.s
*
* @brief ARM low level functions.
*
* Copyright (C) RivieraWaves 2009-2015
*
* $Rev: $
*
****************************************************************************************
*/
.text
.align 4
component/ble/plf/refip/src/arch/ll/armgcc_4_8/ll.h
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/**
****************************************************************************************
*
* @file ll.h
*
* @brief Declaration of low level functions.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef LL_H_
#define LL_H_
#ifndef __GNUC__
#error "File only included with ARM GCC"
#endif // __GNUC__
#include <stdint.h>
extern uint32_t critical_sec_cnt;
/** @brief Enable interrupts globally in the system.
* This macro must be used when the initialization phase is over and the interrupts
* can start being handled by the system.
*/
#define GLOBAL_INT_START() \
do { \
uint32_t __l_cpsr_tmp; \
__asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp)); \
__asm volatile("BIC %0, %1, #0x80" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp)); \
} while(0)
/** @brief Disable interrupts globally in the system.
* This macro must be used when the system wants to disable all the interrupt
* it could handle.
*/
#define GLOBAL_INT_STOP() \
do { \
uint32_t __l_cpsr_tmp; \
__asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp)); \
__asm volatile("ORR %0, %1, #0x80" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp)); \
} while(0)
/** @brief Disable interrupts globally in the system.
* This macro must be used in conjunction with the @ref GLOBAL_INT_RESTORE macro since this
* last one will close the brace that the current macro opens. This means that both
* macros must be located at the same scope level.
*/
#define GLOBAL_INT_DISABLE() \
do { \
uint32_t __l_cpsr_tmp; \
uint32_t __l_irq_rest; \
__asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp)); \
__asm volatile("AND %0, %1, #0x80" : "=r"(__l_irq_rest) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("ORR %0, %1, #0x80" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp)); \
critical_sec_cnt++; \
/** @brief Restore interrupts from the previous global disable.
* @sa GLOBAL_INT_DISABLE
*/
#define GLOBAL_INT_RESTORE() \
critical_sec_cnt--; \
__asm volatile("MRS %0, CPSR" : "=r"(__l_cpsr_tmp)); \
__asm volatile("BIC %0, %1, #0x80" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp)); \
__asm volatile("ORR %0, %1, %2" : "=r"(__l_cpsr_tmp) : \
"r"(__l_cpsr_tmp), "r"(__l_irq_rest)); \
__asm volatile("MSR CPSR_cxsf, %0" : : "r"(__l_cpsr_tmp)); \
} while(0)
/** @brief Invoke the wait for interrupt procedure of the processor.
*
* @warning It is suggested that this macro is called while the interrupts are disabled
* to have performed the checks necessary to decide to move to sleep mode.
*
*/
#define WFI() \
do { \
uint32_t __l_rd; \
if(critical_sec_cnt != 1) \
*((uint32_t*) 0x00000) = 0xDEAD; \
__asm volatile("MOV %0, #0" : "=r"(__l_rd)); \
__asm volatile("MCR p15, 0, %0, c7, c0, 4" : "=r"(__l_rd)); \
} while(0)
#endif // LL_H_
component/ble/plf/refip/src/arch/ll/armgcc_4_8/ll.s
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/**
****************************************************************************************
*
* @file ll.s
*
* @brief ARM low level functions.
*
* Copyright (C) RivieraWaves 2009-2015
*
* $Rev: $
*
****************************************************************************************
*/
.text
.align 4
component/ble/plf/refip/src/arch/ll/gnuarm/ll.h
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/**
****************************************************************************************
*
* @file ll.h
*
* @brief Declaration of low level functions.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef LL_H_
#define LL_H_
#ifndef __arm__
#error "File only included with RVDS!"
#endif // __arm__
#include <stdint.h>
#include "arch.h"
#include "reg_intc.h"
/** @brief Enable interrupts globally in the system.
* This macro must be used when the initialization phase is over and the interrupts
* can start being handled by the system.
*/
#define GLOBAL_INT_START() ; \
do { \
__enable_irq(); \
} while(0);
#define GLOBAL_INT_STOP() ; \
do { \
__disable_irq(); \
} while(0);
#define GLOBAL_INT_DISABLE() ; \
do { \
uint32_t irq_temp; \
irq_temp = __disable_irq();
#define GLOBAL_INT_RESTORE() ; \
if(!irq_temp) \
{ \
__enable_irq(); \
} \
} while(0);
#define WFI() ; \
do { \
__wfi(); \
}while(0);
#endif // LL_H_
component/ble/plf/refip/src/arch/ll/gnuarm/ll.s
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/**
****************************************************************************************
*
* @file ll.s
*
* @brief ARM low level functions.
*
* Copyright (C) RivieraWaves 2009-2015
*
* $Rev: $
*
****************************************************************************************
*/
.text
.align 4
component/ble/plf/refip/src/arch/ll/rvds/ll.h
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/**
****************************************************************************************
*
* @file ll.h
*
* @brief Declaration of low level functions.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef LL_H_
#define LL_H_
#ifndef __arm__
#error "File only included with RVDS!"
#endif // __arm__
#include <stdint.h>
#include "arch.h"
#include "reg_intc.h"
/** @brief Enable interrupts globally in the system.
* This macro must be used when the initialization phase is over and the interrupts
* can start being handled by the system.
*/
#define GLOBAL_INT_START() ; \
do { \
__enable_irq(); \
} while(0);
#define GLOBAL_INT_STOP() ; \
do { \
__disable_irq(); \
} while(0);
#define GLOBAL_INT_DISABLE() ; \
do { \
uint32_t irq_temp; \
irq_temp = __disable_irq();
#define GLOBAL_INT_RESTORE() ; \
if(!irq_temp) \
{ \
__enable_irq(); \
} \
} while(0);
#define WFI() ; \
do { \
__wfi(); \
}while(0);
#endif // LL_H_
component/ble/plf/refip/src/arch/ll/rvds/ll.s
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;/**
; ****************************************************************************************
; *
; * @file ll.s
; *
; * @brief ARM low level functions.
; *
; * Copyright (C) RivieraWaves 2009-2015
; *
; * $Rev: $
; *
; ****************************************************************************************
; */
AREA ||.text||, CODE, READONLY
IF {CPU} /= "Cortex-M3"
IF {CPU} /= "Cortex-M1"
IF {CPU} /= "Cortex-M0"
CODE32
ENDIF
ENDIF
ENDIF
END
component/ble/plf/refip/src/arch/plf.h
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/**
****************************************************************************************
*
* @file plf.h
*
* @brief This file contains the definitions of the macros and functions that are
* platform dependent. The implementation of those is implemented in the
* appropriate platform directory.
*
* Copyright (C) RivieraWaves 2009-2015
*
*
****************************************************************************************
*/
#ifndef _PLF_H_
#define _PLF_H_
/**
****************************************************************************************
* @defgroup PLF
* @ingroup DRIVERS
*
* @brief Platform register driver
*
* @{
*
****************************************************************************************
*/
/*
* FUNCTION DECLARATIONS
****************************************************************************************
*/
#define plf_read_rf_board_id() 0
#define plf_rf_switch() 1
/// @} PLF
#endif // _PLF_H_