hpw422移植新的sdk
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xushaoxiang
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/*!
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* \file rf_2_4g.h
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*
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* \brief The head file of rf_2_4g.c
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __RF_2_4G_H__
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#define __RF_2_4G_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "rf_config.h"
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#include "xc6xxx.h"
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#include "xc_rf_24g_register.h"
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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/* RF Command Code */
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#define R_REG 0x00
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#define W_REG 0x20
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#define R_RX_PL_WID 0x60
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#define R_RX_PLOAD 0x61
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#define W_TX_PLOAD 0xA0
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#define W_TX_PLOAD_NOACK 0xB0
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#define W_ACK_PLOAD 0xA8
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#define FLUSH_TX 0xE1
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#define FLUSH_RX 0xE2
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#define REUSE_TX_PL 0xE3
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#define CMD_NOP 0xFF
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#define CMD_DONE 0x100
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/* FIFO status */
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#define STAT_TX_REUSE (0x1 << 6)
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#define STAT_TX_FULL (0x1 << 5)
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#define STAT_TX_EMPTY (0x1 << 4)
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#define STAT_RX_FULL (0x02)
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#define STAT_RX_EMPTY (0x01)
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/* STATUS Interrupt status */
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#ifdef XC62XX
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#define MASK_PBT_CRC_FAIL (0x1 << 8)
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#define MASK_RX_SYNC (0x1 << 7)
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#endif
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#define MASK_RX_DR (0x1 << 6)
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#define MASK_TX_DS (0x1 << 5)
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#define MASK_MAX_RT (0x1 << 4)
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#define MASK_ALL_INTER (MASK_RX_DR | MASK_TX_DS | MASK_MAX_RT)
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/* RF State Machine */
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#define CE_CTL_HIGH XC_RF_2_4G->CFG_TOP |= 0x4000
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#define CE_CTL_LOW XC_RF_2_4G->CFG_TOP &= ~0x4000
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/* Number of CRC bytes */
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#define CRC_0BYTE 0U
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#define CRC_1BYTE 1U
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#define CRC_2BYTE 2U
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/* Communication rate */
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#define DR_1M 0x02
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#define DR_2M 0x0A
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#define DR_250K 0x22
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#define DR_125K 0x2A
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/* Communication mode */
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#define TX_MODE 0
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#define RX_MODE 1
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#define TRX_MODE 2
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#define RTX_MODE 3
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#define DELAY_CNT 0U
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#define LOGI(...) printf(__VA_ARGS__)
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#ifdef RF_DEMO
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#define RF_FAIL 0U
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#define RF_SUCCESS 1U
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#define ASSERT while (1)
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#endif
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#define XINCHIP_PACKET 0
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#define PANCHIP_PACKET 1
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#define BELKEN_PACKET 2
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#define TELINK_PACKET 3
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#define HUNTERSUN_PACKET 4
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#ifdef XC62XX
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/* The maximum payload is 256 bytes */
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#define XINCX_2_4G_PIPE0_LEN 32
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#else
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#if (XINCX_RF_NORMAL_PACKET_MODE)
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/* The maximum payload of static packets is 63 bytes */
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#define XINCX_2_4G_PIPE0_LEN 32
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#else
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/* The maximum payload of a dynamic packet is 128 bytes */
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#define XINCX_2_4G_PIPE0_LEN 32
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#endif //XINCX_RF_NORMAL_PACKET_MODE
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#endif //XC62XX
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#define BUFF_LEN XINCX_2_4G_PIPE0_LEN
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#define readl(addr) (*(volatile unsigned int *)(addr))
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#define writel(addr, value) (*(volatile unsigned int *)(addr) = (value))
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/* RF Tx Status Typedef */
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typedef enum
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{
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TX_DATA_OK = 0,
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TX_DATA_INVALID = 1,
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TX_RETRANS_MAX = 2
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} eRF_Tx_Status;
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/*------------------------------------------------------------------------------------
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Global Variables
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Exported Functions
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-------------------------------------------------------------------------------------*/
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void nop_cnt(uint32_t cnt);
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void rf_wr_cmd(uint8_t cmd);
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void rf_rc_calib(void);
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void reset_rf2_4g(void);
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void freq_ctune(uint8_t val);
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void rf24g_modem_init(void);
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void rf24g_config(void);
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void rf24g_init(void);
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void set_rf_dynpd(uint8_t dynpd);
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void set_rf_power(uint8_t tx_pwr);
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void set_rf_afc(void);
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void rf_set_channel(uint16_t channel);
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void set_rf_channel(uint16_t channel);
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void set_rf_txaddr(uint32_t addr_l, uint32_t addr_h);
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void set_rf_pipe0_rxaddr(uint32_t addr_l, uint32_t addr_h);
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void set_rf_tx_addr_width(uint8_t bytes);
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void set_rf_DR(uint8_t rate);
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void set_rf_feature(uint8_t long_pld, uint8_t fec, uint8_t whiten, uint8_t dpl, uint8_t ack_pay, uint8_t dyn_ack);
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void set_rf_compatility_featue(uint8_t guard_cfg, uint8_t long_pld_type, uint8_t preamble_num,
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uint8_t preamble_type, uint8_t crc_scope_header, uint8_t crc_scope_addr);
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uint8_t set_rf_preamble(uint32_t preamble_word);
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void set_rf_guard_woard(uint16_t guard_word);
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void set_rf_mode(uint8_t mode);
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void set_rf_crc(uint8_t crc_byte);
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#ifdef XC62XX
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void set_rf_pipe_rx_payLen(uint16_t p0_len, uint16_t p1_len, uint16_t p2_len, uint16_t p3_len, uint16_t p4_len,
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uint16_t p5_len);
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#else
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void set_rf_pipe_rx_payLen(uint8_t p0_len, uint8_t p1_len, uint8_t p2_len, uint8_t p3_len, uint8_t p4_len,
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uint8_t p5_len);
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#endif
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void set_rf_retr(uint8_t cnt, uint8_t delay);
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void set_rf_enaa(uint8_t pipe0_enaa, uint8_t pipe1_enaa, uint8_t pipe2_enaa, uint8_t pipe3_enaa, uint8_t pipe4_enaa,
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uint8_t pipe5_enaa);
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void set_rf_en_pipe(uint8_t user_pipe);
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void rf_24g_callback(void *context);
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void rf_2M_config(void);
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uint8_t rf_tx_packet(uint8_t *data, uint16_t len);
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uint16_t rf_rx_packet(uint8_t *buff);
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void rf_fill_ack_packet(uint8_t *buff, uint8_t len);
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uint8_t rf_read_ack_packet(uint8_t *buff);
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void rf_off_and_on(void);
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void rf_ana24_set(void);
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int16_t rf_get_rssi(void);
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#ifdef XC62XX
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void rf_pbt_init(void);
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uint8_t rf_set_pbt_hl_ord(bool ord);
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uint8_t rf_set_pbt_hl_offset(uint16_t hl_offset);
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uint8_t rf_set_pbt_h_len(uint8_t handler_len);
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uint8_t rf_set_pbt_en(void);
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uint8_t rf_set_pbt_off(void);
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uint8_t rf_set_crc_bit_inv(bool crc_inv);
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uint8_t rf_set_ack_type(bool ack_type);
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uint8_t rf_set_pid_det(bool pin_en);
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uint8_t rf_set_fifo_len(bool length_fifo);
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uint16_t rf_get_pend_rxfrem_len(void);
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uint8_t rf_set_pbt_auto_trx(bool auto_trx);
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uint8_t rf_set_pbt_pld_len_offset(uint8_t offset);
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uint8_t rf_set_pbt_crc_init(uint32_t init_val);
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uint32_t rf_get_pbt_timer(void);
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uint32_t rf_get_pbt_sync_timer(void);
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uint8_t rf_set_pbt_tx_head(uint8_t *hadnler_buff);
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uint32_t rf_get_pbt_tx_head(void);
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uint32_t rf_get_pbt_rx_head(void);
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uint8_t rf_set_pbt_rx2tx_timer(uint16_t timer);
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uint8_t rf_set_pbt_tx2rx_timer(uint16_t timer);
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uint8_t rf_set_pbt_crc_fail_on(void);
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uint8_t rf_set_pbt_crc_fail_off(void);
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uint8_t rf_set_sync_inter_on(void);
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uint8_t rf_set_sync_inter_off(void);
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uint8_t rf_set_whiten_value(uint8_t value);
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uint8_t rf_set_panchip_whiten_on(void);
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uint8_t rf_set_panchip_whiten_off(void);
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uint8_t rf_set_whiten_opt(uint8_t whiten_opt);
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uint8_t rf_set_pllon_lock_time(uint8_t pll_timer);
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uint8_t rf_set_pbt_auto_trx_timer(uint16_t pbt_rx2tx_timer, uint16_t pbt_tx2rx_timer);
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uint8_t rf_set_pbt_config(uint8_t pbt_auto_trx, int len_offset, uint32_t pbt_crc_init);
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uint8_t rf_clk_div23_en_soften_on(void);
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uint8_t rf_clk_div23_en_soften_off(void);
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uint8_t rf_clk_div23_en_soft_on(void);
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uint8_t rf_clk_div23_en_soft_off(void);
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uint8_t rf_chan_mult_1p5_soften_on(void);
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uint8_t rf_chan_mult_1p5_soften_off(void);
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uint8_t rf_chan_mult_1p5_soft_on(void);
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uint8_t rf_chan_mult_1p5_soft_off(void);
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uint8_t rf_chan_frac_offset(uint32_t value);
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#endif
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void rf_set_freq_dev(uint16_t freq_dev);
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uint16_t rf_get_freq_dev(void);
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void rf_ack_payload_config(void);
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#define INFO_BUFF(buff, len) rf_buff_info(buff, len)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __RF_2_4G__ */
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