hpw422移植新的sdk
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xushaoxiang
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/*!
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* \file xc62xx.h
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*
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* \brief The header of xc62xx chip
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __XC62XX_H__
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#define __XC62XX_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#define __RAM_CODE __attribute__((section("ram_code")))
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#define __WEAK __attribute__((weak))
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
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#endif
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#define __STATIC_INLINE static __inline
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#define FMC_SPI_DMA_OFF
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#define SPI_OFF
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#define SPI_DMA_OFF
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#define UART_DMA_OFF
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#define QDEC_USE_P12_P13
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#define HFCLK_SRC_XTAL_IS_32M
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#define XC62XX_CLOCK_CONFIG
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#define XC62XX_ROM_DRIVER_ADDR
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#define XC62XX_ADC_CALI_PARA
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#define XC62XX_ADC_CHANNEL
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#define BOR_VERSION_IS_V2
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#define NO_SUPPORT_UART2
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#define NO_SUPPORT_HFCLK_RC_16M
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#define NO_SUPPORT_HFCLK_BBPLL_96M
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#define NO_SUPPORT_HFCLK_BBPLL_128M
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#define NO_SUPPORT_LFCLK_XTAL_32768
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#define NO_SUPPORT_PWM_CAPTURE
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#define NO_SUPPORT_PWM_ADC
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#define NO_SUPPORT_PWM_BRAKE
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#define NO_SUPPORT_PWM_LOWPOWER
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#define NO_SUPPORT_DMA
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#define NO_SUPPORT_DMA_LINKLIST
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#define NO_SUPPORT_QUAD_SPI
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#define NO_SUPPORT_M4FPU_FUNTION
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
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/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
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/****** Device Specific Interrupt Numbers ********************************************************/
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/* ToDo: add here your device specific external interrupt numbers
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according the interrupt handlers defined in startup_Device.s
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eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
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BLE_IRQn = 0, /*!< Device Interrupt */
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CPR_IRQn = 2,
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GPIO_IRQn = 3,
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RTC_IRQn = 4,
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TIMER0_IRQn = 5,
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TIMER1_IRQn = 6,
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TIMER2_IRQn = 7,
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TIMER3_IRQn = 8,
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WDT_IRQn = 9,
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I2C_IRQn = 10,
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UART0_IRQn = 11,
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UART1_IRQn = 12,
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SPI0_IRQn = 13,
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KBS_IRQn = 15,
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QDEC_IRQn = 16,
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GADC_IRQn = 17,
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PWM_IRQn = 18,
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AES_IRQn = 19,
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USB_IRQn = 20,
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AUDIO_IRQn = 21,
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RF24G_IRQn = 22,
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MPU_IRQn = 24,
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I2S_IRQn = 26,
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TIMER_AO0_IRQn = 27,
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TIMER_AO1_IRQn = 28,
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CMP_IRQn = 29,
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FMC_IRQn = 30,
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CAN_IRQn = 31
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M# Processor and Core Peripherals */
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/* ToDo: set the defines according your Device */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#if defined ( __CC_ARM )
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#if defined (__TARGET_FPU_VFP)
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#define __FPU_PRESENT 1 /*!< FPU present or not */
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#else
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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#endif
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#else
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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#endif
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/*@}*/ /* end of group <Device>_CMSIS */
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#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __XC62XX_H__ */
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