hpw422移植新的sdk
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xushaoxiang
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/*!
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* \file xc6xxx.h
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*
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* \brief CMSIS xc6xxx Device Peripheral Access Layer Header File.
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __XC6xxx_H
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#define __XC6xxx_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(XC65XX)
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#include "xc65xx.h"
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#elif defined(XC62XX)
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#include "xc62xx.h"
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#elif defined(XC6AXX)
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#include "xc6axx.h"
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#elif defined(XC20XX)
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#include "xc20xx.h"
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#elif defined(XC26XX)
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#include "xc26xx.h"
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#elif defined(XC_LORA_XX)
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#include "xc_lora_xx.h"
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#else
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#error "Please select first the target XC6xxx device used in your application (in xc6xxx.h file)"
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#endif
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#include "sdk_config.h"
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/**
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* @}
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*/
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/*------------------------------------------------------------------------------------
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TypeDef
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-------------------------------------------------------------------------------------*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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XR_OK = 0,
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XR_ERROR,
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XR_TIMEOUT,
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XR_UNKNOWN = 0xFF,
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} eXC_RESULT;
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/**
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* @}
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*/
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extern __RAM_CODE int sendchar(int c);
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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/** @addtogroup Exported_macro
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* @{
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*/
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#define XC_CHECK(module_enabled) (module_enabled)
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#define GD_FlASH_RDID 0x1364c8
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#define BIT(n) ((1UL << (n)))
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
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WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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#define REG_BIT_VAL_GET(REG, MSK, POS) ((REG & MSK) >> POS)
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#define BIT_BUILD(VAL, POS, MSK) ((uint32_t)(((VAL) << POS) & MSK))
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#define MAX(a, b) ((a) < (b) ? (b) : (a))
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// power of 2 macro
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#define POW2(pow) (1 << (pow))
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// Is A greater than or equal to B macro ?
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#define A_MAXEQ_B(a, b) ((a) >= (b))
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#define ALIGN_DOWN_ADDR(a, size) (a & (~(size - 1)))
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#define ALIGN_UP_ADDR(a, size) ((a + size - 1) & (~(size - 1)))
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#if ((defined(DEBUG_ENABLE) && (DEBUG_ENABLE != 1)) || (!defined(DEBUG_ENABLE)))
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#define DEBUG_ENABLE 0
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#else
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#define DEBUG_ENABLE 1
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#endif
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#if (DEBUG_ENABLE == 1)
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#define DEBUG(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#define PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#define RAM_DEBUG(str) \
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{ \
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const char* s = (str); \
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while (*s) { \
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sendchar(*s++); \
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} \
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}
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#else
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#define DEBUG(fmt, ...)
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#define PRINT(fmt, ...)
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#define RAM_DEBUG(str)
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#endif
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#define RSTN_VALID (0UL)
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#define RSTN_INVALID (1UL)
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#ifndef ENABLE
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#define ENABLE 0x01
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#endif
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#ifndef DISABLE
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#define DISABLE 0x00
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#endif
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#ifndef RSTCTL_ENABLE
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#define RSTCTL_ENABLE 0x00
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#endif
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#ifndef RSTCTL_DISABLE
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#define RSTCTL_DISABLE 0x01
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#endif
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#ifndef ASSERT_ERR
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#define ASSERT_ERR(cond) \
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{ \
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}
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#endif
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/** @brief Enable interrupts globally in the system.
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* This macro must be used when the initialization phase is over and the interrupts
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* can start being handled by the system.
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*/
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#define GLOBAL_INT_START() ; \
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do { \
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__enable_irq(); \
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} while(0);
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#define GLOBAL_INT_STOP() ; \
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do { \
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__disable_irq(); \
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} while(0);
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#define GLOBAL_INT_DISABLE() ; \
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do { \
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uint32_t irq_temp; \
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irq_temp = __disable_irq();
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#define GLOBAL_INT_RESTORE() ; \
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if(!irq_temp) \
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{ \
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__enable_irq(); \
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} \
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} while(0);
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/**
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* @}
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*/
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#include "xc_drv_conf.h"
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/**
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* @brief HAL Status structures definition
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*/
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typedef enum
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{
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HAL_OK = 0x00U,
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HAL_ERROR = 0x01U,
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HAL_BUSY = 0x02U,
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HAL_TIMEOUT = 0x03U
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} HAL_StatusTypeDef;
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/**
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* @brief HAL Lock structures definition
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*/
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typedef enum
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{
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HAL_UNLOCKED = 0x00U,
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HAL_LOCKED = 0x01U
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} HAL_LockTypeDef;
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#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
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#define HAL_Delay delay_ms
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void HAL_Delay(unsigned int Delay);
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void Error_Handler(void);
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#define __HAL_LOCK(__HANDLE__) \
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do { \
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if ((__HANDLE__)->Lock == HAL_LOCKED) { \
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return HAL_BUSY; \
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} else { \
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(__HANDLE__)->Lock = HAL_LOCKED; \
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} \
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} while (0U)
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#define __HAL_UNLOCK(__HANDLE__) \
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do { \
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(__HANDLE__)->Lock = HAL_UNLOCKED; \
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} while (0U)
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#if ((__ARMCC_VERSION % 1000) != 960)
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#error "Compiler build number mismatch. Required: build 960."
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#endif
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/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive
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* "#pragma data_alignment=4" must be used instead */
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#if defined(__ARMCC_VERSION) && \
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(__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
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#ifndef __ALIGN_BEGIN
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#define __ALIGN_BEGIN
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#endif
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#ifndef __ALIGN_END
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#define __ALIGN_END __attribute__((aligned(4)))
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#endif
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#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
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#ifndef __ALIGN_END
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#define __ALIGN_END __attribute__((aligned(4)))
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#endif /* __ALIGN_END */
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#ifndef __ALIGN_BEGIN
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#define __ALIGN_BEGIN
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#endif /* __ALIGN_BEGIN */
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#else
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#ifndef __ALIGN_END
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#define __ALIGN_END
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#endif /* __ALIGN_END */
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#ifndef __ALIGN_BEGIN
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#if defined(__CC_ARM) /* ARM Compiler V5*/
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#define __ALIGN_BEGIN __align(4)
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#elif defined(__ICCARM__) /* IAR Compiler */
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#define __ALIGN_BEGIN
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#endif /* __CC_ARM */
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#endif /* __ALIGN_BEGIN */
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#endif /* __GNUC__ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __XCxxxx_H */
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