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hpw422移植新的sdk

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xushaoxiang
2026-07-03 18:08:25 +08:00
commit 945a5a5b0b
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project/example/2.4g/RF24_AutoAck/app/src/main.c
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/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
volatile bool rf24g_rx_irq_flag = false;
volatile bool rf24g_tx_irq_flag = false;
volatile bool rf24g_rx_to_irq_flag = false;
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
#ifdef XC62XX
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
#else
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
#endif
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
#ifdef DEBUG_LOG
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
#ifdef XC62XX
LOGI("HW_CONFIG: 0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
LOGI("PBT_CONFIG: 0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
LOGI("PBT_TIMER: 0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
LOGI("PBT_TX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
LOGI("PBT_RX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
#endif
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
#endif
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint8_t len)
{
for (uint8_t i = 0; i < len; i++)
LOGI("%02x ", buff[i]);
LOGI("\r\n");
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
/* switch mode and set channel */
void rf_switch_mode(uint8_t mode, uint16_t channel)
{
CE_CTL_LOW;
switch (mode) {
case TX_MODE:
case RX_MODE:
break;
default:
LOGI("The mode is set incorrectly\n");
while(1);
}
set_rf_mode(mode);
rf_set_channel(channel);
#ifdef XC62XX
XC_RF_2_4G->STATUS = ((XC_RF_2_4G->CFG_TOP >> 30) & 0x3 << 7) | ((XC_RF_2_4G->CFG_TOP >> 4) & 0x7 << 4);
#else
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
#endif
rf_wr_cmd(FLUSH_RX);
rf_wr_cmd(FLUSH_TX);
if (mode) {
CE_CTL_HIGH;
}
}
/* RF接收完成回调 */
void rf_24g_rx_dr_cb(void)
{
/* set flag */
rf24g_rx_irq_flag = true;
}
/* RF发送完成回调 */
void rf_24g_tx_ds_cb(void)
{
rf24g_tx_irq_flag = true;
}
/* RF接收超时回调 */
void rf_24g_max_rt_cb(void)
{
rf24g_rx_to_irq_flag = true;
}
/* RF 发送数据（自动应答） */
__RAM_CODE eRF_Tx_Status rf_tx_autoack(uint8_t *buff, uint16_t len)
{
eRF_Tx_Status ret = TX_DATA_INVALID;
/* len can't be 0 */
if (len == 0)
{
return ret;
}
/* rf_off_and_on */
rf_off_and_on();
rf24g_tx_irq_flag = false;
rf24g_rx_to_irq_flag = false;
/* send data */
rf_tx_packet(buff, len);
/* wait for ack */
while(1)
{
/* recv ack */
if(rf24g_tx_irq_flag)
{
ret = TX_DATA_OK;
break;
}
/* time out */
else if(rf24g_rx_to_irq_flag)
{
ret = TX_RETRANS_MAX;
break;
}
}
return ret;
}
__RAM_CODE void rf24g_AckPayload_tx_demo(void)
{
uint8_t ack_status = TX_DATA_INVALID;
uint8_t ack_buff[BUFF_LEN] = {0};
uint8_t tx_buff[BUFF_LEN] = {0};
uint8_t ack_len = 0;
uint32_t ack_cnt = 0;
uint32_t tx_cnt = 0;
/* Set testing frequency points */
rf_switch_mode( TX_MODE, XINCX_2_4G_CHANNEL);
/* fill data */
for (uint8_t i = 0; i < BUFF_LEN; i++)
{
tx_buff[i] = i;
}
LOGI( "AutoAck Tx Demo start!\r\n");
/* main loop */
while(true)
{
/* data transmission */
tx_cnt ++;
LOGI( "\r\ntx_cnt = %d\r\n",tx_cnt);
ack_status = rf_tx_autoack(tx_buff, BUFF_LEN);
/* recv ack */
if(ack_status == TX_DATA_OK)
{
ack_cnt += 1;
/* read ack payload */
ack_len = rf_read_ack_packet(ack_buff);
LOGI( "ack_cnt:%d,len=%d\r\n", ack_cnt, ack_len);
if(ack_len)
{
/* print ack data */
rf_buff_info( ack_buff, ack_len);
}
}
else
{
LOGI( "No ack,ack_cnt=%d\r\n",ack_cnt);
}
delay_ms(10);
}
}
__RAM_CODE void rf24g_AckPayload_rx_demo(void)
{
uint8_t ack_buff[BUFF_LEN] = {0};
uint8_t rx_buff[BUFF_LEN] = {0};
uint8_t rx_len;
uint32_t rx_cnt = 0;
/* fill data */
for (uint8_t i = 0; i < BUFF_LEN; i++)
{
ack_buff[i] = BUFF_LEN - i;
}
/* Fill ack pyaload of next packet */
rf_fill_ack_packet(ack_buff, BUFF_LEN);
/* Set the communication mode */
rf_switch_mode( RX_MODE, XINCX_2_4G_CHANNEL);
LOGI( "AutoAck Rx Demo start!\r\n");
while(true)
{
if (rf24g_rx_irq_flag)
{
rf24g_rx_irq_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
/* Read rf data */
rx_len = rf_rx_packet(rx_buff);
/* Receive Count */
rx_cnt += 1;
LOGI("recv:%d\r\n", rx_cnt);
/* Print the received data. */
//rf_buff_info(rx_buff, rx_len);
delay_us(200);
/* rf_off_and_on */
rf_off_and_on();
/* Fill ack pyaload of next packet */
rf_fill_ack_packet(ack_buff, BUFF_LEN);
/* Start recv */
CE_CTL_HIGH;
}
}
}
int main(void)
{
/* Clock initialization */
clock_init();
/* Serial port initialization */
app_uart_init();
/* rf 2.4g initialization configuration */
rf24g_init();
#if (XINCX_RF_TRANS_RATE == DR_250K)
rf_ack_payload_config();
#elif (XINCX_RF_TRANS_RATE == DR_2M)
/* Set 2M mode register configuration */
/* Don't move this function interface */
rf_2M_config();
#endif
#if (XINCX_RF_NVIC_MODE)
/* Enable RF2.4G interrupts */
NVIC_EnableIRQ(RF24G_IRQn);
/* Configure the RF2.4G interrupt priority */
NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
xc_system_param_check_rf24g();
#if XINCX_RF_MODE == TX_MODE
rf24g_AckPayload_tx_demo();
#elif XINCX_RF_MODE == RX_MODE
rf24g_AckPayload_rx_demo();
#endif
while(true);
}