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hpw422移植新的sdk

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xushaoxiang
2026-07-03 18:08:25 +08:00
commit 945a5a5b0b
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project/example/2.4g/RF24_SingleWave/app/rf_config/rf_config.h
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#ifndef SDK_CONFIG_H
#define SDK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> XINCX_RF_NORMAL_PEACKET_MODE - RF normal packet mode
// <i> Configure the frame format, which is a static packet format and can only communicate in one direction.
#ifndef XINCX_RF_NORMAL_PACKET_MODE
#define XINCX_RF_NORMAL_PACKET_MODE 1
#endif
// <o>XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <0=> Xinchip
// <1=> Panchip
// <2=> Beken
// <3=> Telink
// <4=> Huntersun
#ifndef XINCX_RF_COMPATIBILITY_MODE
#define XINCX_RF_COMPATIBILITY_MODE 0
#endif
#if (XINCX_RF_NORMAL_PACKET_MODE == 1)
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
// <2=> TRX Mode
// <3=> RTX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 3
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2424
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7 // 0xCCDDEEDD
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7 // 0xAA
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 1
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
//
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 0
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 0
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 0
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 0
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 0
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 0
#endif
//
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 0
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x00
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 0
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 0
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 0
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 0
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 0
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 0
#endif
// XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 0
#endif
#endif
// </e> //XINCX_RF_PEACKET_MODE normal normal
// <e> XINCX_RF_EMHAMCED_PEACKET_MODE - RF enhanced packet mode
// <i> Configure the frame format, which is a dynamic packet configuration, which can communicate in both directions,and
// <i> ACK can dynamically carry data.
#ifndef XINCX_RF_EMHAMCED_PACKET_MODE
#define XINCX_RF_EMHAMCED_PACKET_MODE 0
#endif
#if (XINCX_RF_EMHAMCED_PACKET_MODE == 1)
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2440
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 1
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 1
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 1
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 1
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 1
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 1
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 1
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x3f
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 1
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 1
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 1
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 1
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 1
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 1
#endif
// <o.0..5> XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 1
#endif
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
// <0=> No retransmission
// <1=> 1 time
// <2=> 2 times
// <3=> 3 times
// <4=> 4 times
// <5=> 5 times
// <6=> 6 times
// <7=> 7 times
// <8=> 8 times
// <9=> 9 times
// <10=> 10 times
// <11=> 11 times
// <12=> 12 times
// <13=> 13 times
// <14=> 14 times
// <15=> 15 times
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
// <0=> 250us
// <1=> 500us
// <2=> 750us
// <3=> 1000us
// <4=> 1250us
// <5=> 1500us
// <6=> 1750us
// <7=> 2000us
// <8=> 2250us
// <9=> 2500us
// <10=> 2750us
// <11=> 3000us
// <12=> 3250us
// <13=> 3500us
// <14=> 3750us
// <15=> 4000us
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 3
#endif
#endif
// </e> //XINCX_RF_PEACKET_MODE enhanced normal
// RF 2.4g Compatibility configuration
//==========================================================
// Compatibility configuration, when you need to be compatible with other RF chips, you don't need to configure this
// option when using our company's chips.
// XINCX_2_4G_PREAMBLE - 2.4g preamble
#ifndef XINCX_2_4G_PREAMBLE
#define XINCX_2_4G_PREAMBLE 0x710f5555
#endif
// XINCX_2_4G_GUARD - 2.4g guard
#ifndef XINCX_2_4G_GUARD
#define XINCX_2_4G_GUARD 0x8fc9
#endif
//
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
//==========================================================
// Crystal capacitor array, adjust to modify the frequency offset of the crystal oscillator.
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
#endif
#endif
//
// <<< end of configuration section >>>
#endif // SDK_CONFIG_H
project/example/2.4g/RF24_SingleWave/app/rf_config/rf_single_config.h
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#ifndef SDK_SINGLE_CONFIG_H
#define SDK_SINGLE_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <o> XINCX_2_4G_CHANNEL_SINGLE - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL_SINGLE
#define XINCX_2_4G_CHANNEL_SINGLE 2440
#endif
// <o> XINCX_POWER_SINGLE - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER_SINGLE
#define XINCX_POWER_SINGLE 0x00006
#endif
// <o> XINCX_2_4G_FREQ_DEV - 2.4g freq dev
//<0x0=> 0 k
//<0x8=> 10 k
//<0x10=> 20 k
//<0x19=> 30 k
//<0x21=> 40 k
//<0x29=> 50 k
//<0x31=> 60 k
//<0x39=> 70 k
//<0x42=> 80 k
//<0x4a=> 90 k
//<0x52=> 100 k
//<0x5a=> 110 k
//<0x62=> 120 k
//<0x6b=> 130 k
//<0x73=> 140 k
//<0x7b=> 150 k
//<0x83=> 160 k
//<0x8b=> 170 k
//<0x94=> 180 k
//<0x9c=> 190 k
//<0xa4=> 200 k
//<0xac=> 210 k
//<0xb4=> 220 k
//<0xbd=> 230 k
//<0xc5=> 240 k
//<0xcd=> 250 k
//<0xd5=> 260 k
//<0xdd=> 270 k
//<0xe6=> 280 k
//<0xee=> 290 k
//<0xf6=> 300 k
//<0xfe=> 310 k
//<0x106=> 320 k
//<0x10f=> 330 k
#ifndef XINCX_2_4G_FREQ_DEV
#define XINCX_2_4G_FREQ_DEV 0x00
#endif
// XINCX_2_4G_CRY_CPT_ARRAY_SINGLE - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY_SINGLE
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY_SINGLE 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY_SINGLE 0x36
#endif
#endif
// <<< end of configuration section >>>
#endif // SDK_SINGLE_CONFIG_H