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hpw422移植新的sdk

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This commit is contained in:
xushaoxiang
2026-07-03 18:08:25 +08:00
commit 945a5a5b0b
2583 changed files with 713209 additions and 0 deletions
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project/example/2.4g/RF24_TRx/app/src/app_64m.c
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#include "app_64m.h"
void use_64m_crtstal_init(void)
{
testpin_64M_config();
xc_pwr_pwrkey_init();
Init_rtc_gpio(4, 0x00);
}
__RAM_CODE void rf_64M_set_rx_channel(uint16_t channel)
{
channel -= 1;
uint16_t ch = channel % 2;
XC_RF_2_4G->RF_CH &= ~(0x3fff);
switch (ch) {
case 0:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16));
break;
case 1:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16) | 0x80008000);
break;
default:
break;
}
(*(volatile unsigned int *)(0x53023010)) &= ~((1 << 24) | (2 << 28));
}
__RAM_CODE void rf_64M_set_tx_channel(uint16_t channel)
{
uint16_t ch = channel % 2;
XC_RF_2_4G->RF_CH &= ~(0x3fff);
switch (ch) {
case 0:
XC_RF_2_4G->RF_CH |= (channel / 2);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16));
break;
case 1:
XC_RF_2_4G->RF_CH |= (channel / 2 + 1);
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16) | 0x80008000);
break;
default:
break;
}
(*(volatile unsigned int *)(0x53023010)) |= ((0x3 << 16) | (1 << 24) | (2 << 28));
}
void testpin_64M_config(void)
{
uint32_t val;
val = (*(volatile unsigned int *)(0x53022040));
val |= (0x7 << 4) | (0x7);
(*(volatile unsigned int *)(0x53022040)) = val; // TPORT_DATA0_SEL set
val = (*(volatile unsigned int *)(0x40000134));
(*(volatile unsigned int *)(0x40000134)) = ((val & ~(0xfu << 28)) | (1u << 28)); // testpin1_ctrl[3:0]=1
// printf("after 0x40000134=0x%x, 0x40000134=0x%x\n", *(volatile unsigned int *)(0x40000134),
// *(volatile unsigned int *)(0x40000134));
val = (*(volatile unsigned int *)(0x53023010));
val &= ~(3 << 28);
#if 1 // diag = 0xc //diag = 0x3
val |= (0x3 << 20) | (0x3 << 16 | 1 << 24 | 2 << 28); // 0xc
(*(volatile unsigned int *)(0x53023010)) = val; // diag_sel[3:0] set
#endif
// LOGI("after 0x53022040=0x%x, 0x53022010=0x%x\n", *(volatile unsigned int *)(0x53022040),
//*(volatile unsigned int *)(0x53023010));
uint32_t addr_val = 0;
xc_gpio_fun_sel(GPIO_4, GPIO_Dx);
xc_gpio_mux_ctl(GPIO_4, GPIO_Mux3); // en test_pin[1]
addr_val = 0x40000174;
*((uint32_t volatile *)addr_val) = 7;
}
void Init_rtc_gpio(uint32_t num, uint8_t inter_mode)
{
uint32_t val;
// if(!((inter_mode>=0x08) &&(inter_mode<=0x0c))) return;
__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x20002);
__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x20002);
__read_hw_reg32(AO_GPIO_MODE, val);
val &= ~(0x0f << (num << 2));
val |= (inter_mode << (num << 2));
__write_hw_reg32(AO_GPIO_MODE, val);
__read_hw_reg32(AO_GPIO_CTL, val);
val |= (1 << (8 + num));
__write_hw_reg32(AO_GPIO_CTL, val);
// rtc_ao_gpio_mode__aogpio_debounce_en3__setf(1);
NVIC_EnableIRQ(RTC_IRQn);
}
project/example/2.4g/RF24_TRx/app/src/main.c
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/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define ACK_WAIT_TO 500000/* 500ms */
/*------------------------------------------------------------------------------------
Static Variables
-------------------------------------------------------------------------------------*/
static uint32_t rx_cnt = 0;
static uint32_t tx_cnt = 0;
static uint32_t tx_ack_cnt = 0;
static uint8_t tx_buf[256] = {0};
static uint8_t rx_buf[256] = {0};
static uint16_t rx_len = 0;
static bool rf24g_rx_irq_flag = false;
static bool rf24g_tx_irq_flag = false;
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
#ifdef XC62XX
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
#else
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
#endif
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
#ifdef DEBUG_LOG
/**
* @brief RF 2.4g register information printing
* @param void
* @retval void
*/
void rf_2M_reg_info(void)
{
/* Register information printing */
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG_L: 0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("rccal_reg_l: 0x%08x\r\n", XC_BT_RF->rccal_reg_l);
LOGI("ana2_reg_l: 0x%08x\r\n", XC_BT_RF->ana2_reg_l);
LOGI("ana3_reg_l: 0x%08x\r\n", XC_BT_RF->ana3_reg_l);
LOGI("ana4_reg_l: 0x%08x\r\n", XC_BT_RF->ana4_reg_l);
LOGI("ana5_reg_l: 0x%08x\r\n", XC_BT_RF->ana5_reg_l);
LOGI("ana14_reg_l: 0x%08x\r\n", XC_BT_RF->ana14_reg_l);
LOGI("ana15_reg_l: 0x%08x\r\n", XC_BT_RF->ana15_reg_l);
LOGI("ana16_reg_l: 0x%08x\r\n", XC_BT_RF->ana16_reg_l);
LOGI("ana17_reg_l: 0x%08x\r\n", XC_BT_RF->ana17_reg_l);
LOGI("ana18_reg_l: 0x%08x\r\n", XC_BT_RF->ana18_reg_l);
LOGI("ana21_reg_l: 0x%08x\r\n", XC_BT_RF->ana21_reg_l);
LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
#ifdef XC62XX
LOGI("HW_CONFIG: 0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
LOGI("PBT_CONFIG: 0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
LOGI("PBT_TIMER: 0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
LOGI("PBT_TX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
LOGI("PBT_RX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
#endif
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
#endif // DEBUG_LOG
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint16_t len)
{
for (uint16_t i = 0; i < len; i++)
LOGI("%02x ", buff[i]);
LOGI("\r\n");
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
/* switch mode and set channel */
void rf_switch_mode(uint8_t mode, uint16_t channel)
{
CE_CTL_LOW;
switch (mode) {
case TX_MODE:
case RX_MODE:
break;
default:
LOGI("The mode is set incorrectly\n");
while(1);
}
set_rf_mode(mode);
rf_set_channel(channel);
#ifdef XC62XX
XC_RF_2_4G->STATUS = ((XC_RF_2_4G->CFG_TOP >> 30) & 0x3 << 7) | ((XC_RF_2_4G->CFG_TOP >> 4) & 0x7 << 4);
#else
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
#endif
rf_wr_cmd(FLUSH_RX);
rf_wr_cmd(FLUSH_TX);
if (mode) {
CE_CTL_HIGH;
}
}
/* RF发送完成回调 */
void rf_24g_tx_ds_cb(void)
{
/* set flag */
rf24g_tx_irq_flag = true;
}
/* RF接收完成回调 */
void rf_24g_rx_dr_cb(void)
{
/* stop RF */
CE_CTL_LOW;
/* set flag */
rf24g_rx_irq_flag = true;
/* recv data */
rx_len = rf_rx_packet(rx_buf);
/* start RF */
CE_CTL_HIGH;
}
void rf24g_trx_demo()
{
uint32_t i;
volatile uint32_t to = 0;
/* fill data */
for(i=0;i<BUFF_LEN;i++)
{
tx_buf[i] = i;
}
LOGI("%s start!\n",__FUNCTION__);
/* main loop */
while(true)
{
/* Set the communication mode */
rf_switch_mode( TX_MODE, XINCX_2_4G_CHANNEL);
tx_buf[0] = tx_cnt;
tx_cnt += 1;
rf24g_tx_irq_flag = false;
rf_tx_packet(tx_buf, BUFF_LEN);
/* wait for tx done */
while(!rf24g_tx_irq_flag)
{
}
/* rf_off_and_on */
rf_off_and_on();
/* switch to Rx Mode */
rf_switch_mode( RX_MODE, XINCX_2_4G_CHANNEL);
to = 0;
while(to<ACK_WAIT_TO)
{
if(rf24g_rx_irq_flag)
{
/* receive ack */
rf24g_rx_irq_flag = false;
if (rx_len)
{
/* transmit success */
tx_ack_cnt += 1;
LOGI("\nsendCnt=%d,ackCnt=%d\nAck:", tx_cnt, tx_ack_cnt);
rf_buff_info( rx_buf, rx_len);
}
else
{
}
break;
}
delay_us(100);
to += 100;
}
if(to>=ACK_WAIT_TO)
{
LOGI("\nsendCnt=%d,ackCnt=%d\nNoAck.", tx_cnt, tx_ack_cnt);
}
else
{
while(to<ACK_WAIT_TO)
{
delay_us(100);
to += 100;
}
}
//while(1);
}
}
void rf24g_rtx_demo()
{
/* Set the communication mode */
rf_switch_mode( RX_MODE, XINCX_2_4G_CHANNEL);
LOGI("%s start!\n",__FUNCTION__);
/* main loop */
while(true)
{
if (rf24g_rx_irq_flag)
{
rf24g_rx_irq_flag = false;
if (rx_len)
{
/* Receive Count */
rx_cnt += 1;
/* delay 200us to wait for the other end ready */
delay_us(200);
/* send Ack */
rf_switch_mode( TX_MODE, XINCX_2_4G_CHANNEL);
memcpy( tx_buf, rx_buf, rx_len);
rf24g_tx_irq_flag = false;
rf_tx_packet(tx_buf, rx_len);
/* wait for tx done */
while(!rf24g_tx_irq_flag)
{
}
/* rf_off_and_on */
rf_off_and_on();
/* switch to Rx Mode */
rf_switch_mode( RX_MODE, XINCX_2_4G_CHANNEL);
LOGI("\nrecvCnt=%d\npayload:", rx_cnt);
rf_buff_info( rx_buf, rx_len);
}
}
}
}
void main_loop(void)
{
#if XINCX_RF_MODE == TRX_MODE
rf24g_trx_demo();
#elif XINCX_RF_MODE == RTX_MODE
rf24g_rtx_demo();
#endif
}
int main(void)
{
/* Clock initialization */
clock_init();
/* Serial port initialization */
app_uart_init();
/* rf 2.4g initialization configuration */
rf24g_init();
//rf_compatible_config();
#if (XINCX_RF_TRANS_RATE == RATE_2M)
/* Set 2M mode register configuration */
/* Don't move this function interface */
rf_2M_config();
#endif //(XINCX_RF_TRANS_RATE == RATE_2M)
#if (XINCX_RF_NVIC_MODE)
/* Enable RF2.4G interrupts */
NVIC_EnableIRQ(RF24G_IRQn);
/* Configure the RF2.4G interrupt priority */
NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
xc_system_param_check_rf24g();
#if XINCX_RF_MODE == TRX_MODE
rf24g_trx_demo();
#elif XINCX_RF_MODE == RTX_MODE
rf24g_rtx_demo();
#endif
while(true);
}
void gpio_test(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLDOWN;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = GPIO_Dx;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
gpio_cfg.Pin = TEST_GPIO_1;
xc_gpio_init(&gpio_cfg);
xc_gpio_write_pin(TEST_GPIO_1, GPIO_PIN_RESET);
gpio_cfg.Pin = TEST_GPIO_2;
xc_gpio_init(&gpio_cfg);
xc_gpio_write_pin(TEST_GPIO_2, GPIO_PIN_RESET);
}
project/example/2.4g/RF24_TRx/app/src/rf_compatible_normal.c
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#include "rf_compatible_normal.h"
uint16_t crc = 0;
uint8_t panchip_data_length = XINCX_2_4G_PIPE0_LEN - XINCX_2_4G_CRC_BYTE;
uint16_t rf_addr_crc = 0;
uint8_t panchip_addr_whiten;
uint8_t addr_buff[5] = {0};
uint32_t send_cnt = 0;
uint32_t recv_cnt = 0;
/**
* @brief Rf 2.4g get addr
* @param uint8_t *addr_buff
*
* @retval void
*/
void rf_addr_map(uint8_t *addr_buff)
{
uint8_t addr_xsb = (XC_RF_2_4G->CFG_TOP >> 11) & (0x1);
LOGI("addr_xsb %02x\r\n", addr_xsb);
if (!addr_xsb) {
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
} else {
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
}
}
/**
* @brief RF 2.4g get address crc
* @param void
* @retval crc data
*/
uint16_t rf_get_addr_crc(void)
{
#if (1 == XINCX_2_4G_CRC_BYTE)
return crc8_rohc(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#elif (2 == XINCX_2_4G_CRC_BYTE)
return crc16_ccitt_false(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#endif
}
/**
* @brief Address whitening and writing
* @param void
* @retval uint8_t whiten_addr
*/
uint8_t rf_recv_addr(void)
{
uint16_t whiten_addr = whiten_data((uint8_t *)addr_buff, RF_ADDR_LEN, PANCHIP_WHITEN_INIT_VAL);
/* Set PTX address */
set_rf_txaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
/* Set PRX address */
set_rf_pipe0_rxaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
return whiten_addr;
}
void rf_compatible_config(void)
{
#if (XINCX_RF_COMPATIBILITY_MODE == BELKEN_PACKET)
#if XC62XX
set_rf_retr(XINCX_2_4G_RETRANS_CNT, XINCX_2_4G_RETRANS_DELAY);
XC_RF_2_4G->FEATURE &= ~(1 << 5);
rf_set_ack_type(1);
rf_set_freq_dev(RF_FREQ_DEV);
#endif
#elif (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
XC_RF_2_4G->FEATURE |= (1 << 11) | (2 << 12) | (1 << 14) | (1 << 18);
XC_RF_2_4G->PREAMBLE = 0x710f55;
/* 白化cc2500、同步字中断、CRC中断 */
XC_RF_2_4G->CFG_TOP |= (1 << 30) | (1 << 22);
/* get addr */
rf_addr_map(addr_buff);
/* Calculate the CRC of the address block */
rf_addr_crc = rf_get_addr_crc();
/* The address range is whitened and the whitened address is rewritten */
panchip_addr_whiten = rf_recv_addr();
#if XC62XX
rf_set_whiten_value(panchip_addr_whiten);
rf_set_fifo_len(1);
#else
XC_RF_2_4G->FEATURE |= (1 << 5);
XC_RF_2_4G->CFG_TOP &= ~(0x7f << 23);
XC_RF_2_4G->CFG_TOP |= (panchip_addr_whiten << 23);
#endif
set_rf_crc(CRC_0BYTE);
#endif
}
uint8_t rf_panchip_normal_recv_data_cfg(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return 1;
}
uint16_t crc_data = 0;
/* Whiten */
whiten_data(buff, len + 2, panchip_addr_whiten);
/* CRC */
crc = ~crc16_ccitt_false(buff, len, rf_addr_crc, PACKET_NORMAL);
crc_data = ((buff[len] << 8) | (buff[len + 1]));
if (crc == crc_data) {
buff_bigandsmallend(buff, len);
} else {
len = 0;
}
return len;
}
uint8_t rf_panchip_normal_send_data_cfg(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return 1;
}
buff_bigandsmallend(buff, len);
crc = ~crc16_ccitt_false(buff, panchip_data_length, rf_addr_crc, PACKET_NORMAL);
buff[panchip_data_length] = (crc >> 8) & 0xff;
buff[panchip_data_length + 1] = crc & 0xff;
/* Whiten */
whiten_data(buff, len + 2, panchip_addr_whiten);
return 0;
}
uint32_t rf_rx_normal_manage(void)
{
if (rf24g_rx_irq_flag) {
rf24g_rx_irq_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
uint8_t len = recv_len;
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
#endif
len = rf_panchip_normal_recv_data_cfg(recv_buf, len - 2);
if (len) {
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
#endif
// rf_buff_info(recv_buf, len);
/* Receive Count */
recv_cnt++;
LOGI("recv:%d, len:%d\r\n", recv_cnt, len);
/* Receive read data buffer reset */
memset(recv_buf, 0, len);
len = 0;
}
#if (DEBUG_PIN)
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
#endif
/* Entering the receiver */
CE_CTL_HIGH;
}
return 0;
}
uint32_t rf_tx_normal_manage(uint8_t *buff, uint8_t length)
{
if (rf24g_tx_irq_flag) {
rf24g_tx_irq_flag = false;
buff[0] = send_cnt++;
/* Filling in software frame number */
LOGI("data len:%d, send_cnt:%d\n", length - XINCX_2_4G_CRC_BYTE, send_cnt);
// rf_buff_info(buff, length);
rf_panchip_normal_send_data_cfg(buff, length - XINCX_2_4G_CRC_BYTE);
/* data transmission */
rf_tx_packet(buff, length);
}
return 0;
}