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hpw422移植新的sdk

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This commit is contained in:
xushaoxiang
2026-07-03 18:08:25 +08:00
commit 945a5a5b0b
2583 changed files with 713209 additions and 0 deletions
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project/example/driver/pwr/app/src/main.c
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/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
clock_cfg.lfclk_src = CLOCK_LFCLK_SRC_RC;
if(clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if(clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get( ) / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
void bor_init(void)
{
#if (!defined(BOR_VERSION_IS_V2) && !defined(XC62XX))
Bor_InitCfg_t bor_cfg = {
.mode = BOR_MODE_INTRST,
.rst_volt = BOR_RST_VOLT_2V,
};
#else
Bor_InitCfg_t bor_cfg = {
.mode = BOR_MODE_DIRECTRST,
.rst_volt = BOR_RST_VOLT_2V,
};
#endif // !defined(BOR_VERSION_IS_V2) && !defined(XC62XX)
xc_bor_init(&bor_cfg);
}
void wdt_init(void)
{
WDT_InitCfg_t wdt_cfg ;
wdt_cfg.WorkMode = WDT_WORK_MODE0;
wdt_cfg.ReloadValue = WDT_CLK_32K_RESET_MODE0_2048MS;
wdt_cfg.PclkSel = WDT_WORK_32K;
xc_wdt_init(&wdt_cfg);
xc_wdt_start();
}
int main(void)
{
wdt_init();
// Clock Initialization
clock_init();
app_uart_init();
bor_init();
DEBUG("__START__\n");
#ifdef USED_DCDC
xc_pwr_dcdc_init(4);
xc_pwr_dcdc_open();
#endif
/* pwr demo */
pwr_demo( );
while(1)
{
/* main loop */
;
}
}
project/example/driver/pwr/app/src/pwr.c
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/*!
* \file pwr.c
*
* \brief Target pwr implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "pwr.h"
#include "xc_drv_pwr.h"
#include "xc_drv_fmc_spi.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define GPIO_DUMMY (0xFF)
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
* @brief pwr_demo
* @details
* @param void
* @retval void
*/
void wakeup_timer_set(uint32_t time)
{
cprao_aon_reg1__timer_ao_sleep_clksw__setf(0);
AOTimer_InitCfg_t aotimer_cfg;
aotimer_cfg.aotimer_mode = AOTIMER_MODE_CYCLE;
// Timer0 Config & Start
xc_aotimer_init(AOTIMER0_IDX, &aotimer_cfg);
xc_aotimer_set_value(AOTIMER0_IDX, time);
xc_aotimer_start(AOTIMER0_IDX);
}
void wakeup_timer_init()
{
Timer_InitCfg_t timer_cfg;
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32K;
timer_cfg.timer_div_clk = TIMER_DIV_CLK_32000Hz;
timer_cfg.timer_mode = TIMER_MODE_SINGLE;
// Timer0 Config & Start
xc_timer_init(TIMER0_IDX, &timer_cfg);
}
static void system_sleep_init()
{
uint32_t wake_it_src;
#if (USE_XIP == 1)
#if (USE_ROM_FLASH)
FMC_SPI_Init_Oprt();
#else // (USE_ROM_FLASH)
xc_fmc_spi_init_oprt();
#endif // (USE_ROM_FLASH)
#endif
#if (USE_XIP != 1)
SPI_InitCfg_t spi_cfg = {0};
spi_cfg.Mode = SPI_MODE_MASTER;
spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
spi_cfg.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
spi_cfg.CLKPhase = SPI_CPHA_LEAD;
spi_cfg.FirstBit = SPI_FirstBit_MSB;
xc_spi_init(XC_SPI0, &spi_cfg);
SPI_Flash_PowerDown(XC_SPI0);
#endif
xc_pwr_gpio_sleep_config();
wake_it_src = GPIO_IRQn_WAKE | RTC_IRQn_WAKE|TIMER_AO0_IRQn_WAKE| TIMER0_IRQn_WAKE | MPU_IRQn_WAKE;
xc_pwr_wake_it_set(wake_it_src);
}
static void system_lightsleep_cfg()
{
#if (USE_XIP != 1)
cprao_aon_puctrl1_set(0x4); /* puctrl1= 0x4 , SSI0RX must pulldown*/
#endif
cprao_aon_sys_time_set((RST_READY_TIME << 12) | (OSC32_STABLE_TIME));
xc_pwr_pd_lightsleep_set();
xc_pwr_sleepsrc_mask_set(0x1e001e);
xc_pwr_osc_off();
}
void system_deepsleep_cfg()
{
#if (USE_XIP!=1)
cprao_aon_puctrl1_set(0xf);
#endif
cprao_aon_sys_time_set((RST_READY_TIME<<12) | (OSC32_STABLE_TIME));
xc_pwr_pd_deepsleep_set();
delay_us(100);
xc_pwr_sleepsrc_mask_set(0x1e001e);
xc_pwr_osc_off();
}
void sleep_reg_flag_set()
{
uint32_t val=0;
val=cprao_aon_reg0_get();
val=WAKE_DEEP_SLEEP;
cprao_aon_reg0_set(val);
}
void DeepSleep_Demo()
{
uint32_t val=0;
val=cprao_aon_reg0_get();
if(val==WAKE_POWER_DOWN)
{
DEBUG("POWER DOWN RESET\n");
}else if(val==WAKE_DEEP_SLEEP)
{
DEBUG("DEEPSLEEP WAKE\n");
}
system_sleep_init();
sleep_reg_flag_set();
// PWRKEY Initialization is required after deep sleep wakeup
xc_pwr_pwrkey_init();
xc_pwr_pwrkey_deepsleep_wake_config(GPIO_2, DEEP_SLEEP_GPIO_WAKE_HIGH_LEVEL);
xc_pwr_pwrkey_deepsleep_wake_config(GPIO_3, DEEP_SLEEP_GPIO_WAKE_LOW_LEVEL);
system_deepsleep_cfg();
while(1)
{
xc_deep_sleep();
}
}
void DeepSleep_Timerwakeup_Demo()
{
system_sleep_init();
// PWRKEY Initialization is required after deep sleep wakeup
xc_pwr_pwrkey_init();
system_deepsleep_cfg();
while(1)
{
wakeup_timer_set(1000*1000);
xc_deep_sleep();
}
}
static void sleep_init(void)
{
system_sleep_init();
system_lightsleep_cfg();
/* Timer for sleep-wake*/
Timer_InitCfg_t timer_cfg;
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32K;
timer_cfg.timer_div_clk = TIMER_DIV_CLK_32000Hz;
timer_cfg.timer_mode = TIMER_MODE_SINGLE;
xc_timer_init(TIMER0_IDX, &timer_cfg);
}
__RAM_CODE void xc_mcu_sleep(void)
{
xc_adc_powerdown();
xc_pwr_usb_off();
xc_pwr_rc16m_off();
xc_pwr_rc32k_calib_off();
xc_pwr_opa_tempsensor_off();
xc_pwr_opa_volr_off();
xc_pwr_revddldo_off();
xc_pwr_dcdc_close();
xc_pwr_rfdigital_off();
xc_pwr_rc32k_calib_off();
cprao_aon_reg4__bb_coreldo_normal_sw_mux__setf(0);
xc_pwr_modem_off();
xc_pwr_pd_lightsleep_set();
#if (USE_XIP == 1)
#if (USE_ROM_FLASH)
FMC_SPI_Flash_PowerDown();
#else // (USE_ROM_FLASH)
xc_fmc_spi_flash_power_down();
#endif // (USE_ROM_FLASH)
xc_pwr_rom_off();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
// cpr_fmc_ctl_set(0x3000 | (1 << 9)); // close FMC
for (int i = 0; i < 10; i++) {
__NOP();
__NOP();
__NOP();
}
#endif
// __disable_irq();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__WFI();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
// cpr_fmc_ctl_set(0x3503);
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
xc_pwr_rom_on();
for (int i = 0; i < 10; i++) {
__NOP();
__NOP();
__NOP();
}
#if (USE_ROM_FLASH)
FMC_SPI_Flash_WakeUp();
#else // (USE_ROM_FLASH)
xc_fmc_spi_flash_wake_up();
#endif // (USE_ROM_FLASH)
xc_pwr_ao_timer_pclk32m_Set();
// __enable_irq();
#ifdef USED_DCDC
xc_pwr_dcdc_open();
#endif
xc_pwr_modem_on();
xc_pwr_rfdigital_on();
xc_adc_wakeup();
}
void Sleep_Demo()
{
xc_rc32k_calib_by_soft();
sleep_init();
xc_pwr_gpio_lightsleep_wake_config(GPIO_3, RIS_EDGE_INT);
xc_pwr_gpio_lightsleep_wake_config(GPIO_2, FAIL_EDGE_INT);
xc_fmc_spi_init_oprt();
xc_fmc_spi_flash_wake_up();
while(1){
// Checks for sleep have to be done with interrupt disabled
GLOBAL_INT_DISABLE();
uint32_t duration_timer = (500*1000); //500ms
xc_timer_set_value(TIMER0_IDX, duration_timer);
xc_timer_start(TIMER0_IDX);
// Before you sleep, turn off the peripheral to make sure it doesn't generate interrupts,
// and then turn it on again after you sleep up.
// For example, timer interrupts
xc_rc32k_soft_calib_disable();
#if (defined(XC62XX_RFANA2_BIT13_SET) && (CONFIG_HFCLK_IS_OSC32M_PLL_32M == 1))
extern void rf_ana2_bit13_disable(void);
rf_ana2_bit13_disable();
#endif // XC62XX_RFANA2_BIT13_SET && CONFIG_HFCLK_IS_OSC32M_PLL_32M==0
xc_mcu_sleep();
#if (defined(XC62XX_RFANA2_BIT13_SET) && (CONFIG_HFCLK_IS_OSC32M_PLL_32M == 1))
extern void rf_ana2_bit13_enable(void);
rf_ana2_bit13_enable();
#endif // XC62XX_RFANA2_BIT13_SET && CONFIG_HFCLK_IS_OSC32M_PLL_32M==0
xc_timer_stop(TIMER0_IDX);
xc_rc32k_soft_calib_enable();
GLOBAL_INT_RESTORE();
// The delay can be omitted, rc32k will calibrate every time it wakes up, and it takes 2ms.
delay_ms(3);
xc_wdt_reload();
}
}
static void uart0_receive_cb(uint8_t *buff, uint16_t len)
{
for (int i = 0; i < len; i++)
DEBUG("UART0:0x%x\n",buff[i]);
}
static void uart0_sleep_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.Pin = GPIO_DUMMY;
gpio_cfg.Dir = GPIO_DIR_INPUT;
gpio_cfg.FunSel = UART0_RX;
xc_gpio_init(&gpio_cfg);
xc_pwr_gpio_lightsleep_wake_config(GPIO_19, FAIL_EDGE_INT);
NVIC_DisableIRQ(UART0_IRQn);
}
static void uart0_wakeup_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
gpio_cfg.FunSel = UART0_RX;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_TCR_STOP_1BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
xc_uart_register_receive_cb(UART0_IDX, uart0_receive_cb);
xc_uart_enable_rx_it(UART0_IDX);
NVIC_EnableIRQ(UART0_IRQn);
}
void uart0_init(void)
{
DEBUG("uart0 init\n");
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
gpio_cfg.FunSel = UART0_TX;
xc_gpio_init(&gpio_cfg);
uart0_wakeup_init();
}
void Sleep_Uartwakeup_Demo()
{
xc_rc32k_calib_by_soft();
// sleep init
system_sleep_init();
system_lightsleep_cfg();
uart0_init();
xc_fmc_spi_init_oprt();
xc_fmc_spi_flash_wake_up();
while (1)
{
// Checks for sleep have to be done with interrupt disabled
GLOBAL_INT_DISABLE();
// Before you sleep, turn off the peripheral to make sure it doesn't generate interrupts,
// and then turn it on again after you sleep up.
// For example, timer interrupts
xc_rc32k_soft_calib_disable();
#if (defined(XC62XX_RFANA2_BIT13_SET) && (CONFIG_HFCLK_IS_OSC32M_PLL_32M == 1))
extern void rf_ana2_bit13_disable(void);
rf_ana2_bit13_disable();
#endif // XC62XX_RFANA2_BIT13_SET && CONFIG_HFCLK_IS_OSC32M_PLL_32M==0
uart0_sleep_init();
xc_mcu_sleep();
uart0_wakeup_init();
#if (defined(XC62XX_RFANA2_BIT13_SET) && (CONFIG_HFCLK_IS_OSC32M_PLL_32M == 1))
extern void rf_ana2_bit13_enable(void);
rf_ana2_bit13_enable();
#endif // XC62XX_RFANA2_BIT13_SET && CONFIG_HFCLK_IS_OSC32M_PLL_32M==0
xc_rc32k_soft_calib_enable();
GLOBAL_INT_RESTORE();
// The delay can be omitted, rc32k will calibrate every time it wakes up, and it takes 2ms.
delay_ms(3000);
}
}
#define SLEEP_DEMO 1
#define DEEPSLEEP_DEMO 0
#define DEEPSLEEP_TIMERWAKEUP_DEMO 0
#define SLEEP_UARTWAKEUP_DEMO 0
void pwr_demo()
{
#if SLEEP_DEMO
Sleep_Demo();
#endif
#if DEEPSLEEP_DEMO
DeepSleep_Demo();
#endif
#if DEEPSLEEP_TIMERWAKEUP_DEMO
DeepSleep_Timerwakeup_Demo();
#endif
#if SLEEP_UARTWAKEUP_DEMO
Sleep_Uartwakeup_Demo();
#endif
}
project/example/driver/pwr/app/src/rom_symdefs.o
+273
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#<SYMDEFS># ARM Linker, 5060750: Last Updated: Tue Sep 05 15:30:26 2023
0x10000808 D co_default_bdaddr
0x00004169 T ke_msg_alloc
0x000041ed T ke_msg_send
0x00004225 T ke_msg_send_basic
0x000042e9 T ke_state_set
0x00004359 T ke_task_create
0x000042b9 T ke_state_get
0x000041af T ke_msg_discard
0x000041b3 T ke_msg_forward
0x000041dd T ke_msg_in_queue
0x00004233 T ke_msg_src_id_get
0x00003e05 T ke_free
0x000041d5 T ke_msg_free
0x00003c21 T ke_check_malloc
0x0000dbf5 T rwip_init
0x0000de79 T rwip_schedule
0x10000938 D rwip_rf
0x00000df9 T BLE_Handler
0x0000238d T co_buf_alloc
0x000024fd T co_buf_copy_data_from_mem
0x00002721 T co_buf_release
0x000028c9 T co_djob_prepare
0x000028d5 T co_djob_reg
0x0000291d T co_djob_unreg
0x00002969 T co_list_extract
0x000029ad T co_list_extract_after
0x00002ac5 T co_list_pop_front
0x00002ae9 T co_list_push_back
0x00002b39 T co_list_push_front
0x00002b55 T co_time_get
0x00002ce5 T co_time_timer_init
0x00002dcd T co_time_timer_set
0x00002df9 T co_time_timer_stop
0x00000e95 T aes_c1
0x00001465 T aes_encrypt
0x000014cd T aes_f4
0x00001521 T aes_f5
0x00001641 T aes_f6
0x000016bd T aes_g2
0x00001c35 T aes_rand
0x000012a1 T aes_cmac
0x000025b1 T co_buf_head_release
0x000025dd T co_buf_head_reserve
0x00002ec5 T co_util_pack
0x000030d5 T co_util_unpack
0x0000ddd9 T rwip_reset
0x00001da5 T aes_rpa_resolve
0x00002799 T co_buf_reuse
0x000027dd T co_buf_size
0x00002489 T co_buf_copy
0x00002569 T co_buf_duplicate
0x000027ed T co_buf_tail_release
0x00002a0d T co_list_init
0x00002285 T ble_util_buf_rx_free
0x00001f69 T ble_util_buf_acl_tx_alloc
0x00002439 T co_buf_cb_free_set
0x00003fad T ke_malloc
0x00002a25 T co_list_insert_after
0x0000459d T ke_timer_active
0x000045ad T ke_timer_clear
0x00004641 T ke_timer_set
0x00002369 T co_buf_acquire
0x00002819 T co_buf_tail_reserve
0x00002531 T co_buf_copy_data_to_mem
0x00002a55 T co_list_insert_before
0x10000e90 D rom_env
0x1000096c D rwip_param
0x0000fe8d D one_bits
0x000039bd T hci_rd_rem_ver_info_cmd_handler
0x00003445 T hci_le_con_upd_cmd_handler
0x00003705 T hci_le_rd_chnl_map_cmd_handler
0x00003761 T hci_le_rd_rem_feats_cmd_handler
0x0000354d T hci_le_en_enc_cmd_handler
0x0000369d T hci_le_ltk_req_reply_cmd_handler
0x0000360d T hci_le_ltk_req_neg_reply_cmd_handler
0x00003851 T hci_le_rem_con_param_req_reply_cmd_handler
0x000037f9 T hci_le_rem_con_param_req_neg_reply_cmd_handler
0x000038d9 T hci_le_set_data_len_cmd_handler
0x00003be5 T hci_vs_set_pref_slave_latency_cmd_handler
0x00003b9d T hci_vs_set_pref_slave_evt_dur_cmd_handler
0x00003ab9 T hci_vs_set_max_rx_size_and_time_cmd_handler
0x00003a39 T hci_rd_rssi_cmd_handler
0x0000d749 T llm_ch_map_update_ind_handler
0x0000650d T llc_loc_llcp_rsp_to_handler
0x00007161 T llc_rem_llcp_rsp_to_handler
0x00005255 T llc_encrypt_ind_handler
0x00006739 T llc_op_ver_exch_ind_handler
0x000066d5 T llc_op_feats_exch_ind_handler
0x00006675 T llc_op_encrypt_ind_handler
0x00006609 T llc_op_dl_upd_ind_handler
0x0000657d T llc_op_con_upd_ind_handler
0x00006525 T llc_op_ch_map_upd_ind_handler
0x0000bda9 T lld_llcp_rx_ind_handler
0x0000bf1d T lld_llcp_tx_cfm_handler
0x00007551 T lld_acl_rx_ind_handler
0x000075dd T lld_acl_tx_cfm_handler
0x00009509 T lld_con_param_upd_cfm_handler
0x00008921 T lld_ch_map_upd_cfm_handler
0x000094cd T lld_con_offset_upd_ind_handler
0x00003435 T hci_command_llc_handler
0x00003385 T hci_acl_data_handler
0x00003cc1 T ke_event_callback_set
0x00003cd9 T ke_event_clear
0x00003db1 T ke_event_set
0x000022e5 T ble_util_nb_good_channels
0x0000230d T ble_util_pkt_dur_in_us
0x0000234d T co_bdaddr_compare
0x000088bd T lld_ch_assess_data_get
0x000088c5 T lld_ch_map_set
0x0000c16d T lld_read_clock
0x0000c30d T lld_res_list_peer_update
0x0000d60d T lld_white_list_add
0x0000dd99 T rwip_prevent_sleep_clear
0x0000ddb9 T rwip_prevent_sleep_set
0x0000f071 T sch_plan_rem
0x00001ce5 T aes_rpa_gen
0x00002029 T ble_util_buf_adv_tx_alloc
0x00002061 T ble_util_buf_adv_tx_free
0x0000feae D co_null_bdaddr
0x0000feb4 D co_null_key
0x000050c9 T llc_con_move_cbk
0x000071d9 T llc_start
0x00007669 T lld_adv_adv_data_update
0x00007ff5 T lld_adv_rand_addr_update
0x00008071 T lld_adv_restart
0x0000817d T lld_adv_scan_rsp_data_update
0x000081c5 T lld_adv_start
0x00008831 T lld_adv_stop
0x0000d6c1 T lld_white_list_rem
0x0000b401 T lld_init_rand_addr_update
0x0000c179 T lld_res_list_add
0x0000c251 T lld_res_list_clear
0x0000c27d T lld_res_list_local_rpa_get
0x0000c2c5 T lld_res_list_peer_rpa_get
0x0000c341 T lld_res_list_priv_mode_update
0x0000c37d T lld_res_list_rem
0x0000cedd T lld_scan_rand_addr_update
0x0000b699 T lld_init_start
0x0000bc9d T lld_init_stop
0x0000f081 T sch_plan_req
0x0000f0d5 T sch_plan_set
0x0000fec4 D co_rate_to_phy
0x0000cb81 T lld_scan_params_update
0x0000d115 T lld_scan_start
0x0000d5c5 T lld_scan_stop
0x0000c3ad T lld_rpa_renew
0x0000408d T ke_mem_init
0x00002609 T co_buf_init
0x0000de9d T rwip_sleep
0x10000810 D em_ble_base_address_table_0
0x10000812 D em_ble_base_address_table_1
0x10000814 D em_ble_base_address_table_2
0x10000816 D em_ble_base_address_table_3
0x10000818 D em_ble_base_address_table_4
0x1000081a D em_ble_base_address_table_5
0x10000822 D em_ble_base_address_table_6
0x1000081c D em_ble_base_address_table_7
0x10000824 D em_ble_base_address_table_8
0x1000081e D em_ble_base_address_table_9
0x10000820 D em_ble_base_address_table_10
0x000021d9 T ble_util_buf_init_env
0x10000978 D PATCH_FUN
0x1000108c D lld_adv_env
0x0000ebe5 T sch_arb_remove
0x0000f739 T sch_slice_fg_remove
0x10000f44 D llc_env
0x0000693d T llc_proc_err_ind
0x000073c1 T llc_stop
0x00004695 T ll_channel_map_ind_handler
0x0000471d T ll_connection_param_req_handler
0x00004809 T ll_connection_param_rsp_handler
0x0000489d T ll_connection_update_ind_handler
0x000049c1 T ll_enc_req_handler
0x00004a85 T ll_enc_rsp_handler
0x00004af9 T ll_feature_req_handler
0x00004b4d T ll_feature_rsp_handler
0x00004ba1 T ll_length_req_handler
0x00004bf9 T ll_length_rsp_handler
0x00004c75 T ll_min_used_channels_ind_handler
0x00004cf1 T ll_pause_enc_req_handler
0x00004d5d T ll_pause_enc_rsp_handler
0x00004db5 T ll_reject_ext_ind_handler
0x00004dd5 T ll_reject_ind_handler
0x00004df5 T ll_slave_feature_req_handler
0x00004e49 T ll_start_enc_req_handler
0x00004e99 T ll_start_enc_rsp_handler
0x00004ee9 T ll_unknown_rsp_handler
0x00004ef9 T ll_version_ind_handler
0x00001fd9 T ble_util_buf_acl_tx_free
0x0000c5c1 T lld_rxdesc_check
0x0000c609 T lld_rxdesc_free
0x0000fee4 D rwip_priority
0x0000e8b1 T sch_arb_insert
0x0000f355 T sch_prog_push
0x0000fde5 T FMC_SPI_Flash_RDID
0x0000fd8d T FMC_SPI_Flash_RUID
0x0000fa71 T FMC_SPI_Flash_WakeUp
0x0000f9f1 T FMC_SPI_Init_Oprt
0x0000fa49 T FMC_SPI_Flash_PowerDown
0x0000fceb T FMC_SPI_FlashRead
0x0000fc1f T FMC_SPI_FlashWrite
0x0000fb09 T FMC_SPI_Flash_Erase_Sector
0x00004fc9 T llc_cleanup
0x00005091 T llc_cmd_stat_send
0x00005a39 T llc_llcp_send
0x00005ac9 T llc_llcp_state_set
0x00006981 T llc_proc_get
0x00006999 T llc_proc_id_get
0x000069b5 T llc_proc_init
0x000069c1 T llc_proc_reg
0x00006a05 T llc_proc_state_get
0x00006a09 T llc_proc_state_set
0x00006a0d T llc_proc_timer_pause_set
0x00006a7d T llc_proc_timer_set
0x00006ae5 T llc_proc_unreg
0x0000a1c1 T lld_con_stop
0x00007869 T lld_adv_evt_start_cbk
0x10000e68 D rwip_env
0x1000080e D rwip_prog_delay
0x0000e041 T rwip_time_get
0x0000e2cd T rwip_wakeup_end
0x1000112c D sch_arb_env
0x00007905 T lld_adv_frm_cbk
0x0000e0b1 T rwip_timer_alarm_handler
0x0000e11d T rwip_timer_arb_handler
0x0000e189 T rwip_timer_co_handler
0x10000f94 D lld_env
0x10000828 D aa_gen
0x00007c25 T lld_adv_init
0x00009301 T lld_con_init
0x0000a7f1 T lld_core_init
0x1000082c D lld_rpa_renew_env
0x00008959 T lld_channel_assess
0x100010dc D lld_con_env
0x0000a4ad T lld_con_tx_len_update
0x10000830 D lld_exp_sync_pos_tab
0x0000bce5 T lld_instant_proc_end
0x1100d555 T prf_dst_task_get
0x1100d689 T rom_env_init
0x11003201 T gapc_get_bdaddr
0x11007595 T gatt_db_svc16_add
0x11007719 T gatt_db_svc_add
0x11008635 T gatt_srv_att_read_get_cfm
0x1100876d T gatt_srv_att_val_set_cfm
0x11009145 T gatt_srv_event_send
0x11009fdd T gatt_user_srv_register
0x1100e0a8 D llc_msg_handler_tab
0x10001bf0 D rom_llc_state
0x00008e4d T lld_con_evt_start_cbk
0x00008ddd T lld_con_evt_canceled_cbk
0x0000fe9e D co_sca2ppm
0x00009051 T lld_con_evt_time_update
0x00009415 T lld_con_max_lat_calc
0x00009a69 T lld_con_sched
0x0000f7e1 T sch_slice_per_add
0x0000d801 T rwble_isr
0x0000dc75 T rwip_isr
0x00009189 T lld_con_frm_isr
0x000044f9 T ke_task_schedule
0x00007949 T lld_adv_frm_isr
0x10001c0b D sv_lock
0x10001c12 D sv_txlen
0x1000177d T rom_lld_con_rx
0x100019fb T rom_lld_con_evt_start_cbk
0x10001a4b T rom_lld_con_frm_isr
0x11006ff5 T gatt_cli_mtu_exch
0x1100d83d T rom_lld_disable_latency
0x1100d889 T rom_lld_enable_latency
0x10001c0a D evt_start
0x11002b21 T co_rand_word
0x11002b29 T co_random_init
0x10001c08 D adv_evt_start