hpw421初始版本

8759df19-2341-4343-bda3-6dffcbfbe243.gitignore

@@ -0,0 +1,33 @@
+#*.uvoptx
+#OutputFiledir & Files
+Listings/
+Objects/
+*.crf
+*.d
+*.o
+*.build_log.htm 
+*.axf
+*.htm
+*.lnp
+*.dep
+*.map
+*.bin
+*.hex
+ 
+#Keil Layout File
+*.uvguix.*
+ 
+#DebugConfig
+DebugConfig/
+ 
+#Keil Project screen layout file
+*.uvguix.*
+*.uvgui.*
+ 
+#JLINK file
+*JLinkLog.txt
+*JLinkSettings.ini
+ 
+#temp files
+~$*
+*.TMP

README.md

@@ -0,0 +1,166 @@
+# hpw421 项目说明
+
+## 项目基本信息
+
+| 项目名称   | hpw421                       |
+| ---------- | ------------------------------ |
+| 产品类型   | 220V单通道智能通断器 |
+| 项目负责人 | 徐少祥                           |
+| 硬件版本   | V1.2                           |
+| 固件版本   | V1.0                           |
+| 创建日期   | 2026-06-05                    |
+
+---
+
+## 主控芯片
+* 433：WS480L  SOP8
+* BLE：XC6517   SOP16
+* Flash：内置 Flash
+
+---
+
+## 开发环境
+
+* Keil MDK V5
+
+
+
+### 编译器
+
+* ARMCC V5
+
+---
+
+## 工程路径
+project\example\ble\ble_peripheral\mdk
+
+打开方式：
+
+双击 MDK/ble_peripheral.uvprojx
+
+---
+
+## 烧录说明
+
+### 烧录器
+*USB TO TTL串口
+
+### 烧录软件
+* ComV14.4.4
+
+### 烧录接口
+
+| 引脚  | 说明 |
+| ----- | ---- |
+| VCC   | 电源 |
+| GND   | 地   |
+| R | 串口接收 |
+| T | 串口发送 |
+| BT   | 电源 |
+
+---
+
+## 编译方法
+
+Rebuild
+
+输出文件：
+project\example\ble\ble_peripheral\mdk\output_bin目录下ble_peripheral.bin文件
+
+
+---
+
+## 仓库目录结构
+
+```text
+hpw421
+│
+├── component
+│   ├── ble
+│   ├── rf24
+│   ├── SBC
+│   └── xc6xx_drivers
+│
+├── doc
+│   ├── hpw421蓝牙协议
+│   └── BOM
+│
+├── project
+│   ├── delete.bat
+│   └── example
+		├── 2.4g
+		├── ble
+		├── driver
+├── tools
+│   └── ComV14.4.4
+│
+│
+├── gitignore文件
+│
+└── README.md
+```
+---
+
+## 蓝牙协议
+
+协议文档位置：
+
+hpw421\doc\hpw421蓝牙协议.xls
+
+---
+
+## Git提交规范
+
+提交前：
+
+```shell
+git pull
+```
+
+提交：
+
+```shell
+git add .
+
+git commit -m "修复BLE连接异常"
+
+git push
+```
+
+禁止：
+
+```text
+修改
+更新
+测试
+123
+abc
+```
+
+推荐：
+
+```text
+修复BLE连接异常
+增加RF433学习码功能
+修复定时器逻辑
+增加OTA升级功能
+```
+
+---
+
+## 注意事项
+
+1. 修改协议必须同步更新协议文档。
+2. 修改硬件必须同步更新BOM。
+3. 发布版本必须同步更新ReleaseNote。
+4. 禁止将源码仅保存在个人电脑。
+5. 所有发布版本必须上传至Gitea仓库。
+6. 离职前必须完成代码交接与文档更新。
+
+---
+
+## 修改记录
+
+| 日期       | 作者 | 内容     |
+| ---------- | ---- | -------- |
+| 2026-06-05 | 徐少祥 | 创建项目 |

component/SBC/encoder/msbc_encoder_port.c

@@ -1,6 +1,6 @@
 //#include "msbc_encoder_port.h"
 #include "sbc_encoder.h"
-#include "xc6xxx.h"
+#include "xc60xx.h"
 
 #define mSBC_SYNCWORD 0xad
 #define SBC_MAX_CHANNELS 2
@@ -12,7 +12,7 @@ struct msbc_encoder_state {
 };
 
 
-__attribute__((section("ram_user"))) static struct msbc_encoder_state encoder_state = {0};
+static struct msbc_encoder_state encoder_state = {0};
 static uint8_t msbc_encode_inited = 0;
 
 int msbc_encoder_init(void)
@@ -56,7 +56,7 @@ uint16_t msbc_encoder_sbc_buffer_length(void)
     return context->u16PacketLength;
 }
 
-void __attribute__((section("ram_sbc_code"))) msbc_encoder_process_data(int16_t * input_buffer)
+void /*__attribute__((section("ram_em")))*/ msbc_encoder_process_data(int16_t * input_buffer)
 {
     if (!msbc_encode_inited) {
        printf("SBC encoder: sbc state is NULL, call btstack_sbc_encoder_init to initialize it\r\n");

component/SBC/encoder/srce/sbc_analysis.c

@@ -26,7 +26,7 @@
 #include "sbc_encoder.h"
 #include "sbc_enc_func_declare.h"
 /*#include <math.h>*/
-#include "xc6xxx.h"
+#include "xc60xx.h"
 
 #if (SBC_IS_64_MULT_IN_WINDOW_ACCU == TRUE)
 #define WIND_4_SUBBANDS_0_1 (SINT32)0x01659F45  /* gas32CoeffFor4SBs[8] = -gas32CoeffFor4SBs[32] = 0x01659F45 */
@@ -893,7 +893,7 @@
 *
 * RETURNS : N/A
 */
-/*__attribute__((section("ram_sbc_code")))*/ void SbcAnalysisFilter4(SBC_ENC_PARAMS *pstrEncParams)
+void __attribute__((section("ram_em"))) SbcAnalysisFilter4(SBC_ENC_PARAMS *pstrEncParams)
 {
     SINT16 *ps16PcmBuf;
     SINT32 *ps32SbBuf;
@@ -987,7 +987,7 @@
 }
 
 /* //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// */
-__attribute__((section("ram_sbc_code"))) void SbcAnalysisFilter8 (SBC_ENC_PARAMS *pstrEncParams)
+void __attribute__((section("ram_em"))) SbcAnalysisFilter8 (SBC_ENC_PARAMS *pstrEncParams)
 {
     SINT16 *ps16PcmBuf;
     SINT32 *ps32SbBuf;

component/SBC/encoder/srce/sbc_dct.c

@@ -25,7 +25,7 @@
 #include "sbc_encoder.h"
 #include "sbc_enc_func_declare.h"
 #include "sbc_dct.h"
-#include "xc6xxx.h"
+#include "xc60xx.h"
 
 
 /*******************************************************************************
@@ -65,7 +65,7 @@ extern const SINT16 gas16AnalDCTcoeff8[];
 extern const SINT16 gas16AnalDCTcoeff4[];
 #endif
 
-void __attribute__((section("ram_sbc_code"))) SBC_FastIDCT8(SINT32 *pInVect, SINT32 *pOutVect)
+void __attribute__((section("ram_em"))) SBC_FastIDCT8(SINT32 *pInVect, SINT32 *pOutVect)
 {
 #if (SBC_FAST_DCT == TRUE)
 #if (SBC_ARM_ASM_OPT==TRUE)
@@ -184,7 +184,7 @@ void __attribute__((section("ram_sbc_code"))) SBC_FastIDCT8(SINT32 *pInVect, SIN
 **
 **
 *******************************************************************************/
-void __attribute__((section("ram_sbc_code"))) SBC_FastIDCT4(SINT32 *pInVect, SINT32 *pOutVect)
+void __attribute__((section("ram_em"))) SBC_FastIDCT4(SINT32 *pInVect, SINT32 *pOutVect)
 {
 #if (SBC_FAST_DCT == TRUE)
 #if (SBC_ARM_ASM_OPT==TRUE)

component/SBC/encoder/srce/sbc_enc_bit_alloc_mono.c

@@ -26,7 +26,7 @@
 /*Includes*/
 #include "sbc_encoder.h"
 #include "sbc_enc_func_declare.h"
-#include "xc6xxx.h"
+#include "xc60xx.h"
 
 /*global arrays*/
 const SINT16 sbc_enc_as16Offset4[4][4] = {  {-1, 0, 0, 0}, {-2, 0, 0, 1},
@@ -43,7 +43,7 @@ const SINT16 sbc_enc_as16Offset8[4][8] = {  {-2, 0, 0, 0, 0, 0, 0, 1},
 * RETURNS : N/A
 */
 
-void __attribute__((section("ram_sbc_code"))) sbc_enc_bit_alloc_mono(SBC_ENC_PARAMS *pstrCodecParams)
+void __attribute__((section("ram_em"))) sbc_enc_bit_alloc_mono(SBC_ENC_PARAMS *pstrCodecParams)
 {
     SINT32 s32MaxBitNeed;   /*to store the max bits needed per sb*/
     SINT32 s32BitCount;     /*the used number of bits*/

component/SBC/encoder/srce/sbc_enc_bit_alloc_ste.c

@@ -26,7 +26,7 @@
 /*Includes*/
 #include "sbc_encoder.h"
 #include "sbc_enc_func_declare.h"
-#include "xc6xxx.h"
+#include "xc60xx.h"
 
 /*global arrays*/
 extern const SINT16 sbc_enc_as16Offset4[4][4];
@@ -39,7 +39,7 @@ extern const SINT16 sbc_enc_as16Offset8[4][8];
 * RETURNS : N/A
 */
 
-/*__attribute__((section("ram_sbc_code")))*/ void sbc_enc_bit_alloc_ste(SBC_ENC_PARAMS *pstrCodecParams)
+void /*__attribute__((section("ram_em")))*/ sbc_enc_bit_alloc_ste(SBC_ENC_PARAMS *pstrCodecParams)
 {
 	/* CAUTIOM -> mips optim for arm 32 require to use SINT32 instead of SINT16 */
 	/* Do not change variable type or name */

component/SBC/encoder/srce/sbc_encoder.c

@@ -25,7 +25,7 @@
 #include <string.h>
 #include "sbc_encoder.h"
 #include "sbc_enc_func_declare.h"
-#include "xc6xxx.h"
+#include "xc60xx.h"
 
 SINT16 EncMaxShiftCounter;
 
@@ -34,7 +34,7 @@ SINT32   s32LRDiff[SBC_MAX_NUM_OF_BLOCKS]    = {0};
 SINT32   s32LRSum[SBC_MAX_NUM_OF_BLOCKS]     = {0};
 #endif
 
-__attribute__((section("ram_sbc_code"))) void SBC_Encoder(SBC_ENC_PARAMS *pstrEncParams)
+void /*__attribute__((section("ram_em")))*/ SBC_Encoder(SBC_ENC_PARAMS *pstrEncParams)
 {
     SINT32 s32Ch;                               /* counter for ch*/
     SINT32 s32Sb;                               /* counter for sub-band*/

component/SBC/encoder/srce/sbc_packing.c

@@ -25,7 +25,7 @@
 #include "sbc_encoder.h"
 #include "sbc_enc_func_declare.h"
 #include <stddef.h>
-#include "xc6xxx.h"
+#include "xc60xx.h"
 
 #if (SBC_ARM_ASM_OPT==TRUE)
 #define Mult32(s32In1,s32In2,s32OutLow)                                                 \
@@ -55,7 +55,7 @@
 }
 #endif
 
-__attribute__((section("ram_sbc_code"))) void EncPacking(SBC_ENC_PARAMS *pstrEncParams)
+void /*__attribute__((section("ram_em")))*/ EncPacking(SBC_ENC_PARAMS *pstrEncParams)
 {
     UINT8       *pu8PacketPtr;                      /* packet ptr*/
     UINT8 Temp;

component/ble/ip/ble/api/xc_gap_api.c

@@ -10,27 +10,27 @@
 #if BLE_APP_PRESENT
 #include "xc_gap_api.h"
 
-//void xc_ble_gapm_reset(void)
-//{
-//    // Reset the stack
-//    struct gapm_reset_cmd *p_cmd =
-//        KE_MSG_ALLOC(GAPM_RESET_CMD, TASK_GAPM, TASK_APP, gapm_reset_cmd);
+void xc_ble_gapm_reset(void)
+{
+    // Reset the stack
+    struct gapm_reset_cmd *p_cmd =
+        KE_MSG_ALLOC(GAPM_RESET_CMD, TASK_GAPM, TASK_APP, gapm_reset_cmd);
 
-//    p_cmd->operation = GAPM_RESET;
+    p_cmd->operation = GAPM_RESET;
 
-//    ke_msg_send(p_cmd);
-//}
+    ke_msg_send(p_cmd);
+}
 
-//void xc_ble_set_dev_config(struct gapm_set_dev_config_cmd *cfg_param)
-//{
-//    struct gapm_set_dev_config_cmd *p_cmd = KE_MSG_ALLOC(
-//        GAPM_SET_DEV_CONFIG_CMD, TASK_GAPM, TASK_APP, gapm_set_dev_config_cmd);
+void xc_ble_set_dev_config(struct gapm_set_dev_config_cmd *cfg_param)
+{
+    struct gapm_set_dev_config_cmd *p_cmd = KE_MSG_ALLOC(
+        GAPM_SET_DEV_CONFIG_CMD, TASK_GAPM, TASK_APP, gapm_set_dev_config_cmd);
 
-//    memcpy(p_cmd, cfg_param, sizeof(struct gapm_set_dev_config_cmd));
-//    p_cmd->operation = GAPM_SET_DEV_CONFIG;
+    memcpy(p_cmd, cfg_param, sizeof(struct gapm_set_dev_config_cmd));
+    p_cmd->operation = GAPM_SET_DEV_CONFIG;
 
-//    ke_msg_send(p_cmd);
-//}
+    ke_msg_send(p_cmd);
+}
 
 void xc_ble_get_dev_info(struct gapm_get_dev_info_cmd *cmd)
 {
@@ -68,7 +68,6 @@ void xc_ble_gen_random_addr(struct gapm_gen_rand_addr_cmd *p_param)
     ke_msg_send(p_cmd);
 }
 
-#if (BLE_SEC_CON)
 void xc_ble_get_pub_key(void)
 {
     struct gapm_get_pub_key_cmd *p_cmd = KE_MSG_ALLOC(
@@ -78,7 +77,6 @@ void xc_ble_get_pub_key(void)
 
     ke_msg_send(p_cmd);
 }
-#endif // (BLE_SEC_CON)
 
 void xc_ble_gen_random_nb(void)
 {
@@ -138,33 +136,33 @@ void xc_ble_set_white_list(uint8_t size, gap_bdaddr_t *wl_info)
     ke_msg_send(p_cmd);
 }
 
-//void xc_ble_advertise_create(
-//    struct gapm_activity_create_adv_cmd *adv_creat_param)
-//{
-//    struct gapm_activity_create_adv_cmd *p_cmd =
-//        KE_MSG_ALLOC(GAPM_ACTIVITY_CREATE_CMD, TASK_GAPM, TASK_APP,
-//                     gapm_activity_create_adv_cmd);
+void xc_ble_advertise_create(
+    struct gapm_activity_create_adv_cmd *adv_creat_param)
+{
+    struct gapm_activity_create_adv_cmd *p_cmd =
+        KE_MSG_ALLOC(GAPM_ACTIVITY_CREATE_CMD, TASK_GAPM, TASK_APP,
+                     gapm_activity_create_adv_cmd);
 
-//    memcpy(p_cmd, adv_creat_param, sizeof(struct gapm_activity_create_adv_cmd));
-//    p_cmd->operation = GAPM_CREATE_ADV_ACTIVITY;
+    memcpy(p_cmd, adv_creat_param, sizeof(struct gapm_activity_create_adv_cmd));
+    p_cmd->operation = GAPM_CREATE_ADV_ACTIVITY;
 
-//    ke_msg_send(p_cmd);
-//}
+    ke_msg_send(p_cmd);
+}
 
-//void xc_ble_set_adv_data(uint8_t actv_idx, uint16_t adv_data_length,
-//                         uint8_t *p_adv_data)
-//{
-//    struct gapm_set_adv_data_cmd *p_cmd =
-//        KE_MSG_ALLOC_DYN(GAPM_SET_ADV_DATA_CMD, TASK_GAPM, TASK_APP,
-//                         gapm_set_adv_data_cmd, adv_data_length);
+void xc_ble_set_adv_data(uint8_t actv_idx, uint16_t adv_data_length,
+                         uint8_t *p_adv_data)
+{
+    struct gapm_set_adv_data_cmd *p_cmd =
+        KE_MSG_ALLOC_DYN(GAPM_SET_ADV_DATA_CMD, TASK_GAPM, TASK_APP,
+                         gapm_set_adv_data_cmd, adv_data_length);
 
-//    p_cmd->operation = GAPM_SET_ADV_DATA;
-//    p_cmd->actv_idx  = actv_idx;
-//    p_cmd->length    = adv_data_length;
-//    memcpy(&p_cmd->data[0], p_adv_data, adv_data_length);
+    p_cmd->operation = GAPM_SET_ADV_DATA;
+    p_cmd->actv_idx  = actv_idx;
+    p_cmd->length    = adv_data_length;
+    memcpy(&p_cmd->data[0], p_adv_data, adv_data_length);
 
-//    ke_msg_send(p_cmd);
-//}
+    ke_msg_send(p_cmd);
+}
 
 void xc_ble_set_scan_rsp_data(uint8_t actv_idx, uint16_t scan_rsp_data_length,
                               uint8_t *p_scan_rsp_data)
@@ -181,16 +179,16 @@ void xc_ble_set_scan_rsp_data(uint8_t actv_idx, uint16_t scan_rsp_data_length,
     ke_msg_send(p_cmd);
 }
 
-//void xc_ble_advertise_start(struct gapm_activity_start_cmd *adv_start_param)
-//{
-//    struct gapm_activity_start_cmd *p_cmd = KE_MSG_ALLOC(
-//        GAPM_ACTIVITY_START_CMD, TASK_GAPM, TASK_APP, gapm_activity_start_cmd);
+void xc_ble_advertise_start(struct gapm_activity_start_cmd *adv_start_param)
+{
+    struct gapm_activity_start_cmd *p_cmd = KE_MSG_ALLOC(
+        GAPM_ACTIVITY_START_CMD, TASK_GAPM, TASK_APP, gapm_activity_start_cmd);
 
-//    memcpy(p_cmd, adv_start_param, sizeof(struct gapm_activity_start_cmd));
-//    p_cmd->operation = GAPM_START_ACTIVITY;
+    memcpy(p_cmd, adv_start_param, sizeof(struct gapm_activity_start_cmd));
+    p_cmd->operation = GAPM_START_ACTIVITY;
 
-//    ke_msg_send(p_cmd);
-//}
+    ke_msg_send(p_cmd);
+}
 
 void xc_ble_scan_create(struct gapm_activity_create_cmd *scan_creat_param)
 {
@@ -287,38 +285,37 @@ void xc_ble_disconnect(int conidx, uint32_t reason)
     ke_msg_send(p_cmd);
 }
 
-//void xc_ble_update_param(int conidx, uint16_t intv_min, uint16_t intv_max,
-//                         uint16_t latency, uint16_t time_out)
-//{
-//    struct gapc_param_update_cmd *p_cmd =
-//        KE_MSG_ALLOC(GAPC_PARAM_UPDATE_CMD, KE_BUILD_ID(TASK_GAPC, conidx),
-//                     TASK_APP, gapc_param_update_cmd);
+void xc_ble_update_param(int conidx, uint16_t intv_min, uint16_t intv_max,
+                         uint16_t latency, uint16_t time_out)
+{
+    struct gapc_param_update_cmd *p_cmd =
+        KE_MSG_ALLOC(GAPC_PARAM_UPDATE_CMD, KE_BUILD_ID(TASK_GAPC, conidx),
+                     TASK_APP, gapc_param_update_cmd);
 
-//    p_cmd->operation  = GAPC_UPDATE_PARAMS;
-//    p_cmd->intv_min   = intv_min;
-//    p_cmd->intv_max   = intv_max;
-//    p_cmd->latency    = latency;
-//    p_cmd->time_out   = time_out;
-//    // not used by a slave device
-//    p_cmd->ce_len_min = CE_LEN_MIN;
-//    // p_cmd->ce_len_min = 0xFFFF;
-//    p_cmd->ce_len_max = CE_LEN_MAX;
+    p_cmd->operation  = GAPC_UPDATE_PARAMS;
+    p_cmd->intv_min   = intv_min;
+    p_cmd->intv_max   = intv_max;
+    p_cmd->latency    = latency;
+    p_cmd->time_out   = time_out;
+    // not used by a slave device
+    p_cmd->ce_len_min = CE_LEN_MIN;
+    // p_cmd->ce_len_min = 0xFFFF;
+    p_cmd->ce_len_max = CE_LEN_MAX;
     
-//    ke_msg_send(p_cmd);
-//}
+    ke_msg_send(p_cmd);
+}
 
-//void xc_ble_conn_cfm(int conidx, struct gapc_connection_cfm *p_cfm)
-//{
-//    struct gapc_connection_cfm *p_cmd =
-//        KE_MSG_ALLOC(GAPC_CONNECTION_CFM, KE_BUILD_ID(TASK_GAPC, conidx),
-//                     TASK_APP, gapc_connection_cfm);
+void xc_ble_conn_cfm(int conidx, struct gapc_connection_cfm *p_cfm)
+{
+    struct gapc_connection_cfm *p_cmd =
+        KE_MSG_ALLOC(GAPC_CONNECTION_CFM, KE_BUILD_ID(TASK_GAPC, conidx),
+                     TASK_APP, gapc_connection_cfm);
 
-//    memcpy(p_cmd, p_cfm, sizeof(struct gapc_connection_cfm));
+    memcpy(p_cmd, p_cfm, sizeof(struct gapc_connection_cfm));
 
-//    ke_msg_send(p_cmd);
-//}
+    ke_msg_send(p_cmd);
+}
 
-#if (MIN_STACK)
 void xc_ble_get_peer_info(int conidx, struct gapc_get_info_cmd *get_info)
 {
     struct gapc_get_info_cmd *p_cmd =
@@ -329,21 +326,20 @@ void xc_ble_get_peer_info(int conidx, struct gapc_get_info_cmd *get_info)
 
     ke_msg_send(p_cmd);
 }
-#endif // (MIN_STACK)
 
-//void xc_ble_param_update_cfm(int conidx,
-//                             struct gapc_param_update_cfm *update_cfm)
-//{
-//    struct gapc_param_update_cfm *p_cmd =
-//        KE_MSG_ALLOC(GAPC_PARAM_UPDATE_CFM, KE_BUILD_ID(TASK_GAPC, conidx),
-//                     TASK_APP, gapc_param_update_cfm);
+void xc_ble_param_update_cfm(int conidx,
+                             struct gapc_param_update_cfm *update_cfm)
+{
+    struct gapc_param_update_cfm *p_cmd =
+        KE_MSG_ALLOC(GAPC_PARAM_UPDATE_CFM, KE_BUILD_ID(TASK_GAPC, conidx),
+                     TASK_APP, gapc_param_update_cfm);
 
-//    memcpy(p_cmd, update_cfm, sizeof(struct gapc_param_update_cfm));
-//    p_cmd->ce_len_min = CE_LEN_MIN;
-//    p_cmd->ce_len_max = CE_LEN_MAX;
+    memcpy(p_cmd, update_cfm, sizeof(struct gapc_param_update_cfm));
+    p_cmd->ce_len_min = CE_LEN_MIN;
+    p_cmd->ce_len_max = CE_LEN_MAX;
 
-//    ke_msg_send(p_cmd);
-//}
+    ke_msg_send(p_cmd);
+}
 
 void xc_ble_bond(int conidx, struct gapc_bond_cmd *p_param)
 {
@@ -366,27 +362,33 @@ void xc_ble_bond_cfm(int conidx, struct gapc_bond_cfm *p_param)
     ke_msg_send(p_cmd);
 }
 
-//void xc_ble_get_dev_info_cfm(int conidx, struct gapc_get_dev_info_cfm *p_param)
-//{
-//    if ((p_param->req == GAPC_DEV_NAME) ||
-//        (p_param->req == GAPC_DEV_APPEARANCE) ||
-//        (p_param->req == GAPC_DEV_SLV_PREF_PARAMS)) {
-//        ke_msg_send(p_param);
-//    } else {
-//        // do nothing;
-//    }
-//}
+void xc_ble_get_dev_info_cfm(int conidx, struct gapc_get_dev_info_cfm *p_param)
+{
+    if ((p_param->req == GAPC_DEV_NAME) ||
+        (p_param->req == GAPC_DEV_APPEARANCE) ||
+        (p_param->req == GAPC_DEV_SLV_PREF_PARAMS)) {
+        struct gapc_get_dev_info_cfm *p_cmd = KE_MSG_ALLOC_DYN(
+            GAPC_GET_DEV_INFO_CFM, KE_BUILD_ID(TASK_GAPC, conidx), TASK_APP,
+            gapc_get_dev_info_cfm, DEVICE_NAME_MAX_LEN);
 
-//void xc_ble_set_dev_info_cfm(int conidx, struct gapc_set_dev_info_cfm *p_param)
-//{
-//    struct gapc_set_dev_info_cfm *p_cmd =
-//        KE_MSG_ALLOC(GAPC_SET_DEV_INFO_CFM, KE_BUILD_ID(TASK_GAPC, conidx),
-//                     TASK_APP, gapc_set_dev_info_cfm);
+        memcpy(p_cmd, p_param, sizeof(struct gapc_get_dev_info_cfm));
 
-//    memcpy(p_cmd, p_param, sizeof(struct gapc_set_dev_info_cfm));
+        ke_msg_send(p_cmd);
+    } else {
+        // do nothing;
+    }
+}
 
-//    ke_msg_send(p_cmd);
-//}
+void xc_ble_set_dev_info_cfm(int conidx, struct gapc_set_dev_info_cfm *p_param)
+{
+    struct gapc_set_dev_info_cfm *p_cmd =
+        KE_MSG_ALLOC(GAPC_SET_DEV_INFO_CFM, KE_BUILD_ID(TASK_GAPC, conidx),
+                     TASK_APP, gapc_set_dev_info_cfm);
+
+    memcpy(p_cmd, p_param, sizeof(struct gapc_set_dev_info_cfm));
+
+    ke_msg_send(p_cmd);
+}
 
 void xc_ble_encrypt(int conidx, struct gapc_encrypt_cmd *p_param)
 {

component/ble/ip/ble/api/xc_gatt_client_api.c

@@ -8,10 +8,8 @@
  */
 #include "rwip_config.h"
 #include "stdint.h"
-#include "xc_gatt_client_api.h"
-#include "gatt.h"
 #if (BLE_GATT_CLI)
-
+#include "xc_gatt_client_api.h"
 
 uint16_t xc_ble_gatt_user_cli_register(uint16_t pref_mtu, uint8_t prio_level,
                                    const gatt_cli_cb_t *p_cb,
@@ -20,12 +18,10 @@ uint16_t xc_ble_gatt_user_cli_register(uint16_t pref_mtu, uint8_t prio_level,
     return gatt_user_cli_register(pref_mtu, prio_level, p_cb, p_user_lid);
 }
 
-#if (MIN_STACK)
 uint16_t xc_ble_gatt_user_unregister(uint8_t user_lid)
 {
     return gatt_user_unregister(user_lid);
 }
-#endif // (MIN_STACK)
 
 uint16_t xc_ble_gatt_cli_discover_svc(uint8_t conidx, uint8_t user_lid,
                                   uint16_t dummy, uint8_t disc_type, bool full,
@@ -36,7 +32,6 @@ uint16_t xc_ble_gatt_cli_discover_svc(uint8_t conidx, uint8_t user_lid,
                                  start_hdl, end_hdl, uuid_type, p_uuid);
 }
 
-#if (MIN_STACK_MASTER)
 uint16_t xc_ble_gatt_cli_discover_inc_svc(uint8_t conidx, uint8_t user_lid,
                                       uint16_t dummy, uint16_t start_hdl,
                                       uint16_t end_hdl)
@@ -44,7 +39,6 @@ uint16_t xc_ble_gatt_cli_discover_inc_svc(uint8_t conidx, uint8_t user_lid,
     return gatt_cli_discover_inc_svc(conidx, user_lid, dummy, start_hdl,
                                      end_hdl);
 }
-#endif // (MIN_STACK_MASTER)
 
 uint16_t xc_ble_gatt_cli_discover_char(uint8_t conidx, uint8_t user_lid,
                                    uint16_t dummy, uint8_t disc_type,
@@ -109,13 +103,11 @@ uint16_t xc_ble_gatt_cli_event_register(uint8_t conidx, uint8_t user_lid,
     return gatt_cli_event_register(conidx, user_lid, start_hdl, end_hdl);
 }
 
-#if (MIN_STACK_MASTER)
 uint16_t xc_ble_gatt_cli_event_unregister(uint8_t conidx, uint8_t user_lid,
                                       uint16_t start_hdl, uint16_t end_hdl)
 {
     return gatt_cli_event_unregister(conidx, user_lid, start_hdl, end_hdl);
 }
-#endif // (MIN_STACK_MASTER)
 
 uint16_t xc_ble_gatt_cli_indicate_cfm(uint8_t conidx, uint8_t user_lid,
                                    uint16_t token)
@@ -124,7 +116,7 @@ uint16_t xc_ble_gatt_cli_indicate_cfm(uint8_t conidx, uint8_t user_lid,
 }
 #endif // (BLE_GATT_CLI)
 
-//uint16_t xc_ble_gatt_cli_mtu_exch(uint8_t conidx, uint8_t user_lid)
-//{
-//    return gatt_cli_mtu_exch(conidx, user_lid);
-//}
+uint16_t xc_ble_gatt_cli_mtu_exch(uint8_t conidx, uint8_t user_lid)
+{
+    return gatt_cli_mtu_exch(conidx, user_lid);
+}

component/ble/ip/ble/api/xc_gatt_client_api.h

@@ -311,7 +311,7 @@ uint16_t xc_ble_gatt_cli_mtu_exch(uint8_t conidx, uint8_t user_lid);
  ****************************************************************************************
  */
 uint16_t xc_ble_gatt_cli_indicate_cfm(uint8_t conidx, uint8_t user_lid, uint16_t token);
-uint16_t xc_ble_gatt_cli_mtu_exch(uint8_t conidx, uint8_t user_lid);
+
 
 
 #endif // __XC_GATT_CLIENT_API_H__

component/ble/ip/ble/api/xc_gatt_server_api.c

@@ -10,12 +10,12 @@
 #if (BLE_APP_PRESENT)
 #include "xc_gatt_server_api.h"
 
-//uint16_t xc_ble_gatt_user_srv_register(uint16_t pref_mtu, uint8_t prio_level,
-//                                       const gatt_srv_cb_t *p_cb,
-//                                       uint8_t *p_user_lid)
-//{
-//    return gatt_user_srv_register(pref_mtu, prio_level, p_cb, p_user_lid);
-//}
+uint16_t xc_ble_gatt_user_srv_register(uint16_t pref_mtu, uint8_t prio_level,
+                                       const gatt_srv_cb_t *p_cb,
+                                       uint8_t *p_user_lid)
+{
+    return gatt_user_srv_register(pref_mtu, prio_level, p_cb, p_user_lid);
+}
 
 uint16_t xc_ble_gatt_service_add(uint8_t user_lid, uint8_t info,
                                  const uint8_t *p_uuid, uint8_t nb_att,
@@ -27,15 +27,15 @@ uint16_t xc_ble_gatt_service_add(uint8_t user_lid, uint8_t info,
                            nb_att_rsvd, p_start_hdl);
 }
 
-//uint16_t xc_ble_gatt_service16_add(uint8_t user_lid, uint8_t info,
-//                                   uint16_t uuid16, uint8_t nb_att,
-//                                   const uint8_t *p_att_mask,
-//                                   const gatt_att16_desc_t *p_atts,
-//                                   uint8_t nb_att_rsvd, uint16_t *p_start_hdl)
-//{
-//    return gatt_db_svc16_add(user_lid, info, uuid16, nb_att, p_att_mask, p_atts,
-//                             nb_att_rsvd, p_start_hdl);
-//}
+uint16_t xc_ble_gatt_service16_add(uint8_t user_lid, uint8_t info,
+                                   uint16_t uuid16, uint8_t nb_att,
+                                   const uint8_t *p_att_mask,
+                                   const gatt_att16_desc_t *p_atts,
+                                   uint8_t nb_att_rsvd, uint16_t *p_start_hdl)
+{
+    return gatt_db_svc16_add(user_lid, info, uuid16, nb_att, p_att_mask, p_atts,
+                             nb_att_rsvd, p_start_hdl);
+}
 
 #if (MIN_STACK)
 uint16_t xc_ble_gatt_service_remove(uint8_t user_lid, uint16_t start_hdl)
@@ -44,29 +44,29 @@ uint16_t xc_ble_gatt_service_remove(uint8_t user_lid, uint16_t start_hdl)
 }
 #endif // (MIN_STACK)
 
-//uint16_t xc_ble_gatt_srv_notify(uint8_t conidx, uint8_t user_lid,
-//                                uint16_t dummy, uint16_t hdl, uint16_t length,
-//                                const uint8_t *p_value)
-//{
-//    co_buf_t *p_data;
-//    uint16_t status;
+uint16_t xc_ble_gatt_srv_notify(uint8_t conidx, uint8_t user_lid,
+                                uint16_t dummy, uint16_t hdl, uint16_t length,
+                                const uint8_t *p_value)
+{
+    co_buf_t *p_data;
+    uint16_t status;
 
-//    // allocate a buffer for event transmission
-//    if (co_buf_alloc(&p_data, GATT_BUFFER_HEADER_LEN, length,
-//                     GATT_BUFFER_TAIL_LEN) != CO_BUF_ERR_NO_ERROR) {
-//        status = ATT_ERR_INSUFF_RESOURCE;
-//    } else {
-//        // copy data into buffer
-//        co_buf_copy_data_from_mem(p_data, p_value, length);
+    // allocate a buffer for event transmission
+    if (co_buf_alloc(&p_data, GATT_BUFFER_HEADER_LEN, length,
+                     GATT_BUFFER_TAIL_LEN) != CO_BUF_ERR_NO_ERROR) {
+        status = ATT_ERR_INSUFF_RESOURCE;
+    } else {
+        // copy data into buffer
+        co_buf_copy_data_from_mem(p_data, p_value, length);
 
-//        // request event to be sent
-//        status = gatt_srv_event_send(conidx, user_lid, dummy, GATT_NOTIFY, hdl,
-//                                     p_data);
+        // request event to be sent
+        status = gatt_srv_event_send(conidx, user_lid, dummy, GATT_NOTIFY, hdl,
+                                     p_data);
 
-//        co_buf_release(p_data);
-//    }
-//    return status;
-//}
+        co_buf_release(p_data);
+    }
+    return status;
+}
 
 uint16_t xc_ble_gatt_srv_indicate(uint8_t conidx, uint8_t user_lid,
                                   uint16_t dummy, uint16_t hdl, uint16_t length,
@@ -92,39 +92,39 @@ uint16_t xc_ble_gatt_srv_indicate(uint8_t conidx, uint8_t user_lid,
     return status;
 }
 
-//uint16_t xc_ble_gatt_srv_read_cfm(uint8_t conidx, uint8_t user_lid,
-//                                  uint16_t token, uint16_t status,
-//                                  uint16_t att_length, uint16_t length,
-//                                  const uint8_t *p_value)
-//{
+uint16_t xc_ble_gatt_srv_read_cfm(uint8_t conidx, uint8_t user_lid,
+                                  uint16_t token, uint16_t status,
+                                  uint16_t att_length, uint16_t length,
+                                  const uint8_t *p_value)
+{
 
-//    co_buf_t *p_data = NULL;
-//    uint8_t state;
-//    if (status == GAP_ERR_NO_ERROR) {
-//        // allocate a buffer for event transmission
-//        if (co_buf_alloc(&p_data, GATT_BUFFER_HEADER_LEN, length,
-//                         GATT_BUFFER_TAIL_LEN) != CO_BUF_ERR_NO_ERROR) {
-//            status = ATT_ERR_INSUFF_RESOURCE;
-//        } else {
-//            // copy data into buffer
-//            co_buf_copy_data_from_mem(p_data, p_value, length);
-//        }
-//    }
+    co_buf_t *p_data = NULL;
+    uint8_t state;
+    if (status == GAP_ERR_NO_ERROR) {
+        // allocate a buffer for event transmission
+        if (co_buf_alloc(&p_data, GATT_BUFFER_HEADER_LEN, length,
+                         GATT_BUFFER_TAIL_LEN) != CO_BUF_ERR_NO_ERROR) {
+            status = ATT_ERR_INSUFF_RESOURCE;
+        } else {
+            // copy data into buffer
+            co_buf_copy_data_from_mem(p_data, p_value, length);
+        }
+    }
 
-//    // execute confirmation native function
-//    state = gatt_srv_att_read_get_cfm(conidx, user_lid, token, status,
-//                                      att_length, p_data);
+    // execute confirmation native function
+    state = gatt_srv_att_read_get_cfm(conidx, user_lid, token, status,
+                                      att_length, p_data);
 
-//    // release buffer
-//    if (p_data != NULL) {
-//        co_buf_release(p_data);
-//    }
-//    return state;
-//}
+    // release buffer
+    if (p_data != NULL) {
+        co_buf_release(p_data);
+    }
+    return state;
+}
 
-//uint16_t xc_ble_gatt_srv_write_cfm(uint8_t conidx, uint8_t user_lid,
-//                                   uint16_t token, uint16_t status)
-//{
-//    return gatt_srv_att_val_set_cfm(conidx, user_lid, token, status);
-//}
+uint16_t xc_ble_gatt_srv_write_cfm(uint8_t conidx, uint8_t user_lid,
+                                   uint16_t token, uint16_t status)
+{
+    return gatt_srv_att_val_set_cfm(conidx, user_lid, token, status);
+}
 #endif // (BLE_APP_PRESENT)

component/ble/ip/ble/hl/api/gapc_msg.h

@@ -409,7 +409,7 @@ enum gapc_cli_feat
 enum gapc_srv_feat
 {
     /// Enhanced ATT bearer supported
-    GAPC_SRV_EATT_SUPPORTED_BIT     = (0 << 0),
+    GAPC_SRV_EATT_SUPPORTED_BIT     = (1 << 0),
     GAPC_SRV_EATT_SUPPORTED_POS     = 0,
 };
 

component/ble/ip/ble/hl/api/gatt.h

@@ -1414,29 +1414,6 @@ typedef struct gatt_cli_cb
     void (*cb_svc_changed) (uint8_t conidx, uint8_t user_lid, bool out_of_sync, uint16_t start_hdl, uint16_t end_hdl);
 } gatt_cli_cb_t;
 
-/*
- * IOT_INDIRECTION_TABLE for ROM patch
- * as all the function maybe in ROM, so we should consider it
- * from the beginning of modularization when design them.
- * For exist SW module, we could use an external API table
- * for all the global interface functions, and the API we can
- * just declare to macro function.
- */
-typedef struct {
-    uint16_t (*gatt_srv_att_read_get_cfm)(uint8_t conidx, uint8_t user_lid, uint16_t token, uint16_t status,
-                                   uint16_t att_length, co_buf_t* p_data);
-} indir_gatt_srv_read_api_tbl_t;
-extern indir_gatt_srv_read_api_tbl_t gatt_srv_read_api_tbl;
-
-typedef struct {
-    uint16_t (*gatt_srv_att_info_get_cfm)(uint8_t conidx, uint8_t user_lid, uint16_t token, uint16_t status, uint16_t att_length);
-    uint16_t (*gatt_srv_att_val_set_cfm)(uint8_t conidx, uint8_t user_lid, uint16_t token, uint16_t status);
-    void (*gatt_srv_write_queue_cleanup)(uint8_t conidx);
-} indir_gatt_srv_write_api_tbl_t;
-extern indir_gatt_srv_write_api_tbl_t gatt_srv_write_api_tbl;
-
-
-
 /*
  * FUCTION DEFINITION
  ****************************************************************************************
@@ -1849,11 +1826,8 @@ uint16_t gatt_srv_event_mtp_cancel(uint8_t user_lid, uint16_t dummy);
  * @return Status of the function execution (@see enum hl_err)
  ****************************************************************************************
  */
-#if 0
 uint16_t gatt_srv_att_read_get_cfm(uint8_t conidx, uint8_t user_lid, uint16_t token, uint16_t status,
                                    uint16_t att_length, co_buf_t* p_data);
-#endif
-#define gatt_srv_att_read_get_cfm(conidx, user_lid, token, status, att_length, p_data) gatt_srv_read_api_tbl.gatt_srv_att_read_get_cfm(conidx, user_lid, token, status, att_length, p_data)
 
 /**
  ****************************************************************************************
@@ -1887,10 +1861,7 @@ uint16_t gatt_srv_att_event_get_cfm(uint8_t conidx, uint8_t user_lid, uint16_t t
  * @return Status of the function execution (@see enum hl_err)
  ****************************************************************************************
  */
-#if 0
 uint16_t gatt_srv_att_info_get_cfm(uint8_t conidx, uint8_t user_lid, uint16_t token, uint16_t status, uint16_t att_length);
-#endif
-#define gatt_srv_att_info_get_cfm(conidx, user_lid, token, status, att_length) gatt_srv_write_api_tbl.gatt_srv_att_info_get_cfm(conidx, user_lid, token, status, att_length)
 
 /**
  ****************************************************************************************
@@ -1904,10 +1875,7 @@ uint16_t gatt_srv_att_info_get_cfm(uint8_t conidx, uint8_t user_lid, uint16_t to
  * @return Status of the function execution (@see enum hl_err)
  ****************************************************************************************
  */
-#if 0
 uint16_t gatt_srv_att_val_set_cfm(uint8_t conidx, uint8_t user_lid, uint16_t token, uint16_t status);
-#endif
-#define gatt_srv_att_val_set_cfm(conidx, user_lid, token, status) gatt_srv_write_api_tbl.gatt_srv_att_val_set_cfm(conidx, user_lid, token, status)
 
 /**
  ****************************************************************************************

component/ble/ip/ble/hl/src/gap/gapc/gapc_sdt_itl.h

@@ -1,20 +0,0 @@
-#ifndef GAPC_SDT_ITL_H_
-#define GAPC_SDT_ITL_H_
-
-/// Structure of handlers
-typedef struct gapc_sdt_handler
-{
-    /// Timer Handler
-    gapc_sdt_timer_handler_t timer;
-    /// Function defer handler
-    gapc_sdt_defer_handler_t defer;
-} gapc_sdt_handler_t;
-
-typedef struct
-{
-    gapc_sdt_handler_t* (*gapc_get_sdt_handler)(gapc_sdt_t* p_hdl);
-} indir_gapc_sdt_itl_api_tbl_t;
-extern indir_gapc_sdt_itl_api_tbl_t gapc_sdt_itl_api_tbl;
-
-#define gapc_get_sdt_handler(p_hdl) gapc_sdt_itl_api_tbl.gapc_get_sdt_handler(p_hdl)
-#endif

component/ble/ip/ble/hl/src/gap/gapc/gapc_smp_itl.h

@@ -1,25 +0,0 @@
-#ifndef GAPC_SMP_ITL_H_
-#define GAPC_SMP_ITL_H_
-
-typedef uint8_t (*gapc_smp_handler_func_t)(uint8_t conidx, l2cap_smp_pdu_t* p_pdu, co_buf_t* p_buf);
-
-
-/// L2CAP PDU handler information for packing/unpacking and function handler
-typedef struct gapc_smp_handler_info
-{
-    /// Message handler
-    gapc_smp_handler_func_t    handler;
-    /// Pack/Unpack format string
-    const char*                 pack_format;
-    /// Length of L2CAP PDU
-    uint16_t                    length;
-} gapc_smp_handler_info_t;
-
-typedef struct
-{
-    gapc_smp_handler_func_t (*gapc_get_l2cap_smp_handler)(uint8_t opcode);
-} indir_gapc_smp_itl_api_tbl_t;
-extern indir_gapc_smp_itl_api_tbl_t gapc_smp_itl_api_tbl;
-
-#define gapc_get_l2cap_smp_handler(opcode) gapc_smp_itl_api_tbl.gapc_get_l2cap_smp_handler(opcode)
-#endif

component/ble/ip/ble/hl/src/gatt/gatt_int.h

@@ -356,10 +356,7 @@ void gatt_proc_cleanup(uint8_t conidx, uint16_t reason);
  * @param[in]  conidx       Connection index
  ****************************************************************************************
  */
-#if 0
 void gatt_srv_write_queue_cleanup(uint8_t conidx);
-#endif
-#define gatt_srv_write_queue_cleanup(conidx) gatt_srv_write_api_tbl.gatt_srv_write_queue_cleanup(conidx)
 
 #if (BLE_GATT_CLI)
 

component/ble/ip/ble/hl/src/gatt/gatt_srv_discover_itl.h

@@ -1,47 +0,0 @@
-#ifndef GATT_SRV_DISCOVER_ITL_H_
-#define GATT_SRV_DISCOVER_ITL_H_
-
-/// Server discover procedure structure.
-typedef struct gatt_srv_discover_proc
-{
-    /// Procedure header - required for any Attribute procedure
-    gatt_proc_handler_t     hdr;
-    /// Pointer to the searched value
-    co_buf_t*               p_val_buf;
-    /// Pointer to the buffer used for response
-    co_buf_t*               p_rsp_buf;
-    /// Search start handle
-    uint16_t                start_hdl;
-    /// Seatch end handle
-    uint16_t                end_hdl;
-    /// Found handle
-    uint16_t                hdl;
-    /// Found End Group handle
-    uint16_t                end_grp_hdl;
-    /// Maximum size for the response
-    uint16_t                max_rsp_len;
-    /// ATT Operation code received
-    uint8_t                 pdu_code;
-    /// Searched UUID Type (@enum gatt_uuid_type)
-    uint8_t                 uuid_type;
-    /// Searched UUID
-    uint8_t                 uuid[GATT_UUID_128_LEN];
-} gatt_srv_discover_proc_t;
-
-typedef struct
-{
-    uint16_t (*gatt_srv_discover_l2cap_att_find_req_handler)(uint8_t conidx, gatt_srv_discover_proc_t* p_proc,
-                                                               l2cap_att_find_info_req_t* p_pdu, co_buf_t* p_buf, uint16_t mtu);
-    uint16_t (*gatt_srv_discover_rsp_val_prepare)(gatt_srv_discover_proc_t* p_proc, uint16_t hdl, uint16_t end_grp_hdl,
-                                                    gatt_db_svc_t* p_svc, gatt_db_att_t* p_att,
-                                                    uint8_t* p_out, uint16_t* p_length);
-    void (*gatt_srv_discover_proc_continue)(uint8_t conidx, gatt_srv_discover_proc_t* p_proc, uint8_t proc_state,
-                                           uint16_t status);
-} indir_gatt_srv_discover_itl_api_tbl_t;
-extern indir_gatt_srv_discover_itl_api_tbl_t gatt_srv_discover_itl_api_tbl;
-
-#define gatt_srv_discover_l2cap_att_find_req_handler(conidx, p_proc, p_pdu, p_buf, mtu) gatt_srv_discover_itl_api_tbl.gatt_srv_discover_l2cap_att_find_req_handler(conidx, p_proc, p_pdu, p_buf, mtu)
-#define gatt_srv_discover_rsp_val_prepare(p_proc, hdl, end_grp_hdl, p_svc, p_att, p_out, p_length) gatt_srv_discover_itl_api_tbl.gatt_srv_discover_rsp_val_prepare(p_proc, hdl, end_grp_hdl, p_svc, p_att, p_out, p_length)
-#define gatt_srv_discover_proc_continue(conidx, p_proc, proc_state, status) gatt_srv_discover_itl_api_tbl.gatt_srv_discover_proc_continue(conidx, p_proc, proc_state, status)
-
-#endif

component/ble/ip/ble/hl/src/gatt/gatt_srv_mtu_exch_itl.h

@@ -1,27 +0,0 @@
-#ifndef GATT_SRV_MTU_EXCH_ITL_H_
-#define GATT_SRV_MTU_EXCH_ITL_H_
-
-/// Server Mtu Exchange procedure structure.
-typedef struct gatt_srv_mtu_exch_proc
-{
-    /// Procedure header - required for any Attribute procedure
-    gatt_proc_handler_t     hdr;
-    /// Negotiated MTU
-    uint16_t                mtu_nego;
-    /// Use to know if MTU request has been accepted
-    bool                    accept;
-} gatt_srv_mtu_exch_proc_t;
-
-typedef struct
-{
-    uint16_t (*gatt_srv_write_l2cap_att_mtu_req_handler)(uint8_t conidx, gatt_srv_mtu_exch_proc_t* p_proc,
-                                                            l2cap_att_mtu_req_t* p_pdu, co_buf_t* p_buf, uint16_t mtu);
-    void (*gatt_srv_mtu_exch_proc_continue)(uint8_t conidx, gatt_srv_mtu_exch_proc_t* p_proc, uint8_t proc_state,
-                                              uint16_t status);
-} indir_gatt_srv_mtu_exch_itl_api_tbl_t;
-extern indir_gatt_srv_mtu_exch_itl_api_tbl_t gatt_srv_mtu_exch_itl_api_tbl;
-
-#define gatt_srv_write_l2cap_att_mtu_req_handler(conidx, p_proc, p_pdu, p_buf, mtu) gatt_srv_mtu_exch_itl_api_tbl.gatt_srv_write_l2cap_att_mtu_req_handler(conidx, p_proc, p_pdu, p_buf, mtu)
-#define gatt_srv_mtu_exch_proc_continue(conidx, p_proc, proc_state, status) gatt_srv_mtu_exch_itl_api_tbl.gatt_srv_mtu_exch_proc_continue(conidx, p_proc, proc_state, status)
-
-#endif

component/ble/ip/ble/hl/src/gatt/gatt_srv_read_itl.h

@@ -1,41 +0,0 @@
-#ifndef GATT_SRV_READ_ITL_H_
-#define GATT_SRV_READ_ITL_H_
-
-/// Server read procedure structure.
-typedef struct gatt_srv_read_proc
-{
-    /// Procedure header - required for any Attribute procedure
-    gatt_proc_handler_t     hdr;
-    /// Pointer to received PDU buffer (used only for multiple read)
-    co_buf_t*               p_pdu_buf;
-    /// Queue of buffer that represents value to return (multiple read values)
-    co_list_t               buf_queue;
-    /// Attribute handle targeted.
-    uint16_t                hdl;
-    /// offset of the attribute value
-    uint16_t                offset;
-    /// Response PDU length
-    uint16_t                rsp_len;
-    /// Maximum response size that remains
-    uint16_t                rsp_remain_len;
-    /// received PDU code
-    uint8_t                 pdu_code;
-} gatt_srv_read_proc_t;
-
-typedef struct
-{
-    uint16_t (*gatt_srv_read_l2cap_att_rd_req_handler)(uint8_t conidx, gatt_srv_read_proc_t* p_proc,
-                                                         l2cap_att_rd_blob_req_t* p_pdu, co_buf_t* p_buf, uint16_t mtu);
-    uint16_t (*gatt_srv_read_next_hdl_get)(gatt_srv_read_proc_t* p_proc);
-    uint16_t (*gatt_srv_read_l2cap_att_rd_mult_req_handler)(uint8_t conidx, gatt_srv_read_proc_t* p_proc,
-                                                              l2cap_att_rd_mult_req_t* p_pdu, co_buf_t* p_buf, uint16_t mtu);
-    void (*gatt_srv_read_proc_continue)(uint8_t conidx, gatt_srv_read_proc_t* p_proc, uint8_t proc_state,
-                                          uint16_t status);
-} indir_gatt_srv_read_itl_api_tbl_t;
-extern indir_gatt_srv_read_itl_api_tbl_t gatt_srv_read_itl_api_tbl;
-
-#define gatt_srv_read_l2cap_att_rd_req_handler(conidx, p_proc, p_pdu, p_buf, mtu) gatt_srv_read_itl_api_tbl.gatt_srv_read_l2cap_att_rd_req_handler(conidx, p_proc, p_pdu, p_buf, mtu)
-#define gatt_srv_read_next_hdl_get(p_proc) gatt_srv_read_itl_api_tbl.gatt_srv_read_next_hdl_get(p_proc)
-#define gatt_srv_read_l2cap_att_rd_mult_req_handler(conidx, p_proc, p_pdu, p_buf, mtu) gatt_srv_read_itl_api_tbl.gatt_srv_read_l2cap_att_rd_mult_req_handler(conidx, p_proc, p_pdu, p_buf, mtu)
-#define gatt_srv_read_proc_continue(conidx, p_proc, proc_state, status) gatt_srv_read_itl_api_tbl.gatt_srv_read_proc_continue(conidx, p_proc, proc_state, status)
-#endif

component/ble/ip/ble/hl/src/gatt/gatt_srv_write_itl.h

@@ -1,95 +0,0 @@
-#ifndef GATT_SRV_WRITE_ITL_H_
-#define GATT_SRV_WRITE_ITL_H_
-
-/// Bit field used to retrieve a procedure during AES-CMAC operation
-enum gatt_srv_write_info_bf
-{
-    /// Connection Index
-    GATT_SRV_WRITE_CONIDX_MASK      = 0x000000FF,
-    GATT_SRV_WRITE_CONIDX_LSB       = 0,
-    /// Procedure token
-    GATT_SRV_WRITE_TOKEN_MASK       = 0x00FFFF00,
-    GATT_SRV_WRITE_TOKEN_LSB        = 8,
-};
-/// Server write procedure structure.
-typedef struct gatt_srv_write_proc
-{
-    /// Procedure header - required for any Attribute procedure
-    gatt_proc_handler_t     hdr;
-    /// Pointer to current buffer
-    co_buf_t*               p_buf;
-    /// Pointer to buffer in prepare queue list where new buffer should be inserted after
-    co_buf_t*               p_prev_prep_buf;
-    /// Attribute handle targeted.
-    uint16_t                hdl;
-    /// offset of the attribute value
-    uint16_t                offset;
-    /// Current Attribute value length
-    uint16_t                att_val_len;
-    /// Current Attribute maximum value length
-    uint16_t                att_max_len;
-    /// Write access type
-    uint8_t                 access;
-    /// Local Service User identifier
-    uint8_t                 svc_user_lid;
-    /// On prepare write, push data of same handle in same buffer
-    bool                    append_data;
-    /// Used to know if write a value with offset is authorized or not
-    bool                    write_with_offset_authz;
-} gatt_srv_write_proc_t;
-
-
-/// Server execute write procedure structure.
-typedef struct gatt_srv_write_exe_proc
-{
-    /// Procedure header - required for any Attribute procedure
-    gatt_proc_handler_t     hdr;
-    /// write execution request flag
-    uint8_t                 exe_flag;
-    /// Attribute handle targeted.
-    uint16_t                hdl;
-} gatt_srv_write_exe_proc_t;
-
-
-/// Buffer meta-data value for prepare write
-typedef struct gatt_srv_write_prep_meta
-{
-    /// Attribute handle
-    uint16_t               hdl;
-    /// Value offset
-    uint16_t               offset;
-    /// Current Attribute value length
-    uint16_t               att_val_len;
-    /// Current Attribute maximum value length
-    uint16_t               att_max_len;
-    /// Total value length
-    uint16_t               total_len;
-    /// User local identifier targeted
-    uint8_t                svc_user_lid;
-} gatt_srv_write_prep_meta_t;
-
-typedef struct
-{
-    uint16_t (*gatt_srv_write_l2cap_att_wr_req_handler)(uint8_t conidx, gatt_srv_write_proc_t* p_proc,
-                                                          l2cap_att_prep_wr_req_t* p_pdu, co_buf_t* p_buf, uint16_t mtu);
-    uint16_t (*gatt_srv_write_l2cap_att_exe_wr_req_handler)(uint8_t conidx, gatt_srv_write_exe_proc_t* p_proc,
-                                                              l2cap_att_exe_wr_req_t* p_pdu, co_buf_t* p_buf, uint16_t mtu);
-#if (MIN_STACK)
-    void (*gatt_cli_write_aes_cmac_cb)(uint8_t aes_status, const uint8_t* aes_res, uint32_t src_info);
-#endif
-    void (*gatt_srv_write_proc_continue)(uint8_t conidx, gatt_srv_write_proc_t* p_proc, uint8_t proc_state,
-                                           uint16_t status);
-    void (*gatt_srv_write_exe_proc_continue)(uint8_t conidx, gatt_srv_write_exe_proc_t* p_proc, uint8_t proc_state,
-                                               uint16_t status);
-} indir_gatt_srv_write_itl_api_tbl_t;
-extern indir_gatt_srv_write_itl_api_tbl_t gatt_srv_write_itl_api_tbl;
-
-#define gatt_srv_write_l2cap_att_wr_req_handler(conidx, p_proc, p_pdu, p_buf, mtu) gatt_srv_write_itl_api_tbl.gatt_srv_write_l2cap_att_wr_req_handler(conidx, p_proc, p_pdu, p_buf, mtu)
-#define gatt_srv_write_l2cap_att_exe_wr_req_handler(conidx, p_proc, p_pdu, p_buf, mtu) gatt_srv_write_itl_api_tbl.gatt_srv_write_l2cap_att_exe_wr_req_handler(conidx, p_proc, p_pdu, p_buf, mtu)
-#if (MIN_STACK)
-#define gatt_cli_write_aes_cmac_cb(aes_status, aes_res, src_info) gatt_srv_write_itl_api_tbl.gatt_cli_write_aes_cmac_cb(aes_status, aes_res, src_info)
-#endif
-#define gatt_srv_write_proc_continue(conidx, p_proc, proc_state, status) gatt_srv_write_itl_api_tbl.gatt_srv_write_proc_continue(conidx, p_proc, proc_state, status)
-#define gatt_srv_write_exe_proc_continue(conidx, p_proc, proc_state, status) gatt_srv_write_itl_api_tbl.gatt_srv_write_exe_proc_continue(conidx, p_proc, proc_state, status)
-
-#endif

component/ble/ip/ble/hl/src/l2cap/l2cap_int.h

@@ -51,11 +51,8 @@
 /// Size of SDU Length Field in first segment
 #define L2CAP_SDU_LEN          (2)
 /// only provide 5 buffers per transmission loops
-#if (CONFIG_XMBOX_RC)
-#define L2CAP_ACL_BUF_PER_LOOP (7)
-#else
 #define L2CAP_ACL_BUF_PER_LOOP (5)
-#endif
+
 
 /// L2CAP Connection state Bit Field
 enum  l2cap_state_bf

component/ble/ip/ble/hl/src/l2cap/l2cap_sig_itl.h

@@ -1,28 +0,0 @@
-#ifndef L2CAP_SIG_ITL_H_
-#define L2CAP_SIG_ITL_H_
-
-/*
- * INCLUDE FILES
- ****************************************************************************************
- */
-#include "rwip_config.h"
-
-#if BLE_HOST_PRESENT
-#if (BLE_L2CAP)
-#if (BLE_LECB)
-
-typedef void (*l2cap_sig_handler_func_t)(uint8_t conidx, uint8_t pkt_id, l2cap_sig_pdu_t* p_pdu, co_buf_t* p_buf);
-
-typedef struct
-{
-    l2cap_sig_handler_func_t (*l2cap_sig_get_handler)(uint8_t opcode);
-} indir_l2cap_sig_itl_api_tbl_t;
-extern indir_l2cap_sig_itl_api_tbl_t l2cap_sig_itl_api_tbl;
-
-#define l2cap_sig_get_handler(opcode) l2cap_sig_itl_api_tbl.l2cap_sig_get_handler(opcode)
-
-#endif  // (BLE_LECB)
-#endif // (BLE_L2CAP)
-#endif // (BLE_HOST_PRESENT)
-
-#endif // L2CAP_SIG_ITL_H_

component/ble/ip/ble/ll/api/rwble_config.h

@@ -27,50 +27,50 @@
 /* --------------------------   FEATURE SETUP       --------------------------------------*/
 /******************************************************************************************/
 
+/// Features byte 0
 #define BLE_FEATURES_BYTE0  (  (1 << BLE_FEAT_ENC                   ) \
                              | (1 << BLE_FEAT_CON_PARAM_REQ_PROC    ) \
-                             | (0 << BLE_FEAT_EXT_REJ_IND           ) \
-                             | (0 << BLE_FEAT_SLAVE_INIT_FEAT_EXCHG ) \
-                             | (0 << BLE_FEAT_PING                  ) \
-                             | (BLE_DL_UPD_PRESENT << BLE_FEAT_DATA_PKT_LEN_EXT      ) \
-                             | (0 << BLE_FEAT_LL_PRIVACY            ) \
-                             | (0 << BLE_FEAT_EXT_SCAN_FILT_POLICY  ) )
+                             | (1 << BLE_FEAT_EXT_REJ_IND           ) \
+                             | (1 << BLE_FEAT_SLAVE_INIT_FEAT_EXCHG ) \
+                             | (1 << BLE_FEAT_PING                  ) \
+                             | (1 << BLE_FEAT_DATA_PKT_LEN_EXT      ) \
+                             | (1 << BLE_FEAT_LL_PRIVACY            ) \
+                             | (1 << BLE_FEAT_EXT_SCAN_FILT_POLICY  ) )
 
 /// Features byte 1
-#define BLE_FEATURES_BYTE1  (  (0         << (BLE_FEAT_2M_PHY            - 8) ) \
-                             | (0 << (BLE_FEAT_STABLE_MOD_IDX_TX - 8) ) \
-                             | (0 << (BLE_FEAT_STABLE_MOD_IDX_RX - 8) ) \
-                             | (0         << (BLE_FEAT_CODED_PHY         - 8) ) \
-                             | (0                             << (BLE_FEAT_EXT_ADV           - 8) ) \
-                             | (0                            << (BLE_FEAT_PER_ADV           - 8) ) \
+#define BLE_FEATURES_BYTE1  (  (BLE_PHY_2MBPS_SUPPORT         << (BLE_FEAT_2M_PHY            - 8) ) \
+                             | (BLE_STABLE_MOD_IDX_TX_SUPPORT << (BLE_FEAT_STABLE_MOD_IDX_TX - 8) ) \
+                             | (BLE_STABLE_MOD_IDX_RX_SUPPORT << (BLE_FEAT_STABLE_MOD_IDX_RX - 8) ) \
+                             | (BLE_PHY_CODED_SUPPORT         << (BLE_FEAT_CODED_PHY         - 8) ) \
+                             | (1                             << (BLE_FEAT_EXT_ADV           - 8) ) \
+                             | (1                             << (BLE_FEAT_PER_ADV           - 8) ) \
                              | (1                             << (BLE_FEAT_CHAN_SEL_ALGO_2   - 8) ) \
-                             | (0       << (BLE_FEAT_PWR_CLASS_1       - 8) ) )
+                             | (BLE_PWR_CLASS_1_SUPPORT       << (BLE_FEAT_PWR_CLASS_1       - 8) ) )
 
 /// Features byte 2
-#define BLE_FEATURES_BYTE2  (  (0                                     << (BLE_FEAT_MIN_NUM_USED_CHAN_PROC - 16) ) \
-                             | (0                        << (BLE_FEAT_CON_CTE_REQ            - 16) ) \
-                             | (0                        << (BLE_FEAT_CON_CTE_RSP            - 16) ) \
-                             | (0                     << (BLE_FEAT_CONLESS_CTE_TX         - 16) ) \
-                             | (0                     << (BLE_FEAT_CONLESS_CTE_RX         - 16) ) \
-                             | (0                                << (BLE_FEAT_AOD                    - 16) ) \
-                             | (0                                << (BLE_FEAT_AOA                    - 16) ) \
-                             | (0 << (BLE_FEAT_CTE_RX                 - 16) ) )
+#define BLE_FEATURES_BYTE2  (  (1                                      << (BLE_FEAT_MIN_NUM_USED_CHAN_PROC - 16) ) \
+                             | (BLE_CON_CTE_REQ                        << (BLE_FEAT_CON_CTE_REQ            - 16) ) \
+                             | (BLE_CON_CTE_RSP                        << (BLE_FEAT_CON_CTE_RSP            - 16) ) \
+                             | (BLE_CONLESS_CTE_TX                     << (BLE_FEAT_CONLESS_CTE_TX         - 16) ) \
+                             | (BLE_CONLESS_CTE_RX                     << (BLE_FEAT_CONLESS_CTE_RX         - 16) ) \
+                             | (BLE_AOD                                << (BLE_FEAT_AOD                    - 16) ) \
+                             | (BLE_AOA                                << (BLE_FEAT_AOA                    - 16) ) \
+                             | ((BLE_CON_CTE_REQ | BLE_CONLESS_CTE_RX) << (BLE_FEAT_CTE_RX                 - 16) ) )
 
 /// Features byte 3
-#define BLE_FEATURES_BYTE3  (  (0 << (BLE_FEAT_PER_ADV_SYNC_TRANSF_TX - 24) ) \
-                             | (0 << (BLE_FEAT_PER_ADV_SYNC_TRANSF_RX - 24) ) \
-                             | (0 << (BLE_FEAT_SLEEP_CLK_ACC_UPD - 24) ) \
-                             | (0 << (BLE_FEAT_PUB_KEY_VALID - 24) ) \
-                             | (0 << (BLE_FEAT_CON_ISO_STREAM_MASTER - 24) ) \
-                             | (0 << (BLE_FEAT_CON_ISO_STREAM_SLAVE - 24) ) \
-                             | (0 << (BLE_FEAT_ISO_BROADCASTER - 24) ) \
-                             | (0 << (BLE_FEAT_SYNCED_RECEIVER - 24) ) )
+#define BLE_FEATURES_BYTE3  (  (1 << (BLE_FEAT_PER_ADV_SYNC_TRANSF_TX - 24) ) \
+                             | (1 << (BLE_FEAT_PER_ADV_SYNC_TRANSF_RX - 24) ) \
+                             | (1 << (BLE_FEAT_SLEEP_CLK_ACC_UPD - 24) ) \
+                             | (1 << (BLE_FEAT_PUB_KEY_VALID - 24) ) \
+                             | (1 << (BLE_FEAT_CON_ISO_STREAM_MASTER - 24) ) \
+                             | (1 << (BLE_FEAT_CON_ISO_STREAM_SLAVE - 24) ) \
+                             | (1 << (BLE_FEAT_ISO_BROADCASTER - 24) ) \
+                             | (1 << (BLE_FEAT_SYNCED_RECEIVER - 24) ) )
 
 /// Features byte 4
-#define BLE_FEATURES_BYTE4  (  (0 << (BLE_FEAT_POWER_CONTROL_REQ - 32) ) ) \
-                             | (0 << (BLE_FEAT_POWER_CHANGE_IND - 32) ) \
-                             | (0 << (BLE_FEAT_PATH_LOSS_MONITORING - 32) )
-
+#define BLE_FEATURES_BYTE4  (  (BLE_PWR_CTRL << (BLE_FEAT_POWER_CONTROL_REQ - 32) ) ) \
+                             | (BLE_PWR_CTRL << (BLE_FEAT_POWER_CHANGE_IND - 32) ) \
+                             | (BLE_PWR_CTRL << (BLE_FEAT_PATH_LOSS_MONITORING - 32) )
 
 /// Features byte 5
 #define BLE_FEATURES_BYTE5  (0)
@@ -232,10 +232,9 @@
 #define BLE_DATA_BUF_SIZE_RX         (260)
 /// Guard space reserved for HCI ACL header in BLE RX buffers
 #define BLE_ACL_RX_BUF_HEADER_SPACE  (HCI_ACL_HDR_LEN + 1)
-
 /// Number of TX ACL data buffers
 // #define BLE_ACL_BUF_NB_TX            (BLE_ACTIVITY_MAX + 2)
-#define BLE_ACL_BUF_NB_TX          ((CFG_CON)+ 4 )  //This value can be dynamically configured.
+#define BLE_ACL_BUF_NB_TX          ((CFG_CON) + 4)  //This value can be dynamically configured.
 
 /// Number of advertising data buffers
 #define BLE_ADV_BUF_NB_TX            ((BLE_ACTIVITY_MAX+1) / 2)

component/ble/ip/ble/ll/src/llm/llm_int.h

@@ -454,18 +454,16 @@ struct llm_hci_cfg_params
 /// LLM environment structure
 struct llm_env_tag
 {
-#if defined(CFG_MIN_STACK)
     /// RAL content
-    struct ral_entry ral[0];
-#else
     struct ral_entry ral[BLE_RESOL_ADDR_LIST_MAX];
-#endif // defined(CFG_MIN_STACK)
+
     /// Bit field indicating the accurate clock is required (for each activity, indexed by activity ID)
     uint32_t act_clk_acc;
 
     /// LE Event mask
     struct evt_mask                     le_event_mask;
 
+    /// State and parameters for all activities
     struct llm_act_info                 act_info[BLE_ACTIVITY_MAX];
 
     /// Local public BD address
@@ -476,12 +474,10 @@ struct llm_env_tag
 
     /// Channel map management parameters
     struct llm_ch_map_info              ch_map_info;
-#if defined(CFG_MIN_STACK)
+
     /// Device list information table
-    struct dev_list_entry dev_list[0];
-#else
     struct dev_list_entry dev_list[BLE_WHITELIST_MAX];
-#endif // defined(CFG_MIN_STACK)
+
     /// HCI configuration parameters
     struct llm_hci_cfg_params hci;
 
@@ -510,12 +506,9 @@ struct llm_env_tag
     /// CTE type (@see enum sync_cte_type)
     uint8_t   past_cte_type;
     #endif //(BLE_CENTRAL || BLE_PERIPHERAL)
-#if (BLE_SEC_CON)
+
     /// Private P256 key for secure connection
     uint8_t                             secret_key256[PRIV_KEY_256_LEN];
-#else
-    uint8_t                             secret_key256[0];
-#endif //(BLE_SEC_CON)
 
     /// Resolvable private addresses renew timeout (in seconds)
     uint16_t                            rpa_renew_to;

component/ble/modules/common/api/co_bt_defines.h

@@ -86,8 +86,7 @@ enum random_addr_type
 #define LE_PASSKEY_LEN      0x04
 #define BD_NAME_SIZE        0xF8 // Was 0x20 for BLE HL
 #define ADV_DATA_LEN        0x1F
-// #define EXT_ADV_DATA_MAX_LEN    229 // HCI:7.7.65.13
-#define EXT_ADV_DATA_MAX_LEN 31
+#define EXT_ADV_DATA_MAX_LEN    31 // HCI:7.7.65.13
 #define PER_ADV_DATA_MAX_LEN    247 // 248 // HCI:7.7.65.16
 #define BLE_DATA_LEN        0x1B
 #define SCAN_RSP_DATA_LEN   0x1F

component/ble/modules/common/api/co_math.h

@@ -219,43 +219,43 @@ __INLINE uint32_t co_ctz(uint32_t val)
  * @param[in] seed The seed number to use to generate the random sequence.
  ****************************************************************************************
  */
- void co_random_init(uint32_t seed);
-//{
-//    srand(seed);
-//}
+__INLINE void co_random_init(uint32_t seed)
+{
+    srand(seed);
+}
 
-///**
-// ****************************************************************************************
-// * @brief Function to get an 8 bit random number.
-// * @return Random byte value.
-// ****************************************************************************************
-// */
- uint8_t co_rand_byte(void);
-//{
-//    return (uint8_t)(rand() & 0xFF);
-//}
+/**
+ ****************************************************************************************
+ * @brief Function to get an 8 bit random number.
+ * @return Random byte value.
+ ****************************************************************************************
+ */
+__INLINE uint8_t co_rand_byte(void)
+{
+    return (uint8_t)(rand() & 0xFF);
+}
 
-///**
-// ****************************************************************************************
-// * @brief Function to get an 16 bit random number.
-// * @return Random half word value.
-// ****************************************************************************************
-// */
- uint16_t co_rand_hword(void);
-//{
-//    return (uint16_t)(rand() & 0xFFFF);
-//}
+/**
+ ****************************************************************************************
+ * @brief Function to get an 16 bit random number.
+ * @return Random half word value.
+ ****************************************************************************************
+ */
+__INLINE uint16_t co_rand_hword(void)
+{
+    return (uint16_t)(rand() & 0xFFFF);
+}
 
-///**
-// ****************************************************************************************
-// * @brief Function to get an 32 bit random number.
-// * @return Random word value.
-// ****************************************************************************************
-// */
- uint32_t co_rand_word(void);
-//{
-//    return (uint32_t)rand();
-//}
+/**
+ ****************************************************************************************
+ * @brief Function to get an 32 bit random number.
+ * @return Random word value.
+ ****************************************************************************************
+ */
+__INLINE uint32_t co_rand_word(void)
+{
+    return (uint32_t)rand();
+}
 
 /**
  ****************************************************************************************

component/ble/modules/dbg/api/dbg.h

@@ -37,11 +37,7 @@
  * FUNCTION DECLARATION
  ****************************************************************************************
  */
-#if (defined(FAST_OTA))
-#define _DEBUG_ 0
-#else
-#define _DEBUG_ 1
-#endif // (defined(FAST_OTA))
+
 
 
 #if CMD_TEST

component/ble/modules/flash/xc6xxx_fmc_spi.h

@@ -75,7 +75,7 @@ extern "C" {
 
 #define FMC_IDLE_Pos                   (31U)
 #define FMC_IDLE_Msk                   (1UL << FMC_IDLE_Pos)
-//#define FMC_IDLE_STATUS                FMC_IDLE_Msk
+#define FMC_IDLE_STATUS                FMC_IDLE_Msk
 
 #define FMC_SSI_STS_BUSY               (1UL)
 
@@ -96,24 +96,24 @@ extern "C" {
 #define OTP_PROGRAM_PAGE_2                (uint8_t)0x20
 #define OTP_PROGRAM_PAGE_3                (uint8_t)0x30 
 
-//#define CMD_READ_DATA                 (uint8_t)0x03
-//#define CMD_READ_STATUS               (uint8_t)0x05
-//#define CMD_CHIP_ERASE                (uint8_t)0xc7
-//#define CMD_WRITE_ENABLE              (uint8_t)0x06
-//#define CMD_WRITE_DISABLE             (uint8_t)0x04
-//#define CMD_PAGE_PROGRAM              (uint8_t)0x02
-//#define CMD_BLOCK_ERASE               (uint8_t)0xD8
-//#define CMD_SECTOR_ERASE              (uint8_t)0x20
-//#define CMD_PAGE_ERASE                (uint8_t)0x81
-//#define CMD_RELEASE_PWRDWN            (uint8_t)0xAB
-//#define CMD_PWRDWN                    (uint8_t)0xB9
-//#define CMD_RUID                      (uint8_t)0x4B
-//#define CMD_RDID                      (uint8_t)0x9F
+#define CMD_READ_DATA                 (uint8_t)0x03
+#define CMD_READ_STATUS               (uint8_t)0x05
+#define CMD_CHIP_ERASE                (uint8_t)0xc7
+#define CMD_WRITE_ENABLE              (uint8_t)0x06
+#define CMD_WRITE_DISABLE             (uint8_t)0x04
+#define CMD_PAGE_PROGRAM              (uint8_t)0x02
+#define CMD_BLOCK_ERASE               (uint8_t)0xD8
+#define CMD_SECTOR_ERASE              (uint8_t)0x20
+#define CMD_PAGE_ERASE                (uint8_t)0x81
+#define CMD_RELEASE_PWRDWN            (uint8_t)0xAB
+#define CMD_PWRDWN                    (uint8_t)0xB9
+#define CMD_RUID                      (uint8_t)0x4B
+#define CMD_RDID                      (uint8_t)0x9F
 
-//#define FLASH_PAGE_SIZE               256
+#define FLASH_PAGE_SIZE               256
 
-//#define CUR_PAGE_NUM(addr)            (addr/FLASH_PAGE_SIZE)
-//#define CUR_START_PSR(addr)           (addr%FLASH_PAGE_SIZE)
+#define CUR_PAGE_NUM(addr)            (addr/FLASH_PAGE_SIZE)
+#define CUR_START_PSR(addr)           (addr%FLASH_PAGE_SIZE)
 
 
 

component/ble/modules/nvds/api/nvds.h

@@ -59,10 +59,7 @@
 #define NVDS_8BIT_TAGLENGTH      1
 
 #define FLASH_BASE         (252*1024)
-//#define FLASH_SECTOR_SIZE  (4*1024)
-/// NVDS size in RAM : 0x00010000 (128KB)
-#define NVDS_FLASH_SIZE    (0x00000200)
-//#define NVDS_FLASH_SIZE    (0x00000c00)
+#define FLASH_SECTOR_SIZE  (4*1024)
 
 /// Type of the tag length (8 or 16 bits)
 #if (NVDS_8BIT_TAGLENGTH)
@@ -71,7 +68,7 @@ typedef uint8_t  nvds_tag_len_t;
 typedef uint16_t nvds_tag_len_t;
 #endif // NVDS_8BIT_TAGLENGTH
 
-__RAM_CODE void rom_xc_fmc_spi_flash_erase_page(uint32_t addr);
+
 /*
  * ENUMERATION DEFINITIONS
  ****************************************************************************************
@@ -105,7 +102,7 @@ enum NVDS_STATUS
  *  used init nvds flash base addr
  ****************************************************************************************
  */
-void nvds_space_init(uint32_t flash_size);
+uint8_t nvds_space_init(uint32_t flash_size);
 /**
  ****************************************************************************************
  * @brief Initialize NVDS.

component/ble/modules/nvds/src/nvds.c

@@ -40,9 +40,6 @@
 #include "mailbox.h"
 #endif // NVDS_RAM_SUPPORT
 #include "dbg.h"
-#include "xc_drv_fmc_spi.h"
-
-__RAM_EM uint8_t write_buffer[NVDS_FLASH_SIZE];
 
 /*
  * DEFINES
@@ -429,7 +426,7 @@ __STATIC void nvds_purge(uint32_t length, uint8_t *buf);
  * LOCAL FUNCTION DEFINITIONS
  ****************************************************************************************
  */
-extern uint8_t *get_fota_env_addr(uint16_t len);
+//extern uint8_t *get_fota_env_addr(uint16_t len);
 
 __STATIC bool nvds_is_magic_number_ok(void)
 {
@@ -635,22 +632,21 @@ __STATIC void nvds_write(uint32_t address, uint32_t length, uint8_t *buf)
 
 __STATIC void nvds_erase(uint32_t address, uint32_t length)
 {
-    uint8_t page_cnt     = length / FLASH_PAGE_SIZE;
+
+    uint8_t sector_cnt     = length / FLASH_SECTOR_SIZE;
     uint32_t erase_base    = (uint32_t)nvds_env.nvds_space + address;
     uint32_t erase_address = 0;
-LOGI("nvds_erase size = %d\n", length);
-    if(length % FLASH_PAGE_SIZE){
-        LOGI("nvds length error = %d\n", length);
-        return;
+    if (length % FLASH_SECTOR_SIZE) {
+        sector_cnt = sector_cnt + 1;
     }
 
-    for (uint16_t i = 0; i < page_cnt; i++) {
+    for (uint16_t i = 0; i < sector_cnt; i++) {
         // flash_erase(nvds_env.flash_id, (uint32_t)nvds_env.nvds_space +
         // address, length, NULL);
-        erase_address = erase_base + i * FLASH_PAGE_SIZE;
+        erase_address = erase_base + i * FLASH_SECTOR_SIZE;
 #if (USE_XIP)
         GLOBAL_INT_DISABLE();
-        rom_xc_fmc_spi_flash_erase_page(erase_address);
+        FMC_SPI_Flash_Erase_Sector(erase_address);
         GLOBAL_INT_RESTORE();
 #endif // (USE_XIP)
     }
@@ -725,27 +721,9 @@ __STATIC void nvds_purge(uint32_t length, uint8_t *buf)
  * used init nvds flash base addr
  ****************************************************************************************
  */
-void nvds_space_init(uint32_t flash_size)
+uint8_t nvds_space_init(uint32_t flash_size)
 {
-    //nvds_env.nvds_space = flash_size - FLASH_PAGE_SIZE * 4 * 6; // the last 6K
-
-    uint16_t flash_type;
-
-    flash_size_and_type_get(&flash_size, &flash_type);
-	switch(flash_type)
-	{
-		case PURAN_128K_FLASH:
-			nvds_env.nvds_space = (uint8_t *)(flash_size - FLASH_SECTOR_SIZE -NVDS_FLASH_SIZE);
-			break;
-		case GD25WD40_512K_FLASH:
-			LOGI("ERR FLASH ADDR NEED CHANGE!!!\n");
-			nvds_env.nvds_space = (uint8_t *)(flash_size - NVDS_FLASH_SIZE - FLASH_PAGE_SIZE * 4 * 4); // the last 6K
-			while(1);
-		default:
-			LOGI("default\n");
-			nvds_env.nvds_space = (uint8_t *)(flash_size - NVDS_FLASH_SIZE); // the last 2K
-			break;
-	}
+    nvds_env.nvds_space = flash_size - FLASH_PAGE_SIZE * 4 * 6; // the last 6K
 }
 
 /*
@@ -753,18 +731,9 @@ void nvds_space_init(uint32_t flash_size)
  ****************************************************************************************
  */
 
-uint8_t *get_fota_env_addr(uint16_t len)
-{
-    if (len > 2048) {
-        // LOGI(" len error\n ");
-        return NULL;
-    }
-    return (uint8_t *)(&write_buffer);
-}
-
 uint8_t nvds_init(uint32_t len)
 {
-    // LOGI("nvds_init base=%x len=%d\n", nvds_env.nvds_space, len);
+    LOGI("nvds_init base=%x len=%d\n", nvds_env.nvds_space, len);
     uint8_t status      = NVDS_OK;
 
     // Initialize the pointer to the NVDS
@@ -774,7 +743,7 @@ uint8_t nvds_init(uint32_t len)
     nvds_env.write      = &nvds_write;
     nvds_env.erase      = &nvds_erase;
     nvds_env.total_size = len;
-    nvds_temp_buf       = get_fota_env_addr(NVDS_FLASH_SIZE);
+    //nvds_temp_buf       = get_fota_env_addr(2048);
     // Check if NVDS is correctly initialized
     if (!nvds_is_magic_number_ok()) {
         nvds_init_memory();

component/ble/modules/rf/api/rf.h

@@ -28,8 +28,6 @@
 #define TRANS_POWER_13_06DBM            0x67e5  //12.06,line loss 1DBM
 #define TRANS_POWER_13_05DBM            0x6825  //12.05,line loss 1DBM
 #define TRANS_POWER_13_35DBM            0x6865  //12.35,line loss 1DBM
-
-
 /**
  ****************************************************************************************
  * @addtogroup RF
@@ -63,7 +61,7 @@ struct rwip_rf_api;  // forward declaration to avoid including rw.h
 void rf_init(struct rwip_rf_api *api);
 
 //modem init
-void modem_init(uint16_t config);
+void modem_init(void);
 
 
 /// @} RF

component/ble/modules/rf/src/rf_extrc.c

@@ -68,9 +68,9 @@
  * GLOBAL VARIABLE DEFINITIONS
  ****************************************************************************************/
 // Power table
-//__STATIC const int8_t RF_TX_PW_CONV_TBL[RF_PWR_TBL_SIZE] = {
-//    [0] = -23, [1] = -20, [2] = -17, [3] = -14,
-//    [4] = -11, [5] = -8,  [6] = -5,  [7] = -2};
+__STATIC const int8_t RF_TX_PW_CONV_TBL[RF_PWR_TBL_SIZE] = {
+    [0] = -23, [1] = -20, [2] = -17, [3] = -14,
+    [4] = -11, [5] = -8,  [6] = -5,  [7] = -2};
 
 /*****************************************************************************************
  * FUNCTION DEFINITIONS
@@ -103,27 +103,20 @@ __STATIC void rf_em_init(void)
 
 #if (BT_EMB_PRESENT)
     // First half part of frequency table is for the even frequencies
-    while (idx < (EM_RF_FREQ_TABLE_LEN / 2))
-    {
+    while (idx < (EM_RF_FREQ_TABLE_LEN / 2)) {
         temp_freq_tbl[idx] = 2 * idx;
         idx++;
     }
 
-    while (idx < EM_RF_FREQ_TABLE_LEN)
-    {
+    while (idx < EM_RF_FREQ_TABLE_LEN) {
         temp_freq_tbl[idx] = 2 * (idx - (EM_RF_FREQ_TABLE_LEN / 2)) + 1;
         idx++;
     }
 
     em_wr(&temp_freq_tbl[0], EM_FT_OFFSET, EM_RF_FREQ_TABLE_LEN);
 #elif (BLE_EMB_PRESENT)
-    while (idx < EM_RF_FREQ_TABLE_LEN)
-    {
-#if defined(USE_64M_CRYSTAL)
-        temp_freq_tbl[idx] = idx;
-#else
+    while (idx < EM_RF_FREQ_TABLE_LEN) {
         temp_freq_tbl[idx] = 2 * idx;
-#endif
         idx++;
     }
 
@@ -176,27 +169,26 @@ __RAM_CODE __STATIC int8_t rf_rssi_convert(uint8_t rssi_reg)
  */
 __STATIC uint8_t rf_txpwr_cs_get(int8_t txpwr_dbm, uint8_t option)
 {
-//    ASSERT_ERR(option <= TXPWR_CS_NEAREST);
+    ASSERT_ERR(option <= TXPWR_CS_NEAREST);
 
-//    uint8_t i;
+    uint8_t i;
 
-//    for (i = RF_POWER_MIN; i < RF_POWER_MAX; i++) {
-//        // Loop until we find a power higher than or equal to the requested one
-//        if (RF_TX_PW_CONV_TBL[i] >= txpwr_dbm)
-//            break;
-//    }
+    for (i = RF_POWER_MIN; i < RF_POWER_MAX; i++) {
+        // Loop until we find a power higher than or equal to the requested one
+        if (RF_TX_PW_CONV_TBL[i] >= txpwr_dbm)
+            break;
+    }
 
-//    if ((RF_TX_PW_CONV_TBL[i] > txpwr_dbm) && (i > RF_POWER_MIN)) {
-//        if ((option == TXPWR_CS_LOWER) ||
-//            ((option == TXPWR_CS_NEAREST) &&
-//             (co_abs(txpwr_dbm - RF_TX_PW_CONV_TBL[i - 1]) <
-//              co_abs(txpwr_dbm - RF_TX_PW_CONV_TBL[i])))) {
-//            i--;
-//        }
-//    }
+    if ((RF_TX_PW_CONV_TBL[i] > txpwr_dbm) && (i > RF_POWER_MIN)) {
+        if ((option == TXPWR_CS_LOWER) ||
+            ((option == TXPWR_CS_NEAREST) &&
+             (co_abs(txpwr_dbm - RF_TX_PW_CONV_TBL[i - 1]) <
+              co_abs(txpwr_dbm - RF_TX_PW_CONV_TBL[i])))) {
+            i--;
+        }
+    }
 
-//    return (i);
-	  return RF_POWER_MIN;
+    return (i);
 }
 
 /**
@@ -293,8 +285,7 @@ __STATIC void rf_force_agc_enable(bool en) { return; }
 __STATIC int8_t rf_txpwr_dbm_get(uint8_t txpwr_idx, uint8_t modulation)
 {
     // power table is the same for BR and EDR
-//    return (RF_TX_PW_CONV_TBL[txpwr_idx]);
-	return RF_POWER_MIN;
+    return (RF_TX_PW_CONV_TBL[txpwr_idx]);
 }
 
 /**
@@ -310,82 +301,79 @@ __STATIC void rf_sleep(void)
                       IP_OSC_SLEEP_EN_BIT);   // Oscillator sleep
 }
 
+#if 0
+void rf_test_pin_init(void)
+{
+	// writel(0x53022040, 6<<4| 6);   
+    writel(0x53022040, 6<<4| 0);
+	// writel(0x53022040, 0);   
+	xc_gpio_fun_sel(3,0);
+	xc_gpio_mux_ctl(3,3); // en test_pin[0]
+    *((uint32_t volatile*)0x40000170)  =   0;
 
-//void rf_test_pin_init(void)
-//{
-//#if 0	
-//    // writel(0x53022040, 6<<4| 6);   
-//    writel(0x53022040, 6<<4| 0);
-//	// writel(0x53022040, 0);   
-//	xc_gpio_fun_sel(3,0);
-//	xc_gpio_mux_ctl(3,3); // en test_pin[0]
-//    *((uint32_t volatile*)0x40000170)  =   0;
+	xc_gpio_fun_sel(4,0);
+	xc_gpio_mux_ctl(4,3); // en test_pin[1]
+    *((uint32_t volatile*)0x40000174)  =   1;
     
-//	xc_gpio_fun_sel(4,0);
-//	xc_gpio_mux_ctl(4,3); // en test_pin[1]
-//    *((uint32_t volatile*)0x40000174)  =   1;
-//    
-//	// xc_gpio_fun_sel(5,0);
-//	// xc_gpio_mux_ctl(5,3); // en test_pin[2]
-//    // *((uint32_t volatile*)0x40000178)  =   2;
+	// xc_gpio_fun_sel(5,0);
+	// xc_gpio_mux_ctl(5,3); // en test_pin[2]
+    // *((uint32_t volatile*)0x40000178)  =   2;
 
-//	xc_gpio_fun_sel(6,0);
-//	xc_gpio_mux_ctl(6,3); // en test_pin[3]
-//    *((uint32_t volatile*)0x4000017c)  =   2;
+	xc_gpio_fun_sel(6,0);
+	xc_gpio_mux_ctl(6,3); // en test_pin[3]
+    *((uint32_t volatile*)0x4000017c)  =   2;
 
-//	// xc_gpio_fun_sel(7,0);
-//	// xc_gpio_mux_ctl(7,3); // en test_pin[4]
-//    // *((uint32_t volatile*)0x40000180)  =   3;
+	// xc_gpio_fun_sel(7,0);
+	// xc_gpio_mux_ctl(7,3); // en test_pin[4]
+    // *((uint32_t volatile*)0x40000180)  =   3;
 
-//	xc_gpio_fun_sel(8,0);
-//	xc_gpio_mux_ctl(8,3); // en test_pin[5]
-//    *((uint32_t volatile*)0x40000184)  =   3;
+	xc_gpio_fun_sel(8,0);
+	xc_gpio_mux_ctl(8,3); // en test_pin[5]
+    *((uint32_t volatile*)0x40000184)  =   3;
 
-//	// xc_gpio_fun_sel(9,0);
-//	// xc_gpio_mux_ctl(9,3); // en test_pin[6]
-//    // *((uint32_t volatile*)0x40000188)  =  5;
+	// xc_gpio_fun_sel(9,0);
+	// xc_gpio_mux_ctl(9,3); // en test_pin[6]
+    // *((uint32_t volatile*)0x40000188)  =  5;
 
-//	xc_gpio_fun_sel(23, GPIO_Dx);
-//	xc_gpio_mux_ctl(23, GPIO_Mux3); // en test_pin[7]
-//   *((uint32_t volatile*)0x4000018c)  =   4;
+	xc_gpio_fun_sel(23, GPIO_Dx);
+	xc_gpio_mux_ctl(23, GPIO_Mux3); // en test_pin[7]
+   *((uint32_t volatile*)0x4000018c)  =   4;
 
-// 	xc_gpio_fun_sel(24, GPIO_Dx);
-// 	xc_gpio_mux_ctl(24, GPIO_Mux3); // en test_pin[8]
-//    *((uint32_t volatile*)0x40000190)  =   5;
-//	xc_gpio_fun_sel(22,0);
-//	xc_gpio_mux_ctl(22,3); // en test_pin[6]
-//    *((uint32_t volatile*)0x40000188)  =  6;
+ 	xc_gpio_fun_sel(24, GPIO_Dx);
+ 	xc_gpio_mux_ctl(24, GPIO_Mux3); // en test_pin[8]
+    *((uint32_t volatile*)0x40000190)  =   5;
+	xc_gpio_fun_sel(22,0);
+	xc_gpio_mux_ctl(22,3); // en test_pin[6]
+    *((uint32_t volatile*)0x40000188)  =  6;
 
-//    uint32_t val = (*(volatile unsigned *)(0x40000000 + 0x134));
-//    (*(volatile unsigned *)(0x40000000 + 0x134)) = val | (0x1<<28);       
+    uint32_t val = (*(volatile unsigned *)(0x40000000 + 0x134));
+    (*(volatile unsigned *)(0x40000000 + 0x134)) = val | (0x1<<28);       
 
-//	xc_gpio_fun_sel(15,0);
-//	xc_gpio_mux_ctl(15,3); // en test_pin[0]
+	xc_gpio_fun_sel(15,0);
+	xc_gpio_mux_ctl(15,3); // en test_pin[0]
 
-//	xc_gpio_fun_sel(16,0);
-//	xc_gpio_mux_ctl(16,3); // en test_pin[1]
-//    
-//	xc_gpio_fun_sel(5,0);
-//	xc_gpio_mux_ctl(5,3); // en test_pin[3]
+	xc_gpio_fun_sel(16,0);
+	xc_gpio_mux_ctl(16,3); // en test_pin[1]
     
-//	xc_gpio_fun_sel(26,0);
-//	xc_gpio_mux_ctl(26,3); // en test_pin[4]
+	xc_gpio_fun_sel(5,0);
+	xc_gpio_mux_ctl(5,3); // en test_pin[3]
 
-//	xc_gpio_fun_sel(27,0);
-//	xc_gpio_mux_ctl(27,3); // en test_pin[5]
+	xc_gpio_fun_sel(26,0);
+	xc_gpio_mux_ctl(26,3); // en test_pin[4]
 
-//	xc_gpio_fun_sel(28,0);
-//	xc_gpio_mux_ctl(28,3); // en test_pin[6]
+	xc_gpio_fun_sel(27,0);
+	xc_gpio_mux_ctl(27,3); // en test_pin[5]
 
-//	// xc_gpio_fun_sel(29,0);
-//	// xc_gpio_mux_ctl(29,3); // en test_pin[7]
+	xc_gpio_fun_sel(28,0);
+	xc_gpio_mux_ctl(28,3); // en test_pin[6]
 
-//	// xc_gpio_fun_sel(30,0);
-//	// xc_gpio_mux_ctl(30,3); // en test_pin[8]
-//    #endif
-
-//}
+	// xc_gpio_fun_sel(29,0);
+	// xc_gpio_mux_ctl(29,3); // en test_pin[7]
 
+	// xc_gpio_fun_sel(30,0);
+	// xc_gpio_mux_ctl(30,3); // en test_pin[8]
+}
+#endif
 
 /****************************************************************************************
  * MODEM FUNCTION INTERFACE
@@ -432,11 +420,10 @@ void delay_ms_test()
 
 //--- chip realated setting
 // Rx Parameter Configuration
-#define EXTRC_RXPWRUP         (120)
+#define EXTRC_RXPWRUP         (87)
 // #define RF_RX_ON_DELAY        (70)
 // #define MODEM_RXON_DELAY      (75)
-// #define RF_RX_ON_DELAY        (64)
-#define RF_RX_ON_DELAY        (59)
+#define RF_RX_ON_DELAY        (64)
 #define MODEM_RXON_DELAY      (68)
 #define SYNC_ERR_BIT          (7)
 
@@ -452,19 +439,8 @@ void delay_ms_test()
 // #define SYNC_ERR_BIT          (6)
 
 // Tx Parameter Configuration
-#if defined(USE_64M_CRYSTAL)
-#define EXTRC_TXPWRUP (120)
-#define RF_TX_ON_DELAY (70)
-// #define EXTRC_TXPWRUP (87)
-// #define RF_TX_ON_DELAY (75)
-// #define EXTRC_TXPWRUP (100)
-// #define RF_TX_ON_DELAY (88)
-
-#else
 #define EXTRC_TXPWRUP         (87)
 #define RF_TX_ON_DELAY        (75)
-#endif // defined(USE_64M_CRYSTAL)
-
 #define MODEM_TXON_DELAY      (32)
 
 // //ble1m
@@ -524,7 +500,7 @@ void rf_rccalib(void)
         return;
     uint32_t timeout = 0;
     uint16_t val     = 0;
-    wbit(0x0080, 10, 8, "101"); // RG_RCCAL_CTRL(Rccal �����ֵ����) def"100"
+    wbit(0x0080, 10, 8, "111"); // RG_RCCAL_CTRL(Rccal �����ֵ����) def"100"
     delay_ms_test();
     wbit(0x0080, 5, 5, "1"); // RG_RCCAL_RESETN=1
     delay_ms_test();
@@ -552,7 +528,7 @@ void rf_rccalib(void)
     tb[0] = ((val & 0x10) ? '1' : '0');
     wbit(0x0080, 15, 11, tb);
     rccalib_flag = 1;
-    // printf("\nRG_RCCAL_CC:%X \n", rbit(0x80));
+    printf("\nRG_RCCAL_CC:%X \n", rbit(0x80));			
 }
 
 #if 0
@@ -649,146 +625,14 @@ void auto_agc_init()
     *((uint32_t volatile *)0x5302200c) = 25; // cfg_turner_gain
 }
 
-#if defined(USE_64M_CRYSTAL)
-void modem_init(void)
+void rf_xtal_cal_set(uint8_t set_value)
 {
-    uint32_t value = 0;
-    uint32_t value2;
-    // open bt clock
-    writel(0x40000040, readl(0x40000040) | (0x01 << 4) | 0xFFFF0000); // 0x40[4] bt_clk_en //32M
-    // writel(0x40000040, (readl(0x40000040) & ~(0xf)) | (0x01 << 4) | 0xFFFF0000);  // 0x40[4] bt_clk_en  //16M
-    writel(0x40000048, readl(0x40000048) | (0x01 << 4) | 0xFFFF0000);  // 0x48[4] bt_modem_clk_en
-    writel(0x40000070, readl(0x40000070) | (0x01 << 10) | 0xFFFF0000); // 0x70[10]bt_pclk_en
-    writel(0x40000074, readl(0x40000074) | (0x01 << 2) | 0xFFFF0000);  // 0x74[2] bt32k_clk_en
-    writel(0x4000247c, 0x200020);                                      // bt32k_clk_ao_en
-    writel(0x53022048, ((MODEM_TXON_DELAY << 8) | MODEM_RXON_DELAY));
-    writel(0x53020368, readl(0x53020368) | (0x01 << 31)); // EXT_CORRCODE_EN[31]
-    writel(0x53020204, readl(0x53020204) | (0x01 << 2));  // int_rx_cfg_sel = 1
-
-    // writel(0x53022044, readl(0x53022044) & ~(0x1 << 13));       // neg sample adc
-    writel(0x53022044, readl(0x53022044) | (0x1 << 13)); //  pos sample adc
-    value = readl(rf_ana25) & ~(0x1<<8);  writel(rf_ana25, value);  //64M 
-
-    writel(0x530210B0, readl(0x530210B0) & 0xFFFF | (1 << 14)); // bt_en_pm = 1
-    writel(0x40002450, 1);                                      // CPR_AO BB_CORELDORF_EN
-
-    writel(0x53020244, readl(0x53020244) & 0xFFFF | (0x1e00 << 16)); // int_fe_ifshift1[12:0] 512->1M IF
-
-    // writel(0x5302204C, RF_TX_ON_DELAY<<8|RF_RX_ON_DELAY); //rf_delay_ctrl
-    writel(0x5302204C, RF_TX_ON_DELAY << 8 | RF_RX_ON_DELAY); // rf_delay_ctrl
-    writel(0x530210B8, (0x1 << 0x1) | (0x1 << 0x2));          // 正常工作
-
-    // 开启两点调制 0x53020214 fmtxen = 1， fm2ptxen = 0
-    writel(0x53020214, 0x1);
-
-    // SYNC_ERR_BLE
-    value = readl(0x53020368) & ~(0x7 << 8);
-    writel(0x53020368, value | (SYNC_ERR_BIT << 8));
-    // printf("rf_ana29 = %x\n", readl(rf_ana29));
-    // printf("rf_ana28 = %x\n", readl(rf_ana28));
-    writel(rf_ana29, readl(rf_ana29) & ~(0x01 << 1));
-    // writel(rf_ana28, 0x0);
-    // printf("rf_ana29 = %x\n", readl(rf_ana29));
-    // printf("rf_ana28 = %x\n", readl(rf_ana28));
-
-    // 频点范围更大
-    /*
-
-    */
-    writel(rf_ana2, 0x615f); // 用这个值发射会变化，指标都能通过！
-
-// writel(rf_ana30, 0x1000);
-// writel(rf_ana22, 0x080C);
-// rf_rccalib(); //加上后会变差 32M 不对! 只能在16M 下面做
-#if defined(CFG_RSSI_ENABLE) //auto_agc
-    auto_agc_init();
-#else
-    value = readl(rf_ana0);
-    writel(rf_ana0, value | (0x1 << 7));
-    // value = readl(rf_ana0) & (~0x7f);
-    // writel(rf_ana0, value | (0x7A));
-    value = readl(rf_ana0) & (~0x7f);
-    // writel(rf_ana0, value | (0x79));
-    writel(rf_ana0, value | (0x77));
-#endif
-
-    // value = readl(rf_ana17) & ~(0x7f<<9); writel(rf_ana17, value | (0x44 << 9));
-    // ana4<15:12>默认1001改成1000；pabias
-    // value = readl(rf_ana4) & ~(0xf<<12); writel(rf_ana4, value | (0x08 << 12));
-    // ana4<8:6>默认010改成100；pacas
-    // value = readl(rf_ana4) & ~(0x7<<6); writel(rf_ana4, value | (0x04 << 6));
-    // ana21<11:6>默认010000改成001000；pagc
-    // value = readl(rf_ana21) & ~(0x3f<<6); writel(rf_ana21, value | (0x08 << 6));   //调发射功率!
-    // value = readl(rf_ana21) & ~(0x3f<<6); writel(rf_ana21, value | (0x10<< 6));
-    // value = readl(rf_ana21) & ~(0x3f<<6); writel(rf_ana21, value | (0x20<< 6));
-    // value = readl(rf_ana21) & ~(0x3f<<6); writel(rf_ana21, value | (0x3F<< 6));
-    // ana21<11:6> 发射功率  001000 为0db
-    /*
-    #define TRANS_POWER_NEGTIVE_8_9_DBM     0x6065  //-9.90,line loss 1DBM
-    #define TRANS_POWER_NEGTIVE_2_7_DBM     0x6125  //-3.70,line loss 1DBM
-    #define TRANS_POWER_0_5DBM              0x6165  //-0.50,line loss 1DBM
-    #define TRANS_POWER_0_6DBM              0x61a5  //-0.4,line loss 1DBM
-    #define TRANS_POWER_2_85DBM             0x61e5  //1.85,line loss 1DBM
-    #define TRANS_POWER_2_9DBM              0x6225  //1.90,line loss 1DBM
-    #define TRANS_POWER_4_68DBM             0x6265  //3.68,line loss 1DBM
-    #define TRANS_POWER_4_6DBM              0x62a5  //3.60,line loss 1DBM
-    #define TRANS_POWER_6_1DBM              0x62e5  //5.10,line loss 1DBM
-    #define TRANS_POWER_7_3DBM              0x6365  //6.30,line loss 1DBM
-    #define TRANS_POWER_8_3DBM              0x6425  //7.30,line loss 1DBM
-    #define TRANS_POWER_9_2DBM              0x6465  //8.20,line loss 1DBM
-    #define TRANS_POWER_13_06DBM            0x67e5  //12.06,line loss 1DBM
-    #define TRANS_POWER_13_05DBM            0x6825  //12.05,line loss 1DBM
-    #define TRANS_POWER_13_35DBM            0x6865  //12.35,line loss 1DBM
-    */
-    // writel(rf_ana21, 0x6225); //  6225  TRANS_POWER_NEGTIVE_2_7_DBM
-    writel(rf_ana21, 0x6265);
-    
-    // 配置 VCO 电流ana18<2:0> --000, ana18<5:3> --001
-    value = readl(rf_ana18) & ~(0x7);
-    writel(rf_ana18, value);
-    value = readl(rf_ana18) & ~(0x7 << 3);
-    writel(rf_ana18, value | 0x1);
-
-    // 如果2416信道发射有问题，1M模式可以把ana2<8:5>1mtxr2,默认1011改成1010,1001,1000,0111 试试。
-    //  value = readl(rf_ana2) & ~(0xf<<5); writel(rf_ana2, value | (0x7 << 5));
-    value = readl(rf_ana2) & ~(0xf << 5);
-    writel(rf_ana2, value | (0x8 << 5));
-
-/*--------------------64M setting -------------------------*/
-#if 1
-    // writel(0x53021008, 0x609f); // rf_ana2
-    // writel(0x53021008, 0xe0df); // rf_ana2
-
-    // // writel(0x53021018, 0x4b18);  //rf_ana6
-    // writel(0x53021018, 0x4118); // rf_ana6
-    // writel(0x53021020, 0xece4); // rf_ana8
-    writel(0x53021020, 0xec64); // rf_ana8
-    // writel(rf_ana2, 0xe0bf);
-    // writel(0x5302100c, 0x1920);
-     writel(rf_ana2, 0xe0ff);
-    //writel(rf_ana2, 0xe0df);
-    writel(0x5302100c, 0x2920);
-    // *((uint32_t volatile*)0x53022050) = 0x4b1;   //2426
-    // *((uint32_t volatile *)0x53022050) = 0x4d8; // 2480
-    // *((uint32_t volatile*)0x53022050) = 0x4d7;   //2478
-    // *((uint32_t volatile*)0x53022050) = 0x4b1;   //2402
-    // *((uint32_t volatile*)0x53022050) = 0x4c4;   //2440
-    // *((uint32_t volatile*)0x53022050) = 0x4d6;   //2476
-
-    // *((uint32_t volatile *)0x53022060) = 0x550080;
-    cpr_bt_clk_ctl__bt_clk_div__setf(0x3);
-
-    // 晶振频偏
-    value2 = cprao_aon_rf_aonreg_get();
-    // cprao_aon_rf_aonreg_set((value2 & (~(0x3f << 20))) | ((0x22 & 0x3f) << 20));
-    // cprao_aon_rf_aonreg_set((value2 & (~(0x3f << 20))) | ((0x30 & 0x3f) << 20));
-    cprao_aon_rf_aonreg_set((value2 & (~(0x3f << 20))) | ((0x25 & 0x3f) << 20));
-    // w4 0x53022060 0x550080
-    writel(0x53022060, 0x550085);
-#endif
+    uint32_t value;
+    value = readl(CPRAO_AON_RF_AONREG_ADDR) & ~(0x3F << 20);
+    writel(CPRAO_AON_RF_AONREG_ADDR, value | (set_value << 20));
 }
-#else
-void modem_init(uint16_t config)
+
+void modem_init(void)
 {
     uint32_t value = 0;
     // open bt clock
@@ -802,14 +646,10 @@ void modem_init(uint16_t config)
                            0xFFFF0000); // 0x74[2] bt32k_clk_en
     writel(0x4000247c, 0x200020);       // bt32k_clk_ao_en
     writel(0x53022048, ((MODEM_TXON_DELAY << 8) | MODEM_RXON_DELAY));
-    writel(0x53020368, readl(0x53020368) | 0x80000000); // EXT_CORRCODE_EN[31] (0x01 << 31)
+    writel(0x53020368, readl(0x53020368) | (0x01 << 31)); // EXT_CORRCODE_EN[31]
     writel(0x53020204, readl(0x53020204) | (0x01 << 2));  // int_rx_cfg_sel = 1
 
-    // writel(0x53022044, readl(0x53022044) & ~(0x1 << 13)); // neg sample adc
-    writel(0x53022044, readl(0x53022044) | (0x1 << 13)); //  pos sample adc
-
-
-
+    writel(0x53022044, readl(0x53022044) & ~(0x1 << 13)); // neg sample adc
     writel(0x530210B0, readl(0x530210B0) & 0xFFFF | (1 << 14)); // bt_en_pm = 1
     writel(0x40002450, 1); // CPR_AO BB_CORELDORF_EN
 
@@ -829,21 +669,25 @@ void modem_init(uint16_t config)
 
     writel(rf_ana2, 0x615f);
 
-    rf_rccalib(); //rc fix 16M
-    // 用ana25<8>切换，默认1=16M，0=32M
-    value = readl(rf_ana25) & ~(0x1<<8);  writel(rf_ana25, value);  
-    if(config & 0x1){  //bit
+    rf_rccalib();
+#if CFG_RSSI_ENABLE //auto_agc
     auto_agc_init();
-    }else{
+#else
     ////ana0<7>默认0改成1，进入手动agc模式。用ana0<6:0>配置增益
     value = readl(rf_ana0);
     writel(rf_ana0, value | (0x1 << 7));
     // value = readl(rf_ana0) & (~0x7f) ;  writel(rf_ana0, value | (0x7A));
     value = readl(rf_ana0) & (~0x7f);
     writel(rf_ana0, value | (0x77));
-    }
+#endif
+
+#ifdef USED_DCDC
+    writel(rf_ana21, TRANS_POWER_9_2DBM);
+#error
+#else
+    writel(rf_ana21, TRANS_POWER_NEGTIVE_8_9_DBM);
+#endif // USED_DCDC
 
-    writel(rf_ana21, TRANS_POWER_0_5DBM);
     // 配置 VCO 电流ana18<2:0> --000, ana18<5:3> --001
     value = readl(rf_ana18) & ~(0x7);
     writel(rf_ana18, value);
@@ -851,7 +695,11 @@ void modem_init(uint16_t config)
     writel(rf_ana18, (value | (0x1 << 3)));
     value = readl(rf_ana2) & ~(0xf << 5);
     writel(rf_ana2, value | (0x8 << 5));
+    value = readl(rf_ana24);
   
+    value=0x952c;
+
+    writel(rf_ana24, value);
 #ifdef VCO_POWER
     // ana4<15:12>默认1001（量产版默认值1000）改成0000
     value = readl(rf_ana4) & ~(0xf << 12);
@@ -868,33 +716,10 @@ void modem_init(uint16_t config)
     value = readl(rf_ana28) & ~(0x7 << 2);
     writel(rf_ana28, value);
 #endif // VCO_POWER
-    //ana24<5:3> pllldovout ，默认100改成101.  
-    value = readl(rf_ana24) & (~(0x7 << 3));
-    writel(rf_ana24, (value | (0x5 << 3)));
-    // printf("rf_ana24=0x%x\n", readl(rf_ana24));
 
-    // printf("rf_ana8=0x%x rf_ana15=0x%x\n", readl(rf_ana8), readl(rf_ana15));
     // rf_test_pin_init();
-
-    writel(rf_ana2, 0xe0df);
-    writel(0x53022060, 0x550105);
-    writel(0x5302100c, 0x4920);
-    writel(rf_ana17, (readl(rf_ana17) | (0xEE << 8) ));
 }
 
-void rf_xtal_cal_set(uint8_t set_value)
-{
-    uint32_t value;
-    value = readl(CPRAO_AON_RF_AONREG_ADDR) & ~(0x3F << 20);
-    writel(CPRAO_AON_RF_AONREG_ADDR, value | (set_value << 20));
-}
-
-void rf_tx_power_set(uint32_t value)
-{
-    writel(rf_ana21, value);
-}
-
-#endif //defined(USE_64M_CRYSTAL)
 /****************************************************************************************
  * RADIO FUNCTION INTERFACE
  ***************************************************************************************/

component/ble/modules/rwip/api/rwip.h

@@ -33,11 +33,9 @@
 
 #include <stdint.h>               // standard integer definitions
 #include <stdbool.h>              // standard boolean definitions
-#include "co_bt_defines.h"
 
 #define __RAM_EM                              __attribute__((section("ram_em")))
-#define KE_HEAP0                    __attribute__((section("ke_heap0")))
-#define KE_HEAP1                    __attribute__((section("ke_heap1")))
+
 /*
  * DEFINES
  ****************************************************************************************
@@ -74,6 +72,7 @@
 *  ____________________________|______________________________________|________________________________
 */
 #define HALF_SLOT_INV(x)  (HALF_SLOT_SIZE - x - 1)
+#define __RAM_EM_CODE                     __attribute__((section("ram_em")))
 
 /// result of sleep state.
 enum rwip_sleep_state
@@ -820,7 +819,7 @@ void rwip_init(uint32_t error);
  *
  ****************************************************************************************
  */
-void rwip_reset(void);
+//void rwip_reset(void);
 
 
 

component/ble/modules/rwip/api/rwip_config.h

@@ -41,7 +41,11 @@
 /******************************************************************************************/
 /* -------------------------   PATCH PARTITIONING      -----------------------------------*/
 /******************************************************************************************/
-#define __RAM_OTA                     __attribute__((section("ota_data")))
+#if defined(CFG_CONFIG_XMBOX_RC)
+#define CONFIG_XMBOX_RC                 1
+#else
+#define CONFIG_XMBOX_RC                 0
+#endif
 
 #if defined(CFG_CONFIG_AES)
 #define RWIP_AES_ENCRYPT                1
@@ -141,13 +145,11 @@
 #endif // defined(CFG_EATT)
 
 #if defined(CFG_LECB)
-#define BLE_LECB              1
+#define BLE_LECB              0
 #else // defined(CFG_LECB)
 #define BLE_LECB              0
 #endif // defined(CFG_LECB)
 
-#define BLE_LECB_COC          0
-
 #if defined(CFG_HL_L2CAP_MSG_API)
 #define BLE_HL_L2CAP_MSG_API              0
 #else // defined(CFG_HL_L2CAP_MSG_API)
@@ -172,6 +174,13 @@
 #define BLE_SCH_SLICE              1
 #endif // defined(CFG_SCH_SLICE)
 
+// #if defined(CFG_ADV_LOW_POWER)
+// #define ADV_LOW_POWER             1
+// #else // defined(CFG_ADV_LOW_POWER)
+// #define ADV_LOW_POWER             0
+// #endif // defined(CFG_ADV_LOW_POWER)
+#define ADV_LOW_POWER  0
+
 #if defined(CFG_SCAN_PERFORMANCE)
 #define SCAN_PERFORMANCE             1
 #else // defined(CFG_SCAN_PERFORMANCE)
@@ -189,40 +198,16 @@
 #else // defined(CFG_MTU_SIZE)
 #define USER_PREF_MTU                (512) 
 #endif // defined(CFG_MTU_SIZE)
-#if CFG_SACN_RESPONSE
-#define CFG_SCAN_RESPONSE_SET 1
-#else
-#define CFG_SCAN_RESPONSE_SET 0
-#endif
+
 #if defined(CFG_MIN_STACK)
 #define MIN_STACK             0
 #define OPEN_GAP_SERVER       1
-#define MIN_STACK_MASTER      0
 #else // defined(CFG_MIN_STACK)
 #define MIN_STACK             1
 #define OPEN_GAP_SERVER       1
-#define MIN_STACK_MASTER      1
 #endif // defined(CFG_MIN_STACK)
 
-
-// Mode 0: delay in sends packet.
-// Mode 1: delay in connection events.
-// Mode 2: xip runs 1M/2M rates, in connection events.
-// Mode 3: delay with tx only, in connection events.
-#if defined(NOT_RUN_XIP_TX_ONLY)
-#define CONN_EVENT_NOT_RUN_XIP    (3)
-#else
-#define CONN_EVENT_NOT_RUN_XIP    (1)
-#endif //  defined(NOT_RUN_XIP_TX_ONLY)
-
-#if defined(NOT_RUN_XIP_TX_ONLY)
-// Prevent xip interference when advertising.
-#define ADV_EVENT_NOT_RUN_XIP     (0)
-#else
-#define ADV_EVENT_NOT_RUN_XIP     (1)
-#endif // defined(NOT_RUN_XIP_TX_ONLY)
-// No timeout disconnections in latency scenarios.
-#define NOT_DISCONN_WITH_LATENCY   (0)
+#define CONN_EVENT_NOT_RUN_XIP    0
 
 // CFG_RSSI_ENABLE ��enable auto agc��
 //  connect mode��rf_rssi_convert get value,open debug rssi
@@ -351,7 +336,7 @@
 
 /// Maximum number of simultaneous BLE activities (scan, connection, advertising, initiating)
 // #define BLE_ACTIVITY_MAX          (CFG_ACT)
-#define BLE_ACTIVITY_MAX          (CFG_ACT)
+#define BLE_ACTIVITY_MAX          (20)
 
 #if (BLE_HOST_PRESENT)
 /// Maximum number of simultaneous connections
@@ -427,22 +412,6 @@
     #define BLE_AOA                        (0)
 #endif // defined(CFG_AOA)
 
-/******************************************************************************************/
-/* --------------------------   APP       -------------------------*/
-/******************************************************************************************/
-#if defined(CFG_CONFIG_XMBOX_RC)
-#define CONFIG_XMBOX_RC                 1
-//When BLE TX isr the cpu not run in XIP.
-//This opt just fit to ble tx no-delay solution.
-#define CONFIG_XIP_OPT_HIGH_LEVEL       1
-//#define  CONFIG_DEBUG_ON_EVB
-#define BLE_GATT_CLI_GATT_CLI_MTU_EXCH  1
-#undef BLE_LECB
-#define BLE_LECB                        1
-#else
-#define CONFIG_XMBOX_RC                 0
-#endif
-
 /******************************************************************************************/
 /* --------------------------   ISOCHRONOUS CONFIGURATION        -------------------------*/
 /******************************************************************************************/
@@ -571,7 +540,7 @@
 
 /// Size and number of big buffers available by default
 #define CO_BUF_BIG_SIZE        (GAP_LE_MTU_MAX)
-#define CO_BUF_BIG_NB          (1)
+#define CO_BUF_BIG_NB          (2)
 #define CO_BUF_BIG_POOL_SIZE   ((CO_ALIGN4_HI(sizeof(co_buf_t) + CO_BUF_BIG_SIZE)) * CO_BUF_BIG_NB)
 
 
@@ -1100,11 +1069,7 @@ enum KE_MEM_HEAP
 #endif //BLE_HOST_PRESENT
 
 #if (BT_EMB_PRESENT || BLE_EMB_PRESENT)
-#if (CONFIG_XMBOX_RC)
-#define ECC_HEAP_NON_RET_SIZE_   (2048)//(328*2) // Could only have 2 ECC computations simultaneously
-#else
-#define ECC_HEAP_NON_RET_SIZE_   (328*2)
-#endif
+#define ECC_HEAP_NON_RET_SIZE_   (328*2) // Could only have 2 ECC computations simultaneously
 #else // (BT_EMB_PRESENT || BLE_EMB_PRESENT)
 #define ECC_HEAP_NON_RET_SIZE_   (0)
 #endif // (BT_EMB_PRESENT || BLE_EMB_PRESENT)

component/ble/plf/refip/src/arch/compiler/gnuarm/compiler.h

@@ -87,12 +87,11 @@
 #endif // __ARMCC_VERSION
 
 /// define the static keyword for this compiler
-//#ifdef CFG_STATIC
-//#define __STATIC static
-//#else // CFG_STATIC
-//#define __STATIC
-//#endif // CFG_STATIC
+#ifdef CFG_STATIC
+#define __STATIC static
+#else // CFG_STATIC
 #define __STATIC
+#endif // CFG_STATIC
 
 /// define the force inlining attribute for this compiler
 //#define __INLINE __forceinline static

component/boot2/app/main.c

@@ -1,258 +0,0 @@
-/*----------------------------------------------------------------------------------------------------
-    INCLUDE HEADE FILES
-----------------------------------------------------------------------------------------------------*/
-//#include "Includes.h"
-#include "xc6xxx.h"
-#include <stdio.h>
-#include <stdarg.h>
-#include <string.h>
-#include "BootSecond.h"
-
-
-extern void makeCRC32table(unsigned int table[]);
-extern unsigned int crc32table[];
-
-void clock_init(void)
-{
-    clock_cb.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
-    clock_cb.hfclk_in = CLOCK_HFCLK_IN_32M;
-    clock_cb.systick_unit = (Systick_Unit_Typedef)(clock_cb.hfclk_in / 1000000);
-
-    /* Set the voltages of bbldo and lpldo */
-    cprao_aon_bbldo_adj_set(0x2c);
-    cprao_aon_lpoldo_adj_set(7);
-
-    /* Set the 32K lfclk */
-    clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
-    clock_cb.lfclk_in = CLOCK_LFCLK_IN_32K;
-
-    SysTick_Config(xc_clock_hfclk_in_get() / 100);
-    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-}
-
-void app_uart_init(void)
-{
-    GPIO_InitCfg_t gpio_cfg = {0};
-
-    gpio_cfg.Mux            = GPIO_Mux0;
-    gpio_cfg.Pull           = GPIO_PULLUP;
-    gpio_cfg.Int            = NOT_INT;
-    gpio_cfg.FunSel         = UART0_TX;
-
-    gpio_cfg.Pin            = GPIO_18;
-    gpio_cfg.Dir            = GPIO_DIR_OUTPUT;
-    xc_gpio_init(&gpio_cfg);
-
-    gpio_cfg.FunSel = UART0_RX;
-    gpio_cfg.Pin    = GPIO_19;
-    gpio_cfg.Dir    = GPIO_DIR_INPUT;
-    xc_gpio_init(&gpio_cfg);
-
-    UART_InitCfg_t uart_cfg      = {0};
-
-    uart_cfg.Parity              = UART_PARITY_DISABLE;
-    uart_cfg.StopBits            = UART_STOP_1_BITS;
-    uart_cfg.WordLength          = UART_DATA_8_BITS;
-    uart_cfg.BaudRate            = UART_BAUDRATE_115200;
-    uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
-
-    xc_uart_init(UART0_IDX, &uart_cfg);
-}
-
-
-void printf_string(char *strings)
-{
-	while(*strings != '\0')
-	{
-		xc_uart_send_byte(UART0_IDX, *strings);
-		strings ++;
-	}
-}
- 
-void printf_hex(uint32_t input_data)
-{
-	uint8_t temp[96];
-	uint8_t i = 0;
-    
-	while(input_data > 0)
-	{
-        if((input_data % 16) > 9)
-            temp[i]=(input_data % 16) - 10 + 'a';
-        else
-            temp[i]=(input_data % 16) + '0';   
-		
-		input_data = input_data / 16;
-		i ++;
-	}
-    
-	for( ; i>0; i --)
-	{
-		xc_uart_send_byte(UART0_IDX, temp[i-1]);
-	}
-}
-int uart_printf(const char *fmt,...)
-{
-	char chr;
-	int argint;
-    char temp;
-
-	char *argstr;
-	va_list va;				
-	va_start(va,fmt);		
-	
-	while((chr= *fmt++) != '\0')
-	{
-		if(chr != '%')
-		{
-			xc_uart_send_byte(UART0_IDX, chr);
-			continue;
-		}
-        if(*fmt != '\0')
-            temp=*fmt++;
-        else
-            temp='\0';
-		
-		switch(temp)
-		{
-			case '\0':
-				xc_uart_send_byte(UART0_IDX, '%');
-                break;
-			case 'c':
-				xc_uart_send_byte(UART0_IDX, va_arg(va,int));
-                break;
-			case 's':
-				argstr = va_arg(va,char *);
-				printf_string(argstr);				
-			    break;
-			case 'x':
-			case 'X':
-				argint = va_arg(va,int);
-				printf_hex(argint);
-		        break;
-			default :		
-				xc_uart_send_byte(UART0_IDX, '%');
-				fmt --;
-				break;
-			
-		}
-	}
-	va_end(va);		
-    return 0;
-}
-
-__RAM_CODE void Wdt_Rreset(void)
-{
-	xc_pwr_rom_on();
-    cprao_aon_slp_pd_mask_set(0x001);
-#if XTAL_32K 
-    cprao_aon_ctl_clk32k_set(0x109);
-#endif
-	
-	WDT_InitCfg_t wdt_cfg ;
-
-    wdt_cfg.WorkMode      = WDT_WORK_MODE0;
-    wdt_cfg.ReloadValue   = WDT_CLK_32M_RESET_MODE0_4096US;
-    wdt_cfg.PclkSel       = WDT_WORK_32M;
-//    xc_wdt_init(&wdt_cfg);
-//    xc_wdt_start();
-    
-    // xc_wdt_init
-    cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
-    cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
-    cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
-
-    /*
-    SYS_DISABLE | M0_ENABLE :    SYS RST, for low-power reset or quick system reset;
-    SYS_ENABLE  | M0_DISABLE:    M0 RST,  only for m0 reset;
-    SYS_DISABLE | M0_DISABLE:    M0 RST,  m0 reset and low-power reset;
-    */
-    cpr_rstctl_wdtrst_mask_set(
-        (WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
-    cpr_lp_ctl__wdt_pclk_sel__setf(wdt_cfg.PclkSel);
-    cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
-
-    wdt_cr__wdt_rmod__setf(wdt_cfg.WorkMode);
-    wdt_torr__wdt_top__setf(wdt_cfg.ReloadValue);
-
-    //xc_wdt_start();
-    wdt_cr__wdt_rpl__setf(WDT_CR_RPL_4PCLK);
-    wdt_cr__wdt_en__setf(ENABLE);
-    wdt_crr__setf(WDT_CRR_CRR_ENABLE);
-    cpr_ctlapbclken_grctl__wdt_pclk_en__setf(DISABLE);
-    while(1);
-}
-
-void wdt_init(void)
-{
-    WDT_InitCfg_t wdt_cfg ;
-
-    wdt_cfg.WorkMode      = WDT_WORK_MODE0;
-    wdt_cfg.ReloadValue   = WDT_CLK_32K_RESET_MODE0_4096MS;
-    wdt_cfg.PclkSel       = WDT_WORK_32K;
-    
-    xc_wdt_init(&wdt_cfg);
-    xc_wdt_start();
-}
-
-void bor_init(void)
-{
-    cprao_aon_bor_ctr_reg0__bor_ctrl__setf(0x4);
-    cprao_aon_bor_ctr_reg0__bor_rstn_mask__setf(1);
-    cprao_aon_bor_ctr_reg0__bor_intr_mask__setf(0);
-    NVIC_EnableIRQ(MPU_IRQn);
-}
-
-__RAM_CODE void MPU_Handler(void)
-{
-    Wdt_Rreset();
-}
-
-__RAM_CODE void HardFault_Handler()
-{
-    printf_string("HardFault_Handler\n");
-    Wdt_Rreset();
-}
-
-int main(void)
-{
-    wdt_init();
-    bor_init();
-#ifdef WITHOUT_OTA
-
-#ifdef QUAD_ENABLE
-    init_xip(QUAD_MODE);
-#else
-    init_xip(DUAL_MODE);
-    jump_app();
-#endif
-#endif
-    
-#ifdef BLE_OTA 
-    clock_init();
-	app_uart_init();
-	uart_printf("boot init\n");
-	 
-
-
-
-    // Init_spi_master(0, SPIM_CLK_16MHZ);
-    flash_init();
-//    makeCRC32table(crc32table);
-    boot_run_sec();
-#endif
-
-#ifdef OTA_24G
-    config_2_4g_rf();
-    Init_spi_master(0, SPIM_CLK_16MHZ);
-    makeCRC32table(crc32table);
-
-    spi_flash_Release_powerdown();
-    *((uint32_t volatile *)0x40002450) |= 0x0; //- open rf digital
-    // erase_flash_chip();
-    printf("erase_flash_chip\n");
-
-    rx_24g_ota();
-#endif
-    while (1)
-        ;
-}

component/boot2/app/sdk_config.h

@@ -1,145 +0,0 @@
-
-#ifndef SDK_DRIVER_CONFIG_H
-#define SDK_DRIVER_CONFIG_H
-// <<< Use Configuration Wizard in Context Menu >>>\n
-#ifdef USE_APP_CONFIG
-#include "app_config.h"
-#endif
-// <h> XC_Drivers
-
-// <e> XC_CLOCK_ENABLED
-//==========================================================
-#ifndef XC_CLOCK_ENABLED
-#define XC_CLOCK_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_PWR_ENABLED
-//==========================================================
-#ifndef XC_PWR_ENABLED
-#define XC_PWR_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_WDT_ENABLED
-//==========================================================
-#ifndef XC_WDT_ENABLED
-#define XC_WDT_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_BOR_ENABLED
-//==========================================================
-#ifndef XC_BOR_ENABLED
-#define XC_BOR_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_SYSTICK_ENABLED
-//==========================================================
-#ifndef XC_SYSTICK_ENABLED
-#define XC_SYSTICK_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_TIMER_ENABLED
-//==========================================================
-#ifndef XC_TIMER_ENABLED
-#define XC_TIMER_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_AOTIMER_ENABLED
-//==========================================================
-#ifndef XC_AOTIMER_ENABLED
-#define XC_AOTIMER_ENABLED 0
-#endif
-// </e>
-
-// <e> XC_GPIO_ENABLED
-//==========================================================
-#ifndef XC_GPIO_ENABLED
-#define XC_GPIO_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_ADC_ENABLED
-//==========================================================
-#ifndef XC_ADC_ENABLED
-#define XC_ADC_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_UART_ENABLED
-//==========================================================
-#ifndef XC_UART_ENABLED
-#define XC_UART_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_PWM_ENABLED
-//==========================================================
-#ifndef XC_PWM_ENABLED
-#define XC_PWM_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_FMC_SPI_ENABLED
-//==========================================================
-#ifndef XC_FMC_SPI_ENABLED
-#define XC_FMC_SPI_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_SPI_ENABLED
-//==========================================================
-#ifndef XC_SPI_ENABLED
-#define XC_SPI_ENABLED 1
-#endif
-// </e>
-
-// <e> XC_IIC_ENABLED
-//==========================================================
-#ifndef XC_IIC_ENABLED
-#define XC_IIC_ENABLED 0
-#endif
-// </e>
-
-// <e> XC_RTC_ENABLED
-//==========================================================
-#ifndef XC_RTC_ENABLED
-#define XC_RTC_ENABLED 0
-#endif
-// </e>
-
-// <e> XC_DMA_ENABLED
-//==========================================================
-#ifndef XC_DMA_ENABLED
-#define XC_DMA_ENABLED 0
-#endif
-// </e>
-
-// <e> XC_PGA_ENABLED
-//==========================================================
-#ifndef XC_PGA_ENABLED
-#define XC_PGA_ENABLED 0
-#endif
-// </e>
-
-// <e> XC_QDEC_ENABLED
-//==========================================================
-#ifndef XC_QDEC_ENABLED
-#define XC_QDEC_ENABLED 0
-#endif
-// </e>
-
-// <e> XC_CALIB_ENABLED
-//==========================================================
-#ifndef XC_CALIB_ENABLED
-#define XC_CALIB_ENABLED 0
-#endif
-// </e>
-
-// <<< end of configuration section >>>
-#endif //SDK_DRIVER_CONFIG_H
-

component/boot2/boot2_tools/Debug/ram_program.bat

@@ -1 +0,0 @@
-Xincboot_tool.exe s.bin download.bin 0 0 0 0 1

component/boot2/boot2_tools/Debug/xinchip_bootloader2.bat

@@ -1,4 +0,0 @@
-xinchip_bootloader2_tool.exe  boot2  ^
-sxip11003000.bin  0x11003000  0  ^
-s2.bin            0x10000000  1  ^
-download.bin

component/boot2/boot2_tools/xinchip_bootloader2_tool.c

@@ -1,398 +0,0 @@
-/********************************************************************
-*本程序由VC++6.0编译
-*主要实现修改bin文件中的几个字节(将这几个字节变为Mac地址的相关信息)
-*2019-09-20 17:38
-********************************************************************/
-#include<string.h>
-#include<stdio.h>
-#include <malloc.h>
-
-
-#define PARAM_CNT      5
-#define PARAM_LENGTH   240
-typedef enum{
-    	InvalidStat         = 0,
-		ActiveAStat         = 1,
-		EraseAStat          = 2,
-		OverwriteAStat      = 3,
-		ActiveBStat         = 4,
-		EraseBStat          = 5,
-		OverwriteBStat      = 6,
-}STATUS_T;
-
-typedef enum{
-	    ErrNone          =0,
-		ErrParamDamage   =1,
-		ErrOverWrite     =2,
-		ErrCheck         =3,
-}ERROR_T;
- 
-typedef struct{
-    unsigned int Status;/**/
-	unsigned int SoftVer;/**/
-	unsigned int ACheck;/*crc32*/
-	unsigned int AAddr;/*sector align*/
-	unsigned int ALen;/*page align*/
-	unsigned int BCheck;/**/
-	unsigned int BAddr;/**/
-	unsigned int BLen;/**/
-    unsigned int ALoadAddr;/**/
-	unsigned int BLoadAddr;/**/
-	unsigned int RESERVED0[2];
-}PARAM_UNIT; 
-
-typedef struct{
-    PARAM_UNIT ParamUnit[PARAM_CNT];
-	unsigned int ParamCrc32;
-    unsigned int RESERVED1[3];	
-}sBOOT_MESSAGE;
-
-
-sBOOT_MESSAGE bms={0};
-
-#define SECTOR_OFFSET  3
-#define SECTOR_BYTE    4096
-
-#define MAC_INFO_ADD   136
-#define SUM_CHECK_ADD  64
-#define BURN_TIMES_ADD 72
-/************************************************
-
-************************************************/
-
-unsigned int my_atoi(unsigned char *p)
-{
-    unsigned char i=0;
-    unsigned int  temp=0;
-    while(p[i])
-    {
-		if((p[i]=='0')&&(p[i+1]=='x')||(p[i]=='0')&&(p[i+1]=='X'))
-		{
-            i+=2;
-            continue;
-		}
-		switch(p[i])
-		{
-	   	case '0':temp=temp*16 +0;break;
-		case '1':temp=temp*16 +1; break;
-		case '2':temp=temp*16 +2; break;
-		case '3':temp=temp*16 +3; break;
-		case '4':temp=temp*16 +4; break;
-		case '5':temp=temp*16 +5; break;
-		case '6':temp=temp*16 +6; break;
-		case '7':temp=temp*16 +7; break;
-		case '8':temp=temp*16 +8; break;
-		case '9':temp=temp*16 +9; break;
-		case 'A': case 'a':temp=temp*16 +10; break;
-		case 'B': case 'b':temp=temp*16 +11; break;
-		case 'C': case 'c':temp=temp*16 +12; break;
-		case 'D': case 'd':temp=temp*16 +13; break;
-		case 'E': case 'e':temp=temp*16 +14; break;
-		case 'F': case 'f':temp=temp*16 +15; break;
-		}
-		i++; 
-		
-		
-    }
-	
-	
-    return temp;
-}
-
-/************************************************
-*函 数 名:GetBinSize
-*功    能:获取bin文件的长度(单位字节)
-*日期作者:2019-09-23 11:40-陈俊伟
-************************************************/
-int GetBinSize(char *filename)  
-{     
-    int  siz = 0;     
-    FILE  *fp = fopen(filename, "rb");     
-    if (fp)   
-    {        
-        fseek(fp, 0, SEEK_END);        
-        siz = ftell(fp);        
-        fclose(fp);     
-    }     
-    return siz;  
-}
-
-
-/************************************************
-*函 数 名:read_bin
-*功    能:将bin文件的内容读取到buf里
-*日期作者:2019-09-20 11:48-陈俊伟
-************************************************/
-void read_bin(char *path, unsigned char *buf, int size)  
-{  
-    FILE *infile;  
-      
-    if((infile=fopen(path,"rb"))==NULL)  
-    {  
-        printf( "\nCan not open the path: %s \n", path);  
-		getchar();
-        exit(-1);  
-    }  
-    fread(buf, sizeof(unsigned char), size, infile);
-    fclose(infile);  
-}
-
-/************************************************
-*函 数 名:write_bin
-*功    能:将bin文件的内容写入到buf里
-*日期作者:2019-09-23 14:33
-************************************************/
-void write_bin(char *path, unsigned char *buf, int size)  
-{  
-    FILE *infile;  
-      
-    if((infile=fopen(path,"wb"))==NULL)  
-    {  
-        printf( "\nCan not open the path: %s \n", path);
-		getchar();
-        exit(-1);  
-    }  
-  //fread (buf,sizeof(unsigned char),size,infile);
-	fwrite(buf,sizeof(unsigned char),size,infile);
-    fclose(infile);  
-}
-
-
-//CRC32
-
-#define  CRC32_INITVAL   0 
-unsigned int crc32table[256];
-
-
-extern void makeCRC32table(unsigned int table[]){
-    unsigned int value;
-    unsigned int i, j;
-    for(i=0; i<256; i++){
-        value = i;
-        for(j=0; j<8; j++){
-            if(value&1){
-                value = (value >> 1) ^ 0xedb88320;
-            }
-            else{
-                value = (value >> 1);
-            }
-        }
-        table[i] = value;
-    }
-}
-
-unsigned int get_crc32(unsigned int crc, unsigned char *buf, unsigned int len)
-{
-  const unsigned char *buffer = (const unsigned char *)buf;
-  int i = 0;
-  while (len--) {
-    crc ^= (unsigned int)(*buffer++) << 24;
-
-    for (i = 0; i < 8; i++) {
-      if (crc & 0x80000000) {
-        crc = (crc << 1) ^ 0xEDB88320;
-      } else {
-        crc <<= 1;
-      }
-    }
-  }
-  return crc;
-}
- 
-
-int main(int argc,char **argv)
-{
-   // FILE * fp;
-	unsigned char *buf=NULL;
-	unsigned char *ptr=NULL;
-    char *src1;
-	char *src2;
-	char *src3;
-	//char *src4;
-	//char *src5;
-	//char *src6;
-    char *des;
-    unsigned int laod_addr1;
-    unsigned int laod_addr2;
-    char status1;
-	char status2;
-
-	int bin_size0=0;
-	int bin_size1=0;
-	int bin_size2=0;
-
-	int sectorCNT1=0;
-	int sectorCNT2=0;
-    unsigned char *pbm;
-    int all_size=0; 
-    int i=0,j=0; 
-    unsigned char val=0;
-    unsigned int crc32_val=CRC32_INITVAL;
-	makeCRC32table(crc32table);
-    printf("总有%d个命令行参数\n",argc);
-    if(argc<9)
-	{  
-		printf("命令参数中请加上源文件名、加载域地址、状态和目的文件名，比如：xinchip_boot2_tool.exe boot2 s1.bin 0x10000000 1 s2.bin 0x11000000 0  download.bin\n");
-		//printf("命令参数中请加上源文件名和目的文件名，比如：xinchip_boot2_tool.exe boot2 s1.bin 0x10000000 1 download.bin\n");
-		getchar();
-		return -1;
-	}
-    printf("可 执 行文 件 名:%s\n",*argv);    //xinchip_boot2_tool.exe 程序名字
-    printf("第一个命令行参数[bootloader program ]:%s\n",*(argv+1));     //第一个命令行参数  boot2      [bootloader program ]
-    printf("第二个命令行参数[APP1 program]:%s\n",*(argv+2));            //第二个命令行参数  s1.bin     [APP1 program]
-    printf("第三个命令行参数[load_addr: sector align]:%s\n",*(argv+3)); //第三个命令行参数  0x10000000 [load_addr: sector align]
-	printf("第四个命令行参数[1:active,0:invalid]:%s\n",*(argv+4));      //第四个命令行参数  1          [1:active,0:invalid] 
-
-     
-
-    printf("第五个命令行参数[APP2 program]:%s\n",*(argv+5));                //第五个命令行参数   //s2.bin     [APP2 program]
-    printf("第六个命令行参数[load_addr: sector align]:%s\n",*(argv+6));     //第六个命令行参数   //0x11010000 [load_addr: sector align]
-	printf("第七个命令行参数[1:active,0:invalid]:%s\n",*(argv+7));          //第七个命令行参数   //0          [1:active,0:invalid]  
-    printf("第八个命令行参数[生成的最终bin]:%s\n",*(argv+8));               //第八个命令行参数 
-
-
-	src1=*(argv+1);
-	src2=*(argv+2);
-	src3=*(argv+5);
-	des=*(argv+8);
-
-    laod_addr1=my_atoi(*(argv+3));
-	laod_addr2=my_atoi(*(argv+6));
-	status1=my_atoi(*(argv+4));
-	status2=my_atoi(*(argv+7));
-	
-    printf("src1=%s\n",src1);
-	printf("src2=%s\n",src2);
-	printf("src3=%s\n",src3);
-	printf("des=%s\n",des);
-	
-	printf("laod_addr1=0x%08x\n",laod_addr1);
-	printf("laod_addr2=0x%08x\n",laod_addr2);
-	printf("status1=%d\n",status1);
-    printf("status2=%d\n",status2);
-
-    if(laod_addr1>=0x11000000)
-	{
-	    if(status1>1)
-		{
-		   bms.ParamUnit[0].SoftVer |=0x8000;//quad mode  
-		}
-	}
-	if(laod_addr2>=0x11000000)
-	{
-		if(status2>1)
-		{
-			bms.ParamUnit[1].SoftVer |=0x8000;//quad mode
-		}
-	}
- 
-	status1= (status1==0) ? 0:1;
-    status2= (status2==0) ? 0:1;
-
-	bms.ParamUnit[0].Status=status1;
-	bms.ParamUnit[0].ALoadAddr=laod_addr1;
-	bms.ParamUnit[1].Status=status2;
-    bms.ParamUnit[1].ALoadAddr=laod_addr2;
-
-
-    bin_size0=GetBinSize(src1);//bin_size=GetBinSize("./boot2.bin");
-	bin_size1=GetBinSize(src2);//bin_size=GetBinSize("./s1.bin");
-	bin_size2=GetBinSize(src3);//bin_size=GetBinSize("./s2.bin");
-
-    sectorCNT1= (bin_size1%4096 ==0 ) ? (bin_size1/4096):((bin_size1/4096)+1);
-    sectorCNT2= (bin_size2%4096 ==0 ) ? (bin_size2/4096):((bin_size2/4096)+1);
-
-	bms.ParamUnit[0].AAddr=SECTOR_OFFSET*SECTOR_BYTE;
-	bms.ParamUnit[0].ALen=bin_size1;
-    bms.ParamUnit[1].AAddr=(sectorCNT1+SECTOR_OFFSET)*SECTOR_BYTE;
-	bms.ParamUnit[1].ALen=bin_size2;
-
-    all_size=SECTOR_BYTE*(SECTOR_OFFSET+sectorCNT1+sectorCNT2);
-     
-	if(NULL==(buf = (unsigned char *)malloc(sizeof(unsigned char)*all_size)))
-	{
-		printf("malloc memory fail !\n");
-		getchar();
-		return -3;
-		
-	}
-	for(i=0;i<all_size;i++) buf[i]=0xFF;
-    
-    read_bin(src1, buf, bin_size0);                                                 //read_bin("./boot2.bin", buf, bin_size0);
-	read_bin(src2, buf+(SECTOR_BYTE*SECTOR_OFFSET), bin_size1);                     //read_bin("./s1.bin", buf+.., bin_size1);
-    read_bin(src3, buf+(SECTOR_BYTE*(sectorCNT1+SECTOR_OFFSET)), bin_size2);        //read_bin("./s2.bin", buf+.., bin_size2); 
-    
-	bms.ParamUnit[0].ACheck=get_crc32(CRC32_INITVAL,buf+(SECTOR_BYTE*SECTOR_OFFSET),bin_size1);
-    bms.ParamUnit[1].ACheck=get_crc32(CRC32_INITVAL,buf+(SECTOR_BYTE*(sectorCNT1+SECTOR_OFFSET)),bin_size2);
-	bms.ParamCrc32=get_crc32(CRC32_INITVAL,(unsigned char *)&bms,PARAM_LENGTH);
-	for(i=0,pbm=(unsigned char *)&bms;i<sizeof(bms);i++)  buf[SECTOR_BYTE*(SECTOR_OFFSET-1)+i]=pbm[i];      
-
-#if 0
-	j=bin_size/4;
-	ptr=buf+4096;
-    for(i=0;i<j;i++)
-	{
-	    val=ptr[4*i];
-        ptr[4*i]=ptr[4*i+2];  
-        ptr[4*i+2]=val;
-
-		val=ptr[4*i+1];
-        ptr[4*i+1]=ptr[4*i+3];
-		ptr[4*i+3]=val;
-	}
-#else
-	/*
-    j=bin_size/4;
-	ptr=buf+4096;
-    for(i=0;i<j;i++)
-	{
-		val=ptr[4*i];
-        ptr[4*i]=ptr[4*i+1];  
-        ptr[4*i+1]=val;
-		
-	 
-	}
-	*/
-    if(laod_addr1 >= 0x11000000) //xip program
-	{
-		j=bin_size1/4;
-		ptr=buf+(SECTOR_BYTE*SECTOR_OFFSET);
-		for(i=0;i<j;i++)
-		{
-			val=ptr[4*i];
-			ptr[4*i]=ptr[4*i+3];  
-			ptr[4*i+3]=val;
-			
-			val=ptr[4*i+1];
-			ptr[4*i+1]=ptr[4*i+2];
-		    ptr[4*i+2]=val;
-		}
-	}
-	if(laod_addr2 >= 0x11000000)  //xip program
-	{
-		j=bin_size2/4;
-		ptr=buf+(SECTOR_BYTE*(sectorCNT1+SECTOR_OFFSET));
-		for(i=0;i<j;i++)
-		{
-			val=ptr[4*i];
-			ptr[4*i]=ptr[4*i+3];  
-			ptr[4*i+3]=val;
-			
-			val=ptr[4*i+1];
-			ptr[4*i+1]=ptr[4*i+2];
-			ptr[4*i+2]=val;
-		}
-	}
-#endif
-
-
-    write_bin(des, buf, all_size);  //write_bin("./download.bin", buf, all_size); 
-
-    printf("updata file success !\n");
-	free(buf);
-	
-
-	
-    //getchar();
-	return 0;
-}

component/boot2/bsp/DMA_uart_debug.c

@@ -1,43 +0,0 @@
-
-#include "DMA_uart_debug.h"
-
-volatile uint8_t __attribute__((aligned(4))) DMA_buf[16] = {0XAA, 0XAA, 0XAA, 0XAA};
-#define DMAS_BASE 0x50001000
-
-// #define     	DMAS_CHx_SAR(a)     	((volatile unsigned *)(DMAS_BASE + 0x40 + (a * 0x20)))
-// #define     	DMAS_CHx_DAR(a)     	((volatile unsigned *)(DMAS_BASE + 0x44 + (a * 0x20)))
-// #define     	DMAS_CHx_CTL0(a)    	((volatile unsigned *)(DMAS_BASE + 0x48 + (a * 0x20)))
-// #define     	DMAS_CHx_CTL1(a)    	((volatile unsigned *)(DMAS_BASE + 0x4C + (a * 0x20)))
-// #define     	DMAS_CHx_CA(a)      	((volatile unsigned *)(DMAS_BASE + 0x50 + (a * 0x20)))
-// #define         DMAS_EN                 ((volatile unsigned *)(DMAS_BASE + 0))
-#define DMAS_STA ((volatile unsigned *)(DMAS_BASE + 0x08))
-
-__XIP_RAM_CODE void DMA_Uart(uint8_t ch)
-{
-    __write_hw_reg32(DMAS_CHx_SAR(ch), (uint32_t)DMA_buf);
-    __write_hw_reg32(DMAS_CHx_DAR(ch), (ch * 0x1000 + 0x40010000));
-    __write_hw_reg32(DMAS_CHx_CTL1(ch), ((2 << 8)));
-    __write_hw_reg32(DMAS_CHx_CTL0(ch), 4);
-}
-__XIP_RAM_CODE void DMA_Uart_SendChar(uint8_t ch)
-{
-    __write_hw_reg32(DMAS_CHx_CTL0(ch), 4);
-    while ((*(DMAS_STA)) & (0x01 << ch))
-        ;
-    *(DMAS_EN) = ch;
-}
-
-__XIP_RAM_CODE void DMA_Uart_SendNumChar(uint8_t ch, uint8_t bt)
-{
-    __write_hw_reg32(DMAS_CHx_CTL0(ch), bt);
-    while ((*(DMAS_STA)) & (0x01 << ch))
-        ;
-    *(DMAS_EN) = ch;
-}
-
-/*
-void DMA_Uart_SendChar_1(uint8_t ch)
-{
-   while((*(DMAS_STA))&(0x01<<ch));
-   *(DMAS_EN)=ch;
-}*/

component/boot2/bsp/DMA_uart_debug.h

@@ -1,13 +0,0 @@
-#ifndef _DMA_UART_DEBUG_H_
-#define _DMA_UART_DEBUG_H_
-
-#include "xinc_reg.h"
-
-extern volatile uint8_t __attribute__((aligned(4))) DMA_buf[16];
-void DMA_Uart_SendChar(uint8_t ch);
-#define __XIP_RAM_CODE   __attribute__((section("ram_code")))
-__XIP_RAM_CODE void DMA_Uart_SendNumChar(uint8_t ch,uint8_t bt);
-
-#define DMA_Uart_SendChar_1 DMA_Uart_SendChar
-
-#endif

component/boot2/bsp/Includes.h

@@ -1,34 +0,0 @@
-#ifndef 	__INCLUDES_H
-#define 	__INCLUDES_H
- 
-//#include    "bsp_gpio.h"
-//#include    "bsp_spi_master.h"
-//#include    "bsp_aes128.h"
-//#include    "bsp_uart.h"
-#include    "bsp_xip.h"
-//#include    "bsp_timer.h"
-#include    <stdio.h> 
-//#include    "bsp_calib_rc16m.h"
-//#include    "bsp_i2c_slave.h"
-//#include    "bsp_can.h"
-//#include    "bsp_rtc.h"
-//#include    "bsp_pwm.h"
-//#include    "bsp_gpadc.h"
-#include    "BootSecond.h"
-#include    "xc6xxx.h"
-//#include "bsp_2_4G.h"
-extern unsigned int crc32table[];
-extern void makeCRC32table(unsigned int table[]);
-unsigned int get_crc32(unsigned int crc,unsigned char *data, unsigned int length);
-
-
-#define __RAM_CODE          __attribute__((section("ram_code")))
-	
-//#define     printf(...)             (0)	
- 
-//#define QUAD_ENABLE
-
-//#define TEST_XIP_READ
-//#define TEST_SPI_FLASH
-#endif
-

component/boot2/bsp/bsp_2_4G.c

@@ -1,712 +0,0 @@
-/*----------------------------------------------------------------------------------------------------
-    INCLUDE HEADE FILES
-----------------------------------------------------------------------------------------------------*/
-
-#include "Includes.h"
-#include "bsp_2_4G.h"
-
-#define AON_RF_AONREG ((volatile unsigned *)0x40002430)
-
-#define RF_ANA02 ((volatile unsigned *)(0X4002F000 + 0x008))
-#define RF_ANA03 ((volatile unsigned *)(0X4002F000 + 0x00C))
-#define RF_ANA08 ((volatile unsigned *)(0X4002F000 + 0x020))
-#define RF_ANA15 ((volatile unsigned *)(0X4002F000 + 0x03C))
-#define RF_ANA21 ((volatile unsigned *)(0X4002F000 + 0x054))
-#define RF_ANA26 ((volatile unsigned *)(0X4002F000 + 0x068))
-#define RF_ANA27 ((volatile unsigned *)(0X4002F000 + 0x06C))
-#define RF_ANA28 ((volatile unsigned *)(0X4002F000 + 0x070))
-#define RF_ANA29 ((volatile unsigned *)(0X4002F000 + 0x074))
-
-#define BT_RF_CTRL_SEL ((volatile unsigned *)(0X4002F000 + 0x0B8))
-#define CPR_RF_REG0 ((volatile unsigned *)(0x40000000 + 0x1B0))
-#define CPR_RF_REG1 ((volatile unsigned *)(0x40000000 + 0x1B4))
-
-void delay_cn(uint32_t cn)
-{
-    while (cn--)
-        __NOP();
-}
-
-/*! ********************************************************
- * @name    wbit
- * @desc    wbit
- * *********************************************************/
-static void wbit(uint16_t reg_addr, int end, int start, char *bit_str)
-{
-    uint16_t reg_val = 0;
-    char ch = 0;
-    uint16_t i = 0;
-    uint16_t s_len = 0;
-    while (*(bit_str + s_len))
-        s_len++;
-    if (s_len != (end - start + 1))
-        while (1)
-            ;
-    reg_val = *(uint16_t *)(0X4002F000 + reg_addr);
-    for (i = start; i <= end; i++)
-    {
-        int bit_idx = i - start;
-        ch = bit_str[(end - start) - bit_idx] - '0';
-        if (ch == 1)
-            setbit(reg_val, i);
-        else if (ch == 0)
-            clrbit(reg_val, i);
-    }
-    *(uint16_t *)(0X4002F000 + reg_addr) = reg_val;
-}
-/*! ********************************************************
- * @name    wbit
- * @desc    wbit
- * *********************************************************/
-static uint16_t rbit(uint16_t reg_addr)
-{
-    return *(uint16_t *)(0X4002F000 + reg_addr);
-}
-
-/*! ********************************************************
- * @name    rf_rccali
- * @desc    rf rc filter calib
- * *********************************************************/
-void rf_rccalib(void)
-{
-    static uint8_t rccalib_flag = 0;
-    if (rccalib_flag)
-        return;
-    uint32_t timeout = 0;
-    uint16_t val = 0;
-    wbit(0x0080, 10, 8, "111"); // RG_RCCAL_CTRL(Rccal 输出码值控制) def"100"
-    wbit(0x0080, 5, 5, "1");    // RG_RCCAL_RESETN=1
-    wbit(0x0080, 3, 3, "0");    // RG_RCCAL_SEL =0
-    wbit(0x0080, 2, 2, "1");    // RG_RCCAL_EN=1
-    wbit(0x0080, 4, 4, "1");    // RG_RCCAL_START=1
-    while (!(rbit(0x0084) & 0x8000))
-    { // 等待AD_RCCAL_FINISH拉高 得出校准值 AD_RCCAL_CTRIM
-        if ((timeout++) > 0x10000)
-            break;
-    }
-    val = rbit(0x0084);
-    val = (val & 0x7FFF) >> 10; // 将校准值AD_RCCAL_CTRIM保存
-    wbit(0x0080, 3, 3, "1");    // RG_RCCAL_SEL =1
-    wbit(0x0080, 2, 2, "0");    // RG_RCCAL_EN=0
-    wbit(0x0080, 4, 4, "0");    // RG_RCCAL_START=0
-    char tb[6] = {0};           // 将保存的校准值转换成字符串
-    tb[4] = ((val & 0x01) ? '1' : '0');
-    tb[3] = ((val & 0x02) ? '1' : '0');
-    tb[2] = ((val & 0x04) ? '1' : '0');
-    tb[1] = ((val & 0x08) ? '1' : '0');
-    tb[0] = ((val & 0x10) ? '1' : '0');
-    wbit(0x0080, 15, 11, tb);
-    rccalib_flag = 1;
-    //  printf("\nRG_RCCAL_CC:%X \n",rbit(0x80));
-}
-/*! ********************************************************
- * @name    reset_2_4g_modem
- * @desc    reset 2.4g modem
- * *********************************************************/
-void reset_2_4g_modem(void)
-{
-    *CPR_RF_REG1 &= (~(1 << 21)); // reset
-    delay_cn(200);
-    *CPR_RF_REG1 |= (1 << 21); // unreset
-    delay_cn(200);
-}
-/*! ********************************************************
- * @name    _Ctune_Set
- * @desc   frequency offset tune
- * *********************************************************/
-void freq_tune(uint8_t tu)
-{
-    *AON_RF_AONREG = (*AON_RF_AONREG & (~(0x3f << 20))) | ((tu & 0x3f) << 20); //- frequency offset
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void config_2_4g_rf(void)
-{
-
-//    uint32_t val;
-//    *((uint32_t volatile*)0x40000070) = 0x4000400;		       //- bt_pclk
-//    *((uint32_t volatile*)0x40002450)|= 0x1;                   //- open rf digital
-//
-// freq_tune(0x36);                                           //- frequency offset
-#if 1
-    *BT_RF_CTRL_SEL |= 0xE000; //- sel_24G_rfchan sel_24G_rfldoen sel_24G_rampout use 2.4G signal
-    /*2.4 ack
-      ana8<9:6>  0001  to  0000
-      ana15<3:1> 010   to  100
-      ana21<5:2> 1000  to  1011
-      ana2<12> 1 to 0
-    */
-
-    *RF_ANA08 = *RF_ANA08 & (~0x3C0);
-    *RF_ANA15 = (*RF_ANA15 & (~0xE)) | 0x8;
-    *RF_ANA21 = (*RF_ANA21 & (~0x3c)) | 0x2c;
-    *RF_ANA02 &= (~0x1000);
-#if _24G_CLK_SOURCE == CLK_BBPLL64M
-    // bbpll 64M
-    *RF_ANA26 |= 0xF000;
-    *RF_ANA27 |= 0x02;
-    *RF_ANA26 = (*RF_ANA26 & (~0x3F)) | 0x04;
-#elif _24G_CLK_SOURCE == CLK_BBPLL96M
-    // bbpll 96M
-    *RF_ANA26 |= 0xF000;
-    *RF_ANA27 |= 0x02;
-    *RF_ANA26 = (*RF_ANA26 & (~0x3F)) | 0x06;
-#endif
-
-#if (TRANS_RATE == RATE_1M)
-    *RF_ANA21 = (*RF_ANA21 & (0xFFFF8FFF)) | 0x3000; //- tx dac gc def110  Optimization
-#elif (TRANS_RATE == RATE_2M)
-    *RF_ANA21 = (*RF_ANA21 & (0xFFFF8FFF)) | 0x2000;       //- tx dac gc def110  Optimization
-#else
-    *RF_ANA21 = (*RF_ANA21 & (0xFFFF8FFF)) | 0x6000; //- tx dac gc def110  Optimization
-#endif
-
-#if (TRANS_RATE == RATE_2M)
-    *RF_ANA03 |= 0x01;
-#endif
-
-    *RF_ANA29 |= 0x02; //- manual afc
-    *RF_ANA28 |= 0x01; //- afc pulse
-
-    reset_2_4g_modem();
-#if _24G_CLK_SOURCE == CLK_BBPLL64M
-    *CPR_RF_REG1 = (*CPR_RF_REG1 & 0xFFFF3F0F) | 0x00C030; // enable 2.4G_mclk 2.4G_hclk  4div
-                                                           //*CPR_RF_REG1 =(*CPR_RF_REG1&0xFFFF3F0F)|0x00C070;//enable 2.4G_mclk 2.4G_hclk  8div
-#elif _24G_CLK_SOURCE == CLK_BBPLL96M
-    *CPR_RF_REG1 = (*CPR_RF_REG1 & 0xFFFF3F0F) | 0x00C050; // enable 2.4G_mclk 2.4G_hclk  6div
-#endif
-    *CPR_RF_REG0 |= 0x600; // set 2.4G agc and iq from 2.4 modem
-#endif
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_power(uint8_t txgm)
-{
-    *RF_ANA21 = (*RF_ANA21 & (~0xfc0)) | ((txgm & 0x3f) << 6);
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_channel(uint16_t channel)
-{
-    printf("%x\n", *RF_CH);
-#if (TRANS_RATE == RATE_2M)
-    *RF_CH = ((*CFG_TOP & 0x01) ? (channel - 2) : channel);
-#else
-    *RF_CH = ((*CFG_TOP & 0x01) ? (channel - 1) : channel);
-#endif
-    printf("%x\n", *RF_CH);
-    delay_cn(200);
-    *RF_ANA28 &= (~0x1); //- afc pulse
-    delay_cn(200);
-    *RF_ANA28 |= 0x1; //- afc pulse
-    delay_cn(200);
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_txaddr(uint32_t txaddr_l, uint32_t txaddr_h)
-{
-    uint32_t val;
-    __write_hw_reg32(TX_ADDR_L, txaddr_l);
-    __read_hw_reg32(TX_ADDR_H, val);
-    __write_hw_reg32(TX_ADDR_H, (txaddr_h & 0xff) | (val & 0xffffff00));
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_pipe0_rxaddr(uint32_t rxaddr_l, uint32_t rxaddr_h)
-{
-    __write_hw_reg32(RX_ADDR_P0_L, rxaddr_l);
-    __write_hw_reg32(RX_ADDR_P0_H, rxaddr_h & 0xff);
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_trx_addr_len(uint8_t len)
-{
-    switch (len)
-    {
-    case 3:
-        __write_hw_reg32(SETUP_AW, 0xa5);
-        break;
-    case 4:
-        __write_hw_reg32(SETUP_AW, 0xaa);
-        break;
-    case 5:
-        __write_hw_reg32(SETUP_AW, 0xaf);
-        break;
-    }
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_rate(uint8_t rate)
-{
-    __write_hw_reg32(SETUP_RF, rate);
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_feature(uint8_t long_pld, uint8_t fec, uint8_t whiten, uint8_t dpl, uint8_t ack_pay)
-{
-    __write_hw_reg32(FEATURE, (long_pld << 5) | (fec << 4) | (whiten << 3) | (dpl << 2) | (ack_pay << 1));
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_mode(uint8_t mode)
-{
-    uint32_t val;
-    __read_hw_reg32(CFG_TOP, val); //
-#if (TRANS_RATE == RATE_2M)
-    __write_hw_reg32(CFG_TOP, (val & (~0x1ffff3)) | (mode & 0x01) | 0x1b8672);
-#else
-    __write_hw_reg32(CFG_TOP, (val & (~0x1ffff3)) | (mode & 0x01) | 0x0b8272);
-#endif
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_crc(uint8_t enable, uint8_t crc_bit)
-{
-    uint32_t val;
-    __read_hw_reg32(CFG_TOP, val); //
-    if (enable)
-    {
-        if (crc_bit == CRC_1BIT)
-        {
-            __write_hw_reg32(CFG_TOP, (val | (~0x0C)) | 0x08);
-        }
-        else
-        {
-            __write_hw_reg32(CFG_TOP, val | 0x0C);
-        }
-    }
-    else
-    {
-        __write_hw_reg32(CFG_TOP, val & (~0x08));
-    }
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_p012345_revlen(uint32_t p0123len, uint32_t p45len)
-{
-    __write_hw_reg32(RX_PW_PX_L, p0123len);
-    __write_hw_reg32(RX_PW_PX_H, p45len);
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_pipe0_revlen(uint8_t p0len)
-{
-    *RX_PW_PX_L = (*RX_PW_PX_L & (~0xff)) | p0len;
-}
-
-void set_retry_cnt(uint8_t cnt)
-{
-    *SETUP_RETR = (*SETUP_RETR & (~0x0f)) | cnt;
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void send_cmd(uint8_t cmd)
-{
-    nop();
-    __write_hw_reg32(CMD_BYTE, cmd | CMD_DONE);
-    nop();
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void XC_AckPayload(uint8_t *txbuf, uint8_t len)
-{
-    send_cmd(FLUSH_TX);
-    if (!((*STATUS_FIFO) & TX_FULL)) // tx FIFO is not full
-    {
-        send_cmd(W_ACK_PLOAD);
-        for (int i = 0; i < len; i++)
-        {
-            *TXFIFO_WDATA = txbuf[i];
-            nop();
-        }
-    }
-}
-void XC_TxPacket(uint8_t *txbuf, uint8_t len) // r
-{
-
-    send_cmd(FLUSH_TX);
-    __write_hw_reg32(STATUS, ALL_IRQ_STATUS);
-    if (!((*STATUS_FIFO) & TX_FULL)) // tx FIFO is not full
-    {
-        send_cmd(W_TX_PLOAD);
-
-        for (int i = 0; i < len; i++)
-        {
-            *TXFIFO_WDATA = txbuf[i];
-            nop();
-        }
-        CE_High;
-        for (int i = 0; i < 0x1000; i++)
-            ; // delay   us
-        CE_Low;
-    }
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-
-uint8_t XC_RxPacket(uint8_t en_ack_pay, uint8_t *ack_pay_buf, uint8_t ack_len, uint8_t *rxbuf) // r
-{
-    static uint8_t cnt = 0x01;
-    uint32_t status = 0, len = 0;
-    __read_hw_reg32(STATUS, status); // read status
-    if ((status & 0x0e) != 0x0e)
-    {
-        send_cmd(R_RX_PL_WID);
-        len = *RXFIFO_LEN & 0xFF; // pipe = (status & 0xe) >> 1;
-        for (int i = 0; i < 4; i++)
-            send_cmd(R_RX_PLOAD);
-        for (int i = 0; i < len; i++)
-            *(rxbuf + i) = *RXFIFO_RDTA;
-        ack_pay_buf[0] = cnt++;
-        switch (rxbuf[2])
-        {
-
-        case 1: // match packet
-            ack_pay_buf[4] = 0x02;
-            ack_pay_buf[5] = STATUS_OK;
-            break;
-        case 3: // bin info packet
-            ack_pay_buf[4] = 0x04;
-            // ack_pay_buf[5]=STATUS_OK;
-            ack_pay_buf[5] = info_24g.DataStatus;
-            break;
-        case 5: // bin packet
-            ack_pay_buf[4] = 0x05;
-            ack_pay_buf[5] = STATUS_OK;
-            break;
-        case 6: // ota result
-            ack_pay_buf[4] = 0x07;
-            ack_pay_buf[5] = info_24g.CheckStatus; // ack_pay_buf[5]=STATUS_OK;
-            break;
-        case 8: // ready
-            ack_pay_buf[4] = 0x09;
-            ack_pay_buf[5] = STATUS_READY;
-            break;
-        default:
-            break;
-        }
-
-        if (en_ack_pay)
-            XC_AckPayload(ack_pay_buf, ack_len); //
-                                                 // if(en_ack_pay) XC_AckPayload(ack_pay_buf,5);//250K payload max 5
-                                                 // if(en_ack_pay) XC_AckPayload(ack_pay_buf,32);//1M payload max 32
-    }
-    __write_hw_reg32(STATUS, ALL_IRQ_STATUS); // clear all status  inter
-    send_cmd(FLUSH_RX);
-    return len;
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void set_dynpd(uint8_t val)
-{
-    __write_hw_reg32(DYNPD, val);
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void go_rx(uint16_t ch)
-{
-    uint8_t tv = *STATUS_FIFO;
-    if (((tv & 0x2) && (tv & 0x0C)))
-    {
-        printf("reset_2_4g_modem\n");
-        reset_2_4g_modem();
-        init_24G(RX_MODE);
-    }
-    else
-    {
-        send_cmd(FLUSH_RX);
-        set_mode(RX_MODE);
-    }
-    set_channel(ch);
-}
-
-void go_tx(uint16_t ch)
-{
-    send_cmd(FLUSH_TX);
-    set_mode(TX_MODE);
-    set_channel(ch);
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-
-uint8_t wait_ack(uint8_t *ack_pay_buf, uint8_t *len, uint32_t timeout)
-{
-    while (timeout--)
-    {
-        if ((*STATUS) & XC_TX_DS)
-        {
-            if (len != NULL)
-                *len = XC_RxPacket(0, NULL, 0, ack_pay_buf);
-            return 1; // rev  ack
-        }
-        if ((*STATUS) & XC_MAX_RT)
-        {
-            return 0; // no rev ack
-        }
-    }
-    return 0; // no rev ack
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void init_adv(uint8_t mode)
-{
-
-    set_txaddr(0x71917d6b, 0);       // tx addr 4byte
-    set_pipe0_rxaddr(0x71917d6b, 0); // rx pipe0 addr 4byte
-    set_trx_addr_len(4);             // set trx addrlen  is 4byte
-
-    set_rate(TRANS_RATE); // set rate
-    set_crc(DIS_CRC, CRC_2BIT);
-    set_feature(EN_LONG_PLD, DIS_FEC, DIS_WHITEN, DIS_DPL, DIS_ACK_PAY);
-    set_pipe0_revlen(BUFF_ADV_LENGTH); // set_p012345_revlen(0x2A2A2A2A,0x2A2A);//pipe0-1-2-3-4-pipe5 payload 42byte
-    set_mode(mode);                    // set tx  or rx
-    set_power(POWER_LEVEL);
-    rf_rccalib(); // Initialization finally performs the calibration rc filter,This function is executed only once internally
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void init_24G(uint8_t mode)
-{
-    // set_retry_cnt(3);//set auto retransmit count
-    set_dynpd(0x3f);                    // enable dynamic payload
-    set_txaddr(0xE7E7C2E6, 0xC2);       // tx addr 5byte
-    set_pipe0_rxaddr(0xE7E7C2E6, 0xC2); // rx pipe0 addr 5byte
-    set_trx_addr_len(5);                // set trx addrlen  is 5byte
-
-    set_rate(TRANS_RATE); // set rate
-    set_crc(EN_CRC, CRC_2BIT);
-    set_feature(DIS_LONG_PLD, EN_FEC, EN_WHITEN, EN_DPL, EN_ACK_PAY);
-    set_pipe0_revlen(BUFF_24G_LENGTH); // set_p012345_revlen(0x20202020,0x2020); //pipe0-1-2-3-4-pipe5 payload 32byte
-    set_mode(mode);                    // set tx  or rx
-    set_power(POWER_LEVEL);
-    rf_rccalib(); // Initialization finally performs the calibration rc filter,This function is executed only once internally
-}
-
-/*******************************adv**********************************/
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-uint8_t reverseBits(uint8_t input)
-{
-    uint8_t i = 0, temp = 0;
-    for (; i < 8; i++)
-    {
-        temp <<= 1;
-        temp = ((input >> i) & 0x01) ? (temp | 0x01) : (temp | 0x00);
-    }
-    return temp;
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-uint8_t bleWhitenStart(uint16_t Fre)
-{
-    uint8_t chan = (Fre == RF_ADV_CHANNELS_38) ? 38 : ((Fre == RF_ADV_CHANNELS_37) ? 37 : 39);
-    return reverseBits(chan) | 2;
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-/*白化，LFSR的方式进行白化*/
-void bleWhiten(uint8_t *data, uint8_t len, uint8_t whitenCoeff)
-{
-    uint8_t m;
-    while (len--)
-    {
-        for (m = 1; m; m <<= 1)
-        {
-            if (whitenCoeff & 0x80)
-            {
-                whitenCoeff ^= 0x11;
-                (*data) ^= m;
-            }
-            whitenCoeff <<= 1;
-        }
-        *data = reverseBits(*data); // 新增 -- 翻转变量
-        data++;
-    }
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author :
- *
- */
-void BLEcrc(const uint8_t *data, uint8_t dataLen, uint8_t *outputCRC)
-{
-    // calculating the CRC based on a LFSR
-    uint8_t i, temp, tempData;
-    while (dataLen--)
-    {
-
-        tempData = *data++;
-        for (i = 0; i < 8; i++, tempData >>= 1)
-        {
-            temp = outputCRC[0] >> 7;
-
-            outputCRC[0] <<= 1;
-            if (outputCRC[1] & 0x80)
-            {
-                outputCRC[0] |= 1;
-            }
-            outputCRC[1] <<= 1;
-            if (outputCRC[2] & 0x80)
-            {
-                outputCRC[1] |= 1;
-            }
-            outputCRC[2] <<= 1;
-
-            if (temp != (tempData & 1))
-            {
-                outputCRC[2] ^= 0x5B;
-                outputCRC[1] ^= 0x06;
-            }
-        }
-    }
-    outputCRC[2] = reverseBits(outputCRC[2]);
-    outputCRC[1] = reverseBits(outputCRC[1]);
-    outputCRC[0] = reverseBits(outputCRC[0]);
-}

component/boot2/bsp/bsp_2_4G.h

@@ -1,237 +0,0 @@
-#ifndef _BSP_2_4_G_H_
-#define _BSP_2_4_G_H_
-#include    "Includes.h"
-
-
-
-
-
-
-#define    _2_4G_BASE           0x50003000 
-#define    CFG_TOP			    ((volatile unsigned *)(_2_4G_BASE	+ 0x00))
-#define	   EN_AA				((volatile unsigned *)(_2_4G_BASE	+ 0x04))
-#define	   EN_RXADDR			((volatile unsigned *)(_2_4G_BASE	+ 0x08)) 
-#define	   SETUP_AW			    ((volatile unsigned *)(_2_4G_BASE	+ 0x0C)) 
-#define	   SETUP_RETR			((volatile unsigned *)(_2_4G_BASE	+ 0x10)) 
-#define	   RF_CH				((volatile unsigned *)(_2_4G_BASE	+ 0x14)) 
-#define	   SETUP_RF			    ((volatile unsigned *)(_2_4G_BASE	+ 0x18)) 
-#define	   STATUS				((volatile unsigned *)(_2_4G_BASE	+ 0x1C)) 
-#define	   OBSERVE_TX		 	((volatile unsigned *)(_2_4G_BASE	+ 0x20)) 
-#define	   RSSI				    ((volatile unsigned *)(_2_4G_BASE	+ 0x24)) 
-#define	   RX_ADDR_P0_L			((volatile unsigned *)(_2_4G_BASE	+ 0x28)) 
-#define	   RX_ADDR_P0_H			((volatile unsigned *)(_2_4G_BASE	+ 0x2C))    
-#define	   RX_ADDR_P1_L			((volatile unsigned *)(_2_4G_BASE	+ 0x30)) 
-#define	   RX_ADDR_P1_H			((volatile unsigned *)(_2_4G_BASE	+ 0x34)) 
-#define	   RX_ADDR_P2TOP5		((volatile unsigned *)(_2_4G_BASE	+ 0x38)) 
-  
-#define	   BER_RESULT_L			((volatile unsigned *)(_2_4G_BASE	+ 0x3C))
-#define	   BER_RESULT_H			((volatile unsigned *)(_2_4G_BASE	+ 0x40)) 
-    
-#define	   AGC_SETTING			((volatile unsigned *)(_2_4G_BASE	+ 0x44)) 
-#define	   PGA_SETTING_L		((volatile unsigned *)(_2_4G_BASE	+ 0x48))   
-#define	   PGA_SETTING_H		((volatile unsigned *)(_2_4G_BASE	+ 0x50)) 
-    
-#define	   TX_ADDR_L			((volatile unsigned *)(_2_4G_BASE	+ 0x4C)) 
-#define	   TX_ADDR_H			((volatile unsigned *)(_2_4G_BASE	+ 0x50))     
-
-#define	   RX_PW_PX_L			((volatile unsigned *)(_2_4G_BASE	+ 0x54)) 
-#define	   RX_PW_PX_H			((volatile unsigned *)(_2_4G_BASE	+ 0x58))    
-    
-#define	   STATUS_FIFO			((volatile unsigned *)(_2_4G_BASE	+ 0x80)) 
-#define	   RSSIREC				((volatile unsigned *)(_2_4G_BASE	+ 0x84)) 
-#define	   TXPROC_CFG			((volatile unsigned *)(_2_4G_BASE	+ 0x88)) 
-#define	   RXPROC_CFG_L			((volatile unsigned *)(_2_4G_BASE	+ 0x8C)) 
-#define	   RXPROC_CFG_H			((volatile unsigned *)(_2_4G_BASE	+ 0xA8)) 
-#define	   DYNPD				((volatile unsigned *)(_2_4G_BASE	+ 0x94)) 
-#define	   FEATURE				((volatile unsigned *)(_2_4G_BASE	+ 0x98))  
-    
-#define	   CMD_BYTE				((volatile unsigned *)(_2_4G_BASE	+ 0xC0))  
-#define	   TXFIFO_WDATA			((volatile unsigned *)(_2_4G_BASE	+ 0xC4))  
-#define	   RXFIFO_RDTA			((volatile unsigned *)(_2_4G_BASE	+ 0xC8))  
-#define    RXFIFO_LEN           ((volatile unsigned *)(_2_4G_BASE	+ 0xCC)) 
-    
-#define    R_REG				0x00 
-#define    W_REG 				0x20 
-#define    R_RX_PLOAD 			0x61 
-#define    W_TX_PLOAD			0xA0 
-#define    FLUSH_TX			    0xE1 
-#define    FLUSH_RX			    0xE2 
-#define    REUSE_TX_PL			0xE3 
-#define    R_RX_PL_WID			0x60 
-#define    W_ACK_PLOAD			0xA8 
-#define    W_TX_PLOAD_NOACK	    0xB0 
-#define    CMD_NOP				0xFF 
-#define    CMD_DONE				0x100 
-
-#define TX_REUSE        		(0x1 << 6) 
-#define TX_FULL            		(0x1 << 5) 
-#define TX_EMPTY        		(0x1 << 4) 
-#define RX_FULL            		(0x2) 
-#define RX_EMPTY        		(0x1) 
-
-/* STATUS Interrupt status */
-#define XC_RX_DR    		(0x1 << 6)//@
-#define XC_TX_DS    		(0x1 << 5)//@
-#define XC_MAX_RT   		(0x1 << 4)//@
-#define ALL_IRQ_STATUS          (0x70)//@
-
-// 
-#define EN_LONG_PLD        1
-#define EN_FEC             1
-#define EN_WHITEN          1
-#define EN_DPL             1
-#define EN_ACK_PAY         1
-
-#define DIS_LONG_PLD        0
-#define DIS_FEC             0
-#define DIS_WHITEN          0
-#define DIS_DPL             0
-#define DIS_ACK_PAY         0
-
-#define EN_CRC              1
-#define DIS_CRC             0
-
-#define CRC_1BIT            1
-#define CRC_2BIT            2
-
-#define setbit_array(x,y) (setbit((x)[(y)/8],(y)%8))
-#define clrbit_array(x,y) (clrbit((x)[(y)/8],(y)%8))
-
-#define    CE_High    *CFG_TOP |=0x4000 
-#define    CE_Low     *CFG_TOP &=(~0x4000)
- 
- 
-#define 	TX_MODE    0x0
-#define     RX_MODE    0x1
-
-
-#define nop()   __NOP();\
-                __NOP();\
-				__NOP();\
-				__NOP()
-
-
-
-
-
-
-extern void send_cmd(uint8_t cmd);
-extern void     BLEcrc(const uint8_t* data, uint8_t dataLen, uint8_t* outputCRC);  
-extern void     bleWhiten(uint8_t* data, uint8_t len, uint8_t whitenCoeff);        
-extern uint8_t  bleWhitenStart(uint16_t Fre);
-extern uint8_t  reverseBits(uint8_t input);
-extern uint8_t XC_RxPacket(uint8_t en_ack_pay,uint8_t *ack_buf,uint8_t ack_len,uint8_t *rxbuf);
-extern void     XC_TxPacket(uint8_t *txbuf, uint8_t len);
-extern void     init_24G(uint8_t mode);
-extern void     init_adv(uint8_t mode);
-extern void     set_channel(uint16_t channel);
-extern void     config_2_4g_rf(void);
-extern void     set_power(uint8_t gc);
-void  set_txaddr(uint32_t txaddr_l,uint32_t txaddr_h);
-void  set_pipe0_rxaddr(uint32_t rxaddr_l,uint32_t rxaddr_h);
-void  set_trx_addr_len(uint8_t len);
-void  set_rate(uint8_t rate);
-void  set_feature(uint8_t long_pld,uint8_t fec,uint8_t whiten,uint8_t dpl,uint8_t ack_pay);
-void  set_mode(uint8_t mode);
-void  set_crc(uint8_t enable,uint8_t crc_bit);
-void  set_p012345_revlen(uint32_t p0123len,uint32_t p45len);
-void  set_pipe0_revlen(uint8_t p0len);
-void  rf_rccalib(void);
-void  go_tx(uint16_t ch);
-void  go_rx(uint16_t ch);
-void  rx_24g_ota(void);
-
-uint8_t wait_ack(uint8_t *ack_pay_buf,uint8_t *len,uint32_t timeout);
-
-void  set_retry_cnt(uint8_t ch);
-
-/////////////////////////////////////////////////////////
-#define CLK_BBPLL64M        0
-#define CLK_BBPLL96M        1
-#define  _24G_CLK_SOURCE    CLK_BBPLL96M
-///////////////////////////////////////////////////////// 
- 
-#define BUFF_ADV_LENGTH 15
-#define BUFF_24G_LENGTH 32
-#define BUFF_24G_ACK_PAY_LENGTH 7
-
-/////////////////////////////////////////////////////////
-#define RF_ADV_CHANNELS_37    2402
-#define RF_ADV_CHANNELS_38    2426
-#define RF_ADV_CHANNELS_39    2480
-#define RF_ADV_CHANNELS       RF_ADV_CHANNELS_38
-
-#define CHANNEL_24G        2402
-
-/////////////////////////////////////////////////////////
-#define RATE_2M            0x0A
-#define RATE_1M            0x02
-#define RATE_250K          0x22   
-#define RATE_125K          0x2A 
-
-//#define TRANS_RATE         RATE_250K 
-//#define TRANS_RATE         RATE_1M 
-#define TRANS_RATE         RATE_1M  //RATE_250K RATE_125K RATE_1M 
-/////////////////////////////////////////////////////////
-#define POWER_LEVEL        0x10 /////tip:1M Max Power 0x2c(6.8dbm)  
-/////////////////////////////////////////////////////////
-//#define  USE_24G_IRQ
-/////////////////////////////////////////////////////////
-#define  ACK_TOMEOUT       0x10000    //4550
-/////////////////////////////////////////////////////////
-#define TEST_SINGLE       0
-#define TEST_24G          1
-#define TEST_ADV          0
-#define TEST_SWITCH_24G   0
-/////////////////////////////////////////////////////////
-
-
-
-#define DEBUG1
-//#define DEBUG2
-
-
-
-
-#define FLASH_BIN_ADDR_OFFSET    (0x3000)
-#define PACKET_LENGTH            (29) 
-enum{
- 
-    STATUS_OK=0,
-	STATUS_FAIL=1,
-    STATUS_BUSY=2,
-    STATUS_READY=3,
-};
-enum{
-    rFALSE=0,//false
-	rTRUE=1, //true
-};
-typedef struct{
-    
-	uint32_t SoftVer;/**/
-	uint32_t RomVer;
-	uint32_t Len;/*file len*/
-	uint32_t CRC32;/*crc32*/
-	
-	uint32_t PacketNum;
-	uint32_t cPacketNo;
-	
-	uint32_t Channel;
-	
-	uint32_t AddrH;
-	uint32_t AddrL;
-	
-	uint32_t FrameNum;
-	uint32_t cFrameNo;
-	
-	uint32_t WriteAddr;
-	
-	uint32_t DataStatus:8;
-    uint32_t CheckStatus:8; 
-    uint32_t RevComplete:8;
-    uint32_t ResStatus1:8;	
-}INFO_24G;
-extern volatile INFO_24G info_24g;
-
-
-#endif

component/boot2/bsp/bsp_aes128.c

@@ -1,56 +0,0 @@
-
-#include	"Includes.h"
-
-
-
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: aes128_init
-- 函数功能: aes128运算初始化
-- 输入参数: 16个字节的秘钥
-- 创建日期: 2019-12-12
-----------------------------------------------------------------------------------------------------*/
-void aes128_init(uint8_t *aes_key)
-{
-    //__write_hw_reg32(AES_INTE,1);   //使能aes中断
-    __write_hw_reg32(AES_CTL,2);    //标准aes算法，AES 分组数据输入方式控制（CPU 方式）
-    __write_hw_reg32(AES_KEY_LEN,0);//0:128bits秘钥 1:192bits秘钥 2:256bits秘钥
-    //写入aes秘钥
-    __write_hw_reg32(AES_KEY0,(aes_key[0] )|(aes_key[1] <<8)|(aes_key[2] <<16)|(aes_key[3] <<24));
-    __write_hw_reg32(AES_KEY1,(aes_key[4] )|(aes_key[5] <<8)|(aes_key[6] <<16)|(aes_key[7] <<24));
-    __write_hw_reg32(AES_KEY2,(aes_key[8] )|(aes_key[9] <<8)|(aes_key[10]<<16)|(aes_key[11]<<24));
-    __write_hw_reg32(AES_KEY3,(aes_key[12])|(aes_key[13]<<8)|(aes_key[14]<<16)|(aes_key[15]<<24));
-    __write_hw_reg32(AES_KEY_UPDATE,1);    //AES 密钥更新
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: aes128_operation
-- 函数功能: aes128加密解密运算
-- 输入参数: type:0代表解密 1代表加密 source_data:aes运算前的数据 aes_data:aes运算后的数据
-- 创建日期: 2019-04-02 
-----------------------------------------------------------------------------------------------------*/
-void aes128_operation(uint8_t type,uint8_t *source_data,uint8_t *aes_data)
-{
-    if(type==1)__write_hw_reg32(AES_CTL,6);//加密
-    else __write_hw_reg32(AES_CTL,2);      //解密
-    
-    //写入源数据
-    __write_hw_reg32(AES_IN0,(source_data[0] )|(source_data[1] <<8)|(source_data[2] <<16)|(source_data[3] <<24));
-    __write_hw_reg32(AES_IN1,(source_data[4] )|(source_data[5] <<8)|(source_data[6] <<16)|(source_data[7] <<24));
-    __write_hw_reg32(AES_IN2,(source_data[8] )|(source_data[9] <<8)|(source_data[10]<<16)|(source_data[11]<<24));
-    __write_hw_reg32(AES_IN3,(source_data[12])|(source_data[13]<<8)|(source_data[14]<<16)|(source_data[15]<<24));
-    
-    __write_hw_reg32(AES_START,1);//开始aes运算
-    while((!(*AES_INTR)));        //读中断原始状态寄存器,判读aes运算是否完成
-    __write_hw_reg32(AES_INTS,1); //清除中断状态寄存器和中断原始状态寄存器
-    //读出aes运算后的数据
-    uint32_t temp=*AES_OUT0;
-    aes_data[0]=temp;   aes_data[1]=temp>>8;  aes_data[2]=temp>>16;  aes_data[3]=temp>>24;
-    temp=*AES_OUT1;                                                 
-    aes_data[4]=temp;   aes_data[5]=temp>>8;  aes_data[6]=temp>>16;  aes_data[7]=temp>>24;
-    temp=*AES_OUT2;                                                 
-    aes_data[8]=temp;   aes_data[9]=temp>>8; aes_data[10]=temp>>16; aes_data[11]=temp>>24;
-    temp=*AES_OUT3;                                                 
-    aes_data[12]=temp; aes_data[13]=temp>>8; aes_data[14]=temp>>16; aes_data[15]=temp>>24;
-}
-

component/boot2/bsp/bsp_aes128.h

@@ -1,10 +0,0 @@
-#ifndef _BSP_AES128_H_
-#define _BSP_AES128_H_
-
-
-
-void aes128_init(uint8_t *aes_key);
-void aes128_operation(uint8_t type,uint8_t *source_data,uint8_t *aes_data);
-
-
-#endif

component/boot2/bsp/bsp_calib_rc16m.c

@@ -1,232 +0,0 @@
-
-
-#include    "Includes.h"
-
-
-
-
-#define PULSE_DET_PIN 4                  //采样脚（对方通过pwm向此脚灌入百分之五十占空比的方波）
-#define CALIB_TIMES   2                  //校准2次
-#define CYCLE_TIMES   3                  //循环次数 3次--
-#define COLLECT_NUM  ((CYCLE_TIMES*2)-1) //循环3次有六个采样点 可以得到五个采样值
-#define TIMER_REFER   3                  //选择的timer3作为计数参考
-#define GEAR_HZ       71160.0            //总共128个档位 每个步长调节71160HZ的频率
-#define RC16M_COEFFI  400                //rc16M 实际频率的计算系数：(1000ms/5ms)*2
-#define RC16M_STD     16000000.0         //rc16M 
-void timer_cnt(uint8_t ch)//8 cycle is 1us
-{
-	__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL,0x80008); //TIMER_PCLK 时钟使能
-	__write_hw_reg32(CPR_TIMER_CLK_CTL(ch),0x00);    //TIMERx_CLK 时钟控制寄存器 mclk_in(rc16M)/(2*(0x00 + 0x1))=8M
-	__write_hw_reg32(TIMERx_TCR(ch),0x0);            //不屏蔽定时器中断，不使能定时器timer_num，
-	__write_hw_reg32(TIMERx_TCR(ch),0x2);            //设置定时器工作在用户定义计数模式
-	__write_hw_reg32(TIMERx_TLC(ch),0xffffffff);     //载入计数器计数初值(32bits),该值应大于等于 0x4
-    __write_hw_reg32(TIMERx_TCR(ch),0x3);            //使能定时器timer_num
-	
-}
-
-
-void BubbleSort(uint32_t *arr,uint32_t length)
-{
-		for(int i=0;i<length-1;i++){ 
-			for(int j=0;j<length-1-i;j++){
-				if(arr[j]>arr[j+1]){ //相邻两个元素作比较，如果前面元素大于后面，进行交换
-					uint32_t temp = arr[j+1];
-					arr[j+1] = arr[j];
-					arr[j] = temp;
-				}
-			}
-		}
-}
-uint32_t get_average(uint32_t *p,uint32_t len)
-{
-	uint32_t sum=0;
-    BubbleSort(p,len);
-	for(int i=0;i<len-2;i++)
-	{
-	   sum+=p[i+1];
-	}
-    return sum/(len-2);
-}
-
-
-void calib_rc16m_step(void)
-{
-    float freq_hz;
-	uint32_t t1,t2;
-    uint32_t rc16m_buf[CYCLE_TIMES*2];
-	uint32_t collect_buf[COLLECT_NUM];
-    for(int i=0,j=0;i<CYCLE_TIMES;i++)
-	{
-		while(gpio_input_val(PULSE_DET_PIN)==0);
-		rc16m_buf[j++]= *TIMERx_TCV(TIMER_REFER);
-		while(gpio_input_val(PULSE_DET_PIN)==1);
-		rc16m_buf[j++]= *TIMERx_TCV(TIMER_REFER);
-	}
-	for(int i=0;i<COLLECT_NUM;i++)
-	  collect_buf[i]=rc16m_buf[i]-rc16m_buf[i+1];
-	freq_hz=RC16M_COEFFI*get_average(collect_buf+1,COLLECT_NUM-1);
-	
-	if(freq_hz>RC16M_STD){
-		float tv=(freq_hz - RC16M_STD)/GEAR_HZ;
-		uint32_t t1=(((uint32_t)(tv*100))%100)>50 ? 1:0 ;
-	    CPR_RF_REG0->rc16m_rtune -= (t1+((uint32_t)tv));
-	}else if(freq_hz<RC16M_STD){
-	    float tv=(RC16M_STD-freq_hz)/GEAR_HZ;
-		uint32_t t1=(((uint32_t)(tv*100))%100)>50 ? 1:0 ;
-	    CPR_RF_REG0->rc16m_rtune += (t1+((uint32_t)tv));
-	}
-
-
-}
-void calib_rc16m(void)
-{
-	//[00-OSC32M],[01-bbpll direct output],[10-bbpll div output],[11-rc16M]   
-	*((volatile unsigned *)(0x40000000+ 0x130)) |=0x06;  //select clk source rc16M
-	
-	//config  pin
-	gpio_mux_ctl(PULSE_DET_PIN,0); gpio_fun_inter(PULSE_DET_PIN,0);
-	gpio_fun_sel(PULSE_DET_PIN,0); gpio_direction_input(PULSE_DET_PIN,1);//50HZ(10ms) 
-    __write_hw_reg32((GPIO_DEBOUNCE0+(PULSE_DET_PIN>>4)),((0x10000)<<(PULSE_DET_PIN&0x0F)));	//disable debounce
-  //CPR_RF_REG0->rc16m_rtune=0x3f;//set rc16m rtune  default 0x3f  (0-0x7f)
-
-	//calib start
-	timer_cnt(TIMER_REFER);//timer cnt,8 cycle is 1us
-	for(int i=0;i<CALIB_TIMES;i++) calib_rc16m_step();//calib 2 timrs , 60ms
-	//save calib val to 62 sector  offset 32byte
-	 
-	
-	//[00-OSC32M],[01-bbpll direct output],[10-bbpll div output],[11-rc16M]   
-	*((volatile unsigned *)(0x40000000+ 0x130)) &=~0x06;   //select clk source OSC32M
-	printf("CPR_RF_REG0->rc16m_rtune=0x%X\n",CPR_RF_REG0->rc16m_rtune);
-}
-
-
-
-
- 
-
-
-#if 0
-
-uint32_t rc16m_buf[50];
-void calib_rc16m(void)
-{
-#if 0
-	uint32_t t1,t2;
-    *((volatile unsigned *)(0x40000000+ 0x130)) |=0x06;      //[00-OSC32M],[01-bbpll direct output],[10-bbpll div output],[11-rc16M]                                                    //115200
-
- 	CPR_RF_REG0->rc16m_rtune=0x7E;//set rc16m rtune
-    gpio_mux_ctl(7,0);gpio_fun_inter(7,0);gpio_fun_sel(7,0); gpio_direction_input(7,1);
-    __write_hw_reg32(GPIO_DEBOUNCE0,0xffff0000);	
-
-	xc_timer_init(0,4000000);
-	uint8_t timers=50;
-	while(gpio_input_val(7)==0);
-	while(gpio_input_val(7)==1);
-	while(timers--)
-	{
-		while(gpio_input_val(7)==0);
-		t1=*TIMERx_TCV(0);
-		while(gpio_input_val(7)==1);
-		t2=*TIMERx_TCV(0);
-		rc16m_buf[timers]=t1-t2;
-		//printf("%d\n",t1-t2);
-        while(gpio_input_val(7)==0);
-		while(gpio_input_val(7)==1);
-	}
-	*((volatile unsigned *)(0x40000000+ 0x130)) &=~0x06; 
-	printf("****\n");
-	for(int i=0;i<50;i++) printf("%d\n",rc16m_buf[i]); 
-	while(1);
-#endif
-#if 0
-	uint32_t t1,t2;
-    //*((volatile unsigned *)(0x40000000+ 0x130)) |=0x06;      //[00-OSC32M],[01-bbpll direct output],[10-bbpll div output],[11-rc16M]                                                    //115200
-    SET_RC16M_BBPLL_32M();
- 	CPR_RF_REG0->rc16m_rtune=0xf0;//set rc16m rtune
-    gpio_mux_ctl(7,0);gpio_fun_inter(7,0);gpio_fun_sel(7,0); gpio_direction_input(7,1);
-    __write_hw_reg32(GPIO_DEBOUNCE0,0xffff0000);	
-
-	xc_timer_init(0,4000000);
-	uint8_t timers=50;
-	while(gpio_input_val(7)==0);
-	while(gpio_input_val(7)==1);
-	while(timers--)
-	{
-		while(gpio_input_val(7)==0);
-		t1=*TIMERx_TCV(0);
-		while(gpio_input_val(7)==1);
-		t2=*TIMERx_TCV(0);
-		rc16m_buf[timers]=t1-t2;
-		//printf("%d\n",t1-t2);
-        while(gpio_input_val(7)==0);
-		while(gpio_input_val(7)==1);
-	}
-	*((volatile unsigned *)(0x40000000+ 0x130)) &=~0x06; 
-	printf("****\n");
-	for(int i=0;i<50;i++) printf("%d\n",rc16m_buf[i]); 
-	while(1);
-#endif
-}
-
-void test_drift_rc16m(void)
-{
-
-	
-}
-
-
-void test_linear_rc16m(void)
-{
-
-	
-}
-
-void test_calib_rc16m(void)
-{
-  calib_rc16m();
-//gpio_output_high(26);
-//gpio_output_low(26);
-//	//3.19ms
-//    calib_init();
-//	rc32k_calib(3);
-//gpio_output_high(26);
-//gpio_output_low(26);
-#if 0	
-	SET_RC16M_BBPLL_32M();
-  //CPR_RF_REG0->rc16m_rtune=0x00;//set rc16m rtune  uart-89847-bps   415047
-  //CPR_RF_REG0->rc16m_rtune=0x20;//set rc16m rtune  uart-100401-bps  464796
-  //CPR_RF_REG0->rc16m_rtune=0x40;//set rc16m rtune  uart-107032-bps  530170
-  //CPR_RF_REG0->rc16m_rtune=0x60;//set rc16m rtune  uart-134048-bps  619766
-  //CPR_RF_REG0->rc16m_rtune=0x80;//set rc16m rtune  uart-107101-bps  534492
-  //CPR_RF_REG0->rc16m_rtune=0xa0;//set rc16m rtune  uart-134124-bps  618613
-//  CPR_RF_REG0->rc16m_rtune=0xc0;//set rc16m rtune  uart-161290-bps  744983
-//    CPR_RF_REG0->rc16m_rtune=0xE0;//set rc16m rtune  uart-202839-bps  930793
-//  CPR_RF_REG0->rc16m_rtune=0xff;//set rc16m rtune  uart-134048-bps  618332
-	CPR_RF_REG0->rc16m_rtune=0xf0;//set rc16m rtune  uart-231481-bps  1069864
-#endif	
-#if 0	
-
-  *((volatile unsigned *)(0x40000000+ 0x130)) |=0x06;      //[00-OSC32M],[01-bbpll direct output],[10-bbpll div output],[11-rc16M]                                                    //115200
-  CPR_RF_REG0->rc16m_rtune=0x00;//set rc16m rtune  uart-45004-bps  207574
-//  CPR_RF_REG0->rc16m_rtune=0x20;//set rc16m rtune  uart-50479-bps   233145
-//  CPR_RF_REG0->rc16m_rtune=0x40;//set rc16m rtune  uart-57570-bps   266167
-//  CPR_RF_REG0->rc16m_rtune=0x60;//set rc16m rtune  uart-67114-bps   309918
-//  CPR_RF_REG0->rc16m_rtune=0x80;//set rc16m rtune  uart-57670-bps   266128
-//  CPR_RF_REG0->rc16m_rtune=0xa0;//set rc16m rtune  uart-66979-bps   309810
-//  CPR_RF_REG0->rc16m_rtune=0xc0;//set rc16m rtune  uart-80645-bps   371919
-//  CPR_RF_REG0->rc16m_rtune=0xE0;//set rc16m rtune  uart-100704-bps  465464
-//  CPR_RF_REG0->rc16m_rtune=0xff;//set rc16m rtune  uart-134048-bps  618221
-
-//	*((volatile unsigned *)(0x40002400 + 0x20))  =0x44;
-//	*((volatile unsigned *)(0x40002400 + 0x48))  =0x01;	
-	
-#endif	
-	 xc_ao_timer_calib_test();
-	
-	
-
-
-}
-
-#endif

component/boot2/bsp/bsp_calib_rc16m.h

@@ -1,37 +0,0 @@
-#ifndef _BSP_CALIB_RC16M_H_
-#define _BSP_CALIB_RC16M_H_
-
- 
-  
-typedef struct
-{
-	uint32_t USB_RET1N:1;
-	uint32_t AES_RET1N:1;
-	uint32_t NA2:1;
-	uint32_t NA3:1;
-	uint32_t BB_PLL1_64M_EN:1;
-	uint32_t BB_PLL2_480M_EN:1;
-	uint32_t BB_WB_SEL:1;
-	uint32_t BB_WFRX_MODE_SEL:1;
-	uint32_t BB_BT_AGC_MODE:1;
-	uint32_t sel_24g_iq_hwpin:1;
-	uint32_t sel_24g_agc:1;
-	uint32_t usbphy_debug:1;
-	uint32_t rom_pd:1;
-	uint32_t rom_ls:1;
-	uint32_t rf24g_hwagc_en:1;
-	uint32_t rf24g_dac_sample_edge:1;
-	uint32_t rc16m_en_soft:1;
-	uint32_t rc16m_ctune:2;
-	uint32_t NA19:1;
-	uint32_t rc16m_rtune:8;
-	uint32_t boot_done:1;
-	uint32_t rc16m_disalbe:1;
-	uint32_t RESERVED:2;
-}CPR_RF_REG0_T;
-
-
-
-
-
-#endif

component/boot2/bsp/bsp_calib_rc32k.c

@@ -1,305 +0,0 @@
-
-#include    "Includes.h"
-
-
-#if 1
-
-//#define printf(...) (0)
- 
-
-typedef struct
-{
-	uint32_t AO_TIMER_VALUE:16;
-	uint32_t AO_TIMER_CLR:1;
-	uint32_t AO_TIMER_EN:1;
-	uint32_t FREQ_TIMER_EN:1;
-	uint32_t RESERVED:13;
-}AO_TIMER_CTL_T;
-
-static AO_TIMER_CTL_T* ao_timer_ctl = (AO_TIMER_CTL_T*)AO_TIMER_CTL;
-
-
-
-/*
-3fff  3044 --50K 
-2fff  4132 --39K
-1fff  5229 --31K
-0fff  6326 --25K
-*/
-#define MAX_LPO_RTM       0x3fff
-#define MIN_LPO_RTM       0x0
-#define MID_LPO_RTM       0x1fff
-#define RANGE_LPO_RTM     0x400
-#define GEARS_HZ          1.56
-#define _32K_STAND_HZ     32000
-
-#define CALIB_STEP_CYCLE_32K  32      //#define CALIB_STEP_CYCLE_32K  10
-#define COUNT_16M             16000   //#define COUNT_16M  5000
-static void LPO_RTM_SET(uint16_t val)
-{
-	*((volatile unsigned *)0x40002084)=0x1fff4000|val;      //*((volatile unsigned *)0x40002084)=0x1fff4000|0x22C0;	  //printf("LPO_RTM:%08x\n",*((volatile unsigned *)0x40002084));
-}
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : 
- *
- */
-static uint8_t  calib_step(uint32_t _cycle_32k,uint32_t *FREQ_VAL)  
-{
-    uint32_t tsd;
-	ao_timer_ctl->AO_TIMER_VALUE = _cycle_32k;//32 cycle == 1ms
-	ao_timer_ctl->AO_TIMER_EN = 0;
-	ao_timer_ctl->AO_TIMER_CLR = 0; //中断使用在timer 使能之前
-	ao_timer_ctl->FREQ_TIMER_EN = 1;
-	do{
-        __read_hw_reg32(AO_ALL_INTR, tsd);
-    }while((tsd&0x20)==0);
-	__read_hw_reg32(FREQ_TIMER_VAL, *FREQ_VAL);//
-	ao_timer_ctl->AO_TIMER_CLR = 1; // rtc 必须清理中断	
-	ao_timer_ctl->FREQ_TIMER_EN = 0;
-	if(*FREQ_VAL==COUNT_16M) return 0;
-	return ((*FREQ_VAL<COUNT_16M)? 1:2);
-} 
-
-
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Describe : init  calib clk
- *
- */
-static volatile uint32_t mid=MID_LPO_RTM;
-void calib_init(void)
-{
-	//config clk
-	__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x00020002);
-	__write_hw_reg32(CPR_AOCLKEN_GRCTL,0x00020002);
-
-    LPO_RTM_SET(mid);
-}
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Describe : "linear regression" calibration
- *
- */
-void  rc32k_calib(uint16_t cts)
-{
-	uint32_t tsd,frac;
-	while(cts--)
-	{
-		__disable_irq();
-		calib_step(CALIB_STEP_CYCLE_32K,&tsd);
-		__enable_irq();
-        printf("FREQ_TIMER_VAL:%d\n",tsd);
-		
-		frac=(uint32_t)((((float)((16.0)*CALIB_STEP_CYCLE_32K))/tsd)*1000000);
-		if(frac > _32K_STAND_HZ)
-		{
-			mid=mid-((uint32_t)(((float)(frac-_32K_STAND_HZ))/GEARS_HZ));
-		}
-		else if(frac < _32K_STAND_HZ)
-		{
-			mid=mid+((uint32_t)(((float)(_32K_STAND_HZ-frac))/GEARS_HZ));
-		}
-		LPO_RTM_SET(mid);
-
-	}
-    printf("@@LPO_RTM_SET:0x%08x\n",mid);
-
-	
-}
-
-
-
-#else
-
-//////////////////////////校准三次 每次校准用的时间如下//////////////////////////
-//低电压下
-//*((volatile unsigned *)(0x40002400 + 0x20))  =0x44;
-//*((volatile unsigned *)(0x40002400 + 0x48))  =0x01;
-//@@LPO_RTM_SET:0x00002704    32       //1ms校准一次    
-//@@LPO_RTM_SET:0x00002709    32*5     //5ms校准一次  
-//@@LPO_RTM_SET:0x0000270b    320*2    //20ms校准一次  
-//@@LPO_RTM_SET:0x00002708    320*4    //40ms校准一次  
-//@@LPO_RTM_SET:0x00002706    320*6    //60ms校准一次 
-//@@LPO_RTM_SET:0x0000270a    320*8    //80ms校准一次 
-
-//@@LPO_RTM_SET:0x00002706    3200     //100ms校准一次 
-//@@LPO_RTM_SET:0x00002705    3200*2   //200ms校准一次 
-//@@LPO_RTM_SET:0x00002708    3200*3   //300ms校准一次 
-//@@LPO_RTM_SET:0x00002705    3200*4   //400ms校准一次 
-//@@LPO_RTM_SET:0x00002705    3200*5   //400ms校准一次 
-//@@LPO_RTM_SET:0x0000270a    3200*6   //600ms校准一次 
-//@@LPO_RTM_SET:0x00002708    3200*7   //700ms校准一次 
-//@@LPO_RTM_SET:0x00002708    3200*8   //800ms校准一次 
-//@@LPO_RTM_SET:0x00002707    3200*9   //900ms校准一次 
-
-
-//正常电压下：
-//@@LPO_RTM_SET:0x000026db     32       //1ms校准一次 
-//@@LPO_RTM_SET:0x000026da     32*5     //5ms校准一次 
-//@@LPO_RTM_SET:0x000026dc     320*2    //20ms校准一次  
-//@@LPO_RTM_SET:0x000026da     320*4    //40ms校准一次 
-//@@LPO_RTM_SET:0x000026e0     320*6    //60ms校准一次 
-//@@LPO_RTM_SET:0x000026dc     320*8    //80ms校准一次 
-
-//@@LPO_RTM_SET:0x000026dc     3200     //100ms校准一次 
-//@@LPO_RTM_SET:0x000026dc     3200*2   //200ms校准一次 
-//@@LPO_RTM_SET:0x000026df     3200*3   //300ms校准一次 
-//@@LPO_RTM_SET:0x000026dd     3200*4   //400ms校准一次 
-//@@LPO_RTM_SET:0x000026db     3200*5   //400ms校准一次 
-//@@LPO_RTM_SET:0x000026db     3200*6   //600ms校准一次 
-//@@LPO_RTM_SET:0x000026de     3200*7   //700ms校准一次 
-//@@LPO_RTM_SET:0x000026dd     3200*8   //800ms校准一次 
-//@@LPO_RTM_SET:0x000026e0     3200*9   //900ms校准一次 
-
-//#define printf(...) (0)
- 
-
-typedef struct
-{
-	uint32_t AO_TIMER_VALUE:16;
-	uint32_t AO_TIMER_CLR:1;
-	uint32_t AO_TIMER_EN:1;
-	uint32_t FREQ_TIMER_EN:1;
-	uint32_t RESERVED:13;
-}AO_TIMER_CTL_T;
-
-static AO_TIMER_CTL_T* ao_timer_ctl = (AO_TIMER_CTL_T*)AO_TIMER_CTL;
-
-
-
-/*
-3fff  3044 --50K 
-2fff  4132 --39K
-1fff  5229 --31K
-0fff  6326 --25K
-*/
-#define MAX_LPO_RTM       0x3fff
-#define MIN_LPO_RTM       0x0
-#define MID_LPO_RTM       0x1fff
-#define RANGE_LPO_RTM     0x400
-#define GEARS_HZ          1.56
-#define _32K_STAND_HZ     32000
-
-//#define CALIB_STEP_CYCLE_32K  32      //#define CALIB_STEP_CYCLE_32K  10
-//#define COUNT_16M             16000   //#define COUNT_16M  5000
-
-#define TMP_VAL    1
-#define CALIB_STEP_CYCLE_32K  32*TMP_VAL     //#define CALIB_STEP_CYCLE_32K  10
-#define COUNT_16M             16000*TMP_VAL   //#define COUNT_16M  5000
-
-static void LPO_RTM_SET(uint16_t val)
-{
-	*((volatile unsigned *)0x40002084)=0x1fff4000|val;      //*((volatile unsigned *)0x40002084)=0x1fff4000|0x22C0;	  //printf("LPO_RTM:%08x\n",*((volatile unsigned *)0x40002084));
-}
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : 
- *
- */
-static uint8_t  calib_step(uint32_t _cycle_32k,uint32_t *FREQ_VAL)  
-{
-    uint32_t tsd;
-	ao_timer_ctl->AO_TIMER_VALUE = _cycle_32k;//32 cycle == 1ms
-	ao_timer_ctl->AO_TIMER_EN = 0;
-	ao_timer_ctl->AO_TIMER_CLR = 0; //中断使用在timer 使能之前
-	ao_timer_ctl->FREQ_TIMER_EN = 1;
-	do{
-        __read_hw_reg32(AO_ALL_INTR, tsd);
-		//if(*FREQ_TIMER_VAL>=16777210) printf("***********\n");
-    }while((tsd&0x20)==0);
-	__read_hw_reg32(FREQ_TIMER_VAL, *FREQ_VAL);//
-	ao_timer_ctl->AO_TIMER_CLR = 1; // rtc 必须清理中断	
-	ao_timer_ctl->FREQ_TIMER_EN = 0;
-	if(*FREQ_VAL==COUNT_16M) return 0;
-	return ((*FREQ_VAL<COUNT_16M)? 1:2);
-} 
-
-
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Describe : init  calib clk
- *
- */
-static volatile uint32_t mid=MID_LPO_RTM;
-void calib_init(void)
-{
-	//config clk
-	__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x00020002);
-	__write_hw_reg32(CPR_AOCLKEN_GRCTL,0x00020002);
-
-    LPO_RTM_SET(mid);
-}
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Describe : "linear regression" calibration
- *
- */
-void  rc32k_calib(uint16_t cts)
-{
-	uint32_t tsd,frac;
-	while(cts--)
-	{
-		__disable_irq();
-		calib_step(CALIB_STEP_CYCLE_32K,&tsd);
-		__enable_irq();
-        printf("FREQ_TIMER_VAL:%d\n",tsd);
-		
-		frac=(uint32_t)((((float)((16.0)*CALIB_STEP_CYCLE_32K))/tsd)*1000000);
-		if(frac > _32K_STAND_HZ)
-		{
-			mid=mid-((uint32_t)(((float)(frac-_32K_STAND_HZ))/GEARS_HZ));
-		}
-		else if(frac < _32K_STAND_HZ)
-		{
-			mid=mid+((uint32_t)(((float)(_32K_STAND_HZ-frac))/GEARS_HZ));
-		}
-		LPO_RTM_SET(mid);
-
-	}
-    printf("@@LPO_RTM_SET:0x%08x\n",mid);
-
-	
-}
-#endif
-
-#if 0
-void test_main(void)
-{
-	printf("TEST CALIB\n");
-	Init_gpio();
-//	*((volatile unsigned *)(0x40002400 + 0x20))  =0x44;
-//	*((volatile unsigned *)(0x40002400 + 0x48))  =0x01;
-gpio_output_high(26);
-gpio_output_low(26);
-	//3.19ms
-    calib_init();
-	rc32k_calib(3);
-gpio_output_high(26);
-gpio_output_low(26);
-	 xc_ao_timer_calib_test();
-
-	
-}
-#endif
-
-//cmp
- 

component/boot2/bsp/bsp_can.c

@@ -1,201 +0,0 @@
-
-#include    "Includes.h"
-
-
- typedef struct{
-	uint32_t id28_18:11;
-	uint32_t id17_00:18;
-	uint32_t ide:1;
-	uint32_t rtr:1;
-	uint32_t NA0:1;
-	uint32_t len;
-	uint8_t dat[8];
-}CAN_INFO;
- 
-void can_pin_init(void)
-{
-	gpio_mux_ctl(8,2);//tx
-	gpio_mux_ctl(9,2);//rx
-}
-/*
-FPGA OSC_12M
-tq=2*tclk(BRP+1)     //CAN_BTR0->BRP
-
-Tsyncseg=1*tq
-Ttseg1=tq*(TSEG1+1)  //CAN_BTR1->TSEG1
-Ttseg2=tq*(TSEG2+1)  //CAN_BTR1->TSEG2
-
-can_baud=1/(Tsyncseg+Ttseg1+Ttseg2)
-        =1/(tq*(1+6+1+7+1))
-        =1/(tq*16)
-        =1/(16*2*tclk*(2+1))
-        =1/(16*6*tclk) 
-        =1/(96*tclk) 
-        =1/(96*(1/12M))=12M/96=12000000/96=125000bps 
-*/
-
-void can_init(void)
-{
-  
-
-	__write_hw_reg32(((volatile unsigned *)(CPR_BASE+0x24)),0x00110014);//CPR_CTL_PCLK_GRCTL(pclk=mclk/2)
-    CPR_CAN_CLK_CTL->CAN_PCLK_EN=1;
-	CPR_CAN_CLK_CTL->CAN_MCLK_EN=1;
-	CPR_CAN_CLK_CTL->CAN_MCLK_DIV=0;
- 
-	CAN_CDR->CDR3=0x07;
-	CAN_CDR->CDR4=0x0C;
-//	CAN_IER->TIE=1;
-	CAN_IER->RIE=1;
-	
-	CAN_MOD->RM=1;
-	//config can baud
-    CAN_OCR->OCMODE=2;
-	CAN_BTR0->BRP=2;
-	CAN_BTR0->SJW=2;
-	CAN_BTR1->TSEG2=7;
-	CAN_BTR1->TSEG1=6;
-	//config can filter
-    CAN_MOD->AFM=1;//single filter
-	*CAN_ACR0=0x00;//id28-21
-	*CAN_ACR1=0x00;//id20-13
-	*CAN_ACR2=0x00;//id12-05
-	*CAN_ACR3=0x00;//id04-00 +rtr
-	*CAN_AMR0=0x00;//1 identify the corresponding bits as do not care
-	*CAN_AMR1=0x10;
-	*CAN_AMR2=0x00;
-	*CAN_AMR3=0x04;//*CAN_AMR3=0x04;
-
-	CAN_MOD->RM=0;
-	 	//config rev filter
-	
-	
-}
-uint8_t Buffer_Released,Transmission_Complete;
-uint8_t  can_send_mes(CAN_INFO *can_information)
-{
-	uint8_t fifo_index;
-  //if(CAN_SR->TBS == 0) return 1;// CAN_SR->TBS ----volatile
-	while(CAN_SR->TBS == 0); //wait transmit buffer released.  CAN_SR->TBS ----volatile
-	*CAN_FI = (can_information->len&(0xF))|((can_information->rtr)<<6)|((can_information->ide)<<7);//1:remote frame  ,  0:data frame  
-	if(can_information->ide){//extended frame format
-        *CAN_ID1=(can_information->id28_18)>>3;
-	    *CAN_ID2=(((can_information->id28_18)&0x07)<<5)|((can_information->id17_00)>>13);
-		*CAN_ID3=((can_information->id17_00)>>5)&0xFF;
-		*CAN_ID4=((can_information->id17_00)&0x1F)<<3;
-		fifo_index=2;
-	}else{ //standard frame format 
-		*CAN_ID1=(can_information->id28_18)>>3;
-	    *CAN_ID2=((can_information->id28_18)&0x07)<<5;
-		fifo_index=0;
-	}
-    if(can_information->rtr == 0)
-	{
-		for(uint8_t i=0;i<8;i++)
-		{
-		   __write_hw_reg32(CAN_TX_BUFF(fifo_index++), can_information->dat[i]); //set transmission data
-		}
-    }
-	CAN_CMR->TR=0x01;	
-	return 0;
-}
-
-uint8_t can_receive_msg(CAN_INFO *can_information)
-{
-	uint8_t fifo_index;
- 	if(CAN_SR->RBS==0) return 0;
-	can_information->ide = *CAN_FI&0x80 ? 1:0; /*0:standard_frame , 1:extended_frame*/
-	can_information->rtr = *CAN_FI&0x40 ? 1:0; /*0:data frame     , 1:remote frame  */
-	can_information->len = *CAN_FI&0xF;	
-	if(can_information->len>8) 
-	{
-		can_information->len=8;
-	}
-	can_information->id28_18=(*CAN_ID1<<3)|(*CAN_ID2>>5);
-	if(can_information->ide){//1:extended 
-	    can_information->id17_00=((*CAN_ID2&0x1F)<<13)|(*CAN_ID3<<5)|(*CAN_ID4>>3);
-		fifo_index=2;
-	}else{//1:standard 
-	    fifo_index=0;
-	} 
-	if(can_information->rtr==0) 
-	{
-		for(int i=0;i<can_information->len;i++)
-		{
-		   __read_hw_reg32(CAN_RX_BUFF(fifo_index++), can_information->dat[i]);
-		}
-	}
-	CAN_CMR->RRB=1;	/* Release the FIFO */
-	return can_information->len;
-	
-	
-}
-void tx_msg(void)
-{
-	    static CAN_INFO can_tmsg={
-		.rtr=0,//1:remote frame  ,  0:data frame  
-		.ide=1,//1:extended frame format , 0:standard frame format 
-		.len=8,
-		.id28_18=0x12,
-		.id17_00=0x73,
-		.dat[0]=0x01,
-		.dat[1]=0x02,
-		.dat[2]=0x03,
-		.dat[3]=0x04,
-		.dat[4]=0x05,
-		.dat[5]=0x06,
-		.dat[6]=0x07,
-		.dat[7]=0x08,
-	}; 
-#if 1	//tx
-		 can_tmsg.dat[0]++;
-		 if(can_tmsg.rtr)//1: remote frame(remote frame has no data part)
-		 {
-		   if(can_tmsg.len>=8)
-		   {
-		      can_tmsg.len=1;//request length
-		   }else
-		   {
-		      can_tmsg.len++;//request length
-		   }
-	     }
- 		 can_send_mes(&can_tmsg);
-#endif
-	
-	
-
-
-}
-void rx_msg(void)
-{
-	 CAN_INFO can_rmsg;
-	 if(can_receive_msg(&can_rmsg))
-	 {
-		 printf("id28_18=%#x ,id17_00=%#x ,rtr=%#x ,ide=%#x ,len=%#x \n",can_rmsg.id28_18,can_rmsg.id17_00,can_rmsg.rtr,can_rmsg.ide,can_rmsg.len);
-		 if(can_rmsg.rtr==0)
-		 {
-			printf("dat:");
-			for(int i=0;i<can_rmsg.len;i++)  printf("%#x ",can_rmsg.dat[i]);
-			printf("\n");
-		 }
-	 }
-
-
-}
-void CAN_Handler(void)
-{
-   rx_msg();
-}	
-void test_can(void)
-{
-	can_pin_init();
-	can_init();
-    NVIC_EnableIRQ(CAN_IRQn);
-	while(1)
-	{
-      tx_msg();	
-      	
-   	}
-	
-	
-}

component/boot2/bsp/bsp_can.h

@@ -1,190 +0,0 @@
-#ifndef _BSP_CAN_H_
-#define _BSP_CAN_H_
-
-#include "xinc_m0.h"
-
-typedef struct
-{
-    __IO uint32_t CAN_MCLK_DIV : 12; /**/
-    __IO uint32_t CAN_MCLK_EN : 1;   /**/
-    __IO uint32_t CAN_PCLK_EN : 1;
-    __IO uint32_t RESERVED : 18;
-
-} CPR_CAN_CLK_CTL_T;
-#define CPR_CAN_CLK_CTL ((CPR_CAN_CLK_CTL_T *)((CPR_BASE + 0x25c)))
-
-typedef struct
-{
-    __IO uint32_t RM : 1;  /* Reset Mode */
-    __IO uint32_t LOM : 1; /* Listen Only Mode */
-    __IO uint32_t STM : 1; /* Self Test Mode */
-    __IO uint32_t AFM : 1; /* Acceptance Filter Mode */
-    __IO uint32_t SM : 1;  /*Sleep Mode (Can only be written in Operating Mode)*/
-    __IO uint32_t RESERVED : 27;
-} CAN_MOD_T;
-
-typedef struct
-{
-    __IO uint32_t TR : 1;  /* Transmission Request */
-    __IO uint32_t AT : 1;  /* Abort Transmission */
-    __IO uint32_t RRB : 1; /* Release Receive Buffer */
-    __IO uint32_t CDO : 1; /* Clear Data Overrun */
-    __IO uint32_t SRR : 1; /* Self Reception Request */
-    __IO uint32_t RESERVED : 27;
-} CAN_CMR_T;
-
-typedef struct
-{
-    __IO uint32_t RBS : 1; /*Receive Buffer Status*/
-    __IO uint32_t DOS : 1; /*Data Overrun Status*/
-    __IO uint32_t TBS : 1; /*Transmit Buffer Status*/
-    __IO uint32_t TCS : 1; /*Transmission Complete Status*/
-    __IO uint32_t RS : 1;  /*Receive Status */
-    __IO uint32_t TS : 1;  /*Transmit Status */
-    __IO uint32_t ES : 1;  /*Error Status*/
-    __IO uint32_t BS : 1;  /*Bus Status*/
-    __IO uint32_t RESERVED : 24;
-} CAN_SR_T;
-typedef struct
-{
-    __IO uint32_t RI : 1;  /*Receive Interrupt*/
-    __IO uint32_t TI : 1;  /*Transmit Interrupt*/
-    __IO uint32_t EI : 1;  /*Error Warning Interrupt*/
-    __IO uint32_t DOI : 1; /*Data Overrun Interrupt*/
-    __IO uint32_t WUI : 1; /*Wake-Up Interrupt*/
-    __IO uint32_t EPI : 1; /*Error Passive Interrupt */
-    __IO uint32_t ALI : 1; /*Arbitration Lost Interrupt*/
-    __IO uint32_t BEI : 1; /*Bus Error Interrupt*/
-    __IO uint32_t RESERVED : 24;
-} CAN_IR_T;
-typedef struct
-{
-    __IO uint32_t RIE : 1;  /*Receive Interrupt Enable*/
-    __IO uint32_t TIE : 1;  /*Transmit Interrupt Enable*/
-    __IO uint32_t EIE : 1;  /*Error Warning Interrupt Enable*/
-    __IO uint32_t DOIE : 1; /*Data Overrun Interrupt Enable*/
-    __IO uint32_t WUIE : 1; /*Wake-Up Interrupt Enable*/
-    __IO uint32_t EPIE : 1; /*Error Passive Interrupt Enable*/
-    __IO uint32_t ALIE : 1; /*Arbitration Lost Interrupt Enable*/
-    __IO uint32_t BEIE : 1; /*Bus Error Interrupt Enable*/
-    __IO uint32_t RESERVED : 24;
-} CAN_IER_T;
-typedef struct
-{
-    __IO uint32_t BRP : 6; /**/
-    __IO uint32_t SJW : 2; /**/
-    __IO uint32_t RESERVED : 24;
-} CAN_BTR0_T;
-typedef struct
-{
-    __IO uint32_t TSEG1 : 4; /**/
-    __IO uint32_t TSEG2 : 3; /**/
-    __IO uint32_t SAM : 1;   /**/
-    __IO uint32_t RESERVED : 24;
-} CAN_BTR1_T;
-typedef struct
-{
-
-    __IO uint32_t OCMODE : 2; /**/
-    __IO uint32_t RESERVED : 30;
-} CAN_OCR_T;
-typedef struct
-{
-
-    __IO uint32_t ALC : 5; /**/
-    __IO uint32_t RESERVED : 27;
-} CAN_ALC_T;
-typedef struct
-{
-    __IO uint32_t SegmentCode : 5; /**/
-    __IO uint32_t Direction : 1;   /**/
-    __IO uint32_t ErrorCode : 2;   /**/
-    __IO uint32_t RESERVED : 24;
-} CAN_ECC_T;
-typedef struct
-{
-
-    __IO uint32_t EWL : 8; /**/
-    __IO uint32_t RESERVED : 24;
-
-} CAN_EWLR_T;
-typedef struct
-{
-
-    __IO uint32_t RCNT : 8; /**/
-    __IO uint32_t RESERVED : 24;
-
-} CAN_RXERR_T;
-typedef struct
-{
-
-    __IO uint32_t TCNT : 8; /**/
-    __IO uint32_t RESERVED : 24;
-
-} CAN_TXERR_T;
-
-typedef struct
-{
-
-    __IO uint32_t RIE : 5; /**/
-    __IO uint32_t RESERVED : 27;
-
-} CAN_RMC_T;
-
-typedef struct
-{
-
-    __IO uint32_t RBSA : 6; /**/
-    __IO uint32_t RESERVED : 26;
-
-} CAN_RBSA_T;
-typedef struct
-{
-    __IO uint32_t CDR3 : 3;     /**/
-    __IO uint32_t ClockOff : 1; /**/
-    __IO uint32_t CDR4 : 4;     /**/
-    __IO uint32_t RESERVED : 24;
-
-} CAN_CDR_T;
-#define CAN_REG_BASE 0x40011c00
-#define CAN_MOD ((CAN_MOD_T *)((CAN_REG_BASE + (0x00 * 4))))
-#define CAN_CMR ((CAN_CMR_T *)((CAN_REG_BASE + (0x01 * 4))))
-#define CAN_SR ((CAN_SR_T *)((CAN_REG_BASE + (0x02 * 4))))
-#define CAN_IR ((CAN_IR_T *)((CAN_REG_BASE + (0x03 * 4))))
-#define CAN_IER ((CAN_IER_T *)((CAN_REG_BASE + (0x04 * 4))))
-#define CAN_BTR0 ((CAN_BTR0_T *)((CAN_REG_BASE + (0x06 * 4))))
-#define CAN_BTR1 ((CAN_BTR1_T *)((CAN_REG_BASE + (0x07 * 4))))
-#define CAN_OCR ((CAN_OCR_T *)((CAN_REG_BASE + (0x08 * 4))))
-#define CAN_ALC ((CAN_ALC_T *)((CAN_REG_BASE + (0x0B * 4))))
-#define CAN_ECC ((CAN_ECC_T *)((CAN_REG_BASE + (0x0C * 4))))
-#define CAN_EWLR ((CAN_EWLR_T *)((CAN_REG_BASE + (0x0D * 4))))
-#define CAN_RXERR ((CAN_RXERR_T *)((CAN_REG_BASE + (0x0E * 4))))
-#define CAN_TXERR ((CAN_TXERR_T *)((CAN_REG_BASE + (0x0F * 4))))
-#define CAN_RMC ((CAN_RMC_T *)((CAN_REG_BASE + (0x1D * 4))))
-#define CAN_RBSA ((CAN_RBSA_T *)((CAN_REG_BASE + (0x1E * 4))))
-#define CAN_CDR ((CAN_CDR_T *)((CAN_REG_BASE + (0x1f * 4))))
-
-// standard frame format  , extended frame format
-#define CAN_FI ((volatile unsigned *)((CAN_REG_BASE + (0x10 * 4))))
-#define CAN_ID1 ((volatile unsigned *)((CAN_REG_BASE + (0x11 * 4))))
-#define CAN_ID2 ((volatile unsigned *)((CAN_REG_BASE + (0x12 * 4))))
-#define CAN_ID3 ((volatile unsigned *)((CAN_REG_BASE + (0x13 * 4))))
-#define CAN_ID4 ((volatile unsigned *)((CAN_REG_BASE + (0x14 * 4))))
-
-#define CAN_ACR0 (((volatile unsigned *)(CAN_REG_BASE + (0x10 * 4))))
-#define CAN_ACR1 (((volatile unsigned *)(CAN_REG_BASE + (0x11 * 4))))
-#define CAN_ACR2 (((volatile unsigned *)(CAN_REG_BASE + (0x12 * 4))))
-#define CAN_ACR3 (((volatile unsigned *)(CAN_REG_BASE + (0x13 * 4))))
-#define CAN_AMR0 (((volatile unsigned *)(CAN_REG_BASE + (0x14 * 4))))
-#define CAN_AMR1 (((volatile unsigned *)(CAN_REG_BASE + (0x15 * 4))))
-#define CAN_AMR2 (((volatile unsigned *)(CAN_REG_BASE + (0x16 * 4))))
-#define CAN_AMR3 (((volatile unsigned *)(CAN_REG_BASE + (0x17 * 4))))
-
-#define CAN_TX_TFI_FIFO ((volatile unsigned *)(CAN_REG_BASE + (0x60 * 4)))
-#define CAN_TX_ID1_FIFO ((volatile unsigned *)(CAN_REG_BASE + (0x61 * 4)))
-#define CAN_TX_ID2_FIFO ((volatile unsigned *)(CAN_REG_BASE + (0x62 * 4)))
-#define CAN_TX_DATA_FIFO(a) ((volatile unsigned *)(CAN_REG_BASE + ((0x63 + a) * 4)))
-#define CAN_TX_BUFF(a) ((volatile unsigned *)(CAN_REG_BASE + ((0x13 + a) * 4)))
-#define CAN_RX_BUFF(a) ((volatile unsigned *)(CAN_REG_BASE + ((0x13 + a) * 4)))
-
-#endif

component/boot2/bsp/bsp_crc.c

@@ -1,150 +0,0 @@
-
-
-#include "Includes.h"
-
-//unsigned int crc32table[256] = {
-//    0
-    /*
-        0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
-        0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
-        0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
-        0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
-        0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
-        0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
-        0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
-        0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
-
-        0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
-        0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
-        0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
-        0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
-        0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
-        0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
-        0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
-        0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
-
-        0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
-        0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
-        0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
-        0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
-        0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
-        0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
-        0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
-        0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
-
-        0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
-        0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
-        0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
-        0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
-        0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
-        0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
-        0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
-        0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
-
-        0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
-        0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
-        0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
-        0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
-        0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
-        0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
-        0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
-        0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
-
-        0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
-        0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
-        0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
-        0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
-        0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
-        0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
-        0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
-        0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
-
-        0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
-        0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
-        0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
-        0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
-        0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
-        0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
-        0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
-        0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
-
-        0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
-        0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
-        0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
-        0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
-        0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
-        0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
-        0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
-        0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
-    */
-//};
-
-// CRC32
-//extern void makeCRC32table(unsigned int table[])
-//{
-//    unsigned int value;
-//    unsigned int i, j;
-//    for (i = 0; i < 256; i++)
-//    {
-//        value = i;
-//        for (j = 0; j < 8; j++)
-//        {
-//            if (value & 1)
-//            {
-//                value = (value >> 1) ^ 0xedb88320;
-//}
-
-unsigned int get_crc32(unsigned int crc, unsigned char *buf, unsigned int len)
-            {
-  const unsigned char *buffer = (const unsigned char *)buf;
-  int i = 0;
-  while (len--) {
-    crc ^= (unsigned int)(*buffer++) << 24;
-
-    for (i = 0; i < 8; i++) {
-      if (crc & 0x80000000) {
-        crc = (crc << 1) ^ 0xEDB88320;
-      } else {
-        crc <<= 1;
-        }
-    }
-}
-
-
-  return crc;
-}
-
-#if 0
-static unsigned int crc32table[256];
- 
-static void hash_makeCRC32table(unsigned int table[]){
-    unsigned int value;
-    unsigned int i, j;
-    for(i=0; i<256; i++){
-        value = i;
-        for(j=0; j<8; j++){
-            if(value&1){
-                value = (value >> 1) ^ 0xedb88320;
-            }
-            else{
-                value = (value >> 1);
-            }
-        }
-        table[i] = value;
-    }
-}
- 
-
-int	main(void)
-{
-    Init_gpio();
-	hash_makeCRC32table(crc32table);
-	for(int i=0;i<256;i++)
-	{
-		if(i%4==0) printf("\n");
-	   printf("0x%08X  ",crc32table[i]);
-		
-		
-	}
-}
-#endif

component/boot2/bsp/bsp_gpadc.c

@@ -1,331 +0,0 @@
-
-#include    "Includes.h"
-
-
-/*
-2021/09/17
-	1、在芯片FT测试过程中，将ADC工艺误差校正。
-
-	2、ADC 校准值(数据)存储于FLASH 第240K 位置，占用8Byte.(4+4Byte 校准数据和取反校验)
-  
-	3、校准中心值CALI_CENTER_VL=10000 ，ADC计算时，将ADC原始值乘以校准值再除以中心值(10000)
-      value_calibrated = value * calibration_param / CALI_CENTER_VL ;
-   
-	4、读取校准值接口：int gadc_calibration_get(uint32_t *value)
-      具体用法请参考adc-demo，调用接口返回值大于0表示正确获取到校准值。
- 
-2022/02/11
-	1、增加3.3V参考电压时的校准参数。
-*/
-
-
-#define PROG_SECTOR_NUM 60 // = 4*60 = 240k
-#define CALI_CENTER_VL  10000
-#define CALI_OFFSET_VL  1000
- 
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-void adc_gpio_config(uint8_t io_gpadc_channel)
-{
-	if(io_gpadc_channel==0xff) return;
-    gpio_mux_ctl(io_gpadc_channel,0);
-	gpio_fun_sel(io_gpadc_channel,0);
-	gpio_fun_inter(io_gpadc_channel,0); 
-	gpio_direction_input(io_gpadc_channel, 3);/*FLOATING*/
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-void gpadc_config_channel(uint16_t channel)
-{
-    __write_hw_reg32(GPADC_CHAN_CTL ,channel);
-    __write_hw_reg32(GPADC_FIFO_CTL , 0x10);
-    __write_hw_reg32(GPADC_FIFO_CTL , 0x00);
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-extern void init_adc(uint8_t freq,uint8_t gadc_ref)
-{
-	uint32_t adc_reg = 0;
-    __write_hw_reg32(CPR_RSTCTL_CTLAPB_SW , 0x10000000);/*先使GPADC_RSTN=0，再使 GPADC_RSTN=1软复位 GPADC 模块*/ 
-    __write_hw_reg32(CPR_RSTCTL_CTLAPB_SW , 0x10001000);
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , 0x20002000);/*使能GPADC_PCLK_EN 的GPADC_PCLK时钟*/
-    __write_hw_reg32(GPADC_FIFO_CTL , 0x10);/*对FIFO进行一次清空操作*/
-    __write_hw_reg32(GPADC_FIFO_CTL , 0x00);
-    if((freq>GADC_FREQ_500K)||(freq<GADC_FREQ_8M)) freq = GADC_FREQ_1M;
-    if(GADC_REF_2_47V == gadc_ref)
-        adc_reg = (freq<<8)|0x10 ;
-    else
-        adc_reg = (freq<<8)|0x12 ;
-    __write_hw_reg32(GPADC_RF_CTL ,adc_reg);/*GPADC_RF_CTL   GPADC_PCLK/(gpadc_clkdiv*2)=16M/16=1M ,select 2.4V vref*/
-    __write_hw_reg32(GPADC_TIMER0 ,4);      /*通道切换等待时间 4us*/
-	__write_hw_reg32(GPADC_MAIN_CTL , 0x09);/*GPADC_MAIN_CTL 打开GPADC模块，数据采集上升沿.*/
-   
-    //NVIC_EnableIRQ(GADC_IRQn);
-
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-
-int gadc_calibration_get(uint32_t *value)
-{
-	uint32_t vl[2] = {0};
-	uint32_t neg[2] = {0};
-	uint8_t get_buf[16] = {0};
-#if 0 /*SPI0*/
-	Init_spi_master(0, SPIM_CLK_16MHZ);
-	spi_flash_Release_powerdown();
-	spi_flash_Read(PROG_SECTOR_NUM*FLASH_SECTOR_SIZE,get_buf,12);
-	spi_flash_Enter_powerdown();
-#else /*XIP*/
-
-	
-#endif	
-	vl[0]  = get_buf[0]*0x1000000 + get_buf[1]*0x10000 + get_buf[2]*0x100 + get_buf[3] ;
-	neg[0]  = get_buf[4]*0x1000000 + get_buf[5]*0x10000 + get_buf[6]*0x100 + get_buf[7] ;
-	
-	vl[1] = get_buf[8]*0x1000000 + get_buf[9]*0x10000 + get_buf[10]*0x100 + get_buf[11] ;
-	neg[1]  = get_buf[12]*0x1000000 + get_buf[13]*0x10000 + get_buf[14]*0x100 + get_buf[15] ;
-
-	printf("calibration 2.47v=[%d],3.3v=[%d],neg=[%d]\n", vl[0], vl[1], neg[0]);
-	if( (neg[0] == ~vl[0]) && ( (vl[0] > CALI_CENTER_VL-CALI_OFFSET_VL)&&(vl[0] < CALI_CENTER_VL+CALI_OFFSET_VL) ))
-	{
-		value[0] = vl[0];
-		value[1] = vl[1];
-		return 1;
-	}	
-	else
-	{
-		return -1;
-	}	
-		  
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-uint16_t data_average(uint16_t *data,uint16_t len)
-{
-    uint16_t add_cnt = 0;
-    uint32_t sum_data = 0;
-    uint8_t  filter_cnt = 0;
-
-    filter_cnt = len/10;
-
-    for(int i=0; i<len-1; i++)
-    {
-        for(int j=0; j<len-i-1; j++)
-        {
-            if(data[j]>data[j+1])
-            {
-                uint16_t temp = data[j];
-                data[j] = data[j+1];
-                data[j+1] = temp;
-            }
-        }
-    }
-
-    for(int i=6*filter_cnt; i<len-3*filter_cnt; i++)
-    {
-        sum_data += data[i];
-        add_cnt++;
-    }
-
-    if(0 == add_cnt) return -1;
-    else return sum_data/add_cnt;
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-uint16_t gpadc_val_update(uint8_t update_ch)
-{
-    gadc_cache_t *temp_gadc_cache = NULL;
-    uint16_t gadc_value[2*FIFO_DEEP] = {0};
-    uint16_t gadc_count = 0;
-    uint32_t val;
-    temp_gadc_cache = (gadc_cache_t*)&val;
-
-    for(int t=0; t<FIFO_DEEP; t++)
-    {
-        __read_hw_reg32(GPADC_FIFO,val);
-        if(update_ch == temp_gadc_cache->chanel_1) gadc_value[gadc_count++] = temp_gadc_cache->value_1;
-        if(update_ch == temp_gadc_cache->chanel_2) gadc_value[gadc_count++] = temp_gadc_cache->value_2;
-
-        if((update_ch != 0)&&(0 == temp_gadc_cache->chanel_1)) break; //empty
-    }
-
-    if(gadc_count<=2) return -1;
-    else return data_average(gadc_value+2,gadc_count-2); //Remove the first FIFO data
-}
-
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-
-void test_gpadc_3_3V(void)
-{
-
-    uint16_t count = 0;
-    char state=4;
-    uint16_t value = 0;
-    uint16_t value_calibrated = 0;
-    uint32_t calibration_param[2] = {0};
-    if(gadc_calibration_get(calibration_param)>0)
-    {
-        printf("[3.3v] gadc_calibration_get success!,cali param=%d\n",calibration_param[1]);
-    }
-    else
-    {
-        calibration_param[1] = 10000;
-        printf("[3.3v] gadc_calibration_get error!\n");
-    }
-    adc_gpio_config(IO_GPADC_CHANNEL4);
-	adc_gpio_config(IO_GPADC_CHANNEL5);
-	adc_gpio_config(IO_GPADC_CHANNEL6);
-	adc_gpio_config(IO_GPADC_CHANNEL7);
-
-    init_adc(GADC_FREQ_1M,GADC_REF_AVDD);
-    gpadc_config_channel(state);
-    while(1)
-    {
-        //If the delay is less, you have to test it well !
-        for(int i=0; i<0x1000; i++); //delay
-
-        value = gpadc_val_update(state);
-        value_calibrated = value * calibration_param[1] / CALI_CENTER_VL ;
-        int old_state = state;
-
-        switch(state)
-        {
-
-        case 4:
-            gpadc_config_channel(5);
-            state=5;
-            break;
-        case 5:
-            gpadc_config_channel(6);
-            state=6;
-            break;
-        case 6:
-            gpadc_config_channel(7);
-            state=7;
-            break;
-        case 7:
-            gpadc_config_channel(4);
-            state=4;
-            break;
-        default:
-            break;
-        }
-
-        if(count++>=1000)
-        {
-            count =0;
-            //printf("%1d-%3d  ",old_state,value);
-            printf("[3.3v] channel:%d:0x%04X===cali=%d===before cali Voltage:%f V,after cali Voltage:%f V \r\n",\
-                   old_state,value,calibration_param[1],((value)*3.3)/(1.0*1024),((value_calibrated)*3.3)/(1.0*1024));
-            //printf("channel:%d======Voltage:%f V\r\n",old_state,((value_calibrated)*3.3)/(1.0*1024));
-        }
-    }
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-void test_gpadc_2_47V(void)
-{
-    uint16_t count = 0;
-    char state=4;
-    uint16_t value = 0;
-    uint16_t value_calibrated = 0;
-    uint32_t calibration_param[2] = {0};
-    if(gadc_calibration_get(calibration_param)>0)
-    {
-        printf("[2.47v] gadc_calibration_get success!,cali param=%d\n",calibration_param[0]);
-    }
-    else
-    {
-        calibration_param[0] = 10000;
-        printf("[2.47v] gadc_calibration_get error!\n");
-    }
-	
-    adc_gpio_config(IO_GPADC_CHANNEL4);
-	adc_gpio_config(IO_GPADC_CHANNEL5);
-	adc_gpio_config(IO_GPADC_CHANNEL6);
-	adc_gpio_config(IO_GPADC_CHANNEL7);
-    init_adc(GADC_FREQ_1M,GADC_REF_2_47V);
-    gpadc_config_channel(state);
-    while(1)
-    {
-        //If the delay is less, you have to test it well !
-        for(int i=0; i<0x1000; i++); //delay
-
-        value = gpadc_val_update(state);
-        value_calibrated = value * calibration_param[0] / CALI_CENTER_VL ;
-        int old_state = state;
-
-        switch(state)
-        {
-
-        case 4:
-            gpadc_config_channel(5);
-            state=5;
-            break;
-        case 5:
-            gpadc_config_channel(6);
-            state=6;
-            break;
-        case 6:
-            gpadc_config_channel(7);
-            state=7;
-            break;
-        case 7:
-            gpadc_config_channel(4);
-            state=4;
-            break;
-        default:
-            break;
-        }
-
-        if(count++>=1000)
-        {
-            count =0;
-            //printf("%1d-%3d  ",old_state,value);
-            printf("[2.47v] channel:%d:0x%04X===cali=%d===before cali Voltage:%f V,after cali Voltage:%f V \r\n",\
-                   old_state,value,calibration_param[0],((value)*2.47)/(1.0*1024),((value_calibrated)*2.47)/(1.0*1024));
-            //printf("channel:%d======Voltage:%f V\r\n",old_state,((value_calibrated)*3.3)/(1.0*1024));
-        }
-    }
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- * All rights reserved.
- * Author : D
- */
-void test_gpadc(void)
-{
-	test_gpadc_3_3V();
-//    test_gpadc_2_47V();
-}

component/boot2/bsp/bsp_gpadc.h

@@ -1,62 +0,0 @@
-#ifndef _BSP_GP_ADC_H_
-#define _BSP_GP_ADC_H_
-
-#define FIFO_DEEP 16
-
-#define GADC_FREQ_500K 16
-#define GADC_FREQ_1M 8
-#define GADC_FREQ_2M 4
-#define GADC_FREQ_4M 2
-#define GADC_FREQ_8M 1
-
-#define GADC_REF_2_47V 1
-#define GADC_REF_AVDD 2
-
-typedef struct gadc_cache_struct
-{
-    unsigned int value_2 : 10;
-    unsigned int chanel_2 : 4;
-    unsigned int : 2;
-    unsigned int value_1 : 10;
-    unsigned int chanel_1 : 4;
-    unsigned int : 2;
-} gadc_cache_t;
-
-void init_adc(uint8_t freq, uint8_t gadc_ref);
-void adc_gpio_config(uint8_t cio);
-int gadc_calibration_get(uint32_t *value);
-
-#define IO_GPADC_CHANNEL0 21   /*gpio21*/
-#define IO_GPADC_CHANNEL1 20   /*gpio20*/
-#define IO_GPADC_CHANNEL2 19   /*gpio19*/
-#define IO_GPADC_CHANNEL3 18   /*gpio18*/
-#define IO_GPADC_CHANNEL4 0    /*gpio0 */
-#define IO_GPADC_CHANNEL5 1    /*gpio1 */
-#define IO_GPADC_CHANNEL6 4    /*gpio4 */
-#define IO_GPADC_CHANNEL7 5    /*gpio5 */
-#define IO_GPADC_CHANNEL8 0xff /*???????2/3 ???????3.3V????8?????2.2V*/
-#define IO_GPADC_CHANNEL9 0xff
-#define IO_GPADC_CHANNEL10 2 /*gpio2 */
-#define IO_GPADC_CHANNEL11 3 /*gpio3 */
-
-#define GPADC_MAIN_CTL_EX_SAMPLE_NUM_Pos 12
-#define GPADC_MAIN_CTL_EX_SAMPLE_NUM_Msk (0xFul << GPADC_MAIN_CTL_EX_SAMPLE_NUM_Pos)
-
-#define GPADC_MAIN_CTL_EX_TRIGGER_SEL_Pos 8
-#define GPADC_MAIN_CTL_EX_TRIGGER_SEL_Msk (0x7ul << GPADC_MAIN_CTL_EX_TRIGGER_SEL_Pos)
-
-#define GPADC_MAIN_CTL_EX_EDGE_SEL_Pos 4
-#define GPADC_MAIN_CTL_EX_EDGE_SEL_Msk (0x3ul << GPADC_MAIN_CTL_EX_EDGE_SEL_Pos)
-
-#define GPADC_MAIN_CTL_EDGE_SEL_Pos 3
-#define GPADC_MAIN_CTL_EDGE_SEL_Msk (1ul << GPADC_MAIN_CTL_EDGE_SEL_Pos)
-
-#define GPADC_MAIN_CTL_AUTO_SW_Pos 2
-#define GPADC_MAIN_CTL_AUTO_SW_Msk (1ul << GPADC_MAIN_CTL_AUTO_SW_Pos)
-
-#define GPADC_MAIN_CTL_DMAS_ON_Pos 1
-#define GPADC_MAIN_CTL_DMAS_ON_Msk (1ul << GPADC_MAIN_CTL_DMAS_ON_Pos)
-
-#define GPADC_MAIN_CTL_EN_Pos 0
-#define GPADC_MAIN_CTL_EN_Msk (1ul << GPADC_MAIN_CTL_EN_Pos)
-#endif

component/boot2/bsp/bsp_gpio.c

@@ -1,338 +0,0 @@
-
-/*----------------------------------------------------------------------------------------------------
-    INCLUDE HEADE FILES
-----------------------------------------------------------------------------------------------------*/
-#include "Includes.h"
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : D
- *
- * Tips: NA
- */
-extern void Init_gpio(void)
-{
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x40004); /*gpio_pclk enable*/
-    __write_hw_reg32(CPR_OTHERCLKEN_GRCTL, 0x10001);  /*gpio_clk  enable*/
-
-    // NVIC_EnableIRQ(GPIO_IRQn);
-}
-/**
-* Copyright (c) 2022 - 2025, XinChip
-*
-* All rights reserved.
-*
-* Author : D
-*
-* Tips:
-- GPIO0 : 【mux=0 连接到gpio_d[0] 】 【mux=1 kbs_mko_0】        【mux=2 pwm2】       【mux=3 NA】
-- GPIO1 : 【mux=0 连接到gpio_d[1] 】 【mux=1 kbs_mko_1】        【mux=2 pwm3】       【mux=3 NA】
-- GPIO2 : 【mux=0 连接到gpio_d[2] 】 【mux=1 kbs_mko_2】        【mux=2 clk_12M_out】【mux=3 NA】
-- GPIO3 : 【mux=0 连接到gpio_d[3] 】 【mux=1 kbs_mko_3】        【mux=2 NA】         【mux=3 NA】
-- GPIO4 : 【mux=0 连接到gpio_d[4] 】 【mux=1 kbs_mko_4】        【mux=2 NA】         【mux=3 NA】
-- GPIO5 : 【mux=0 连接到gpio_d[5] 】 【mux=1 kbs_mko_5】        【mux=2 NA】         【mux=3 NA】
-- GPIO6 : 【mux=0 连接到gpio_d[6] 】 【mux=1 kbs_mko_6】        【mux=2 txen】       【mux=3 NA】
-- GPIO7 : 【mux=0 连接到gpio_d[7] 】 【mux=1 kbs_mko_7】        【mux=2 rxen】       【mux=3 NA】
-- GPIO8 : 【mux=0 连接到gpio_d[8] 】 【mux=1 kbs_mki_0】        【mux=2 NA】         【mux=3 NA】
-- GPIO9 : 【mux=0 连接到gpio_d[9] 】 【mux=1 kbs_mki_1】        【mux=2 NA】         【mux=3 NA】
-- GPIO10: 【mux=0 连接到gpio_d[10]】 【mux=1 kbs_mki_8】        【mux=2 NA】         【mux=3 NA】
-- GPIO11: 【mux=0 连接到BOOT_CTL0 】 【mux=1 连接到gpio_d[11]】 【mux=2 NA】         【mux=3 NA】
-- GPIO12: 【mux=0 连接到SWI的 SWCK】 【mux=1 连接到gpio_d[12]】 【mux=2 NA】         【mux=3 pwm4】
-- GPIO13: 【mux=0 连接到SWI的 SWD 】 【mux=1 连接到gpio_d[13]】 【mux=2 NA】         【mux=3 pwm5】
-- GPIO14: 【mux=0 连接到gpio_d[14]】 【mux=1 kbs_mki_9】        【mux=2 SPI2_CLK】   【mux=3 NA】
-- GPIO15: 【mux=0 连接到gpio_d[15]】 【mux=1 kbs_mki_10】       【mux=2 SPI2_CS】    【mux=3 NA】
-- GPIO16: 【mux=0 连接到gpio_d[16]】 【mux=1 kbs_mki_11】       【mux=2 SPI2_RX】    【mux=3 NA】
-- GPIO17: 【mux=0 连接到gpio_d[17]】 【mux=1 kbs_mki_12】       【mux=2 SPI2_TX】    【mux=3 NA】
-- GPIO18: 【mux=0 连接到gpio_d[18]】 【mux=1 kbs_mki_16】       【mux=2 NA】         【mux=3 NA】
-- GPIO19: 【mux=0 连接到gpio_d[19]】 【mux=1 kbs_mki_17】       【mux=2 NA】         【mux=3 NA】
-- GPIO20: 【mux=0 连接到gpio_d[20]】 【mux=1 kbs_mki_2】        【mux=2 NA】         【mux=3 NA】
-- GPIO21: 【mux=0 连接到gpio_d[21]】 【mux=1 kbs_mki_3】        【mux=2 NA】         【mux=3 NA】
-- GPIO22: 【mux=0 连接到gpio_d[22]】 【mux=1 kbs_mki_4】        【mux=2 ssi2_clk】   【mux=3 NA】
-- GPIO23: 【mux=0 连接到gpio_d[23]】 【mux=1 kbs_mki_5】        【mux=2 ssi2_ssn】   【mux=3 NA】
-- GPIO24: 【mux=0 连接到gpio_d[24]】 【mux=1 kbs_mki_6】        【mux=2 ssi2_d0 tx】 【mux=3 NA】
-- GPIO25: 【mux=0 连接到gpio_d[25]】 【mux=1 kbs_mki_7】        【mux=2 ssi2_d1 rx】 【mux=3 NA】
-- GPIO26: 【mux=0 连接到gpio_d[26]】 【mux=1 kbs_mki_13】       【mux=2 ssi2_d2】    【mux=3 NA】
-- GPIO27: 【mux=0 连接到gpio_d[27]】 【mux=1 kbs_mki_14】       【mux=2 ssi2_d3】    【mux=3 NA】
-- GPIO28: 【mux=0 连接到gpio_d[28]】 【mux=1 kbs_mki_15】       【mux=2 adcclk】     【mux=3 NA】
-- GPIO29: 【mux=0 连接到gpio_d[29]】 【mux=1 kbs_mki_16】       【mux=2 adcdata】    【mux=3 NA】
-- GPIO30: 【mux=0 连接到gpio_d[30]】 【mux=1 kbs_mki_17】       【mux=2 i2s_sclk】   【mux=3 NA】
-- GPIO31: 【mux=0 连接到gpio_d[31]】 【mux=1  uart2_rx】        【mux=2 i2s_ws】     【mux=3 NA】
-- GPIO32: 【mux=0 连接到gpio_d[27]】 【mux=1  uart2_tx】        【mux=2 i2s_din】    【mux=3 NA】
-- GPIO33: 【mux=0 连接到gpio_d[28]】 【mux=1  NA】              【mux=2 i2s_dout】   【mux=3 NA】
-- GPIO34: 【mux=0 连接到gpio_d[29]】 【mux=1  NA】              【mux=2 NA】         【mux=3 NA】
-- GPIO35: 【mux=0 连接到gpio_d[30]】 【mux=1  NA】              【mux=2 BOOT_CTL1】  【mux=3 NA】
-*/
-extern void gpio_mux_ctl(uint8_t num, uint8_t mux) //(num:0-31  32-34)
-{
-    if (mux > 3)
-        return;
-    uint32_t tv = 0;
-    if (num < 32)
-    {
-        __read_hw_reg32((CPR_CTL_MUXCTL1 + (num / 16)), tv);
-        tv = (tv & (~(0x3 << ((num % 16) * 2)))) | (mux << ((num % 16) * 2));
-        __write_hw_reg32((CPR_CTL_MUXCTL1 + (num / 16)), tv);
-    }
-    else
-    {
-        __read_hw_reg32(CPR_CTL_MUXCTL3, tv);
-        tv = (tv & (~(0x3 << ((num % 16) * 2)))) | (mux << ((num % 16) * 2));
-        __write_hw_reg32(CPR_CTL_MUXCTL3, tv);
-    }
-}
-extern void gpio_mux_ctl_u(uint8_t num, uint8_t mux) //(num:32-34)
-{
-    if (mux > 3)
-        return;
-    uint32_t tv = 0;
-    __read_hw_reg32(CPR_CTL_MUXCTL3, tv);
-    tv = (tv & (~(0x3 << ((num % 16) * 2)))) | (mux << ((num % 16) * 2));
-    __write_hw_reg32(CPR_CTL_MUXCTL3, tv);
-}
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : D
- *
- * Tips: gpio编号0-34  中断类型0无中断 5上升沿中断 7下降沿中断
- */
-extern void gpio_fun_inter(uint8_t num, uint8_t inter)
-{
-    unsigned int tv = 0;
-    if (inter > 0xF)
-        return;
-    switch (num % 4)
-    {
-    case 3:
-        __read_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), tv);
-        tv &= 0x0FFF;
-        tv |= ((inter << 12) | 0xF0000);
-        __write_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), tv);
-        break;
-    case 2:
-        __read_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), tv);
-        tv &= 0xF0FF;
-        tv |= ((inter << 8) | 0xF0000);
-        __write_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), tv);
-        break;
-    case 1:
-        __read_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), tv);
-        tv &= 0xFF0F;
-        tv |= ((inter << 4) | 0xF0000);
-        __write_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), tv);
-        break;
-    case 0:
-        __read_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), tv);
-        tv &= 0xFFF0;
-        tv |= ((inter) | 0xF0000);
-        __write_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), tv);
-        break;
-    default:
-        break;
-    }
-}
-/**
-* Copyright (c) 2022 - 2025, XinChip
-*
-* All rights reserved.
-*
-* Author : D
-*
-* Tips: sel复用【0:GPIO_Dx】   【1:UART0_TX】 【2:UART0_RX】 【3:UART0_CTS】【4:UART0_RTS】【5:I2C_SCL】
-                               【6:I2C_SDA】  【7:UART1_RX】 【8:UART1_TX】 【9:SIM_IO】   【10:SIM_RST】 【11:SIM_CLK_OUT】
-                               【12:PWM0】    【13:PWM1】    【14:SSI1_CLK】【15:SSI1_SSN】【16:SSI1_RX】 【17:SSI1_TX】
-                               【18:PWM0_INV】【19:PWM1_INV】【20:PWM2_INV】【21:PWM3_INV】
-*/
-extern void gpio_fun_sel(uint8_t num, uint8_t sel) //(num:0-28)
-{
-
-    unsigned int tv = 0;
-    if (sel > 21)
-        return;
-    switch (num % 4)
-    {
-    case 0:
-        __read_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), tv);
-        tv &= 0xFFFFFF00;
-        tv |= sel;
-        __write_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), tv);
-        break;
-    case 1:
-        __read_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), tv);
-        tv &= 0xFFFF00FF;
-        tv |= (sel << 8);
-        __write_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), tv);
-        break;
-    case 2:
-        __read_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), tv);
-        tv &= 0xFF00FFFF;
-        tv |= (sel << 16);
-        __write_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), tv);
-        break;
-    case 3:
-        __read_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), tv);
-        tv &= 0x00FFFFFF;
-        tv |= (sel << 24);
-        __write_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), tv);
-        break;
-    default:
-        break;
-    }
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : D
- *
- * Tips: NA
- */
-extern void gpio_output_high(uint8_t num)
-{
-
-    __write_hw_reg32((GPIO_PORT_DR0 + (num >> 4)), (0x00010001 << (num & 0x0F)));
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : D
- *
- * Tips: NA
- */
-extern void gpio_output_low(uint8_t num)
-{
-
-    __write_hw_reg32((GPIO_PORT_DR0 + (num >> 4)), (0x00010000 << (num & 0x0F)));
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : D
- *
- * Tips: NA
- */
-extern void GPIO_Handler(void)
-{
-    uint32_t val[2];
-    __read_hw_reg32(GPIO_INTR_STATUS_C00, val[0]);
-    __read_hw_reg32(GPIO_INTR_STATUS_C01, val[1]);
-    __write_hw_reg32(GPIO_INTR_CLR0, val[0]);
-    __write_hw_reg32(GPIO_INTR_CLR1, val[1]);
-    if (DETECT_INTER_NUM(8, val)) // 判断是否为GPIO24中断
-    {
-        printf("GPIO8 interrupt\n");
-    }
-    if (DETECT_INTER_NUM(9, val)) // 判断是否为GPIO24中断
-    {
-        printf("GPIO9 interrupt\n");
-    }
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : D
- *
- * Tips: NA
- */
-extern uint8_t gpio_input_val(uint8_t num)
-{
-    uint32_t val;
-    __read_hw_reg32((GPIO_EXT_PORT0 + (num >> 5)), val);
-    return (val & (0x01L << (num & 0x1F))) ? (1) : (0);
-}
-
-/**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : D
- *
- * Tips: NA
- */
-extern void gpio_direction_output(uint8_t num)
-{
-    __write_hw_reg32((GPIO_PORT_DDR0 + (num >> 4)), ((0x10001) << (num & 0x0F)));
-}
-
-/**
-* Copyright (c) 2022 - 2025, XinChip
-*
-* All rights reserved.
-*
-* Author : D
-*
-* Tips: gpio编号(0-34) 上下拉状态(0代表上拉 1代表下拉 其他代表无上下拉
-                      【pull_up_type=0  GPIO上拉:GPIO_Mode_Input_Up   】
-                      【pull_up_type=1  GPIO下拉:GPIO_Mode_Input_Down 】
-                      【pull_up_type=2  GPIO浮空:GPIO_Mode_Input_Float】
-*/
-extern void gpio_direction_input(uint8_t num, uint8_t pull_up_type)
-{
-    uint8_t tv = num;
-    uint32_t val;
-    uint32_t *base_reg = 0x0;
-    if (num > 0 && num <= 15)
-    {
-        base_reg = (uint32_t *)(0x40002400 + 0x34);
-    }
-    else if (num >= 16 && num <= 31)
-    {
-        base_reg = (uint32_t *)(0x40002400 + 0x38);
-        num = num % 16;
-    }
-    else if (num >= 32 && num <= 34)
-    {
-        base_reg = (uint32_t *)(0x40002400 + 0x3c);
-        num = 2 + num % 16;
-    }
-    __read_hw_reg32(base_reg, val);
-    if (pull_up_type == 1) // 下拉
-    {
-        setbit(val, num * 2);
-        clrbit(val, num * 2 + 1);
-    }
-    else if (pull_up_type == 0) // 上拉
-    {
-        clrbit(val, num * 2);
-        setbit(val, num * 2 + 1);
-    }
-    else // 无上下拉
-    {
-        clrbit(val, num * 2);
-        clrbit(val, num * 2 + 1);
-    }
-    __write_hw_reg32(base_reg, val);
-
-    __write_hw_reg32((GPIO_PORT_DDR0 + (tv >> 4)), ((0x10000) << (tv & 0x0F)));
-    __write_hw_reg32((GPIO_DEBOUNCE0 + (tv >> 4)), ((0x10001) << (tv & 0x0F)));
-}
-
-void test_gpio(void)
-{
-    Init_gpio();
-    gpio_mux_ctl(8, 0);
-    gpio_fun_inter(8, 5);
-    gpio_fun_sel(8, 0);
-    gpio_direction_input(8, 1);
-    gpio_mux_ctl(9, 0);
-    gpio_fun_inter(9, 5);
-    gpio_fun_sel(9, 0);
-    gpio_direction_input(9, 1);
-}

component/boot2/bsp/bsp_gpio.h

@@ -1,57 +0,0 @@
-#ifndef		__BSP_GPIO_H_
-#define		__BSP_GPIO_H_
-
-#include	"xinc_m0.h"
-
-#define    DETECT_INTER_NUM(num,val)              ((num>=32)?((val[1]>>(num&0x1F))&0x01):((val[0]>>num)&0x01))
-
-typedef enum{
- GPIO_Dx=0,UART0_TX,UART0_RX,UART0_CTS,
- UART0_RTS,I2C_SCL,I2C_SDA,UART1_RX,
- UART1_TX,SIM_IO,SIM_RST,SIM_CLK_OUT,
- PWM0,PWM1,SSI1_CLK,SSI1_SSN,
- SSI1_RX,SSI1_TX,PWM0_INV,PWM1_INV,PWM2_INV,PWM3_INV,
-}GPIO_FUN_SEL_TypeDef;
-typedef enum{
- NOT_INT=0,
- NA1_INT,
- NA2_INT,
- NA3_INT,
- NA4_INT,
- RIS_EDGE_INT,//上升沿中断
- NA6_INT,
- FAIL_EDGE_INT,//下降沿中断
- 
-}GPIO_INT_TypeDef;
-
-typedef enum{
-     GPIO_PIN_0=0,GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3,GPIO_PIN_4, GPIO_PIN_5, GPIO_PIN_6, GPIO_PIN_7, 
-     GPIO_PIN_8, GPIO_PIN_9, GPIO_PIN_10,GPIO_PIN_11,GPIO_PIN_12,GPIO_PIN_13,GPIO_PIN_14,GPIO_PIN_15,
-     GPIO_PIN_16,GPIO_PIN_17,GPIO_PIN_18,GPIO_PIN_19,GPIO_PIN_20,GPIO_PIN_21,GPIO_PIN_22,GPIO_PIN_23,
-     GPIO_PIN_24,GPIO_PIN_25,GPIO_PIN_26,GPIO_PIN_27,GPIO_PIN_28,GPIO_PIN_29,GPIO_PIN_30,GPIO_PIN_31,
-}GPIO_Pin_TypeDef;
-
-typedef enum{
-	GPIO_Mode_Input_Up=0, /*上拉输入*/
-	GPIO_Mode_Input_Down, /*下拉输入*/
-	GPIO_Mode_Input_Float,/*浮空输入*/
-}GPIO_InputMode_TypeDef;
-
-
- 
-typedef void	    (*IoHandler_callback)(uint32_t val);
-extern	void	    Init_gpio(void);
-extern	void	    gpio_Register_Callback(IoHandler_callback callback);
-extern	void        gpio_direction_input(uint8_t num, uint8_t pull_up_type);
-extern	uint8_t     gpio_input_val(uint8_t num);
-extern	void	    gpio_output_low(uint8_t	num);
-extern	void	    gpio_output_high(uint8_t num);
-extern  void        gpio_mux_ctl(uint8_t num,uint8_t mux);
-extern  void        gpio_mux_ctl_u(uint8_t num,uint8_t mux); //(num:32-34)
-
-extern  void        gpio_fun_inter(uint8_t num,uint8_t inter);
-extern  void        gpio_fun_sel(uint8_t num,uint8_t sel);
-extern	void	    gpio_direction_output(uint8_t num);
-
-#endif
-

component/boot2/bsp/bsp_gpio_normal.c

@@ -1,695 +0,0 @@
-
-/*----------------------------------------------------------------------------------------------------
-    INCLUDE HEADE FILES
-----------------------------------------------------------------------------------------------------*/
-
-#include "bsp_gpio_normal.h"
-
-/* ---------------------------------------------------------------------------------------------------
-- 	IO复用控制 -
-----------------------------------------------------------------------------------------------------*/
-typedef union gpio_fun_config
-{
-    uint32_t config;
-    struct bit
-    {
-        uint8_t b0004 : 5;
-        uint8_t b0812 : 5;
-        uint8_t b1620 : 5;
-        uint8_t b2428 : 5;
-    } bits;
-} gpio_fun_config_t;
-
-typedef struct gpio_fun_sel_config
-{
-    gpio_fun_config_t fun_sel0;
-    gpio_fun_config_t fun_sel1;
-    gpio_fun_config_t fun_sel2;
-    gpio_fun_config_t fun_sel3;
-    gpio_fun_config_t fun_sel4;
-    gpio_fun_config_t fun_sel5;
-    gpio_fun_config_t fun_sel6;
-    gpio_fun_config_t fun_sel7;
-} gpio_fun_sel_config_t;
-
-/* ---------------------------------------------------------------------------------------------------
-- 	IO功能
-----------------------------------------------------------------------------------------------------*/
-typedef union mux1_config
-{
-    uint32_t muxctl1;
-    struct bit1
-    {
-        uint8_t gpio0 : 2;
-        uint8_t gpio1 : 2;
-        uint8_t gpio2 : 2;
-        uint8_t gpio3 : 2;
-        uint8_t gpio4 : 2;
-        uint8_t gpio5 : 2;
-        uint8_t gpio6 : 2;
-        uint8_t gpio7 : 2;
-        uint8_t gpio8 : 2;
-        uint8_t gpio9 : 2;
-        uint8_t gpio10 : 2;
-        uint8_t gpio11 : 2;
-        uint8_t gpio12 : 2;
-        uint8_t gpio13 : 2;
-        uint8_t gpio14 : 2;
-        uint8_t gpio15 : 2;
-    } pad1;
-} mux1_config_t;
-
-typedef union mux2_config
-{
-    uint32_t muxctl2;
-    struct bit2
-    {
-        uint8_t gpio16 : 2;
-        uint8_t gpio17 : 2;
-        uint8_t gpio18 : 2;
-        uint8_t gpio19 : 2;
-        uint8_t gpio20 : 2;
-        uint8_t gpio21 : 2;
-        uint8_t gpio22 : 2;
-        uint8_t gpio23 : 2;
-        uint8_t gpio24 : 2;
-        uint8_t gpio25 : 2;
-        uint8_t gpio26 : 2;
-        uint8_t gpio27 : 2;
-        uint8_t gpio28 : 2;
-        uint8_t bootctl : 2;
-        uint16_t swk : 2;
-        uint8_t swd : 2;
-    } pad2;
-} mux2_config_t;
-
-typedef struct gpio_config
-{
-    mux1_config_t mux1_ctl;
-    mux2_config_t mux2_ctl;
-} gpio_config_t;
-
-/* ---------------------------------------------------------------------------------------------------
-- 	IO方向
-----------------------------------------------------------------------------------------------------*/
-typedef union dir_config
-{
-    uint32_t dir;
-    struct bitd
-    {
-        uint8_t gpio0 : 1;
-        uint8_t gpio1 : 1;
-        uint8_t gpio2 : 1;
-        uint8_t gpio3 : 1;
-        uint8_t gpio4 : 1;
-        uint8_t gpio5 : 1;
-        uint8_t gpio6 : 1;
-        uint8_t gpio7 : 1;
-        uint8_t gpio8 : 1;
-        uint8_t gpio9 : 1;
-        uint8_t gpio10 : 1;
-        uint8_t gpio11 : 1;
-        uint8_t gpio12 : 1;
-        uint8_t gpio13 : 1;
-        uint8_t gpio14 : 1;
-        uint8_t gpio15 : 1;
-        uint8_t gpio16 : 1;
-        uint8_t gpio17 : 1;
-        uint8_t gpio18 : 1;
-        uint8_t gpio19 : 1;
-        uint8_t gpio20 : 1;
-        uint8_t gpio21 : 1;
-        uint8_t gpio22 : 1;
-        uint8_t gpio23 : 1;
-        uint8_t gpio24 : 1;
-        uint8_t gpio25 : 1;
-        uint8_t gpio26 : 1;
-        uint8_t gpio27 : 1;
-        uint8_t gpio28 : 1;
-        uint8_t gpio29 : 1;
-        uint8_t gpio30 : 1;
-        uint8_t gpio31 : 1;
-    } pad;
-} dir_config_t;
-
-/* ---------------------------------------------------------------------------------------------------
-- 	IO上下拉
-----------------------------------------------------------------------------------------------------*/
-typedef union pupd1_config
-{
-    uint32_t pupd;
-    struct bita
-    {
-        uint8_t GPIO0 : 2;
-        uint8_t GPIO1 : 2;
-        uint8_t GPIO2 : 2;
-        uint8_t GPIO3 : 2;
-        uint8_t GPIO4 : 2;
-        uint8_t GPIO5 : 2;
-        uint8_t GPIO6 : 2;
-        uint8_t GPIO7 : 2;
-        uint8_t GPIO8 : 2;
-        uint8_t GPIO9 : 2;
-        uint8_t GPIO10 : 2;
-        uint8_t GPIO11 : 2;
-        uint8_t GPIO12 : 2;
-        uint8_t GPIO13 : 2;
-        uint8_t GPIO14 : 2;
-        uint8_t GPIO15 : 2;
-    } pad;
-} pupd1_config_t;
-
-typedef union pupd2_config
-{
-    uint32_t pupd;
-    struct bitb
-    {
-        uint8_t GPIO16 : 2;
-        uint8_t GPIO17 : 2;
-        uint8_t GPIO18 : 2;
-        uint8_t GPIO19 : 2;
-        uint8_t GPIO20 : 2;
-        uint8_t GPIO21 : 2;
-        uint8_t GPIO22 : 2;
-        uint8_t GPIO23 : 2;
-        uint8_t GPIO24 : 2;
-        uint8_t GPIO25 : 2;
-        uint8_t GPIO26 : 2;
-        uint8_t GPIO27 : 2;
-        uint8_t GPIO28 : 2;
-        uint8_t BOOTCTL : 2;
-        uint8_t SWCK : 2;
-        uint8_t SWD : 2;
-    } pad;
-} pupd2_config_t;
-
-typedef struct
-{
-    pupd1_config_t CTL_PECTL1;
-    pupd2_config_t CTL_PECTL2;
-} pupd_config_t;
-
-/* ---------------------------------------------------------------------------------------------------
-- 	IO中断模式
-----------------------------------------------------------------------------------------------------*/
-typedef union int_config
-{
-    uint32_t interrupt;
-    struct bitt
-    {
-        uint8_t mode0 : 4;
-        uint8_t mode1 : 4;
-        uint8_t mode2 : 4;
-        uint8_t mode3 : 4;
-        uint16_t reserved;
-    } pad;
-} int_config_t;
-
-typedef struct int_config_i
-{
-    int_config_t intr_ctl0;
-    int_config_t intr_ctl1;
-    int_config_t intr_ctl2;
-    int_config_t intr_ctl3;
-    int_config_t intr_ctl4;
-    int_config_t intr_ctl5;
-    int_config_t intr_ctl6;
-    int_config_t intr_ctl7;
-} interrupt_config_t;
-
-/* ------------------------------------------------------------------------------------------------------------------
-- 用户配置如下IO复用控制 -
-0:GPIO_Dx   1:UART0_TX  2:UART0_RX      3:UART0_CTS      4:UART0_RTS  5:I2C_SCL     6:I2C_SDA     7:UART1_RX   8:UART1_TX
-9:SIM_IO    10:SIM_RST  11:SIM_CLK_OUT  12:PWM0          13:PWM1      14:SSI1_CLK   15:SSI1_SSN   16:SSI1_RX   17:SSI1_TX
-[32/16PIN新加复用功能--18:PWM0_INV 19:PWM1_INV]
--------------------------------------------------------------------------------------------------------------------*/
-gpio_fun_sel_config_t gpio_fun_sel_config = {
-
-    /*CPR_GPIO_FUN_SEL0*/ .fun_sel0.bits.b0004 = UART1_TX, /*GPIO 0*/ .fun_sel0.bits.b0812 = UART1_RX, /*GPIO 1*/ .fun_sel0.bits.b1620 = GPIO_Dx, /*GPIO 2*/ .fun_sel0.bits.b2428 = GPIO_Dx, /*GPIO 3*/
-    /*CPR_GPIO_FUN_SEL1*/ .fun_sel1.bits.b0004 = GPIO_Dx,
-    /*GPIO 4*/ .fun_sel1.bits.b0812 = GPIO_Dx,
-    /*GPIO 5*/ .fun_sel1.bits.b1620 = GPIO_Dx,
-    /*GPIO 6*/ .fun_sel1.bits.b2428 = GPIO_Dx, /*GPIO 7*/
-    /*CPR_GPIO_FUN_SEL2*/ .fun_sel2.bits.b0004 = GPIO_Dx,
-    /*GPIO 8*/ .fun_sel2.bits.b0812 = GPIO_Dx,
-    /*GPIO 9*/ .fun_sel2.bits.b1620 = GPIO_Dx,
-    /*GPIO10*/ .fun_sel2.bits.b2428 = GPIO_Dx, /*GPIO11*/
-    /*CPR_GPIO_FUN_SEL3*/ .fun_sel3.bits.b0004 = GPIO_Dx,
-    /*GPIO12*/ .fun_sel3.bits.b0812 = GPIO_Dx,
-    /*GPIO13*/ .fun_sel3.bits.b1620 = GPIO_Dx,
-    /*GPIO14*/ .fun_sel3.bits.b2428 = GPIO_Dx, /*GPIO15*/
-    /*CPR_GPIO_FUN_SEL4*/ .fun_sel4.bits.b0004 = GPIO_Dx,
-    /*GPIO16*/ .fun_sel4.bits.b0812 = GPIO_Dx,
-    /*GPIO17*/ .fun_sel4.bits.b1620 = UART0_TX,
-    /*GPIO18*/ .fun_sel4.bits.b2428 = UART0_RX, /*GPIO19*/
-    /*CPR_GPIO_FUN_SEL5*/ .fun_sel5.bits.b0004 = GPIO_Dx,
-    /*GPIO20*/ .fun_sel5.bits.b0812 = GPIO_Dx,
-    /*GPIO21*/ .fun_sel5.bits.b1620 = PWM0_INV,
-    /*GPIO22*/ .fun_sel5.bits.b2428 = PWM0, /*GPIO23*/
-    /*CPR_GPIO_FUN_SEL6*/ .fun_sel6.bits.b0004 = PWM1_INV,
-    /*GPIO24*/ .fun_sel6.bits.b0812 = PWM1,
-    /*GPIO25*/ .fun_sel6.bits.b1620 = GPIO_Dx,
-    /*GPIO26*/ .fun_sel6.bits.b2428 = GPIO_Dx, /*GPIO27*/
-    /*CPR_GPIO_FUN_SEL7*/ .fun_sel7.bits.b0004 = GPIO_Dx,
-    /*GPIO28*/ .fun_sel7.bits.b0812 = GPIO_Dx,
-    /*GPIO29*/ .fun_sel7.bits.b1620 = GPIO_Dx,
-    /*GPIO30*/ .fun_sel7.bits.b2428 = GPIO_Dx /*GPIO31*/
-
-};
-/* ---------------------------------------------------------------------------------------------------
-- 		用户配置如下系统IO功能
-----------------------------------------------------------------------------------------------------*/
-gpio_config_t gpio_config = {
-    /*CPR_CTL_MUXCTL1*/
-    .mux1_ctl.pad1.gpio15 = 0,
-    .mux1_ctl.pad1.gpio14 = 0,
-    .mux1_ctl.pad1.gpio13 = 0,
-    .mux1_ctl.pad1.gpio12 = 0,
-    .mux1_ctl.pad1.gpio11 = 0,
-    .mux1_ctl.pad1.gpio10 = 0,
-    .mux1_ctl.pad1.gpio9 = 0,
-    .mux1_ctl.pad1.gpio8 = 0,
-    .mux1_ctl.pad1.gpio7 = 0,
-    .mux1_ctl.pad1.gpio6 = 0,
-    .mux1_ctl.pad1.gpio5 = 0,
-    .mux1_ctl.pad1.gpio4 = 0,
-    .mux1_ctl.pad1.gpio3 = 0,
-    .mux1_ctl.pad1.gpio2 = 0,
-    .mux1_ctl.pad1.gpio1 = 0,
-    .mux1_ctl.pad1.gpio0 = 0,
-    /*CPR_CTL_MUXCTL2*/
-    .mux2_ctl.pad2.swd = 0,
-    .mux2_ctl.pad2.swk = 0,
-    .mux2_ctl.pad2.bootctl = 0,
-    .mux2_ctl.pad2.gpio28 = 0,
-    .mux2_ctl.pad2.gpio27 = 0,
-    .mux2_ctl.pad2.gpio26 = 0,
-    .mux2_ctl.pad2.gpio25 = 0,
-    .mux2_ctl.pad2.gpio24 = 0,
-    .mux2_ctl.pad2.gpio23 = 0,
-    .mux2_ctl.pad2.gpio22 = 0,
-    .mux2_ctl.pad2.gpio21 = 0,
-    .mux2_ctl.pad2.gpio20 = 0,
-    .mux2_ctl.pad2.gpio19 = 0,
-    .mux2_ctl.pad2.gpio18 = 0,
-    .mux2_ctl.pad2.gpio17 = 0,
-    .mux2_ctl.pad2.gpio16 = 0};
-
-/* ---------------------------------------------------------------------------------------------------
-- 		用户配置如下系统IO的输入/输出 (0:输入1:输出)
-----------------------------------------------------------------------------------------------------*/
-dir_config_t dir_config = {
-    .pad.gpio31 = 0, .pad.gpio30 = 0, .pad.gpio29 = 0, .pad.gpio28 = 1, .pad.gpio27 = 1, .pad.gpio26 = 1, .pad.gpio25 = 0, .pad.gpio24 = 0, .pad.gpio23 = 0, .pad.gpio22 = 0, .pad.gpio21 = 0, .pad.gpio20 = 0, .pad.gpio19 = 0, .pad.gpio18 = 0, .pad.gpio17 = 0, .pad.gpio16 = 0, .pad.gpio15 = 0, .pad.gpio14 = 0, .pad.gpio13 = 0, .pad.gpio12 = 0, .pad.gpio11 = 0, .pad.gpio10 = 0, .pad.gpio9 = 0, .pad.gpio8 = 0, .pad.gpio7 = 0, .pad.gpio6 = 0, .pad.gpio5 = 0, .pad.gpio4 = 0, .pad.gpio3 = 0, .pad.gpio2 = 0, .pad.gpio1 = 0, .pad.gpio0 = 0};
-
-/* ---------------------------------------------------------------------------------------------------
-- 	用户配置IO上下拉
-----------------------------------------------------------------------------------------------------*/
-pupd_config_t pupd_config = {
-    .CTL_PECTL1.pad.GPIO15 = 0, .CTL_PECTL1.pad.GPIO14 = 0, .CTL_PECTL1.pad.GPIO13 = 0, .CTL_PECTL1.pad.GPIO12 = 3, .CTL_PECTL1.pad.GPIO11 = 3, .CTL_PECTL1.pad.GPIO10 = 3, .CTL_PECTL1.pad.GPIO9 = 3, .CTL_PECTL1.pad.GPIO8 = 3, .CTL_PECTL1.pad.GPIO7 = 3, .CTL_PECTL1.pad.GPIO6 = 3, .CTL_PECTL1.pad.GPIO5 = 3, .CTL_PECTL1.pad.GPIO4 = 0, .CTL_PECTL1.pad.GPIO3 = 0, .CTL_PECTL1.pad.GPIO2 = 0, .CTL_PECTL1.pad.GPIO1 = 0, .CTL_PECTL1.pad.GPIO0 = 0,
-
-    .CTL_PECTL2.pad.SWD = 3,
-    .CTL_PECTL2.pad.SWCK = 3,
-    .CTL_PECTL2.pad.BOOTCTL = 0,
-    .CTL_PECTL2.pad.GPIO28 = 0,
-    .CTL_PECTL2.pad.GPIO27 = 0,
-    .CTL_PECTL2.pad.GPIO26 = 0,
-    .CTL_PECTL2.pad.GPIO25 = 0,
-    .CTL_PECTL2.pad.GPIO24 = 1,
-    .CTL_PECTL2.pad.GPIO23 = 0,
-    .CTL_PECTL2.pad.GPIO22 = 3,
-    .CTL_PECTL2.pad.GPIO21 = 3,
-    .CTL_PECTL2.pad.GPIO20 = 3,
-    .CTL_PECTL2.pad.GPIO19 = 3,
-    .CTL_PECTL2.pad.GPIO18 = 3,
-    .CTL_PECTL2.pad.GPIO17 = 3,
-    .CTL_PECTL2.pad.GPIO16 = 0};
-
-/* ---------------------------------------------------------------------------------------------------
-- 用户配置如下系统IO的中断模式 NOT_INT(无中断)  RIS_EDGE_INT(上升沿中断)  FAIL_EDGE_INT(下降沿中断)
-----------------------------------------------------------------------------------------------------*/
-interrupt_config_t interrupt_config = {
-    /*GPIO_INTR_CTRL0*/ .intr_ctl0.pad.mode3 = NOT_INT, /*GPIO 3*/ .intr_ctl0.pad.mode2 = NOT_INT, /*GPIO 2*/ .intr_ctl0.pad.mode1 = NOT_INT, /*GPIO 1*/ .intr_ctl0.pad.mode0 = NOT_INT, /*GPIO 0*/
-    /*GPIO_INTR_CTRL1*/ .intr_ctl1.pad.mode3 = NOT_INT,
-    /*GPIO 7*/ .intr_ctl1.pad.mode2 = NOT_INT,
-    /*GPIO 6*/ .intr_ctl1.pad.mode1 = NOT_INT,
-    /*GPIO 5*/ .intr_ctl1.pad.mode0 = NOT_INT, /*GPIO 4*/
-    /*GPIO_INTR_CTRL2*/ .intr_ctl2.pad.mode3 = NOT_INT,
-    /*GPIO11*/ .intr_ctl2.pad.mode2 = NOT_INT,
-    /*GPIO10*/ .intr_ctl2.pad.mode1 = NOT_INT,
-    /*GPIO 9*/ .intr_ctl2.pad.mode0 = NOT_INT, /*GPIO 8*/
-    /*GPIO_INTR_CTRL3*/ .intr_ctl3.pad.mode3 = NOT_INT,
-    /*GPIO15*/ .intr_ctl3.pad.mode2 = NOT_INT,
-    /*GPIO14*/ .intr_ctl3.pad.mode1 = NOT_INT,
-    /*GPIO13*/ .intr_ctl3.pad.mode0 = NOT_INT, /*GPIO12*/
-    /*GPIO_INTR_CTRL4*/ .intr_ctl4.pad.mode3 = NOT_INT,
-    /*GPIO19*/ .intr_ctl4.pad.mode2 = NOT_INT,
-    /*GPIO18*/ .intr_ctl4.pad.mode1 = NOT_INT,
-    /*GPIO17*/ .intr_ctl4.pad.mode0 = NOT_INT, /*GPIO16*/
-    /*GPIO_INTR_CTRL5*/ .intr_ctl5.pad.mode3 = NOT_INT,
-    /*GPIO23*/ .intr_ctl5.pad.mode2 = NOT_INT,
-    /*GPIO22*/ .intr_ctl5.pad.mode1 = NOT_INT,
-    /*GPIO21*/ .intr_ctl5.pad.mode0 = NOT_INT, /*GPIO20*/
-    /*GPIO_INTR_CTRL6*/ .intr_ctl6.pad.mode3 = NOT_INT,
-    /*GPIO27*/ .intr_ctl6.pad.mode2 = NOT_INT,
-    /*GPIO26*/ .intr_ctl6.pad.mode1 = NOT_INT,
-    /*GPIO25*/ .intr_ctl6.pad.mode0 = NOT_INT, /*GPIO24*/
-    /*GPIO_INTR_CTRL7*/ .intr_ctl7.pad.mode3 = NOT_INT,
-    /*GPIO31*/ .intr_ctl7.pad.mode2 = NOT_INT,
-    /*GPIO30*/ .intr_ctl7.pad.mode1 = NOT_INT,
-    /*GPIO29*/ .intr_ctl7.pad.mode0 = NOT_INT, /*GPIO28*/
-};
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: Init_gpio
-- 函数功能: Gpio模块初始化
-- 输入参数: 无
-- 创建日期: 2016-05-24
-----------------------------------------------------------------------------------------------------*/
-extern void Init_gpio(void)
-{
-
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x40004);
-    __write_hw_reg32(CPR_OTHERCLKEN_GRCTL, 0x10001);
-    for(int i=0;i<35;i++)
-    {
-        gpio_direction_input(i,1);
-    }
-#if (TEST_SPI1_MASTER_A == 1 && TEST_SPI1_MASTER_B == 0 && TEST_SPI1_MASTER_C == 0)   /*四根SPI线全采用模拟方式*/
-    gpio_fun_sel_config.fun_sel3.bits.b0812 = GPIO_Dx;                                // GPIO13复用功能
-    gpio_fun_sel_config.fun_sel3.bits.b1620 = GPIO_Dx;                                // GPIO14复用功能
-    gpio_fun_sel_config.fun_sel3.bits.b2428 = GPIO_Dx;                                // GPIO15复用功能
-    gpio_fun_sel_config.fun_sel4.bits.b0004 = GPIO_Dx;                                // GPIO16复用功能
-#elif (TEST_SPI1_MASTER_A == 0 && TEST_SPI1_MASTER_B == 1 && TEST_SPI1_MASTER_C == 0) /*CS (SSN) 线采用模拟方式*/
-    gpio_fun_sel_config.fun_sel3.bits.b0812 = SSI1_CLK; // GPIO13复用功能
-    gpio_fun_sel_config.fun_sel3.bits.b1620 = GPIO_Dx;  // GPIO14复用功能
-    gpio_fun_sel_config.fun_sel3.bits.b2428 = SSI1_RX;  // GPIO15复用功能
-    gpio_fun_sel_config.fun_sel4.bits.b0004 = SSI1_TX;  // GPIO16复用功能
-#else
-    // gpio_fun_sel_config.fun_sel3.bits.b0812 = SSI1_CLK; //GPIO13复用功能
-    // gpio_fun_sel_config.fun_sel3.bits.b1620 = SSI1_SSN; //GPIO14复用功能
-    // gpio_fun_sel_config.fun_sel3.bits.b2428 = SSI1_RX;  //GPIO15复用功能
-    // gpio_fun_sel_config.fun_sel4.bits.b0004 = SSI1_TX;  //GPIO16复用功能
-    gpio_fun_sel_config.fun_sel0.bits.b0004 = SSI1_CLK, /*GPIO 0*/ gpio_fun_sel_config.fun_sel0.bits.b0812 = SSI1_SSN,   /*GPIO 1*/
-        gpio_fun_sel_config.fun_sel1.bits.b0004 = SSI1_RX, /*GPIO 4*/ gpio_fun_sel_config.fun_sel1.bits.b0812 = SSI1_TX, /*GPIO 5*/
-#endif
-
-
-    __write_hw_reg32(CPR_GPIO_FUN_SEL0, gpio_fun_sel_config.fun_sel0.config);
-    __write_hw_reg32(CPR_GPIO_FUN_SEL1, gpio_fun_sel_config.fun_sel1.config);
-    __write_hw_reg32(CPR_GPIO_FUN_SEL2, gpio_fun_sel_config.fun_sel2.config);
-    __write_hw_reg32(CPR_GPIO_FUN_SEL3, gpio_fun_sel_config.fun_sel3.config);
-    __write_hw_reg32(CPR_GPIO_FUN_SEL4, gpio_fun_sel_config.fun_sel4.config);
-    __write_hw_reg32(CPR_GPIO_FUN_SEL5, gpio_fun_sel_config.fun_sel5.config);
-    __write_hw_reg32(CPR_GPIO_FUN_SEL6, gpio_fun_sel_config.fun_sel6.config);
-    __write_hw_reg32(CPR_GPIO_FUN_SEL7, gpio_fun_sel_config.fun_sel7.config);
-
-    __write_hw_reg32(CPR_CTL_MUXCTL1, gpio_config.mux1_ctl.muxctl1);
-    __write_hw_reg32(CPR_CTL_MUXCTL2, gpio_config.mux2_ctl.muxctl2);
-
-    __write_hw_reg32(GPIO_PORT_DDR0, (0xFFFF0000 | ((dir_config.dir) & 0xFFFF)));
-    __write_hw_reg32(GPIO_PORT_DDR1, (0xFFFF0000 | ((dir_config.dir) >> 16)));
-
-    //__write_hw_reg32(CPR_CTL_PECTL1, pupd_config.CTL_PECTL1.pupd);
-    //__write_hw_reg32(CPR_CTL_PECTL2, pupd_config.CTL_PECTL2.pupd);
-
-    __write_hw_reg32(GPIO_INTR_CTRL0, (0xF0000 | (interrupt_config.intr_ctl0.interrupt)));
-    __write_hw_reg32(GPIO_INTR_CTRL1, (0xF0000 | (interrupt_config.intr_ctl1.interrupt)));
-    __write_hw_reg32(GPIO_INTR_CTRL2, (0xF0000 | (interrupt_config.intr_ctl2.interrupt)));
-    __write_hw_reg32(GPIO_INTR_CTRL3, (0xF0000 | (interrupt_config.intr_ctl3.interrupt)));
-    __write_hw_reg32(GPIO_INTR_CTRL4, (0xF0000 | (interrupt_config.intr_ctl4.interrupt)));
-    __write_hw_reg32(GPIO_INTR_CTRL5, (0xF0000 | (interrupt_config.intr_ctl5.interrupt)));
-    __write_hw_reg32(GPIO_INTR_CTRL6, (0xF0000 | (interrupt_config.intr_ctl6.interrupt)));
-    __write_hw_reg32(GPIO_INTR_CTRL7, (0xF0000 | (interrupt_config.intr_ctl7.interrupt)));
-
-    NVIC_EnableIRQ(GPIO_IRQn);
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: gpio_mux_ctl (0-31)
-- 函数功能: pin脚连接控制
-- 输入参数: mux
-- 创建日期: 2021-5-18
-- GPIO0 : 【mux=0 连接到gpio_d[0] 】 【mux=1 kbs_mko_0】        【mux=2 pwm2】       【mux=3 NA】
-- GPIO1 : 【mux=0 连接到gpio_d[1] 】 【mux=1 kbs_mko_1】        【mux=2 pwm3】       【mux=3 NA】
-- GPIO2 : 【mux=0 连接到gpio_d[2] 】 【mux=1 kbs_mko_2】        【mux=2 clk_12M_out】【mux=3 NA】
-- GPIO3 : 【mux=0 连接到gpio_d[3] 】 【mux=1 kbs_mko_3】        【mux=2 NA】         【mux=3 NA】
-- GPIO4 : 【mux=0 连接到gpio_d[4] 】 【mux=1 kbs_mko_4】        【mux=2 NA】         【mux=3 NA】
-- GPIO5 : 【mux=0 连接到gpio_d[5] 】 【mux=1 kbs_mko_5】        【mux=2 NA】         【mux=3 NA】
-- GPIO6 : 【mux=0 连接到gpio_d[6] 】 【mux=1 kbs_mko_6】        【mux=2 txen】       【mux=3 NA】
-- GPIO7 : 【mux=0 连接到gpio_d[7] 】 【mux=1 kbs_mko_7】        【mux=2 rxen】       【mux=3 NA】
-- GPIO8 : 【mux=0 连接到gpio_d[8] 】 【mux=1 kbs_mki_0】        【mux=2 NA】         【mux=3 NA】
-- GPIO9 : 【mux=0 连接到gpio_d[9] 】 【mux=1 kbs_mki_1】        【mux=2 NA】         【mux=3 NA】
-- GPIO10: 【mux=0 连接到gpio_d[10]】 【mux=1 kbs_mki_8】        【mux=2 NA】         【mux=3 NA】
-- GPIO11: 【mux=0 连接到BOOT_CTL0 】 【mux=1 连接到gpio_d[11]】 【mux=2 NA】         【mux=3 NA】
-- GPIO12: 【mux=0 连接到SWI的 SWCK】 【mux=1 连接到gpio_d[12]】 【mux=2 NA】         【mux=3 pwm4】
-- GPIO13: 【mux=0 连接到SWI的 SWD 】 【mux=1 连接到gpio_d[13]】 【mux=2 NA】         【mux=3 pwm5】
-- GPIO14: 【mux=0 连接到gpio_d[14]】 【mux=1 kbs_mki_9】        【mux=2 SPI2_CLK】   【mux=3 NA】
-- GPIO15: 【mux=0 连接到gpio_d[15]】 【mux=1 kbs_mki_10】       【mux=2 SPI2_CS】    【mux=3 NA】
-- GPIO16: 【mux=0 连接到gpio_d[16]】 【mux=1 kbs_mki_11】       【mux=2 SPI2_RX】    【mux=3 NA】
-- GPIO17: 【mux=0 连接到gpio_d[17]】 【mux=1 kbs_mki_12】       【mux=2 SPI2_TX】    【mux=3 NA】
-- GPIO18: 【mux=0 连接到gpio_d[18]】 【mux=1 kbs_mki_16】       【mux=2 NA】         【mux=3 NA】
-- GPIO19: 【mux=0 连接到gpio_d[19]】 【mux=1 kbs_mki_17】       【mux=2 NA】         【mux=3 NA】
-- GPIO20: 【mux=0 连接到gpio_d[20]】 【mux=1 kbs_mki_2】        【mux=2 NA】         【mux=3 NA】
-- GPIO21: 【mux=0 连接到gpio_d[21]】 【mux=1 kbs_mki_3】        【mux=2 NA】         【mux=3 NA】
-- GPIO22: 【mux=0 连接到gpio_d[22]】 【mux=1 kbs_mki_4】        【mux=2 ssi2_clk】   【mux=3 NA】
-- GPIO23: 【mux=0 连接到gpio_d[23]】 【mux=1 kbs_mki_5】        【mux=2 ssi2_ssn】   【mux=3 NA】
-- GPIO24: 【mux=0 连接到gpio_d[24]】 【mux=1 kbs_mki_6】        【mux=2 ssi2_d0 tx】 【mux=3 NA】
-- GPIO25: 【mux=0 连接到gpio_d[25]】 【mux=1 kbs_mki_7】        【mux=2 ssi2_d1 rx】 【mux=3 NA】
-- GPIO26: 【mux=0 连接到gpio_d[26]】 【mux=1 kbs_mki_13】       【mux=2 ssi2_d2】    【mux=3 NA】
-- GPIO27: 【mux=0 连接到gpio_d[27]】 【mux=1 kbs_mki_14】       【mux=2 ssi2_d3】    【mux=3 NA】
-- GPIO28: 【mux=0 连接到gpio_d[28]】 【mux=1 kbs_mki_15】       【mux=2 adcclk】     【mux=3 NA】
-- GPIO29: 【mux=0 连接到gpio_d[29]】 【mux=1 kbs_mki_16】       【mux=2 adcdata】    【mux=3 NA】
-- GPIO30: 【mux=0 连接到gpio_d[30]】 【mux=1 kbs_mki_17】       【mux=2 i2s_sclk】   【mux=3 NA】
-- GPIO31: 【mux=0 连接到gpio_d[31]】 【mux=1  uart2_rx】        【mux=2 i2s_ws】     【mux=3 NA】
-- GPIO32: 【mux=0 连接到gpio_d[27]】 【mux=1  uart2_tx】        【mux=2 i2s_din】    【mux=3 NA】
-- GPIO33: 【mux=0 连接到gpio_d[28]】 【mux=1  NA】              【mux=2 i2s_dout】   【mux=3 NA】
-- GPIO34: 【mux=0 连接到gpio_d[29]】 【mux=1  NA】              【mux=2 NA】         【mux=3 NA】
-- GPIO35: 【mux=0 连接到gpio_d[30]】 【mux=1  NA】              【mux=2 BOOT_CTL1】  【mux=3 NA】
-- ----------------------------------------------------------------------------------------------------*/
-extern void gpio_mux_ctl(uint8_t num, uint8_t mux) //(num:0-31)
-{
-    if (mux > 3)
-        return;
-    uint32_t temp = 0;
-    __read_hw_reg32((CPR_CTL_MUXCTL1 + (num / 16)), temp);
-    temp = (temp & (~(0x3 << ((num % 16) * 2)))) | (mux << ((num % 16) * 2));
-    __write_hw_reg32((CPR_CTL_MUXCTL1 + (num / 16)), temp);
-}
-extern void gpio_mux_ctl_u(uint8_t num, uint8_t mux) //(num:32-34)
-{
-    if (mux > 3)
-        return;
-    uint32_t temp = 0;
-    __read_hw_reg32(CPR_CTL_MUXCTL3, temp);
-    temp = (temp & (~(0x3 << ((num % 16) * 2)))) | (mux << ((num % 16) * 2));
-    __write_hw_reg32(CPR_CTL_MUXCTL3, temp);
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: gpio_fun_inter  (0-34)
-- 函数功能: gpio中断模式设置
-- 输入参数: gpio编号0-28  中断类型0无中断 5上升沿中断 7下降沿中断
-- 创建日期: 2019-12-03
-----------------------------------------------------------------------------------------------------*/
-extern void gpio_fun_inter(uint8_t num, uint8_t inter)
-{
-    unsigned int temp = 0;
-    if (inter > 0xF)
-        return;
-    switch (num % 4)
-    {
-    case 3:
-        __read_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), temp);
-        temp &= 0x0FFF;
-        temp |= ((inter << 12) | 0xF0000);
-        __write_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), temp);
-        break;
-    case 2:
-        __read_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), temp);
-        temp &= 0xF0FF;
-        temp |= ((inter << 8) | 0xF0000);
-        __write_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), temp);
-        break;
-    case 1:
-        __read_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), temp);
-        temp &= 0xFF0F;
-        temp |= ((inter << 4) | 0xF0000);
-        __write_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), temp);
-        break;
-    case 0:
-        __read_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), temp);
-        temp &= 0xFFF0;
-        temp |= ((inter) | 0xF0000);
-        __write_hw_reg32((GPIO_INTR_CTRL0 + (num / 4)), temp);
-        break;
-    default:
-        break;
-    }
-}
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: gpio_fun_sel  (0-28)
-- 函数功能: gpio复用功能设置
-- 输入参数: gpio编号0-28 sel复用【0:GPIO_Dx】  【1:UART0_TX】 【2:UART0_RX】 【3:UART0_CTS】【4:UART0_RTS】【5:I2C_SCL】
-                                【6:I2C_SDA】  【7:UART1_RX】 【8:UART1_TX】 【9:SIM_IO】   【10:SIM_RST】 【11:SIM_CLK_OUT】
-                                【12:PWM0】    【13:PWM1】    【14:SSI1_CLK】【15:SSI1_SSN】【16:SSI1_RX】 【17:SSI1_TX】
-                                【18:PWM0_INV】【19:PWM1_INV】【20:PWM2_INV】【21:PWM3_INV】
-- 创建日期: 2019-12-03
-----------------------------------------------------------------------------------------------------*/
-extern void gpio_fun_sel(uint8_t num, uint8_t sel) //(num:0-28)
-{
-
-    unsigned int temp = 0;
-    if (sel > 21)
-        return;
-    switch (num % 4)
-    {
-    case 0:
-        __read_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), temp);
-        temp &= 0xFFFFFF00;
-        temp |= sel;
-        __write_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), temp);
-        break;
-    case 1:
-        __read_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), temp);
-        temp &= 0xFFFF00FF;
-        temp |= (sel << 8);
-        __write_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), temp);
-        break;
-    case 2:
-        __read_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), temp);
-        temp &= 0xFF00FFFF;
-        temp |= (sel << 16);
-        __write_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), temp);
-        break;
-    case 3:
-        __read_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), temp);
-        temp &= 0x00FFFFFF;
-        temp |= (sel << 24);
-        __write_hw_reg32((CPR_GPIO_FUN_SEL0 + (num / 4)), temp);
-        break;
-    default:
-        break;
-    }
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: gpio_output_high
-- 函数功能: Gpio输出高电平
-- 输入参数: gpio编号 (< 29)
-- 创建日期: 2016-05-24
-----------------------------------------------------------------------------------------------------*/
-extern void gpio_output_high(uint8_t num)
-{
-
-    __write_hw_reg32((GPIO_PORT_DR0 + (num >> 4)), (0x00010001 << (num & 0x0F)));
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: gpio_output_low
-- 函数功能: Gpio输出低电平
-- 输入参数: gpio编号  (< 29)
-- 创建日期: 2016-05-24
-----------------------------------------------------------------------------------------------------*/
-extern void gpio_output_low(uint8_t num)
-{
-
-    __write_hw_reg32((GPIO_PORT_DR0 + (num >> 4)), (0x00010000 << (num & 0x0F)));
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: GPIO_Handler  (0-34)
-- 函数功能: GPIO0中断处理函数
-- 输入参数: 无
-- 创建日期: 2016-05-26
-----------------------------------------------------------------------------------------------------*/
-extern void GPIO_Handler(void)
-{
-    uint32_t val[2];
-    __read_hw_reg32(GPIO_INTR_STATUS_C00, val[0]);
-    __read_hw_reg32(GPIO_INTR_STATUS_C01, val[1]);
-    __write_hw_reg32(GPIO_INTR_CLR0, val[0]);
-    __write_hw_reg32(GPIO_INTR_CLR1, val[1]);
-    if (DETECT_INTER_NUM(24, val)) // 判断是否为GPIO24中断
-    {
-        // printf("GPIO24 interrupt\n");
-    }
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: gpio_input_val
-- 函数功能: 获取GPIO管脚状态
-- 输入参数: gpio编号(0-34)
-- 输出参数: 高低电平值
-- 创建日期: 2016-06-07
-----------------------------------------------------------------------------------------------------*/
-extern uint8_t gpio_input_val(uint8_t num)
-{
-    uint32_t val;
-    __read_hw_reg32((GPIO_EXT_PORT0 + (num >> 5)), val);
-    return (val & (0x01L << (num & 0x1F))) ? (1) : (0);
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: gpio_direction_output
-- 函数功能: 设置GPIO管脚方向为输出
-- 输入参数: gpio编号(0-34)
-- 创建日期: 2016-06-07
-----------------------------------------------------------------------------------------------------*/
-extern void gpio_direction_output(uint8_t num)
-{
-    __write_hw_reg32((GPIO_PORT_DDR0 + (num >> 4)), ((0x10001) << (num & 0x0F)));
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: gpio_direction_input (pe_ctrl1: 0x40002400+0x34)(pe_ctrl2:0x40002400+0x38)(pu_ctrl1:0x40002400+0x3c)
-- 函数功能: 设置GPIO管脚方向为输入
-- 输入参数: gpio编号(0-34) 上下拉状态(0代表上拉 1代表下拉 其他代表无上下拉）
--【pull_up_type=0  GPIO上拉:GPIO_Mode_Input_Up   】
--【pull_up_type=1  GPIO下拉:GPIO_Mode_Input_Down 】
--【pull_up_type=2  GPIO浮空:GPIO_Mode_Input_Float】
-- 创建日期: 2021-05-18
-----------------------------------------------------------------------------------------------------*/
-extern void gpio_direction_input(uint8_t num, uint8_t pull_up_type)
-{
-    uint8_t temp_num = num;
-    uint32_t val;
-    uint32_t *base_reg = 0x0;
-    // uint32_t pos = (num&0x0f)<<1;
-
-    if (num > 0 && num <= 15)
-    {
-        base_reg = (uint32_t *)(0x40002400 + 0x34);
-    }
-    else if (num >= 16 && num <= 31)
-    {
-        base_reg = (uint32_t *)(0x40002400 + 0x38);
-        num = num % 16;
-    }
-    else if (num >= 32 && num <= 34)
-    {
-        base_reg = (uint32_t *)(0x40002400 + 0x3c);
-        num = 2 + num % 16;
-    }
-
-    __read_hw_reg32(base_reg, val);
-    if (pull_up_type == 1) // 下拉
-    {
-        setbit(val, num * 2);
-        clrbit(val, num * 2 + 1);
-    }
-    else if (pull_up_type == 0) // 上拉
-    {
-        clrbit(val, num * 2);
-        setbit(val, num * 2 + 1);
-    }
-
-    else // 无上下拉
-    {
-        clrbit(val, num * 2);
-        clrbit(val, num * 2 + 1);
-    }
-    __write_hw_reg32(base_reg, val);
-
-    __write_hw_reg32((GPIO_PORT_DDR0 + (temp_num >> 4)), ((0x10000) << (temp_num & 0x0F)));
-    __write_hw_reg32((GPIO_DEBOUNCE0 + (temp_num >> 4)), ((0x10001) << (temp_num & 0x0F)));
-}

component/boot2/bsp/bsp_gpio_normal.h

@@ -1,56 +0,0 @@
-#ifndef		__BSP_GPIO_H_
-#define		__BSP_GPIO_H_
-
-#include	"xinc_m0.h"
-
-
-
-#define    DETECT_INTER_NUM(num,val)              ((num>=32)?((val[1]>>(num&0x1F))&0x01):((val[0]>>num)&0x01))
-typedef enum{
- NOT_INT=0,
- NA1_INT,
- NA2_INT,
- NA3_INT,
- NA4_INT,
- RIS_EDGE_INT,//ÉÏÉýÑØ
- NA6_INT,
- FAIL_EDGE_INT,//ϽµÑØ
- 
-}GPIO_INT_TypeDef;
-typedef enum{
- GPIO_Dx=0,//
- UART0_TX,
- UART0_RX,
- UART0_CTS,
- UART0_RTS,
- I2C_SCL,
- I2C_SDA,
- UART1_RX,
- UART1_TX,
- SIM_IO,
- SIM_RST,
- SIM_CLK_OUT,
- PWM0,
- PWM1,
- SSI1_CLK,
- SSI1_SSN,
- SSI1_RX,
- SSI1_TX,
- PWM0_INV,  
- PWM1_INV, 
- PWM2_INV,  
- PWM3_INV,	
-}GPIO_FUN_SEL_TypeDef;
-  
-extern	void	    Init_gpio(void);
-extern	void	    gpio_output_high(uint8_t num);
-extern	void	    gpio_output_low(uint8_t	num);
-extern  void        gpio_mux_ctl_u(uint8_t num,uint8_t mux);  
-extern	uint8_t		gpio_input_val(uint8_t num);
-extern	void		gpio_direction_output(uint8_t num);
-extern	void		gpio_direction_input(uint8_t gpio_id, uint8_t pull_up_enable);
-extern  void        gpio_mux_ctl(uint8_t num,uint8_t mux);
-extern  void        gpio_fun_inter(uint8_t num,uint8_t inter);
-extern  void        gpio_fun_sel(uint8_t num,uint8_t sel);
-#endif
-

component/boot2/bsp/bsp_i2c_slave.c

@@ -1,216 +0,0 @@
-
-#include    "Includes.h"
-
-
-
-
-#if 1
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: i2c_master_StatusCheck
-- 函数功能: 状态检测
-- 输入参数: 第几bit; 对应bit上的值
-- 创建日期: 
-----------------------------------------------------------------------------------------------------*/
-static	void	i2c_master_StatusCheck(uint8_t	nbit, uint8_t bitval)
-{
-	uint8_t	val;
-	
-	for(; ;)	{
-		__read_hw_reg32(I2C_STATUS , val);
-		if( bitval == ((val>>nbit)&0x01) ) break;
-	}	
-
-}
-
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: i2c_slave_init
-- 函数功能: 初始化i2c SLAVE模式
-- 输入参数: i2c器件地址
-- 创建日期: 
-----------------------------------------------------------------------------------------------------*/
-extern	void	i2c_slave_init(uint16_t	i2cAddR)
-{
-	__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x8000800);
-	__write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x400000);
-	__write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x400040);
-	__write_hw_reg32(CPR_I2C_CLK_CTL, 0x110011);                //-> i2c_mclk = 16mhz.
-    
-    i2c_master_StatusCheck(0, 0);
-	__write_hw_reg32(I2C_ENABLE, 0x00);  
-	__write_hw_reg32(I2C_SAR, i2cAddR);		
-
-	__write_hw_reg32(I2C_RX_TL, 0x00);
-	__write_hw_reg32(I2C_TX_TL, 0x00);
-		
-	__write_hw_reg32(I2C_CON, 0x00);
-   
- 	__write_hw_reg32(I2C_INTR_EN, (I2C_SLAVE_RX_DONE | I2C_SLAVE_RD_REQ | I2C_SLAVE_RX_FULL | I2C_SLAVE_STOP )); 
-    
-    __write_hw_reg32(I2C_FS_SCL_HCNT, 12);
-    __write_hw_reg32(I2C_FS_SCL_LCNT, 19); 
-    __write_hw_reg32(I2C_SS_SCL_HCNT, 72);
-    __write_hw_reg32(I2C_SS_SCL_LCNT, 79); 
-
-    i2c_master_StatusCheck(0, 0);
-    __write_hw_reg32(I2C_ENABLE, 0x1);
-    
-    NVIC_EnableIRQ(I2C_IRQn);
-
-}
-#define SELVE_ADDRESS 0xA0
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: I2C_Handler
-- 函数功能: I2C中断处理函数
-- 输入参数: 无
-- 创建日期: 
-----------------------------------------------------------------------------------------------------*/
-extern	void	I2C_Handler(void)
-{
-    uint32_t    stat, VAL;
-    
-     __read_hw_reg32(I2C_INTR_STAT, stat);
-     printf("stat=%#x =>",stat);                                                                                                    //if(stat == 0) return; //if(stat & 0x200) __read_hw_reg32(I2C_CLR_STOP_DET, VAL);//-读 此 寄 存 器 清 除 中 断STOP_DET    //if(stat & 0x40)  __read_hw_reg32(I2C_CLR_TX_ABRT, VAL); //- 读此寄存器清除中断 TX_ABRT
-     __read_hw_reg32(I2C_CLR_INTR, VAL);//- 清除中断 读此寄存器清除组合中断，各个独立中断以及I2C_TX_ABRT_SOURCE 寄存器   
-     if(stat & 0x80)//RX_DONE-作为 slave 发送数据时，如果master 没有响应的话，在发送最后一个字节后产生此中断，表示发送结束
-     {                            
-         printf("RX_DONE--%#x\n",*(I2C_DATA_CMD));  
-     }    
-     if(stat & 0x200)//IIC 停止信号  --STOP_DET  结束条件标志 1：总线出现结束条件  0：无效
-     {         
-         printf("STOP_DET--%#x\n",*(I2C_DATA_CMD));  
-     } 
-     if(stat & 0x4) //从站收到主站的发送的寄存器地址 (并应答主机的读或写的请求)--RX_FULL RX FIFO 满标志 1：RX FIFO 数据大于或者等于 RX FIFO 阈值。此比特随 FIFO状态自动更新  0：无效
-     {
-        uint8_t val= *(I2C_DATA_CMD);        
-        if(val==(1)) //寄存器地址
-        {
-            *(I2C_DATA_CMD)=0xCC;
-        }else if(val==0x02)  //寄存器地址
-        {
-           printf("*****write - %#2x\n",*(I2C_DATA_CMD));
-        }
-        else
-        {
-        
-        }            
-        printf("RX_FULL--%#2x\n",val); 
-     } 
-     if(stat & 0x20) //RD_REQ  //从站收到主站的再次读请求中断，    
-     {   //作为 slave，当另外一个 master尝试从 slave 读数据时产生此中断。Slave 保持 I2C 总线为等待状态（SCL=0）直到中断服务被响应。
-         //这表示 slave 被远端的master 寻址，并且要求其发送数据。处理器必须响应这个中断，并 将 待 发 送 的 数 据 写 入I2C_DATA_CMD 寄存器  
-         static uint8_t count=1;
-         *(I2C_DATA_CMD)=count;
-         printf("RD_REQ--%#x\n",count++); 
-     } 
-}
-
-void test_slave_i2c()
-{
-    //IIC 主机命令1 是读，0是写  空闲状态下IIC 的SCL SDA都为高电平 等待时擎住SCL线到低电平
-    gpio_mux_ctl(4,0);gpio_fun_inter(4,0);gpio_fun_sel(4,6);//sda  6:I2C_SDA
-    gpio_mux_ctl(5,0);gpio_fun_inter(5,0);gpio_fun_sel(5,5);//scl  5:I2C_SCL
-    //i2c_slave_init(0x3D);//IIC上位机侦测的IIC从机地址为0x7A(等于0x3D<<1)
-    i2c_slave_init((SELVE_ADDRESS>>1));
-    
-    while(1);
-
-}
-
-#else
-
-
-i2cHandler_callback_t   i2cHandler_Callback = (i2cHandler_callback_t)0;
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: i2c_slave_init
-- 函数功能: 初始化i2c SLAVE模式
-- 输入参数: i2c器件地址
-- 创建日期: 
-----------------------------------------------------------------------------------------------------*/
-extern	void	i2c_slave_init(uint16_t	i2cAddR)
-{
-	__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x8000800);
-
-	__write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x400000);
-	__write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x400040);
-
-	__write_hw_reg32(CPR_I2C_CLK_CTL, 0x110011);                //-> i2c_mclk = 16mhz.
-
-	__write_hw_reg32(I2C_ENABLE, 0x00);  
-	__write_hw_reg32(I2C_SAR, i2cAddR);		
-
-	__write_hw_reg32(I2C_RX_TL, 0x00);
-	__write_hw_reg32(I2C_TX_TL, 0x00);
-		
-	__write_hw_reg32(I2C_CON, 0x00);
-   
- 	__write_hw_reg32(I2C_INTR_EN, (I2C_SLAVE_RX_DONE | I2C_SLAVE_RD_REQ | I2C_SLAVE_RX_FULL | I2C_SLAVE_STOP )); 
-    
-    
-    __write_hw_reg32(I2C_ENABLE, 0x1);
-    
-    NVIC_EnableIRQ(I2C_IRQn);
-
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: i2c_slave_Register_Callback
-- 函数功能: 为i2c从设备注册中断回调函数
-- 输入参数: 中断状态值
-- 创建日期: 
-----------------------------------------------------------------------------------------------------*/
-extern	void	i2c_slave_Register_Callback(i2cHandler_callback_t callback)
-{
-    i2cHandler_Callback = callback;
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: i2c_slave_WriteSingle
-- 函数功能: 为i2c从设备发送数据
-- 输入参数: 发送的数据
-- 创建日期: 
-----------------------------------------------------------------------------------------------------*/
-extern  void    i2c_slave_WriteSingle(uint8_t val)
-{
-    __write_hw_reg32(I2C_DATA_CMD, val);
-}
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: i2c_slave_ReadSingle
-- 函数功能: 为i2c从设备获取数据
-- 输入参数: 无
-- 创建日期: 
-----------------------------------------------------------------------------------------------------*/
-extern  uint8_t    i2c_slave_ReadSingle(void)
-{
-    uint8_t     val;
-    __read_hw_reg32(I2C_DATA_CMD, val);
-    
-    return (val);
-}
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: I2C_Handler
-- 函数功能: I2C中断处理函数
-- 输入参数: 无
-- 创建日期: 
-----------------------------------------------------------------------------------------------------*/
-extern	void	I2C_Handler(void)
-{
-    uint32_t    stat, VAL;
-    
-    __read_hw_reg32(I2C_INTR_STAT, stat);
-    if(stat == 0) return;
-    
-    if(stat & 0x200) __read_hw_reg32(I2C_CLR_STOP_DET, VAL);    
-    if(stat & 0x40)  __read_hw_reg32(I2C_CLR_TX_ABRT, VAL);
-    __read_hw_reg32(I2C_CLR_INTR, VAL);      //- 清除中断    
-    
-    
-    if(i2cHandler_Callback != (i2cHandler_callback_t)0) {
-        i2cHandler_Callback(stat);
-    }
-       
-}
-#endif
-

component/boot2/bsp/bsp_i2c_slave.h

@@ -1,14 +0,0 @@
-#ifndef __BSP_I2C_SLAVE_H_
-#define __BSP_I2C_SLAVE_H_
-
-extern void i2c_slave_init(uint16_t i2cAddR);
-extern void i2c_slave_WriteSingle(uint8_t val);
-extern uint8_t i2c_slave_ReadSingle(void);
-typedef void (*i2cHandler_callback_t)(uint32_t stat);
-
-#define I2C_SLAVE_RX_DONE (1 << 7)
-#define I2C_SLAVE_RD_REQ (1 << 5)
-#define I2C_SLAVE_RX_FULL (1 << 2)
-#define I2C_SLAVE_STOP (1 << 9)
-
-#endif

component/boot2/bsp/bsp_pwm.c

@@ -1,117 +0,0 @@
-
-#include    "Includes.h"
-
-#define ENABLE_PWMS()     *PWMx_EN(0)|=(0x40)      //enable all select pwm  
-#define DISABLE_PWMS()   *PWMx_EN(0)&=(~0x40) 
-
-void init_pwm(uint32_t ch,uint32_t ocpy,uint32_t period)
-{
- 
-//config pwm clk
-	*CPR_CTLAPBCLKEN_GRCTL=0x10001000; //enable pwm pclk
-	*CPR_PWM_CLK_CTL=0x80000009;       //pwm_clk=mclk_in(24M)/(2*(9+1))=1.2M
-//config regs
-/*PWMx_EN(0)
-  6 pwm_en_all        
-  ............*/	
- /*PWMx_EN(ch)
-  5      sleep_en
-  4      sleep_incr
-  3      pwm_en_sel[0：select pwm_en、1：select pwm_en_all]
-  2:1    pwm_mode[0:100、1:1000、2:4000、3:occupy_ratio_config+1]
-  0      pwm_en */	
-    *PWMx_EN(ch)&=(~0x01);   //disable pwm	
-#if 1
-	 *PWMx_P(ch)=period;                        //freq(HZ)=pwm_clk/((period + 1)*100)) 
-	 *PWMx_OCPY(ch)=ocpy;                       //set pwm ocpy  
-     *PWMx_EN(ch)=(*PWMx_EN(ch)&(~0x06))|(0<<1);//bit2:1 pwm_mode[0:100、1:1000、2:4000、3:occupy_ratio_config+1]
-#else	
-	
-	*PWMx_P(ch)=2;                              //freq(HZ)=pwm_clk/((period + 1)*100))
-	*PWMx_OCPY(ch)=(199<<16)|ocpy;               //set pwm ocpy  
-     *PWMx_EN(ch)=(*PWMx_EN(ch)&(~0x06))|(3<<1);//bit2:1 pwm_mode[0:100、1:1000、2:4000、3:occupy_ratio_config+1]
-#endif	
-	*PWMx_UP(ch)=0x1;        //update ocpy period  
-
-//  *PWMx_EN(ch)=(*PWMx_EN(ch)&(~0x30))|(2<<4);
-	*PWMx_EN(ch)=(*PWMx_EN(ch)&(~0x08))|(1<<3); //bit3 pwm_en_sel[0：select pwm_en、1：select pwm_en_all]
-//  *PWMx_EN(ch)|=(0x1);//enable pwm(ch)  
-
-	
-#if 1   //enable pwm0_inv/pwm1_inv/pwm2_inv/pwm3_inv 
-   if(ch<4)
-   {
-	   *PWMCOMPEN(ch)=0x01;   //enable PWM 0 1 2 3 complementary signal output
-	   *PWMCOMPTIME(ch)=0x01; //[bit2:0]
-   }
-#endif
-   
-#if 1
-/*PWM_BREAK_CTL 
-  19:17  pwm_brk_enable  RW  使能pwm的刹车功能， 1使能
-  16     pwm_brk_sync    R   内部硬件刹车信号的值,用于软件判断硬件刹车状态1:硬件刹车信号有效,0:硬件刹车信号无效
-  14:12  pwm_brk_mask    RW  PWM_BRK信号屏蔽，每位分别屏蔽一路,0:不屏蔽1:屏蔽
-  11:9   pwm_brk_inv     RW  PWM_BRK信号反向，每位分别反向一路,0:不反向1:反向
-  8      brk_mode        RW  硬件恢复模式和软件恢复模式选择：
-  7      brk_dbc_en      RW  PWM_BRK信号的滤毛刺使能
-  6:1    brk_dbc_step    RW  PWM_BRK信号的滤毛刺步长。步长为1个pwm_clk时钟周期
-  0      brk_clear       RC1 软件恢复模式退出刹车模式：1：退出刹车模式 0：无效*/	
-
-    *PWM_BREAK_CTL=0; //clear regs
-    *PWM_BREAK_CTL=(2<<1)|(1<<7)|(0<<8)|(0<<9)|(6<<12)|(7<<17);
-   
-
-#endif   
-   
-}
-
-void test_pwm(void)
-{
-    gpio_mux_ctl(0,2);//pwm2
-	gpio_mux_ctl(1,2);//pwm3
-	gpio_mux_ctl(2,0);gpio_fun_inter(2,0);gpio_fun_sel(2,PWM0);//pwm0
-	gpio_mux_ctl(8,0);gpio_fun_inter(8,0);gpio_fun_sel(8,PWM1);//PWM1  
-	
-	gpio_mux_ctl(3,0);gpio_fun_inter(3,0);gpio_fun_sel(3,PWM0_INV);//pwm0_INV    
-//	gpio_mux_ctl(4,0);gpio_fun_inter(4,0);gpio_fun_sel(4,PWM2_INV);//PWM2_INV  gpio_mux_ctl(4,1);//
-	gpio_mux_ctl(9,0);gpio_fun_inter(9,0);gpio_fun_sel(9,PWM1_INV);//PWM1_INV
-
-//三路刹车单独使用	
-	gpio_mux_ctl(4,1);//pwm_brk[0] 
-//  gpio_mux_ctl(5,1);//pwm_brk[1]
-//	gpio_mux_ctl(6,1);//pwm_brk[2]
-	
-	
-	
-    init_pwm(0,22,119);//100HZ
-	init_pwm(1,33,119);//100HZ
-	init_pwm(2,44,119);//100HZ
-	init_pwm(3,55,119);//100HZ
-	ENABLE_PWMS();  //enable all select pwm  
-	
-    while(1);
-	{
-//		ENABLE_PWMS();  //enable all select pwm  
-		for(int i=0;i<0xA550;i++);
-//		DISABLE_PWMS(); 
-		for(int i=0;i<0xA550;i++);
-		 
-		__NOP();
-		__NOP();
-		__NOP();
-		__NOP();
-		__NOP();
-		__WFI();
-		__NOP();
-		__NOP();
-		__NOP();
-		__NOP();
-		__NOP();
-		printf("sleep...\n");
-		__NOP();
-		__NOP();
-		__NOP();
-		__NOP();
-		__NOP();
-	}
-}

component/boot2/bsp/bsp_pwm.h

@@ -1,4 +0,0 @@
-#ifndef _BSP_PWM_H_
-#define _BSP_PWM_H_
-
-#endif

component/boot2/bsp/bsp_retarget.c

@@ -1,79 +0,0 @@
-
-#include "Includes.h"
-
-void retarget_init(void)
-{
-    unsigned int val;
-    __read_hw_reg32(CPR_GPIO_FUN_SEL4, val);
-    val &= 0xFFFF;
-    /* GPIO18: TX; GPIO19: RX */
-    val |= ((1 << 16) | (2 << 24));
-    __write_hw_reg32(CPR_GPIO_FUN_SEL4, val);
-    /* Reset uart module */
-    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x10000);
-    /* Unreset uart module */
-    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x10001);
-    /* Enable uart0 pclk */
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x100010);
-    /* Set the first-level division ratio of uart0_clk relative to the 12MHz clock */
-    __write_hw_reg32(CPR_UART0_CLK_GRCTL, 0x110018);
-    /* Set the secondary frequency division coefficient of uart0_clk relative to the 12MHz clock */
-    //__write_hw_reg32(CPR_UART0_CLK_CTL, 0x0600271);//57600-OSC12M
-    __write_hw_reg32(CPR_UART0_CLK_CTL, 0x0480271); // 115200-OSC32M
-    //__write_hw_reg32(CPR_UART0_CLK_CTL, 0x1800271);//230400-OSC12M
-    //__write_hw_reg32(CPR_UART0_CLK_CTL, 0x0C00271);//115200-OSC12M
-    /* Enable DLAB */
-    __write_hw_reg32(UART0_TCR, 0x80);
-    /* Control the baud rate */
-    __write_hw_reg32(UART0_DLL, 0x01);
-    /* Control the baud rate */
-    __write_hw_reg32(UART0_DLH, 0x00);
-    /* Set the data bit of the serial port */
-    __write_hw_reg32(UART0_TCR, 0x03);
-    /* Set the interrupt threshold of transmit FIFO and receive FIFO and Clear the transmit and receive FIFO, Finally enable FIFO */
-    __write_hw_reg32(UART0_FCR, 0x37);
-    printf("\n SYSTEM BUILD TIME: %s %s \n", __DATE__, __TIME__);
-}
-
-int sendchar(int c)
-{
-    //return 0;
-    unsigned int status;
-    for (;;)
-    {
-        status = (*((volatile unsigned *)(0x40010000 + 0x14)));
-        status &= 0x20;
-        if (status == 0x20)
-            break;
-    }
-    (*((volatile unsigned *)(0x40010000 + 0x00))) = c;
-    return (1);
-}
-
-struct __FILE
-{
-    int handle; /* Add whatever you need here */
-};
-FILE __stdout;
-
-int fputc(int ch, FILE *f)
-{
-    return (sendchar(ch));
-}
-
-int ferror(FILE *f)
-{
-    /* Your implementation of ferror */
-    return EOF;
-}
-
-void _ttywrch(int ch)
-{
-    sendchar(ch);
-}
-
-void _sys_exit(int return_code)
-{
-label:
-    goto label; /* endless loop */
-}

component/boot2/bsp/bsp_rtc.c

@@ -1,305 +0,0 @@
-
-
-#include    "Includes.h"
-
-
-//#define printf(...) (0)
- 
- 
- 
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : 
- *
- */
-extern	void	Init_rtc(rtc_t *rtc)
-{
-        uint32_t    VAL;
-        
-        if(rtc == (rtc_t*)0) return;
-        VAL = ((rtc->day)<<17) | ((rtc->hour)<<12) | ((rtc->minute)<<6) | (rtc->second);    
-        __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x20002);
-		__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x20002);
-
-        __write_hw_reg32(RTC_ICR, 0x00);
-        __write_hw_reg32(RTC_CLR, VAL);
-        __write_hw_reg32(RTC_WLR, rtc->week);					
-
-        __write_hw_reg32(RTC_RAW_LIMIT, 32000);//32768
-        __write_hw_reg32(RTC_SECOND_LIMIT, 60);	
-        __write_hw_reg32(RTC_MINUTE_LIMIT, 60);
-        __write_hw_reg32(RTC_HOUR_LIMIT, 24);	
-        
-        VAL = 0x100;
-        if(rtc->interrupt != 0)    {
-            
-            VAL |= (rtc->interrupt);
-         	NVIC_EnableIRQ(RTC_IRQn);	   
-        }
-        __write_hw_reg32(RTC_ICR, VAL);             //- 使能RTC开始工作          
-        
-				
-}
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : 
- *
- */
-extern  void   rtc_Current_VAL(rtc_t *rtc)
-{
-        uint32_t    VAL;
-        __read_hw_reg32(RTC_CCVR, VAL);
-    
-        rtc->day = (VAL >> 17) & 0x7FFF;
-        rtc->hour = (VAL >> 12) & 0x1F;
-        rtc->minute = (VAL >> 6)& 0x3F; 
-        rtc->second =  VAL & 0x3F;
-    
-        __read_hw_reg32(RTC_WVR, VAL);    
-        rtc->week = VAL & 0x07; 
-}
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : 
- *
- */
-extern  void    rtc_Alarm_Init(uint32_t no, rtc_t * rtc)
-{
-        uint8_t     TAB[3] = {RTC_INT_T1, RTC_INT_T2, RTC_INT_T3};
-        uint32_t    VAL;
-        
-         no = no - 1;
-    
-        VAL = ((rtc->hour)<<12) | ((rtc->minute)<<6) | (rtc->second);  
-        //VAL |= 1<<((rtc->week)+17);
-        VAL |= rtc->week_alarm;
-        __write_hw_reg32(RTC_CMR_X(no), VAL);
-        __read_hw_reg32(RTC_ICR, VAL);
-        VAL |= TAB[no];
-        __write_hw_reg32(RTC_ICR, VAL);         //- 使能定时匹配中
-		NVIC_EnableIRQ(RTC_IRQn);//使能RTC中断
-}
-
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : 
- *
- */ 
-extern	void	Init_rtc_gpio(uint32_t	num,uint32_t level)
-{
-		uint32_t	val;
-		__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x20002);
-		__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x20002);
-
-	    __write_hw_reg32(PWRKEY_CTRL0, level);/*gpio0-31(1:low,0:high)*/
-        __write_hw_reg32(PWRKEY_CTRL1, num);/*gpio0-31(0:disable,1:enable)*/
-	    __write_hw_reg32(PWRKEY_CTRL2, 0x80000000);/*bit31:enable inter,bit1:inter raw*/
-	
-		NVIC_EnableIRQ(RTC_IRQn);	    
-}
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : 
- *
- */
-extern	void	RTC_Handler(void)
-{
-	/*rtc pclk must be opened here after deep sleep wakeup*/
-	__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x20002);
-	
-	uint32_t    stat;
-	/*bit0:day , bit1:hour , bit2:min , bit3:sec , bit4:t2 , bit5:t1 , bit6:t3 intr*/
-	 __read_hw_reg32(RTC_ISR, stat);
-	if(stat != 0)  
-    {        
-		__write_hw_reg32(RTC_EOI, stat);//clear intr
-		if(stat&0x1)//day  intr
-		{
-			printf("rtc day intr\n");
-			 
-		}
-		if(stat&0x2)//hour intr
-		{
-			printf("rtc hour intr\n");
-			 
-		}
-		if(stat&0x4)//min intr
-		{
-			printf("rtc min intr\n");
-			 
-		}
-		if(stat&0x8)//sec intr
-		{
-			printf("rtc sec intr\n");
-			 
-		}
-		if(stat&0x70)//alarm intr
-		{
-			printf("rtc alarm t2/t1/t3 intr\n");
-			rtc_t rtc={0};
-			Init_rtc(&rtc);
-			rtc.second=rtc.second+2;
-			rtc.week_alarm=0xFE0000;  
-			rtc_Alarm_Init(1,&rtc);
-		}
-	}   
-    /*ao_timer intr*/
-     __read_hw_reg32(AO_ALL_INTR, stat);
-	if(stat&0x20)//ao_timer intr   
-	{ 
-	    *AO_TIMER_CTL |=0x10000;
-		printf("ao_timer intr\n");
-	
-	}
-    /*rtc_gpio inter*/ 
-	 __read_hw_reg32(PWRKEY_CTRL2, stat);
-	if(stat&0x02) /*power key gpio wakeup*/
-	{
-	    printf("rtc_gpio intr\n");
-	   //__write_hw_reg32(PWRKEY_CTRL2, 0x00000000);
-	   //__write_hw_reg32(PWRKEY_CTRL2, 0x80000000);
-	}
-}	
-  
-
-
-/*************************The following is the calibration of rc32k************************************/
-
-static AO_TIMER_CTL_T* ao_timer_ctl = (AO_TIMER_CTL_T*)AO_TIMER_CTL;
-static void LPO_RTM_SET(uint16_t val)
-{
-	*((volatile unsigned *)0x40002084)=0x1fff4000|val;      //*((volatile unsigned *)0x40002084)=0x1fff4000|0x22C0;	  //printf("LPO_RTM:%08x\n",*((volatile unsigned *)0x40002084));
-}
-
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Author : 
- *
- */
-static uint8_t  calib_step(uint32_t _cycle_32k,uint32_t *FREQ_VAL)  
-{
-    uint32_t tsd;
-	ao_timer_ctl->AO_TIMER_VALUE = _cycle_32k;//32 cycle == 1ms
-	ao_timer_ctl->AO_TIMER_EN = 0;
-	ao_timer_ctl->AO_TIMER_CLR = 0; //中断使用在timer 使能之前
-	ao_timer_ctl->FREQ_TIMER_EN = 1;
-	do{
-        __read_hw_reg32(AO_ALL_INTR, tsd);
-    }while((tsd&0x20)==0);
-	__read_hw_reg32(FREQ_TIMER_VAL, *FREQ_VAL);//
-	ao_timer_ctl->AO_TIMER_CLR = 1; // rtc 必须清理中断	
-	ao_timer_ctl->FREQ_TIMER_EN = 0;
-	if(*FREQ_VAL==COUNT_16M) return 0;
-	return ((*FREQ_VAL<COUNT_16M)? 1:2);
-} 
-
-
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Describe : init  calib clk
- *
- */
-static volatile uint32_t mid=MID_LPO_RTM;
-void calib_init(void)
-{
-   __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x20002);
-   __write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x20002);
-    LPO_RTM_SET(mid);
-}
- /**
- * Copyright (c) 2022 - 2025, XinChip
- *
- * All rights reserved.
- *
- * Describe : "linear regression" calibration
- *
- */
-void  rc32k_calib(uint16_t cts)
-{
-	uint32_t tsd,frac;
-	while(cts--)
-	{
-		__disable_irq();
-		calib_step(CALIB_STEP_CYCLE_32K,&tsd);
-		__enable_irq();
-        printf("FREQ_TIMER_VAL:%d\n",tsd);
-		
-		frac=(uint32_t)((((float)((16.0)*CALIB_STEP_CYCLE_32K))/tsd)*1000000);
-		if(frac > _32K_STAND_HZ)
-		{
-			mid=mid-((uint32_t)(((float)(frac-_32K_STAND_HZ))/GEARS_HZ));
-		}
-		else if(frac < _32K_STAND_HZ)
-		{
-			mid=mid+((uint32_t)(((float)(_32K_STAND_HZ-frac))/GEARS_HZ));
-		}
-		LPO_RTM_SET(mid);
-
-	}
-    printf("@@LPO_RTM_SET:0x%08x\n",mid);
-
-	
-}
-/**********************************calibration rc32k end********************************************/
-
-void test_rtc(void)
-{
-   /*rc32k calib*/
-    calib_init();
-	rc32k_calib(3); 
-#if 0                                                       
-    gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,0);gpio_direction_input(1,1);
-	gpio_mux_ctl(4,0);gpio_fun_inter(4,0);gpio_fun_sel(4,0);gpio_direction_input(4,0);
-  	Init_rtc_gpio(0x00000012,0x00000010);/*1:low,0:high*/
-	while(1);
-#endif	
-#if 0
-	rtc_t rtc={0};
-    Init_rtc(&rtc);
-	rtc.second=rtc.second+5; //设定闹钟时间5S后
-	rtc.week_alarm=0xFE0000; //设置闹钟星期几有效，周一到周日都有效
-	rtc_Alarm_Init(1,&rtc);  //设置闹钟--5s后唤醒
-    while(1);
-#endif
-#if 1
-  	rtc_t rtc={
-		.day   = 16,
-        .hour  = 10,
-        .minute= 14,
-        .second= 00,
-        .week  = 5,
-        .interrupt = RTC_INT_SEC
-    };
-	Init_rtc(&rtc);
-	while(1)
-	{
-	    for(int i=0;i<0x455000;i++);
-	    rtc_Current_VAL(&rtc);
-	    printf("%d-%d  %d:%d:%d\n",rtc.day,rtc.week,rtc.hour,rtc.minute,rtc.second);
-	}
-#endif
-
-}
-
-

component/boot2/bsp/bsp_rtc.h

@@ -1,73 +0,0 @@
-#ifndef __BSP_RTC_H_
-#define __BSP_RTC_H_
-
-typedef struct t_rtc
-{
-
-    uint32_t day;
-    uint32_t hour;
-    uint32_t minute;
-    uint32_t second;
-    uint32_t week;
-
-    uint32_t week_alarm;
-    uint32_t interrupt;
-} rtc_t;
-
-extern void Init_rtc(rtc_t *rtc);
-extern void rtc_Current_VAL(rtc_t *rtc);
-extern void rtc_Alarm_Init(uint32_t no, rtc_t *rtc);
-
-extern void Init_rtc_gpio(uint32_t num, uint32_t level);
-
-#define RTC_INT_DAY (1 << 0)
-#define RTC_INT_HOUR (1 << 1)
-#define RTC_INT_MIN (1 << 2)
-#define RTC_INT_SEC (1 << 3)
-#define RTC_INT_T1 (1 << 5)
-#define RTC_INT_T2 (1 << 4)
-#define RTC_INT_T3 (1 << 6)
-
-#define RTC_ALARM_SUN (1 << 17)
-#define RTC_ALARM_MON (1 << 18)
-#define RTC_ALARM_TUES (1 << 19)
-#define RTC_ALARM_WED (1 << 20)
-#define RTC_ALARM_THUR (1 << 21)
-#define RTC_ALARM_FRI (1 << 22)
-#define RTC_ALARM_SAT (1 << 23)
-
-#define PWRKEY_CTRL0 ((volatile unsigned *)(RTC_BASE + 0x005C))
-#define PWRKEY_CTRL1 ((volatile unsigned *)(RTC_BASE + 0x0060))
-#define PWRKEY_CTRL2 ((volatile unsigned *)(RTC_BASE + 0x0064))
-#define PWRKEY_SOFT_CTL0 ((volatile unsigned *)(RTC_BASE + 0x0068))
-#define PWRKEY_SOFT_CTL1 ((volatile unsigned *)(RTC_BASE + 0x006C))
-
-typedef struct
-{
-    uint32_t AO_TIMER_VALUE : 16;
-    uint32_t AO_TIMER_CLR : 1;
-    uint32_t AO_TIMER_EN : 1;
-    uint32_t FREQ_TIMER_EN : 1;
-    uint32_t RESERVED : 13;
-} AO_TIMER_CTL_T;
-
-/*
-3fff  3044 --50K
-2fff  4132 --39K
-1fff  5229 --31K
-0fff  6326 --25K
-*/
-#define MAX_LPO_RTM 0x3fff
-#define MIN_LPO_RTM 0x0
-#define MID_LPO_RTM 0x1fff
-#define RANGE_LPO_RTM 0x400
-#define GEARS_HZ 1.56
-#define _32K_STAND_HZ 32000
-
-// #define CALIB_STEP_CYCLE_32K  32      //32 cycle = 1ms
-// #define COUNT_16M             16000   //
-
-#define CALIB_STEP_CYCLE_32K 320 // 320 cycle = 10ms
-#define COUNT_16M 160000         //
-
-#endif

component/boot2/bsp/bsp_spi1_slave.c

@@ -1,332 +0,0 @@
-#include    "Includes.h"
-
-#if  1  
-
-#define RCV_LEN  1024
-#define SND_LEN  1024
-#define CH_TX  3
-#define CH_RX  11
-
-
-#define   CH11_BLK   (1 << 11) //通道 11 块传输结束
-#define   CH3_BLK_EN (1 << 3)  //通道3 块传输结束使能
-  	
-
-
-static uint8_t  __attribute__((aligned(4))) spi1_rcv_data[RCV_LEN];
-volatile uint16_t spi1_rcv_len = 0;
-
-static uint8_t  __attribute__((aligned(4))) spi1_send_data[SND_LEN];
-volatile uint16_t spi1_send_len = 0;
- 
- 
- 	
-
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: dma_ssi1_send
-- 函数功能: spi slave 发送接口函数
-- 输入参数:   
-- 创建日期:  
-----------------------------------------------------------------------------------------------------*/
-
-void dma_ssi1_send(uint32_t snd_len)
-{
-	__write_hw_reg32(DMAS_CHx_CTL0((CH_TX)) ,snd_len); //set trans byte len
-	__write_hw_reg32(DMAS_CLR ,CH_TX);                 //disable DMA TX channel
-   	__write_hw_reg32(DMAS_EN ,CH_TX);                  //enable DMA TX channel
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: Init_spi_selve
-- 函数功能: spi slave 初始化函数接口
-- 输入参数:   
-- 创建日期:  
-----------------------------------------------------------------------------------------------------*/
-void Init_spi_selve(uint32_t ch)
-{
-    uint32_t    val;
-    __write_hw_reg32(CPR_SPIx_MCLK_CTL(ch), 0x110010);//1分频			//- spi(x)_mclk = 32Mhz(When TXCO=32Mhz).
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000100<<ch)); 	//- 打开spi(x) pclk.
-    __read_hw_reg32(CPR_SSI_CTRL, val);
-    val |= (ch==0)? 0x01: 0x10;
-    __write_hw_reg32(CPR_SSI_CTRL, val); //spi1 set slave  
-	
-    __write_hw_reg32(SSIx_EN(ch), 0x00);
-    __write_hw_reg32(SSIx_IE(ch), 0x10);            /*接收满中断使能 接收FIFO上溢出 下溢出中断使能 */
-    __write_hw_reg32(SSIx_CTRL0(ch) , 0x07);		/* 8bit SPI data */
-    __write_hw_reg32(SSIx_BAUD(ch), 2);			    /*- spix_mclk 分频  selve 在32M时钟下只能忍受4M (内部八分频)*/
-    //Init_dma_ssi1();
-	__write_hw_reg32(SSI1_DMAS , 0x02);
-	__write_hw_reg32(SSI1_DMATDL, 0x04);
-	//- TX Channel CH_TX
-	__write_hw_reg32(DMAS_CHx_SAR(CH_TX) , (uint32_t)spi1_send_data);
-	__write_hw_reg32(DMAS_CHx_DAR(CH_TX) , (uint32_t)SSI1_DATA);
-	__write_hw_reg32(DMAS_CHx_CTL1(CH_TX) ,((2 << 8)));
-	//__write_hw_reg32(DMAS_CHx_CTL0(CH_TX) ,0);//set trans byte len
-	//__write_hw_reg32(DMAS_EN , CH_TX);        //enable DMA TX channel
-	
-	//__write_hw_reg32(DMAS_INT_EN0,(CH3_BLK_EN));
-	//NVIC_EnableIRQ(DMAS_IRQn);
-	
-	__write_hw_reg32(SSIx_EN(ch) , 0x01);  //开启SPI传输
-	NVIC_EnableIRQ(SPI0_IRQn+ch);
-}
-
-//uint8_t rev_num=0;
-extern	void SPI1_Handler(void)
-{
-   uint32_t spi1_data=0;
-   __read_hw_reg32(SSI1_RXFL,spi1_data);
-   while(spi1_data>0)
-   {   
-       spi1_rcv_data[spi1_rcv_len++]=*SSIx_DATA(1);
-	   if(spi1_rcv_len==1024)spi1_rcv_len=0;
-	   //*SSIx_DATA(1)=rev_num++;
-	   __read_hw_reg32(SSI1_RXFL,spi1_data);
-   }	   
-    __read_hw_reg32(SSI1_IC,spi1_data);
-}
-
-
-extern  void    test_spi1_selve(void) 
-{
-	
-    
-	gpio_mux_ctl(0,0);gpio_fun_inter(0,0);gpio_fun_sel(0,SSI1_SSN);
-	gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,SSI1_CLK);
-	gpio_mux_ctl(2,0);gpio_fun_inter(2,0);gpio_fun_sel(2,SSI1_TX);
-	gpio_mux_ctl(3,0);gpio_fun_inter(3,0);gpio_fun_sel(3,SSI1_RX);
-	Init_spi_selve(1);
-	while(1)
-	{
-	       switch(spi1_rcv_data[0])
-		   {
-			   case 'A':
-				   spi1_rcv_data[0]=0;spi1_rcv_len=0;
-			       for(int i=0;i<SND_LEN;i++) spi1_send_data[i]=i;
-			       spi1_send_data[0]=0x11;
-			       dma_ssi1_send(SND_LEN);
-				   break;
-			   case 'B':
-				   spi1_rcv_data[0]=0;spi1_rcv_len=0; 
-			       for(int i=0;i<SND_LEN;i++) spi1_send_data[i]=i;
-			       spi1_send_data[0]=0x22;
-			       dma_ssi1_send(SND_LEN);
-				   break;
-			   case 'C':
-				   spi1_rcv_data[0]=0;spi1_rcv_len=0; 
-			       for(int i=0;i<SND_LEN;i++) spi1_send_data[i]=i;
-			       spi1_send_data[0]=0x33;
-			       dma_ssi1_send(SND_LEN);
-				   break;
-			   case 'D':
-				   spi1_rcv_data[0]=0;spi1_rcv_len=0;
-			       for(int i=0;i<SND_LEN;i++) spi1_send_data[i]=i;
-			       spi1_send_data[0]=0x44;
-			       dma_ssi1_send(SND_LEN);
-				   break;
-			   default:spi1_rcv_len=0; break;
-		   }
-	
-	}
-
-	
-}
- 
-
-
-
-
-
-static uint8_t  __attribute__((aligned(4))) rxbuff[256];
-static uint8_t  __attribute__((aligned(4))) txbuff[256];
-
-void	Init_spi1_master(uint32_t ch, uint32_t freq)
-{
-    uint32_t    val;
-    
-    __write_hw_reg32(CPR_SPIx_MCLK_CTL(ch), 0x110010);//1分频			//- spi(x)_mclk = 32Mhz(When TXCO=32Mhz).
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000100<<ch)); 	//- 打开spi(x) pclk.
-    __read_hw_reg32(CPR_SSI_CTRL, val);
-    val |= (ch==0)? 0x01: 0x30;
-    __write_hw_reg32(CPR_SSI_CTRL, val);
-	
-    __write_hw_reg32(SSIx_EN(ch), 0x00);
-
-    __write_hw_reg32(SSIx_IE(ch), 0x00);
-    __write_hw_reg32(SSIx_CTRL0(ch) , 0x07);					/* 8bit SPI data */
-
-    __write_hw_reg32(SSIx_SE(ch), 0x01);
-    __write_hw_reg32(SSIx_BAUD(ch), freq);						//- spix_mclk 分频.
-
-    __write_hw_reg32(SSIx_RXFTL(ch), 0x00);
-    __write_hw_reg32(SSIx_TXFTL(ch), 0x00);
-
-    //__write_hw_reg32(SSIx_EN(ch) , 0x01);
-}
-
-void spi1_read_write(uint16_t len)
-{
-    
-    uint32_t    iWK = 0;
-    __write_hw_reg32(SSI1_EN , 0x00);
-    __write_hw_reg32(SSI1_DMAS , 0x03);
-    __write_hw_reg32(SSI1_DMATDL, 0x4);          //-
-    __write_hw_reg32(SSI1_DMARDL, 0x4);          //- 1/4 FIFO
-    __write_hw_reg32(SSI1_EN , 0x01);
-  
-	//- RX Channel
-	__write_hw_reg32(DMAS_CHx_SAR(11) , 0x40014060);
-    __write_hw_reg32(DMAS_CHx_DAR(11) , (uint32_t)rxbuff);
-    __write_hw_reg32(DMAS_CHx_CTL1(11) ,((2 << 8)));//8bits
-    __write_hw_reg32(DMAS_CHx_CTL0(11) ,(len));
-    __write_hw_reg32(DMAS_EN , 11);
-
-		//- TX Channel
-	__write_hw_reg32(DMAS_CHx_SAR(3) , (uint32_t)txbuff);
-    __write_hw_reg32(DMAS_CHx_DAR(3) , 0x40014060);
-    __write_hw_reg32(DMAS_CHx_CTL1(3) ,((2 << 8)));//8bits
-    __write_hw_reg32(DMAS_CHx_CTL0(3) ,(len));
-    __write_hw_reg32(DMAS_EN , 3);
-
-    do	{
-    	__read_hw_reg32(DMAS_INT_RAW , iWK);
-    }while((iWK&0x808) != 0x808);
-
-    __write_hw_reg32(DMAS_INT_RAW, 0x808);
-    __write_hw_reg32(DMAS_CLR , 11);
-    __write_hw_reg32(DMAS_CLR , 3);
-    __write_hw_reg32(SSI1_EN , 0x00);
-
-}
-
-void test_spi1_master(void)
-{
-		gpio_mux_ctl(0,0);gpio_fun_inter(0,0);gpio_fun_sel(0,SSI1_SSN);
-		gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,SSI1_CLK);
-		gpio_mux_ctl(2,0);gpio_fun_inter(2,0);gpio_fun_sel(2,SSI1_RX);
-		gpio_mux_ctl(3,0);gpio_fun_inter(3,0);gpio_fun_sel(3,SSI1_TX);
-	    for(int i=0;i<256;i++)
-	    {
-		     rxbuff[i]=i;
-			 txbuff[i]=i;
-		}
-        Init_spi1_master(1,SPIM_CLK_4MHZ);
-	    while(1){  
-		  
-		   spi1_read_write(256);//此函数执行时间1.12ms
-		    
-		   for(int i=0;i<0x455000;i++);
-		}
-}
-
-
-
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#if 0
-
-
-static void wbit16(uint16_t reg_addr,int end,int start,char* bit_str)
-{
-    uint16_t reg_val = 0;
-    char ch = 0;
-	int i = 0;
-
-
-	if(strlen(bit_str) != (end-start+1))
-	{
-		while(1); //error
-	}
-	reg_val = *(uint16_t *)(0X4002F000+reg_addr);
-    for(i=start;i<=end;i++)
-    {
-		
-        int bit_idx = i-start;  //index of bit string
-        
-        ch = bit_str[(end-start)-bit_idx] - '0';
-        if(ch==1)
-        {
-            setbit(reg_val,i);
-        }
-        else if(ch==0)
-        {
-            clrbit(reg_val,i);
-        }
-    }
-	*(uint16_t *)(0X4002F000+reg_addr)=reg_val;
-}
-
-
-void osc32M_to_pll64M(void)
-{
-        //???????
-		//for(uint32_t i=0;i<0x1200000;i++);
-		uint32_t val;
-		//??APB??
-		__read_hw_reg32(((volatile unsigned *)(0x40000000+ 0x130)), val);
-		__write_hw_reg32(((volatile unsigned *)(0x40000000+ 0x130)), (val&0xFFFFFFFE));
-		//??PLLM 48M?? 
-	    wbit16(0x03D8,15,15,"1");   // bbpll ldo en
-	    //wbit16(0x03D8,4,3,"11");      // bbpll fref div4
-		wbit16(0x001C,15,15,"1");   //debug BBPLL reset ,low reset
-		wbit16(0x001C,14,14,"1");   //Enable for BBPLL1,high enable,also control ref clock
-		wbit16(0x001C,13,13,"1");   // debug_DA_BBPLL1_EN
-		wbit16(0x001C,8,8,"1");     // Enable for 104M clk output to digital module
-		wbit16(0x0020,15,15,"1");   // reg  BBPLL reset ,low reset
-		wbit16(0x0020,14,14,"1");   // Enable for BBPLL1,high enable,also control ref clock
-		wbit16(0x0020,13,13,"1");   // debug_DA_BBPLL1_EN
-		wbit16(0x0020,8,8,"1");     // Enable for 104M clk output to digital module
-		///wbit16(0x0024,9,4,"000110");// default 001100, div12,32m 000110,div
-	    wbit16(0x0024,9,4,"001000");  //64M
-	    wbit16(0x03D4,13,11,"011"); // vdd64m res	
-        //xc_delay(1);//Delay 10ms
-    	//??????PLL48M ??bbpll??????
-		*((volatile unsigned *)(CPR_AO_BASE + 0x20))  =0x2E;
-		 __read_hw_reg32(((volatile unsigned *)(0x40000000+ 0x134)), val);
-		__write_hw_reg32(((volatile unsigned *)(0x40000000+ 0x134)), (val&0xFFFFFFE0)|0x11);//bbpll_clk_en ?? bbpll_clk_div ???
-		__read_hw_reg32(((volatile unsigned *)(0x40000000+ 0x130)), val);
-		__write_hw_reg32(((volatile unsigned *)(0x40000000+ 0x130)), (val&0xFFFFFFF9)|0x04);//0x2??RC16M???,0x00??32M osc,0x04 PLL96M 48M????? 
-
-}
-
-void Set_PLL64M(void)
-{
-	CPR_CTL();SYS_Main_Initialise();   
-	osc32M_to_pll64M();
-    uart_64M_source_115200(0);
-    printf("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-//    for(int i=0;i<800;i++);
-//    pll48M_to_osc32M();
-//    Init_uart(0,BAUD_115200);
-//    printf("\nTEST PLL48M\n");
-} 
-
-#endif

component/boot2/bsp/bsp_spi_master.c

@@ -1,511 +0,0 @@
-
-/*----------------------------------------------------------------------------------------------------
-	INCLUDE HEADE FILES
-----------------------------------------------------------------------------------------------------*/
-#include    "Includes.h"
- /*----------------------------------------------------------------------------------------------------
-    SPI 	COMMAND
------------------------------------------------------------------------------------------------------*/
-#define     CMD_RDID                0x9F
-#define		CMD_PAGE_ERASE		    0x81
-#define		CMD_READ_STATUS2		0x35
-#define		CMD_WRITE_STATUS        0x01 
-#define		CMD_READ_DATA			0x03
-#define		CMD_READ_STATUS			0x05
-#define		CMD_CHIP_ERASE			0xc7
-#define		CMD_WRITE_ENABLE		0x06
-#define		CMD_PAGE_PROGRAM		0x02
-#define		CMD_BLOCK_ERASE			0xD8
-#define		CMD_SECTOR_ERASE		0x20
-#define		CMD_RELEASE_PWRDWN	    0xAB
-#define		CMD_PWRDWN	            0xB9
-#define		CMD_ID                  0x4B 
-#define		PACKET_FULL_LEN			FLASH_PAGE_SIZE
-
-
-static uint8_t		__attribute__((aligned(4)))	txbuff[(PACKET_FULL_LEN+4)];
-static uint8_t		__attribute__((aligned(4)))	rxbuff[(PACKET_FULL_LEN+4)];
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: Init_spi_master
-- 函数功能: 初始化spi主模式
-- 创建日期: 2015-09-14
-----------------------------------------------------------------------------------------------------*/
- void	Init_spi_master(uint32_t ch, uint32_t freq)
-{
-    uint32_t    val;
-    
-    __write_hw_reg32(CPR_SPIx_MCLK_CTL(ch), 0x110010);//1分频			//- spi(x)_mclk = 32Mhz(When TXCO=32Mhz).
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000100<<ch)); 	//- 打开spi(x) pclk.
-    __read_hw_reg32(CPR_SSI_CTRL, val);
-    val |= (ch==0)? 0x01: 0x30;
-    __write_hw_reg32(CPR_SSI_CTRL, val);
-	
-    __write_hw_reg32(SSIx_EN(ch), 0x00);
-
-    __write_hw_reg32(SSIx_IE(ch), 0x00);
-    __write_hw_reg32(SSIx_CTRL0(ch) , 0x7);					/* 16bit SPI data */
-
-    __write_hw_reg32(SSIx_SE(ch), 0x01);
-    __write_hw_reg32(SSIx_BAUD(ch), freq);						//- spix_mclk 分频.
-
-    __write_hw_reg32(SSIx_RXFTL(ch), 0x00);
-    __write_hw_reg32(SSIx_TXFTL(ch), 0x00);
-
-}
-
-
- void close_ssi0(void)
-{
-   	__write_hw_reg32(CPR_SPIx_MCLK_CTL(0), 0x110000);//close ssi0 mclk
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000000)); //close ssi0 pclk
-    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040000); //复位ssi0
-    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040004); //复位ssi0
-}
-
-
-
-#ifdef QUAD_ENABLE
- void spi_flash_quad_en(void)
-{
-	uint32_t bWk, cWk;
-	__read_hw_reg32(SSI0_CTRL0 , bWk);
-
-	__write_hw_reg32(SSI0_EN , 0x00);
-	__write_hw_reg32(SSI0_DMAS , 0x00);
-	__write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
-	__write_hw_reg32(SSI0_EN , 0x01);
-	
-	__write_hw_reg32(SSI0_DATA, CMD_WRITE_STATUS);
-	__write_hw_reg32(SSI0_DATA, 0);
-	__write_hw_reg32(SSI0_DATA, 0x02);
-	do {
-	__read_hw_reg32(SSI0_STS, cWk);
-	}while((cWk&0x05) != 0x04);
-
-	__write_hw_reg32(SSI0_EN , 0x00);
-	__write_hw_reg32(SSI0_CTRL0 , bWk);
-
-}
-
- uint8_t spi_flash_read_stat(void)
-{
-    uint32_t  bWk, cWk;
-    uint8_t s8_15;
-    __read_hw_reg32(SSI0_CTRL0 , bWk);
-
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_DMAS , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , 0x07);  /* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN , 0x01);
-
-    __write_hw_reg32(SSI0_DATA, CMD_READ_STATUS2);
-    __write_hw_reg32(SSI0_DATA, 0xff);
-
-    do  {
-    __read_hw_reg32(SSI0_STS, cWk);
-    }while((cWk&0x05) != 0x04);
-    cWk=*SSI0_DATA;//no use
-    s8_15=*SSI0_DATA;
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , bWk);
-
-    return s8_15;
-
-}
-
-#endif
-
- uint32_t spi_flash_read_identific(void)
-{
-    uint32_t  bWk, cWk;
-    uint8_t manufact,memory_type,capacity;
-    __read_hw_reg32(SSI0_CTRL0 , bWk);
-
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_DMAS , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , 0x07);  /* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN , 0x01);
-
-    __write_hw_reg32(SSI0_DATA, CMD_RDID);
-    __write_hw_reg32(SSI0_DATA, 0xff);
-    __write_hw_reg32(SSI0_DATA, 0xff);
-    __write_hw_reg32(SSI0_DATA, 0xff);
-
-    do  {
-    __read_hw_reg32(SSI0_STS, cWk);
-    }while((cWk&0x05) != 0x04);
-    cWk=*SSI0_DATA;//no use
-    manufact=*SSI0_DATA;
-    memory_type=*SSI0_DATA;
-    capacity=*SSI0_DATA;
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , bWk);
-  
-    return (CMD_RDID<<24)|(manufact<<16)|(memory_type<<8)|(capacity<<0);
-
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: spi_flash_write_Sector
-- 函数功能: 向SPI FLASH指定扇区写入数据
-- 创建日期: 2019.04.08
-- 作    者:陈俊伟
----------------------------------------------------------------*/
-extern	void	spi_flash_write_sPages(uint32_t	WriteAddR, uint8_t *buff)
-{
-	uint8_t i=0,j=PAGES_SIZE/FLASH_PAGE_SIZE;
-	uint8_t buf;
-	    for (int k = 0; k < 1024; k += 4)
-            {
-                //	printf("i:%d\n",i);
-                buf = buff[k];
-                buff[k] = buff[k + 3];
-                buff[k + 3] = buf;
-                buf = buff[k + 1];
-                buff[k + 1] = buff[k + 2];
-                buff[k + 2] = buf;
-            }
-	for(i=0;i<j;i++)
-	{
-        spi_flash_write_enable();
-		spi_flash_write_page(WriteAddR,buff);
-        while(spi_flash_wait_till_ready());
-		WriteAddR+=FLASH_PAGE_SIZE;
-		buff+=FLASH_PAGE_SIZE;	
-	}
-}
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: spi_flash_chip_erase
-- 函数功能: 擦除整个芯片的内容
-- 创建日期: 2015-09-16
-----------------------------------------------------------------------------------------------------*/
-extern	void	spi_flash_chip_erase(void)
-{
-	uint32_t	bWk, cWk;
-
-    __read_hw_reg32(SSI0_CTRL0 , bWk);
-
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_DMAS , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , 0x07);				/* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN , 0x01);
-
-
-    __write_hw_reg32(SSI0_DATA, CMD_CHIP_ERASE);
-
-    do	{
-        	__read_hw_reg32(SSI0_STS, cWk);
-    }while((cWk&0x05) != 0x04);
-
-
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , bWk);
-}
-
-__RAM_CODE void	spi_flash_Read_Page(uint32_t	addr, uint8_t *buff)
-{
-	uint32_t    iWK = 0;
-	txbuff[1] = (uint8_t)(addr>>16);
-	txbuff[0] = CMD_READ_DATA;
-	txbuff[3] = (uint8_t)(addr);
-	txbuff[2] = (uint8_t)(addr>>8);		
-
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_DMAS , 0x03);
-    __write_hw_reg32(SSI0_DMATDL, 0x4);          //-
-    __write_hw_reg32(SSI0_DMARDL, 0x4);          //- 1/4 FIFO
-    __write_hw_reg32(SSI0_EN , 0x01);
-
-	//- RX Channel
-	__write_hw_reg32(DMAS_CHx_SAR(10) , 0x40013060);
-    __write_hw_reg32(DMAS_CHx_DAR(10) , (uint32_t)rxbuff);
-    __write_hw_reg32(DMAS_CHx_CTL1(10) ,((2 << 8)|  0));
-    __write_hw_reg32(DMAS_CHx_CTL0(10) ,(PACKET_FULL_LEN+4));
-    __write_hw_reg32(DMAS_EN , 10);
-
-		//- TX Channel
-	__write_hw_reg32(DMAS_CHx_SAR(2) , (uint32_t)txbuff);
-    __write_hw_reg32(DMAS_CHx_DAR(2) , 0x40013060);
-    __write_hw_reg32(DMAS_CHx_CTL1(2) ,((2 << 8)|  0));
-    __write_hw_reg32(DMAS_CHx_CTL0(2) ,(PACKET_FULL_LEN+4));
-    __write_hw_reg32(DMAS_EN , 2);
-
-    do	{
-    	__read_hw_reg32(DMAS_INT_RAW , iWK);
-    }while((iWK&0x404) != 0x404);
-
-    __write_hw_reg32(DMAS_INT_RAW, 0x404);
-    __write_hw_reg32(DMAS_CLR , 10);
-    __write_hw_reg32(DMAS_CLR , 2);
-    __write_hw_reg32(SSI0_EN , 0x00);    
-	for(int i=0;i<PACKET_FULL_LEN;i++){
-		buff[i]=rxbuff[i+4];
-	}
-}
-
-
-
-void	spi_flash_write_page(uint32_t	PageAddR, uint8_t *buff)
-{
-    uint32_t	addr = PageAddR;
-    uint32_t    iWK = 0;
-    uint32_t	i;
-    for(i=0; i<PACKET_FULL_LEN; i++){
-        txbuff[i+4] = buff[i];
-    }
-    txbuff[1] = (uint8_t)(addr>>16);
-    txbuff[0] = CMD_PAGE_PROGRAM;
-    txbuff[3] = (uint8_t)(addr);
-    txbuff[2] = (uint8_t)(addr>>8);
-
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_DMAS , 0x03);
-    __write_hw_reg32(SSI0_DMATDL, 0x4);          //-
-    __write_hw_reg32(SSI0_DMARDL, 0x4);          //- 1/2FIFO
-    __write_hw_reg32(SSI0_EN , 0x01);
-
-		//- RX Channel
-	__write_hw_reg32(DMAS_CHx_SAR(10), 0x40013060);
-    __write_hw_reg32(DMAS_CHx_DAR(10), (uint32_t)rxbuff);
-    __write_hw_reg32(DMAS_CHx_CTL1(10),((2 << 8)|  0));
-    __write_hw_reg32(DMAS_CHx_CTL0(10),(PACKET_FULL_LEN+4));
-    __write_hw_reg32(DMAS_EN, 10);
-
-		//- TX Channel
-	__write_hw_reg32(DMAS_CHx_SAR(2), (uint32_t)txbuff);
-    __write_hw_reg32(DMAS_CHx_DAR(2), 0x40013060);
-    __write_hw_reg32(DMAS_CHx_CTL1(2),((2 << 8)|  0));
-    __write_hw_reg32(DMAS_CHx_CTL0(2),(PACKET_FULL_LEN+4));
-    __write_hw_reg32(DMAS_EN, 2);
-
-    do	{
-    	__read_hw_reg32(DMAS_INT_RAW , iWK);
-    }while((iWK&0x404) != 0x404);
-
-    __write_hw_reg32(DMAS_INT_RAW, 0x404);
-    __write_hw_reg32(DMAS_CLR , 10);
-    __write_hw_reg32(DMAS_CLR , 2);
-    __write_hw_reg32(SSI0_EN , 0x00);
-    
-}
-
-//void	spi_flash_page_erase(uint32_t	addr)
-//{
-
-//    uint32_t  bWk, cWk;
-//    __read_hw_reg32(SSI0_CTRL0 , bWk);
-
-//    __write_hw_reg32(SSI0_EN , 0x00);
-//    __write_hw_reg32(SSI0_DMAS , 0x00);
-//    __write_hw_reg32(SSI0_CTRL0 , 0x07);  /* 8bit SPI data */
-//    __write_hw_reg32(SSI0_EN , 0x01);
-
-//    __write_hw_reg32(SSI0_DATA, CMD_PAGE_ERASE);
-//    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>16));
-//    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>8));
-//    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr));
-
-//    do  {
-//    __read_hw_reg32(SSI0_STS, cWk);
-//    }while((cWk&0x05) != 0x04);
-//    __write_hw_reg32(SSI0_EN , 0x00);
-//    __write_hw_reg32(SSI0_CTRL0 , bWk);
-//}
- 
-
-void	spi_flash_sector_erase(uint32_t	addr)
-{
-
-//    if((addr>=(4096+param_backup_addr))&&(addr<(8192+param_backup_addr))) return;  //forbid erase the calibration parameter area
-    uint32_t  bWk, cWk;
-    __read_hw_reg32(SSI0_CTRL0 , bWk);
-
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_DMAS , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , 0x07);  /* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN , 0x01);
-
-    __write_hw_reg32(SSI0_DATA, CMD_SECTOR_ERASE);
-    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>16));
-    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>8));
-    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr));
-
-    do  {
-    __read_hw_reg32(SSI0_STS, cWk);
-    }while((cWk&0x05) != 0x04);
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , bWk);
-}
- 
-void	spi_flash_block_erase(uint32_t	addr)
-{
-    uint32_t  bWk, cWk;
-    __read_hw_reg32(SSI0_CTRL0 , bWk);
-
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_DMAS , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , 0x07);  /* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN , 0x01);
-
-    __write_hw_reg32(SSI0_DATA, CMD_BLOCK_ERASE);
-    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>16));
-    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>8));
-    __write_hw_reg32(SSI0_DATA, (uint8_t)(addr));
-
-    do  {
-    __read_hw_reg32(SSI0_STS, cWk);
-    }while((cWk&0x05) != 0x04);
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , bWk);    
-}
-
-
-void	spi_flash_write_enable(void)
-{
-    uint32_t	bWk, cWk;
-
-    __read_hw_reg32(SSI0_CTRL0 , bWk);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_DMAS , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , 0x07);				/* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN, 0x01);
-
-
-    __write_hw_reg32(SSI0_DATA, CMD_WRITE_ENABLE);
-
-    do	{
-        	__read_hw_reg32(SSI0_STS, cWk);
-    }while((cWk&0x05) != 0x04);
-
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, bWk);
-
-}
-
-void	spi_flash_Release_powerdown(void)
-{
-	uint32_t	bWk, cWk;
-
-    __read_hw_reg32(SSI0_CTRL0, bWk);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_DMAS, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, 0x07);				/* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN, 0x01);
-
-
-    __write_hw_reg32(SSI0_DATA, CMD_RELEASE_PWRDWN);
-    do	{
-        	__read_hw_reg32(SSI0_STS, cWk);
-    }while((cWk&0x05) != 0x04);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, bWk);
-
-}
-
-void	spi_flash_Enter_powerdown(void)
-{
-	uint32_t	bWk, cWk;
-
-    __read_hw_reg32(SSI0_CTRL0, bWk);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_DMAS, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, 0x07);				/* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN, 0x01);
-
-
-    __write_hw_reg32(SSI0_DATA, CMD_PWRDWN);
-    do	{
-        	__read_hw_reg32(SSI0_STS, cWk);
-    }while((cWk&0x05) != 0x04);
-
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, bWk);
-
-}    
-
-uint8_t		spi_flash_wait_till_ready (void)
-{
-    uint16_t	cmd = (CMD_READ_STATUS<<8);
-    uint32_t	iWK,bWk;
-    uint16_t	dWK = 0;
-
-	__read_hw_reg32(SSI0_CTRL0 , bWk);
-	
-    __write_hw_reg32(SSI0_EN , 0x00);
-    __write_hw_reg32(SSI0_CTRL0 , 0x0F);        /* 16bit SPI data */
-    __write_hw_reg32(SSI0_DMAS , 0x00);			/* turn off dma*/
-    __write_hw_reg32(SSI0_DMATDL, 0x0);      	//-
-    __write_hw_reg32(SSI0_DMARDL, 0x0);      	//-
-    __write_hw_reg32(SSI0_EN , 0x01);
-
-    __write_hw_reg32(SSI0_DATA , cmd);
-
-    do	{
-        	__read_hw_reg32(SSI0_STS, iWK);
-    }while((iWK&0x05) != 0x04);
-
-    __read_hw_reg32(SSI0_DATA , dWK);
-
-    __write_hw_reg32(SSI0_EN , 0x00);    
-    __write_hw_reg32(SSI0_CTRL0 , bWk);
-    return	(uint8_t)(dWK&0x01);
-}
-
-#ifdef  TEST_SPI_FLASH
-void test_spi_master(void)
-{
-	
-	 spi_flash_Release_powerdown();
-#ifdef QUAD_ENABLE
-	if((spi_flash_read_stat()&0x02)==0)
-	{
-		printf("\n@@   QUAD ENABLE   @@\n");
-		spi_flash_write_enable();
-		spi_flash_quad_en();
-		while(spi_flash_wait_till_ready());
-	}
-    printf("s15_8=%#X\n",spi_flash_read_stat());
-#endif	
-	uint8_t tx_arr[256];
-    uint8_t rx_arr[256];
-	static uint8_t flag=0;
-	printf("capacity=%#X\n",spi_flash_read_identific());
-	/*read a page*/
-  	spi_flash_Read_Page(0*4096,rx_arr);
-	for(int i=0;i<256;i++) printf("%02x  ",rx_arr[i]);
-	
-	printf("\n*****************#*******************\n");
- 	if(flag){
-		flag=0;
-	    for(int i=0; i<256; i++) tx_arr[i]=i;	
-	}else{
-	   for(int i=0; i<256; i++) tx_arr[i]=255-i;	
-	   flag=1;
-	}
-	/*erase a page/sector*/
-	spi_flash_write_enable();
-	spi_flash_sector_erase(31*4096); //spi_flash_page_erase(31*4096); 
-    while(spi_flash_wait_till_ready());
-	
-	/*write a page*/
- 	spi_flash_write_enable();
-	spi_flash_write_page(31*4096,tx_arr);
-	while(spi_flash_wait_till_ready());	
-	/*read a page*/
-  	spi_flash_Read_Page(31*4096,rx_arr);
-	for(int i=0;i<256;i++) printf("%02x  ",rx_arr[i]);
-    printf("\n*****************@*******************\n");
- 	
-//  
-   spi_flash_Enter_powerdown();
-
-}
-#endif 
- 

component/boot2/bsp/bsp_spi_master.h

@@ -1,33 +0,0 @@
-#ifndef __BSP_SPI_MASTER_H_
-#define __BSP_SPI_MASTER_H_
-
-#define FLASH_PAGE_WORDS 64
-#define FLASH_PAGE_SIZE 256
-#define FLASH_BLOCK_SIZE 65536
-#define FLASH_SECTOR_SIZE 4096
-#define PAGES_SIZE 1024
-
-#define     SPIM_CLK_1MHZ           32            
-#define     SPIM_CLK_2MHZ           16
-#define     SPIM_CLK_4MHZ           8
-#define     SPIM_CLK_8MHZ           4
-#define     SPIM_CLK_16MHZ          2     
-
-
-uint8_t		spi_flash_wait_till_ready (void);
-extern	void	spi_flash_Enter_powerdown(void);
-extern	void	spi_flash_Release_powerdown(void);
-extern	void	spi_flash_write_enable(void);
-extern	void	spi_flash_block_erase(uint32_t	addr);
-extern	void	spi_flash_sector_erase(uint32_t	addr);
-extern	void	spi_flash_page_erase(uint32_t	addr);
-extern	void	spi_flash_write_page(uint32_t	PageAddR, uint8_t *buff);
-void test_spi_master(void);
-void	spi_flash_Read_Page(uint32_t	addr, uint8_t *buff);
-uint32_t spi_flash_read_identific(void);
-uint8_t spi_flash_read_stat(void);
-void spi_flash_quad_en(void);
-void close_ssi0(void);
-extern void Init_spi_master(uint32_t ch, uint32_t freq);
-
-#endif

component/boot2/bsp/bsp_systick.c

@@ -1,91 +0,0 @@
-#include	"Includes.h"
-
-#define u32  uint32_t 
-	
-volatile  uint32_t  GulSystickCount=0;
-void	SysTick_Handler(void)
-{
- 	GulSystickCount++;//
-	gpio_output_low(0);
-	gpio_output_high(0);
-	  
-}
- 
-
-
-/*
-nus:要延时的us数.	
-nus:0~204522252(最大值即(2^32)/32)	  
-*/
-
-//#define TICK_PER_US   16
-//#define TICK_PER_US   32
-//#define TICK_PER_US   12
-  #define TICK_PER_US   24
-
-void delay_us(u32 nus)
-{		
-	u32 ticks;
-	u32 told,tnow,tcnt=0;
-	u32 reload=SysTick->LOAD;				//LOAD的值	    	 
-	ticks=nus*TICK_PER_US; 				    //需要的节拍数  32M速度 1us需要32个时钟周期
-	told=SysTick->VAL;        				//刚进入时的计数器值
-	while(1)
-	{
-		tnow=SysTick->VAL;	
-		if(tnow!=told)
-		{	    
-			if(tnow<told)tcnt+=told-tnow;	//这里注意一下SYSTICK是一个递减的计数器就可以了.
-			else tcnt+=reload-tnow+told;	    
-			told=tnow;
-			if(tcnt>=ticks)break;			//时间超过/等于要延迟的时间,则退出.
-		}  
-	};										    
-}  
-
- 
-void delay_ms(u32 nms)
-{	
-	for(uint32_t i=0;i<nms;i++) delay_us(1000);
-}
-
-//#define configCPU_CLOCK_HZ   ( ( unsigned long ) 16000000 )
-//#define configCPU_CLOCK_HZ   ( ( unsigned long ) 32000000 )
-//#define configCPU_CLOCK_HZ   ( ( unsigned long ) 12000000 )
-  #define configCPU_CLOCK_HZ   ( ( unsigned long ) 24000000 )
-	  
-//#define configTICK_RATE_HZ   (  20 )   //50ms滴答定时器中断一次调度一次
-#define configTICK_RATE_HZ   (  1000 )   //1ms滴答定时器中断一次调度一次
-void delay_Init(void)
-{
-//	  SysTick->LOAD=( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-//    SysTick->CTRL|=SysTick_CTRL_CLKSOURCE_Msk;  
-//    SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk;    
-	SysTick_Config(configCPU_CLOCK_HZ / configTICK_RATE_HZ);
-}
-
-
-
-extern void test_systick(void)
-{
-    gpio_mux_ctl(0,0);gpio_fun_inter(0,0);gpio_fun_sel(0,0);gpio_direction_output(0);
-	gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,0);gpio_direction_output(1);
-    SysTick_Config(configCPU_CLOCK_HZ / configTICK_RATE_HZ);
-	while(1)
-	{
-#if 0
-		delay_ms(5);
-	    gpio_output_low(1);
-		delay_ms(5);
-	    gpio_output_high(1);
-#endif		
-		
-#if 1
-		delay_us(200);
-	    gpio_output_low(1);
-		delay_us(200);
-	    gpio_output_high(1);
-#endif		
-
-	}
-}

component/boot2/bsp/bsp_timer.c

@@ -1,173 +0,0 @@
-#include	"Includes.h"
-
- 
- 
-void xc_timer_init(uint8_t tn,uint32_t us)
-{
-	__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL,0x80008); //TIMER_PCLK enable
-	__write_hw_reg32(CPR_TIMER_CLK_CTL(tn),0x0B);//TIMERx_CLK   mclk_in(24MHz)/(2*(0x0B + 0x1))
-	__write_hw_reg32(TIMERx_TCR(tn),0x0); 
-	__write_hw_reg32(TIMERx_TCR(tn),0x2); 
-	__write_hw_reg32(TIMERx_TLC(tn),us); 
-    __write_hw_reg32(TIMERx_TCR(tn),0x3); 
-	NVIC_EnableIRQ(TIMER0_IRQn+tn);
-}
-
-
-extern	void	Init_Timer(uint32_t ch, uint32_t msTick) 
-{
-		uint32_t	val;
-		__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , 0x80008);		
-	  //__write_hw_reg32(CPR_TIMER_CLK_CTL(ch) , 0x10000000);	//- TIMER (32K/2) 16Khz 
-	    __write_hw_reg32(CPR_TIMER_CLK_CTL(ch) , 0x30000000);	//- TIMER 32Khz 
-		__read_hw_reg32(CPR_LP_CTL , val);
-		val |= (1<<2);
-		__write_hw_reg32(CPR_LP_CTL , val);						 
-	
-		__read_hw_reg32(TIMERx_TIC(ch) , val);								
-		__write_hw_reg32(TIMERx_TCR(ch) , 0x00);
-		//val = (msTick * 32000)/1000;
-		val = msTick;
-        __write_hw_reg32(TIMERx_TLC(ch) , val);
-		__write_hw_reg32(TIMERx_TCR(ch) , 0x03);
-
-		val = TIMER0_IRQn + ch;
-		NVIC_EnableIRQ((IRQn_Type)val);						
-}
-
-
-void TIMER0_Handler(void)
-{  
-	uint32_t val=0;
-	__read_hw_reg32(TIMER0_TIC , val);
-	//printf("TIMER0_Handler   \n");
-    gpio_output_low(0);
-	gpio_output_high(0);
-
-}
-
-void TIMER1_Handler(void)
-{
-	uint32_t val=0;
-	__read_hw_reg32(TIMER1_TIC , val);
-	//printf("TIMER1_Handler\n");
-	gpio_output_low(1);
-	gpio_output_high(1);
-}
-
-void TIMER2_Handler(void)
-{
-	uint32_t val=0;
-	__read_hw_reg32(TIMER2_TIC , val);
-	//printf("TIMER2_Handler\n");
-	gpio_output_low(2);
-	gpio_output_high(2);
-
-}
-
-void TIMER3_Handler(void)
-{
-	uint32_t val=0;
-	__read_hw_reg32(TIMER3_TIC , val);
-	//printf("TIMER3_Handler\n");
-	gpio_output_low(3);
-	gpio_output_high(3);
-
-	
-}
-
-
-
-/////////////////////////////////////////AO TIMER///////////////////////////////////////
-#define         TIMER_AO_BASE               0x40002800
-#define     	TIMERx_AO_TLC(a)     		((volatile unsigned *)(TIMER_AO_BASE + 0x00 + (a * 0x14)))
-#define     	TIMERx_AO_TCV(a)     		((volatile unsigned *)(TIMER_AO_BASE + 0x04 + (a * 0x14)))
-#define     	TIMERx_AO_TCR(a)     		((volatile unsigned *)(TIMER_AO_BASE + 0x08 + (a * 0x14)))
-#define     	TIMERx_AO_TIC(a)     		((volatile unsigned *)(TIMER_AO_BASE + 0x0C + (a * 0x14)))
-#define     	TIMERx_AO_TIS(a)      		((volatile unsigned *)(TIMER_AO_BASE + 0x10 + (a * 0x14)))
-
-void aotimer_clk_conf(void)
-{
-	uint32_t val=0;
-	__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x100000);// rest ao timer 
-	__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x100010);// rest ao timer 
-	__read_hw_reg32(CPR_AOCLKEN_GRCTL,  val);
-	__write_hw_reg32(CPR_AOCLKEN_GRCTL, val|0xFF001d);// enable ao timer 0 1  clk and pclk
-
-}
-void aotimer_init(uint8_t tn,uint32_t tick) 
-{  
-
-   	__write_hw_reg32(TIMERx_AO_TCR(tn),0x0);
-	__write_hw_reg32(TIMERx_AO_TCR(tn),0x2);
-	__write_hw_reg32(TIMERx_AO_TLC(tn),tick);
-    __write_hw_reg32(TIMERx_AO_TCR(tn),0x3);
-	 NVIC_EnableIRQ(AOTIMER0_IRQn+tn); 
-	
-//    //timer pclk switch to clk32k when sleep
-//	 uint32_t val=0;
-//	__read_hw_reg32(CPR_AO_REG1, val);
-//	__write_hw_reg32(CPR_AO_REG1,val|(1<<19));//bit 19, 1: sleep timer pclk switch
-
-}	
-
-
-void AOTIMER0_Handler(void)
-{  
-	uint32_t val=0;
-//	*CPR_AO_REG1 &=(~(1<<19));//timer pclk switch to pclk when wake up (if no set ,so it is intering)
-	__read_hw_reg32(TIMERx_AO_TIC(0) , val);
-// 	printf("AOTIMER0_Handler \n");
-	gpio_output_low(2);
-	gpio_output_high(2);
-	 
-}
-void AOTIMER1_Handler(void)
-{  
-	uint32_t val=0;
-//	*CPR_AO_REG1 &=(~(1<<19));//timer pclk switch to pclk when wake up (if no set ,so it is intering)
-	__read_hw_reg32(TIMERx_AO_TIC(1) , val);
-//  printf("AOTIMER1_Handler \n");
-    gpio_output_low(3);
-	gpio_output_high(3);
-
-
-	
-}
-void aotimer_disable(uint32_t ch)
-{   
-    __write_hw_reg32(TIMERx_AO_TCR(ch) , 0x00);                    
-	NVIC_DisableIRQ(AOTIMER0_IRQn+ch);							   
-}
-
- 
-
-extern void test_timer(void)
-{
-	//fpga clk fix 12M (no div)
-    gpio_mux_ctl(0,0);gpio_fun_inter(0,0);gpio_fun_sel(0,0);gpio_direction_output(0);
-	gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,0);gpio_direction_output(1);
-	gpio_mux_ctl(2,0);gpio_fun_inter(2,0);gpio_fun_sel(2,0);gpio_direction_output(2);
-	gpio_mux_ctl(3,0);gpio_fun_inter(3,0);gpio_fun_sel(3,0);gpio_direction_output(3);
-#if 0  
-  //Init_Timer(0,12000);
-    xc_timer_init(0,12000);// 
-    xc_timer_init(1,24000);
-	
-  //Init_Timer(2,12);
-  //Init_Timer(3,24);
-    xc_timer_init(2,12000);
-    xc_timer_init(3,12000);
-#endif	
-	
-#if 1	
-    aotimer_clk_conf();
-  	aotimer_init(0,12);  
- 	aotimer_init(1,2400);  
- 	while(1);
-	{
- 		printf("%#X ",*TIMERx_AO_TCV(0));
-	}
-#endif
-}
- 

component/boot2/bsp/bsp_timer.h

@@ -1,19 +0,0 @@
-#ifndef __BSP_TIMER_H_
-#define __BSP_TIMER_H_
-
-typedef short int16_t;
-typedef int int32_t;
-typedef long long int64_t;
-typedef unsigned char uint8_t;
-typedef unsigned short uint16_t;
-typedef unsigned int uint32_t;
-typedef unsigned long long uint64_t;
-
-typedef uint32_t (*tHandler_callback)(uint16_t val);
-
-extern void Init_Timer(uint32_t ch, uint32_t msTick); /* TIMER��ʼ�� */
-extern void Timer_Register_Callback(tHandler_callback callback, uint32_t ch);
-extern void Timer_disable(uint32_t ch);
-extern uint32_t timer_current_count(uint32_t ch);
-
-#endif

component/boot2/bsp/bsp_uart.c

@@ -1,144 +0,0 @@
-
-/*----------------------------------------------------------------------------------------------------
-	INCLUDE HEADE FILES
-----------------------------------------------------------------------------------------------------*/
-
-#include    "Includes.h"
-
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: Init_uart
-- 函数功能: UART初始化
-- 输入参数: 初始化串口号(0:uart0 1:uart1); 波特率
-- 创建日期: 2016-05-26
-----------------------------------------------------------------------------------------------------*/
-extern	void	Init_uart(uint32_t	ch , uint32_t	baud)
-{
-			uint32_t	val;
-			
-			__write_hw_reg32(CPR_RSTCTL_SUBRST_SW , (1<<(16+ch)));	//复位uart模块
-			__write_hw_reg32(CPR_RSTCTL_SUBRST_SW , ((1<<(16+ch))|(1<<ch)));//解复位uart模块		
-			
-			__read_hw_reg32(CPR_LP_CTL , val);
-			val &= ~(1<<(1-ch));
-			__write_hw_reg32(CPR_LP_CTL , val);						//关闭uartx时钟保护
-			
-			val = (1<<(16+ch+4)) | (1<<(ch+4));
-			__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , val); 			//打开uartx pclk
-			__write_hw_reg32(CPR_UARTx_CLK_GRCTL(ch), 0x110018);
-			//__write_hw_reg32(CPR_UARTx_CLK_CTL(ch), 0x480271);
-            __write_hw_reg32(CPR_UARTx_CLK_CTL(ch), baud>>4);	
-    
-			__write_hw_reg32(UARTx_TCR(ch) , 0x80);                	//使能DLAB位
-			//__write_hw_reg32(UARTx_DLL(ch) , baud);
-            __write_hw_reg32(UARTx_DLL(ch) , baud&0x0F);
-			__write_hw_reg32(UARTx_DLH(ch) , 0);                 		
-
-			__write_hw_reg32(UARTx_TCR(ch) , 0x03);                	//清零DLAB位,8个BIT位
-			__write_hw_reg32(UARTx_FCR(ch) , 0xb7);                	//接收FIFO半满报中断, 并使能FIFO中断
-            __write_hw_reg32(UARTx_IER(ch) , 0x01);                	//打开接收中断
-			val = UART0_IRQn + ch;
-			NVIC_EnableIRQ((IRQn_Type)val);
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: UART0_Handler
-- 函数功能: UART0中断处理函数
-- 输入参数: 无
-- 创建日期: 2016-05-26
-----------------------------------------------------------------------------------------------------*/
-extern	void	UART0_Handler(void)
-{
-		uint32_t	iWK = 0 ;
-		uint8_t		tWK = 0 ;
-
-		__read_hw_reg32(UART0_IIR , iWK);
-		iWK &= 0x0F;
-        
-		if((iWK != 0x04) && (iWK != 0x0c)) return;
-		
-		__read_hw_reg32(UART0_RBR , tWK);
-	
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: UART1_Handler
-- 函数功能: UART1中断处理函数
-- 输入参数: 无
-- 创建日期: 2016-05-26
-----------------------------------------------------------------------------------------------------*/
-extern	void	UART1_Handler(void)
-{
-		uint32_t	iWK = 0 ;
-		uint8_t		tWK = 0 ;
-
-		__read_hw_reg32(UART1_IIR , iWK);
-		iWK &= 0x0F;
-    
-		if((iWK != 0x04) && (iWK != 0x0c)) return;
-		
-		__read_hw_reg32(UART1_RBR , tWK);
-#if 1	
-	   Uart_Send_Char(1,'R');
-	   Uart_Send_Char(1,'e');
-	   Uart_Send_Char(1,'v');
-	   Uart_Send_Char(1,':');
-	   Uart_Send_Char(1,tWK);
-	   Uart_Send_Char(1,'\n');
-#endif	    
-
-}
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: Uart_Send_Char
-- 函数功能: Uart发送一个字符
-- 输入参数: 串口号; 要发送的字符
-- 创建日期: 2016-05-26
-----------------------------------------------------------------------------------------------------*/
-extern	void	Uart_Send_Char(uint32_t	ch, uint8_t	c)
-{
-		unsigned	int	status;
-		for(; ;)
-		{			
-				__read_hw_reg32(UARTx_TSR(ch), status);
-				status &= 0x20;
-				if(status == 0x20) break;
-		}
-		__write_hw_reg32(UARTx_THR(ch), c);
-}
-
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: Uart_Send_String
-- 函数功能: Uart发送一个字符串
-- 输入参数: 串口号; 要发送的字符串
-- 创建日期: 2016-05-26
-----------------------------------------------------------------------------------------------------*/
-extern	void	Uart_Send_String(uint32_t	ch, uint8_t	*s)
-{
-		while(*s != '\0')				
-		{	
-				Uart_Send_Char(ch, *s++);
-		}
-}
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: Uart_Send_Buf
-- 函数功能: Uart发送一个长度为length的uint8_t类型的数组
-- 输入参数: 串口号; 要发送的数组，数组长度
-- 创建日期: 2019-04-02
-- 作    者：陈俊伟
-----------------------------------------------------------------------------------------------------*/
-extern	void	Uart_Send_Buf(uint32_t	ch, uint8_t	*s,uint32_t length)
-{
-		while(length--)				
-		{	
-				Uart_Send_Char(ch, *s++);
-		}
-}
-
- 
-extern  void    test_uart(void) 
-{
- 	gpio_mux_ctl(0,0);gpio_fun_inter(0,0);gpio_fun_sel(0,UART1_RX);
-	gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,UART1_TX);
-    Init_uart(1, BAUD_57600);
-	Uart_Send_String(1,"I am uart1...\n");
-}

component/boot2/bsp/bsp_uart.h

@@ -1,14 +0,0 @@
-#ifndef		__BSP_UART_H_
-#define		__BSP_UART_H_
-
- 
-//#define		BAUD_115200				0x0C002711
-//#define		BAUD_57600				0x06002711
- 
-#define		BAUD_115200				0x04802711
-
-extern	void	Init_uart(uint32_t	ch , uint32_t	baud);
-extern	void	Uart_Send_Char(uint32_t	ch, uint8_t	c);
-extern	void	Uart_Send_String(uint32_t	ch, uint8_t	*s);
-extern	void	Uart_Send_Buf(uint32_t	ch, uint8_t	*s,uint32_t length);
-#endif

component/boot2/bsp/bsp_wdog.c

@@ -1,90 +0,0 @@
-
-
-
-#include    "Includes.h"
-
-
-
-typedef 	     unsigned int 		uint32_t;
-#define     	__write_hw_reg32(reg,val)  ((*reg) = (val))
-#define CPR_CTLAPBCLKEN_GRCTL           ((volatile unsigned *)(0x40000000 + 0x070))
-#define CPR_RSTCTL_CTLAPB_SW            ((volatile unsigned *)(0x40000000 + 0x100))
-#define CPR_RSTCTL_WDTRST_MASK          ((volatile unsigned *)(0x40000000 + 0x114))
-#define	WDT_CR							((volatile unsigned *)(0x40004000 + 0x00))
-#define	WDT_TORR						((volatile unsigned *)(0x40004000 + 0x04))
-#define	WDT_CRR						  	((volatile unsigned *)(0x40004000 + 0x0C))
-/* ---------------------------------------------------------------------------------------------------
-//看门狗计数器对应的初值
-(0x0)0000：0x    FFFF
-(0x1)0001：0x   1FFFF
-(0x2)0010：0x   3FFFF
-(0x3)0011：0x   7FFFF
-(0x4)0100：0x   FFFFF
-(0x5)0101：0x  1FFFFF
-(0x6)0110：0x  3FFFFF
-(0x7)0111：0x  7FFFFF
-(0x8)1000：0x  FFFFFF----约2S
-(0x9)1001：0x 1FFFFFF----约5S
-(0xA)1010：0x 3FFFFFF----约10S
-(0xB)1011：0x 7FFFFFF----约20S
-(0xC)1100：0x FFFFFFF
-(0xD)1101：0x1FFFFFFF
-(0xE)1110：0x3FFFFFFF
-(0xF)1111：0x7FFFFFFF
-----------------------------------------------------------------------------------------------------*/
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: xc_wdog_init
-- 函数功能: 初始化看门狗
-- 函数形参：看门狗计数器重装值
-- 创建日期: 2019-04-22
-----------------------------------------------------------------------------------------------------*/
-void xc_wdog_init(uint32_t counter_value) 
-{	 
-	__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL,0x10001); //WDT_PCLK 时钟使能
-    __write_hw_reg32(CPR_RSTCTL_CTLAPB_SW,0x40000);  //WDT 模块软复位    
-	__write_hw_reg32(CPR_RSTCTL_CTLAPB_SW,0x40004);
-	__write_hw_reg32(CPR_RSTCTL_WDTRST_MASK,0x20);//屏蔽 WDT 引起的 M0 的软复位,不屏蔽 WDT 引起的系统的软复位
-	__write_hw_reg32(WDT_CR,0x7);// WDT 使能 ,M0 复位信号，维持4个 pclk 时钟周期,工作模式 0，直接产生复位信号送给 CPR
-	__write_hw_reg32(WDT_TORR,counter_value);
-	__write_hw_reg32(WDT_CRR,0x76);	//重启计数器	
-}
-/* ---------------------------------------------------------------------------------------------------
-- 函数名称: xc_wdog_feed
-- 函数功能: 喂看门狗
-- 函数形参：无
-- 创建日期: 2019-04-22
-----------------------------------------------------------------------------------------------------*/
-void xc_wdog_feed(void)
-{   
-     __write_hw_reg32(WDT_CRR,0x76);	//重启计数器	
-}
-
-
-
-extern  void   test_wdog(void) 
-{
-	uint8_t count=0;
-	xc_wdog_init(0xA);
-	//__write_hw_reg32(CPR_RSTCTL_WDTRST_MASK,0x3);//屏蔽看门狗复位
-	printf("wdog reset\n ");
-	while(1)
-	{
-		
-	    printf("WDT_CCVR=%d\n",*WDT_CCVR);
-		printf("WDT_STAT=%d\n",*WDT_STAT);
-		for(uint32_t i=0; i<0x120000; i++);
-		for(uint32_t i=0; i<0x120000; i++);
-		for(uint32_t i=0; i<0x120000; i++);
-		//不喂狗时可以测试几秒钟看门狗复位
-		if(5==count) 
-		{
-			//xc_wdog_init(0xA);
-			//xc_wdog_feed();//此处不喂狗会引起系统复位
-			count=0;
-		}
-		else
-		{
-			count++;
-		}
-	}
-}

component/boot2/bsp/bsp_wdog.h

@@ -1,6 +0,0 @@
-#ifndef _BSP_WDOG_H
-#define _BSP_WDOG_H
-#include 	"Platform.h"
-void xc_wdog_init(uint32_t counter_value);//看门狗初始化
-void xc_wdog_feed(void);//喂狗
-#endif

component/boot2/bsp/bsp_xip.c

@@ -1,140 +0,0 @@
-#include "Includes.h"
-
-
-// #define     printf(...)             (0)
-
-#ifdef XIP_JUMP
-
-#endif
-typedef void (*iapfun)(void); // 定义一个函数类型的参数.
-iapfun jump2app;
-__asm void MSR_MSP(uint32_t addr) // 设置栈顶地址  addr:栈顶地址
-{
-    MSR MSP, r0 // set Main Stack value
-                 BX r14
-}
-void delay_wait(uint8_t cn)
-{
-    for (int i = 0; i < cn; i++)
-        for (int j = 0; j < 0x200; j++)
-            ;
-}
-void jump_app()
-{
-    uint32_t pes=0x11001000;
-    typedef void (*iapfun)(void); // 定义一个函数类型的参数static iapfun jump2app;
-    jump2app = (iapfun) * (uint32_t *)(pes + 4);
-     MSR_MSP(*(uint32_t *) (pes));
-    jump2app ();
-
-    while(1);
-}
-
-#define __write_hw_reg32(reg,val)  ((*reg) = (val))
-#define __read_hw_reg32(reg, val)  ((val) = (*reg))  
-#define setbit(x,y) ((x) |= (1<<(y)))
-#define clrbit(x,y) ((x) &= ~(1<<(y)))
-
-#define CPR_BASE						0x40000000
-#define CPR_SPIx_MCLK_CTL(a)            ((volatile unsigned *)(CPR_BASE + 0x050 + (a*0x04)))
-#define CPR_CTLAPBCLKEN_GRCTL        ((volatile unsigned *)(CPR_BASE + 0x070))
-#define CPR_RSTCTL_SUBRST_SW         ((volatile unsigned *)(CPR_BASE + 0x104))
-#define CPR_CTL_MUXCTL3              ((volatile unsigned *)(CPR_BASE + 0x19c))
-void close_ssi0(void)
-{
-   	__write_hw_reg32(CPR_SPIx_MCLK_CTL(0), 0x110000);//close ssi0 mclk
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000000)); //close ssi0 pclk
-    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040000); //复位ssi0
-    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040004); //复位ssi0
-}
-
-extern void gpio_mux_ctl_u(uint8_t num, uint8_t mux) //(num:32-34)
-{
-    if (mux > 3)
-        return;
-    uint32_t tv = 0;
-    __read_hw_reg32(CPR_CTL_MUXCTL3, tv);
-    tv = (tv & (~(0x3 << ((num % 16) * 2)))) | (mux << ((num % 16) * 2));
-    __write_hw_reg32(CPR_CTL_MUXCTL3, tv);
-}
-
-extern void init_xip(uint8_t mode)
-{
-
-#ifdef QUAD_ENABLE
-    if (mode == QUAD_MODE)
-    {
-
-        if ((spi_flash_read_stat() & 0x02) == 0)
-        {
-
-            spi_flash_write_enable();
-            spi_flash_quad_en();
-            while (spi_flash_wait_till_ready())
-                ;
-        }
-        else
-        {
-#ifdef DEBUG_PRINT
-            printf("quad has been enabled !!!\n");
-#endif
-        }
-    }
-#endif
-    close_ssi0(); // close ssi0
-
-    // config fmc pin
-    gpio_mux_ctl_u(33, 1); // d2
-    gpio_mux_ctl_u(34, 1); // d3
-
-    gpio_mux_ctl_u(35, 2); // clk
-    gpio_mux_ctl_u(36, 2); // cs
-    gpio_mux_ctl_u(37, 2); // d0 rx
-    gpio_mux_ctl_u(38, 2); // d1 tx
-
-    // open fmc clk
-    __write_hw_reg32(FMC_CTL, 0x0503 | (0 << 11)); //
-    delay_wait(1);
-    __write_hw_reg32(FMC_CTL, 0x3503 | (0 << 11)); //
-    delay_wait(1);
-    // config cache
-    __write_hw_reg32(CACHE_CCR, 0x00);
-    delay_wait(6);
-    __write_hw_reg32(CACHE_CCR, 0x21);
-    delay_wait(6);
-
-    // config fmc contrl
-    __write_hw_reg32(FMC_EN, 0x00); // Disables DWC_ssi
-
-    __write_hw_reg32(FMC_IE, 0x00);
-    __write_hw_reg32(FMC_CTRL0, 0x1F); /* 32bit SPI data */
-    __write_hw_reg32(FMC_SE, 0x01);
-    __write_hw_reg32(FMC_RXFTL, 0x00);
-    __write_hw_reg32(FMC_TXFTL, 0x00);
-
-    __write_hw_reg32(FMC_XIP_SER, 0x01);
-    __write_hw_reg32(FMC_XIP_CNT_TIME_OUT, 0xFF); // XIP time out
-    __write_hw_reg32(FMC_BAUD, 0x2);              // SSI Clock Divider= 2 --mclk/2
-    if (mode == QUAD_MODE)                        // #ifdef  QUAD_ENABLE //1   //quad
-    {
-#ifdef DEBUG_PRINT
-        uart_printf("xip quad cmd\n");
-#endif
-        __write_hw_reg32(FMC_XIP_CTRL, (2) | (6 << 4) | (2 << 9) | (1 << 22) | (1 << 29) | (1 << 23) | (0 << 24) | (8 << 13));
-        __write_hw_reg32(FMC_XIP_INCR_INST, 0x6b); // quad read cmd
-        __write_hw_reg32(FMC_XIP_WRAP_INST, 0x6b); // quad read cmd
-    }
-    else // #else   //dual
-    {
-#ifdef DEBUG_PRINT
-//        printf("xip dual cmd\n");
-#endif
-        __write_hw_reg32(FMC_XIP_CTRL, (1) | (6 << 4) | (2 << 9) | (1 << 22) | (1 << 29) | (1 << 23) | (0) | (8 << 13));
-        __write_hw_reg32(FMC_XIP_INCR_INST, 0x3b); // dual read cmd
-        __write_hw_reg32(FMC_XIP_WRAP_INST, 0x3b); // dual read cmd
-    }                                              // #endif
-
-    __write_hw_reg32(FMC_EN, 0x01); // Enables  DWC_ssi
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x100000);
-    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x10000);
-}

component/boot2/bsp/bsp_xip.h

@@ -1,69 +0,0 @@
-#ifndef __BSP_XIP_H__
-#define __BSP_XIP_H__
-
-#include    "xc6xxx.h"
-
-#define QUAD_MODE  1
-#define DUAL_MODE  0
-
-#define	    FMC_XIP_BASE                             0x11000000
-#define	    FMC_REG_BASE                             0x51000000
-#define	    FMC_CACHE_BASE                           0x52000000
-
-#define		FMC_CTL                         ((volatile unsigned *)(CPR_BASE + 0x270))
-
-#define		        FMC_CTRL0 				((volatile unsigned *)(FMC_REG_BASE + 0x00))
-#define	            FMC_CTRL1	            ((volatile unsigned *)(FMC_REG_BASE + 0x04))
-#define		        FMC_EN 					((volatile unsigned *)(FMC_REG_BASE + 0x08))
-#define		        FMC_SE 					((volatile unsigned *)(FMC_REG_BASE + 0x10))
-#define		        FMC_BAUD 				((volatile unsigned *)(FMC_REG_BASE + 0x14))
-#define		        FMC_TXFTL 				((volatile unsigned *)(FMC_REG_BASE + 0x18))
-#define		        FMC_RXFTL 				((volatile unsigned *)(FMC_REG_BASE + 0x1c))
-#define		        FMC_TXFL 				((volatile unsigned *)(FMC_REG_BASE + 0x20))
-#define		        FMC_RXFL 				((volatile unsigned *)(FMC_REG_BASE + 0x24))
-#define		        FMC_STS 				((volatile unsigned *)(FMC_REG_BASE + 0x28))
-#define		        FMC_IE 					((volatile unsigned *)(FMC_REG_BASE + 0x2c))
-#define		        FMC_IS 					((volatile unsigned *)(FMC_REG_BASE + 0x30))
-#define		        FMC_RIS 				((volatile unsigned *)(FMC_REG_BASE + 0x34))
-#define		        FMC_TXOIC 				((volatile unsigned *)(FMC_REG_BASE + 0x38))
-#define		        FMC_RXOIC 				((volatile unsigned *)(FMC_REG_BASE + 0x3c))
-#define		        FMC_RXUIC 				((volatile unsigned *)(FMC_REG_BASE + 0x40))
-#define		        FMC_IC 					((volatile unsigned *)(FMC_REG_BASE + 0x48))
-#define		        FMC_DMAS 				((volatile unsigned *)(FMC_REG_BASE + 0x4c))
-#define		        FMC_DMATDL 				((volatile unsigned *)(FMC_REG_BASE + 0x50))
-#define		        FMC_DMARDL 				((volatile unsigned *)(FMC_REG_BASE + 0x54))
-#define		        FMC_DATA 			    ((volatile unsigned *)(FMC_REG_BASE + 0x60))
-#define	            FMC_SPI_CTRLR0 	        ((volatile unsigned *)(FMC_REG_BASE + 0xf4))
-
-
-
-#define	    FMC_XIP_INCR_INST 	    	    ((volatile unsigned *)(FMC_REG_BASE + 0x100))
-#define	    FMC_XIP_WRAP_INST 	    	    ((volatile unsigned *)(FMC_REG_BASE + 0x104))
-#define	    FMC_XIP_CTRL 	        	    ((volatile unsigned *)(FMC_REG_BASE + 0x108))
-#define	    FMC_XIP_SER 	        	    ((volatile unsigned *)(FMC_REG_BASE + 0x10c))
-#define	    FMC_XRXOICR 	        	    ((volatile unsigned *)(FMC_REG_BASE + 0x110))
-#define	    FMC_XIP_CNT_TIME_OUT 	        ((volatile unsigned *)(FMC_REG_BASE + 0x114))
- 
-
-#define CACHE_CCR                           ((volatile unsigned *)(FMC_CACHE_BASE + 0x00))
-#define CACHE_SR                            ((volatile unsigned *)(FMC_CACHE_BASE + 0x04))
-#define CACHE_IRQMASK                       ((volatile unsigned *)(FMC_CACHE_BASE + 0x08))
-#define CACHE_IRQSTAT                       ((volatile unsigned *)(FMC_CACHE_BASE + 0x0c))
-#define CACHE_HWPARAMS                      ((volatile unsigned *)(FMC_CACHE_BASE + 0x10))
-#define CACHE_CSHR                          ((volatile unsigned *)(FMC_CACHE_BASE + 0x14))
-#define CACHE_CSMR                          ((volatile unsigned *)(FMC_CACHE_BASE + 0x18))
-#define CACHE_PIDR4                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFD0))
-#define CACHE_PIDR5                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFD4))
-#define CACHE_PIDR6                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFD8))
-#define CACHE_PIDR7                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFDC))
-#define CACHE_PIDR0                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFE0))
-#define CACHE_PIDR1                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFE4))
-#define CACHE_PIDR2                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFE8))
-#define CACHE_PIDR3                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFEC))
-#define CACHE_CIDR0                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFF0))
-#define CACHE_CIDR1                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFF4))
-#define CACHE_CIDR2                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFF8))
-#define CACHE_CIDR3                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFFC))
-
-extern  void   init_xip(uint8_t mode);
-#endif  

component/boot2/bsp/bsp_xip_normal.c

@@ -1,212 +0,0 @@
-#include "Includes.h"
-#include "bsp_xip_normal.h"
-// #include    "test_config.h"
-
-#define CMD_PWRDWN 0xB9
-#define CMD_RELEASE_PWRDWN 0xAB
-#define CMD_WRITE_ENABLE 0x06
-
-#define CMD_WRITE_STATUS1 0x01
-#define CMD_READ_STATUS 0x05
-
-#define CMD_WRITE_STATUS2 0x31
-#define CMD_READ_STATUS2 0x35
-
-#define SPI0_D2_WP 33
-#define SPI0_D3_HOLD 34
-#define printf(...) (0)
-
-typedef void (*iapfun)(void); // 定义一个函数类型的参数.
-iapfun jump2app;
-__asm void MSR_MSP(uint32_t addr) // 设置栈顶地址  addr:栈顶地址
-{
-    MSR MSP, r0 // set Main Stack value
-                 BX r14
-}
-
-//void close_ssi0(void)
-//{
-//    __write_hw_reg32(CPR_SPIx_MCLK_CTL(0), 0x110000);     // close ssi0 mclk
-//    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, (0x1000000)); // close ssi0 pclk
-//    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x040000);     // 复位ssi0
-//    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x040004);     // 复位ssi0
-//}
-
-// #define QUAD_ENABLE
-
-#ifdef QUAD_ENABLE
-#define CMD_WRITE_STATUS 0x01
-void spi_flash_quad_en(void)
-{
-    uint32_t bWk, cWk;
-    __read_hw_reg32(SSI0_CTRL0, bWk);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_DMAS, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, 0x07); /* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN, 0x01);
-
-    __write_hw_reg32(SSI0_DATA, CMD_WRITE_STATUS);
-    __write_hw_reg32(SSI0_DATA, 0);
-    __write_hw_reg32(SSI0_DATA, 0x02);
-    do
-    {
-        __read_hw_reg32(SSI0_STS, cWk);
-    } while ((cWk & 0x05) != 0x04);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, bWk);
-}
-
-#define CMD_READ_STATUS2 0x35
-uint8_t spi_flash_read_stat(void)
-{
-    uint32_t bWk, cWk;
-    uint8_t s8_15;
-    __read_hw_reg32(SSI0_CTRL0, bWk);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_DMAS, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, 0x07); /* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN, 0x01);
-
-    __write_hw_reg32(SSI0_DATA, CMD_READ_STATUS2);
-    __write_hw_reg32(SSI0_DATA, 0xff);
-
-    do
-    {
-        __read_hw_reg32(SSI0_STS, cWk);
-    } while ((cWk & 0x05) != 0x04);
-    cWk = *SSI0_DATA; // no use
-    s8_15 = *SSI0_DATA;
-    // printf("s8_15=%#X\n" , s8_15);
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, bWk);
-
-    return s8_15;
-}
-uint8_t spi_flash_wait_till_ready(void)
-{
-    uint16_t cmd = (CMD_READ_STATUS << 8);
-    uint32_t iWK = 0;
-    uint16_t dWK = 0;
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_DMAS, 0x00);  /* turn off dma*/
-    __write_hw_reg32(SSI0_DMATDL, 0x0); //-
-    __write_hw_reg32(SSI0_DMARDL, 0x0); //-
-    __write_hw_reg32(SSI0_EN, 0x01);
-
-    __write_hw_reg32(SSI0_DATA, cmd);
-
-    do
-    {
-        __read_hw_reg32(SSI0_STS, iWK);
-    } while ((iWK & 0x05) != 0x04);
-
-    __read_hw_reg32(SSI0_DATA, dWK);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-
-    return (uint8_t)(dWK & 0x01);
-}
-
-extern void spi_flash_write_enable(void)
-{
-    uint32_t bWk, cWk;
-
-    __read_hw_reg32(SSI0_CTRL0, bWk);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_DMAS, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, 0x07); /* 8bit SPI data */
-    __write_hw_reg32(SSI0_EN, 0x01);
-
-    __write_hw_reg32(SSI0_DATA, CMD_WRITE_ENABLE);
-
-    do
-    {
-        __read_hw_reg32(SSI0_STS, cWk);
-    } while ((cWk & 0x05) != 0x04);
-
-    __write_hw_reg32(SSI0_EN, 0x00);
-    __write_hw_reg32(SSI0_CTRL0, bWk);
-}
-#endif
-
-void delay_wait(uint8_t cn)
-{
-    for (int i = 0; i < cn; i++)
-        for (int j = 0; j < 0x200; j++)
-            ;
-}
-void init_xip_normal(void)
-{
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x40004); /*gpio_pclk enable*/
-    __write_hw_reg32(CPR_OTHERCLKEN_GRCTL, 0x10001);  /*gpio_clk  enable*/
-    // bootrom init spi0,
-#ifdef QUAD_ENABLE
-    // spi_flash_quad_en();
-    if ((spi_flash_read_stat() & 0x02) == 0)
-    {
-        spi_flash_write_enable();
-        spi_flash_quad_en();
-        while (spi_flash_wait_till_ready())
-            ;
-    }
-#endif
-    close_ssi0(); // close ssi0
-
-    // config fmc pin
-    gpio_mux_ctl_u(33, 1); // d2
-    gpio_mux_ctl_u(34, 1); // d3
-
-    gpio_mux_ctl_u(35, 2); // clk
-    gpio_mux_ctl_u(36, 2); // cs
-    gpio_mux_ctl_u(37, 2); // d0 rx
-    gpio_mux_ctl_u(38, 2); // d1 tx
-
-    // open fmc clk
-    __write_hw_reg32(FMC_CTL, 0x0503 | (0 << 11)); //
-    delay_wait(1);
-    __write_hw_reg32(FMC_CTL, 0x3503 | (0 << 11)); //
-    delay_wait(1);
-    // config cache
-    __write_hw_reg32(CACHE_CCR, 0x00);
-    delay_wait(6);
-    __write_hw_reg32(CACHE_CCR, 0x21);
-    delay_wait(6);
-
-    // config fmc contrl
-    __write_hw_reg32(FMC_EN, 0x00); // Disables DWC_ssi
-
-    __write_hw_reg32(FMC_IE, 0x00);
-    __write_hw_reg32(FMC_CTRL0, 0x1F); /* 32bit SPI data */
-    __write_hw_reg32(FMC_SE, 0x01);
-    __write_hw_reg32(FMC_RXFTL, 0x00);
-    __write_hw_reg32(FMC_TXFTL, 0x00);
-
-    __write_hw_reg32(FMC_XIP_SER, 0x01);
-    __write_hw_reg32(FMC_XIP_CNT_TIME_OUT, 0xFF); // XIP time out
-    __write_hw_reg32(FMC_BAUD, 0x2);              // SSI Clock Divider= 2 --mclk/2
-#ifdef QUAD_ENABLE                                // 1   //quad
-    __write_hw_reg32(FMC_XIP_CTRL, (2) | (6 << 4) | (2 << 9) | (1 << 22) | (1 << 29) | (1 << 23) | (0 << 24) | (8 << 13));
-    __write_hw_reg32(FMC_XIP_INCR_INST, 0x6b); // quad read cmd
-    __write_hw_reg32(FMC_XIP_WRAP_INST, 0x6b); // quad read cmd
-#else                                          // dual
-    __write_hw_reg32(FMC_XIP_CTRL, (1) | (6 << 4) | (2 << 9) | (1 << 22) | (1 << 29) | (1 << 23) | (0) | (8 << 13));
-    __write_hw_reg32(FMC_XIP_INCR_INST, 0x3b); // dual read cmd
-    __write_hw_reg32(FMC_XIP_WRAP_INST, 0x3b); // dual read cmd
-#endif
-    __write_hw_reg32(FMC_EN, 0x01); // Enables  DWC_ssi
-
-
-    __write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x100000);
-    __write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x10000);
-	
-    jump2app = (iapfun) * (uint32_t *)(0x11001000 + 4); // 用户代码区第二个字为程序开始地址(复位地址)
-    MSR_MSP(*(uint32_t *)(0x11001000));                 // 设置栈顶地址  addr:栈顶地址 （用户代码区第一个字为程序的栈顶地址）
-    jump2app(); // 设置好栈顶地址后 二级bootloder跳转到新的程序
-    while (1)
-        ;
-}

component/boot2/bsp/bsp_xip_normal.h

@@ -1,64 +0,0 @@
-#ifndef __BSP_XIP_H__
-#define __BSP_XIP_H__
-extern  void   init_xip_normal(void);
-#define	    FMC_XIP_BASE                             0x11000000
-#define	    FMC_REG_BASE                             0x51000000
-#define	    FMC_CACHE_BASE                           0x52000000
-#define     SPIM_CLK_16MHZ          2     
-#define		FMC_CTL                         ((volatile unsigned *)(CPR_BASE + 0x270))
-
-#define		        FMC_CTRL0 				((volatile unsigned *)(FMC_REG_BASE + 0x00))
-#define	            FMC_CTRL1	            ((volatile unsigned *)(FMC_REG_BASE + 0x04))
-#define		        FMC_EN 					((volatile unsigned *)(FMC_REG_BASE + 0x08))
-#define		        FMC_SE 					((volatile unsigned *)(FMC_REG_BASE + 0x10))
-#define		        FMC_BAUD 				((volatile unsigned *)(FMC_REG_BASE + 0x14))
-#define		        FMC_TXFTL 				((volatile unsigned *)(FMC_REG_BASE + 0x18))
-#define		        FMC_RXFTL 				((volatile unsigned *)(FMC_REG_BASE + 0x1c))
-#define		        FMC_TXFL 				((volatile unsigned *)(FMC_REG_BASE + 0x20))
-#define		        FMC_RXFL 				((volatile unsigned *)(FMC_REG_BASE + 0x24))
-#define		        FMC_STS 				((volatile unsigned *)(FMC_REG_BASE + 0x28))
-#define		        FMC_IE 					((volatile unsigned *)(FMC_REG_BASE + 0x2c))
-#define		        FMC_IS 					((volatile unsigned *)(FMC_REG_BASE + 0x30))
-#define		        FMC_RIS 				((volatile unsigned *)(FMC_REG_BASE + 0x34))
-#define		        FMC_TXOIC 				((volatile unsigned *)(FMC_REG_BASE + 0x38))
-#define		        FMC_RXOIC 				((volatile unsigned *)(FMC_REG_BASE + 0x3c))
-#define		        FMC_RXUIC 				((volatile unsigned *)(FMC_REG_BASE + 0x40))
-#define		        FMC_IC 					((volatile unsigned *)(FMC_REG_BASE + 0x48))
-#define		        FMC_DMAS 				((volatile unsigned *)(FMC_REG_BASE + 0x4c))
-#define		        FMC_DMATDL 				((volatile unsigned *)(FMC_REG_BASE + 0x50))
-#define		        FMC_DMARDL 				((volatile unsigned *)(FMC_REG_BASE + 0x54))
-#define		        FMC_DATA 			    ((volatile unsigned *)(FMC_REG_BASE + 0x60))
-#define	            FMC_SPI_CTRLR0 	        ((volatile unsigned *)(FMC_REG_BASE + 0xf4))
-
-
-
-#define	    FMC_XIP_INCR_INST 	    	    ((volatile unsigned *)(FMC_REG_BASE + 0x100))
-#define	    FMC_XIP_WRAP_INST 	    	    ((volatile unsigned *)(FMC_REG_BASE + 0x104))
-#define	    FMC_XIP_CTRL 	        	    ((volatile unsigned *)(FMC_REG_BASE + 0x108))
-#define	    FMC_XIP_SER 	        	    ((volatile unsigned *)(FMC_REG_BASE + 0x10c))
-#define	    FMC_XRXOICR 	        	    ((volatile unsigned *)(FMC_REG_BASE + 0x110))
-#define	    FMC_XIP_CNT_TIME_OUT 	        ((volatile unsigned *)(FMC_REG_BASE + 0x114))
- 
-
-#define CACHE_CCR                           ((volatile unsigned *)(FMC_CACHE_BASE + 0x00))
-#define CACHE_SR                            ((volatile unsigned *)(FMC_CACHE_BASE + 0x04))
-#define CACHE_IRQMASK                       ((volatile unsigned *)(FMC_CACHE_BASE + 0x08))
-#define CACHE_IRQSTAT                       ((volatile unsigned *)(FMC_CACHE_BASE + 0x0c))
-#define CACHE_HWPARAMS                      ((volatile unsigned *)(FMC_CACHE_BASE + 0x10))
-#define CACHE_CSHR                          ((volatile unsigned *)(FMC_CACHE_BASE + 0x14))
-#define CACHE_CSMR                          ((volatile unsigned *)(FMC_CACHE_BASE + 0x18))
-#define CACHE_PIDR4                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFD0))
-#define CACHE_PIDR5                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFD4))
-#define CACHE_PIDR6                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFD8))
-#define CACHE_PIDR7                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFDC))
-#define CACHE_PIDR0                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFE0))
-#define CACHE_PIDR1                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFE4))
-#define CACHE_PIDR2                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFE8))
-#define CACHE_PIDR3                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFEC))
-#define CACHE_CIDR0                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFF0))
-#define CACHE_CIDR1                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFF4))
-#define CACHE_CIDR2                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFF8))
-#define CACHE_CIDR3                       ((volatile unsigned *)(FMC_CACHE_BASE + 0xFFC))
-
-
-#endif  

component/boot2/bsp/startup/Initialization.ini

@@ -1,12 +0,0 @@
-
-FUNC    void    Initialization(void)
-{
-    SP = _RDWORD(0x10000000);
-    PC = _RDWORD(0x10000004); 
-    _WDWORD(0x4000013C, 0x10000001);
-}
-
-
-
-LOAD %L INCREMENTAL
-Initialization();

component/boot2/bsp/startup/core_cm0.c

@@ -1,241 +0,0 @@
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined(__CC_ARM)
-#define __ASM __asm       /*!< asm keyword for ARM Compiler          */
-#define __INLINE __inline /*!< inline keyword for ARM Compiler       */
-
-#elif defined(__ICCARM__)
-#define __ASM __asm     /*!< asm keyword for IAR Compiler          */
-#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined(__GNUC__)
-#define __ASM __asm     /*!< asm keyword for GNU Compiler          */
-#define __INLINE inline /*!< inline keyword for GNU Compiler       */
-
-#elif defined(__TASKING__)
-#define __ASM __asm     /*!< asm keyword for TASKING Compiler      */
-#define __INLINE inline /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-/* ##########################  Core Instruction Access  ######################### */
-
-#if defined(__CC_ARM) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-                bx lr
-}
-#endif /* __ARMCC_VERSION  */
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-                bx lr
-}
-#endif /* __ARMCC_VERSION  */
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __CLREX(void)
-{
-  clrex
-}
-#endif /* __ARMCC_VERSION  */
-
-#elif (defined(__ICCARM__))  /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined(__GNUC__))    /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined(__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
-
-/* ###########################  Core Function Access  ########################### */
-
-#if defined(__CC_ARM) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-              bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-                   bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_IPSR(void)
-{
-  mrs r0, ipsr
-              bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_APSR(void)
-{
-  mrs r0, apsr
-              bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_xPSR(void)
-{
-  mrs r0, xpsr
-              bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-              bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-               bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-              bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-               bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-              bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-                   bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-#elif (defined(__ICCARM__))  /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined(__GNUC__))    /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined(__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif

component/boot2/bsp/startup/core_cm0.h

@@ -1,703 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V2.01
- * @date     06. December 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )                   
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M0
-   
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
- 
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
- 
-  The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease 
-  access to the Cortex-M Core
- */ 
-
-/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
-  List of Lint messages which will be suppressed and not shown:
-    - not yet checked
-  .
-  Note:  To re-enable a Message, insert a space before 'lint' *
- 
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core 
-   - Cortex-M core Revision Number
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
-
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define     __I     volatile           /*!< defines 'read only' permissions                 */
-#else
-  #define     __I     volatile const     /*!< defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-*/
-
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */ 
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IPR[8];                  /*!< Offset: 0x3EC (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
-       uint32_t RESERVED0;                                      
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;                                      
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-       uint32_t RESERVED2[2];                                   
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-} SCB_Type;                                                
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register   
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24                                             /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup  CMSIS_core_register   
-  @{
- */
- 
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    This function enables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
-
-    \param [in]      IRQn  Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    This function disables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value. 
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt. 
-
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    This function sets the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    This function clears the pending bit for the specified interrupt. 
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    This function sets the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    Note: The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    This function reads the priority for the specified interrupt. The interrupt 
-    number can be positive to specify an external (device specific) 
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
-
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */              
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */              
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*lint -restore */

component/boot2/bsp/startup/core_cmFunc.h

@@ -1,844 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-/* ARM armcc specific functions */
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* IAR iccarm specific functions */
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-  
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-  
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H__ */