/*! * \file xc_drv_aotimer.h * * \brief The header of xc_drv_aotimer.c * * \copyright Revised BSD License, see section \ref LICENSE. * * \code * * _ __ _ ________ _ * | |/ /(_)___ / ____/ /_ (_)___ * | // / __ \/ / / __ \/ / __ \ * / |/ / / / / /___/ / / / / /_/ / * /_/|_/_/_/ /_/\____/_/ /_/_/ .___/ * /_/ * (C) 2022-2025 XinChip * * \endcode * * \author ( XinChip ) Alex-J * * \author ( XinChip ) */ #ifndef _XC_DRV_SPI_H_ #define _XC_DRV_SPI_H_ /*----------------------------------------------------------------------------------- INCLUDE HEADE FILES ------------------------------------------------------------------------------------*/ #include #include #include "xc6xxx.h" /*------------------------------------------------------------------------------------ Macros -------------------------------------------------------------------------------------*/ #define SPI_WAIT_TIMEOUT 65535 // temporary macros -- alex revised #define SSI_CTRL0_FRF_MOTOROLA (0x1UL) #define SSI_CTRL0_FRF_TI (0x0UL) /* SPI_Mode SPI Mode */ #define SPI_MODE_SLAVE (0x00000000U) #define SPI_MODE_MASTER (0x00000001U) /* SPI_data_size */ #define SSI_CTRL0_DFS_LEN_16BIT ((uint16_t)0x0fUL) #define SSI_CTRL0_DFS_LEN_8BIT ((uint16_t)0x07UL) /* SPI_data_direction */ #define SSI_CTRL0_TMOD_WR (0x0UL) #define SSI_CTRL0_TMOD_W (0x1UL) #define SSI_CTRL0_TMOD_R (0x2UL) /* SPI_BaudRate_Prescaler */ #define SSI_BAUD_DIV_2 (0x02UL) #define SSI_BAUD_DIV_4 (0x04UL) #define SSI_BAUD_DIV_6 (0x06UL) #define SSI_BAUD_DIV_8 (0x08UL) #define SSI_BAUD_DIV_10 (0x0aUL) #define SSI_BAUD_DIV_12 (0x0cUL) /* SPI_Clock_Polarity */ #define SSI_CTRL0_SCPOL_HIGH (0x1UL) #define SSI_CTRL0_SCPOL_LOW (0x0UL) /* SPI_Clock_Phase */ #define SSI_CTRL0_SCPHA_LEAD (0x0UL) #define SSI_CTRL0_SCPHA_TRAIL (0x1UL) /* SPI_MSB_transmission */ #define SPI_FirstBit_MSB ((uint16_t)0x0000) #define SSI_TXFTL_FIFO_0 (0x00UL) #define SSI_TXFTL_FIFO_1 (0x01UL) #define SSI_TXFTL_FIFO_2 (0x02UL) #define SSI_TXFTL_FIFO_3 (0x03UL) #define SSI_TXFTL_FIFO_4 (0x04UL) #define SSI_TXFTL_FIFO_5 (0x05UL) #define SSI_TXFTL_FIFO_6 (0x06UL) #define SSI_TXFTL_FIFO_7 (0x07UL) #define SSI_RXFTL_FIFO_0 (0x00UL) #define SSI_RXFTL_FIFO_1 (0x01UL) #define SSI_RXFTL_FIFO_2 (0x02UL) #define SSI_RXFTL_FIFO_3 (0x03UL) #define SSI_RXFTL_FIFO_4 (0x04UL) #define SSI_RXFTL_FIFO_5 (0x05UL) #define SSI_RXFTL_FIFO_6 (0x06UL) #define SSI_RXFTL_FIFO_7 (0x07UL) #define SSI_IE_TXEIE_ENABLE (0x1UL << SSI_TXEIE_POS) #define SSI_IE_TXEIE_DISABLE (0x0UL << SSI_TXEIE_POS) #define SSI_IE_TXOIE_ENABLE (0x1UL << SSI_TXOIE_POS) #define SSI_IE_TXOIE_DISABLE (0x0UL << SSI_TXOIE_POS) #define SSI_IE_RXUIE_ENABLE (0x1UL << SSI_RXUIE_POS) #define SSI_IE_RXUIE_DISABLE (0x0UL << SSI_RXUIE_POS) #define SSI_IE_RXOIE_ENABLE (0x1UL << SSI_RXOIE_POS) #define SSI_IE_RXOIE_DISABLE (0x0UL << SSI_RXOIE_POS) #define SSI_IE_RXFIE_ENABLE (0x1UL << SSI_RXFIE_POS) #define SSI_IE_RXFIE_DISABLE (0x0UL << SSI_RXFIE_POS) #define SSI_IS_TXEIS_SET (0x1UL << SSI_TXEIS_POS) #define SSI_IS_TXEIS_RESET (0x0UL << SSI_TXEIS_POS) #define SSI_IS_TXOIS_SET (0x1UL << SSI_TXOIS_POS) #define SSI_IS_TXOIS_RESET (0x0UL << SSI_TXOIS_POS) #define SSI_IS_RXUIS_SET (0x1UL << SSI_RXUIS_POS) #define SSI_IS_RXUIS_RESET (0x0UL << SSI_RXUIS_POS) #define SSI_IS_RXOIS_SET (0x1UL << SSI_RXOIS_POS) #define SSI_IS_RXOIS_RESET (0x0UL << SSI_RXOIS_POS) #define SSI_IS_RXFIS_SET (0x1UL << SSI_RXFIS_POS) #define SSI_IS_RXFIS_RESET (0x0UL << SSI_RXFIS_POS) /*------------------------------------------------------------------------------------ TypeDef -------------------------------------------------------------------------------------*/ typedef struct { uint16_t Mode; uint32_t Direction; uint32_t DataSize; uint32_t CLKPolarity; uint32_t CLKPhase; uint32_t NSS; uint32_t BaudRatePrescaler; uint32_t FirstBit; } SPI_InitCfg_t; /*------------------------------------------------------------------------------------ Global Variables -------------------------------------------------------------------------------------*/ typedef void (*timer_handler_callback)(void *context); /*------------------------------------------------------------------------------------ Exported Functions -------------------------------------------------------------------------------------*/ void xc_spi_init(uint8_t reg_idx, SPI_InitCfg_t *init_cfg); void xc_spi_rxftl_fifo_set(uint8_t reg_idx, uint8_t val); void xc_spi_txftl_fifo_set(uint8_t reg_idx, uint8_t val); void xc_spi_enable_it(uint8_t reg_idx, uint8_t val); void xc_spi_disable_it(uint8_t reg_idx, uint8_t val); void xc_spi_flash_power_down(uint8_t reg_idx); void xc_spi_flash_wake_up(uint8_t reg_idx); uint8_t xc_spi_flash_wait_busy(uint8_t reg_idx); eXC_RESULT xc_spi_flash_erase_sector(uint8_t reg_idx, uint32_t Dst_Addr); void xc_spi_flash_erase_page(uint8_t reg_idx, uint32_t Dst_Addr); void xc_spi_flash_write_page(uint8_t reg_idx, uint32_t WriteAddr, uint8_t *pBuffer); void xc_spi_flash_read_page(uint8_t reg_idx, uint32_t ReadAddr, uint8_t *pBuffer); eXC_RESULT xc_spi_flash_write(uint8_t reg_idx, uint32_t writeAddr, uint8_t *buff, uint16_t size); eXC_RESULT xc_spi_flash_read(uint8_t reg_idx, uint32_t readAddr, uint8_t *buff, uint16_t size); void xc_spi_flash_read_128bit_uid(uint8_t reg_idx, uint8_t *buff); eXC_RESULT xc_spi_flash_rdid(uint8_t reg_idx, uint8_t *buff); void xc_spi_write_and_read_data(uint8_t reg_idx, uint8_t *w_data, uint16_t w_size, uint8_t *r_data, uint16_t r_size); #endif // _XC_DRV_AOTIMER_H_