/*!
 * \file      main.c
 *
 * \brief     Target main implementation
 *
 * \copyright Revised BSD License, see section \ref LICENSE.
 *
 * \code
 *
 *            _  __ _       ________    _
 *           | |/ /(_)___  / ____/ /_  (_)___
 *           |   // / __ \/ /   / __ \/ / __ \
 *          /   |/ / / / / /___/ / / / / /_/ /
 *         /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
 *                                   /_/
 *           (C) 2022-2025 XinChip
 *
 * \endcode
 *
 * \author     ( XinChip ) Alex-J
 *
 * \author     ( XinChip )
 */

/*-----------------------------------------------------------------------------------
                                   INCLUDE HEADE FILES
 ------------------------------------------------------------------------------------*/
#include "main.h"
#include "xc6xxx_rf_single.h"

/*------------------------------------------------------------------------------------
                                         Macros
 -------------------------------------------------------------------------------------*/
#define RF_SINGLE_MAX   2483
#define RF_SINGLE_MIN   2402

/*------------------------------------------------------------------------------------
                                     Static Variables
 -------------------------------------------------------------------------------------*/





/*------------------------------------------------------------------------------------
                                     Func Prototype
 -------------------------------------------------------------------------------------*/

/*------------------------------------------------------------------------------------
                                        Functions
 -------------------------------------------------------------------------------------*/

/**
 ****************************************************************************************
 * @brief      Clock Initialization
 *
 * @param[in]
 * @param[in]
 ****************************************************************************************
 */

 void clock_init(void)
 {
     CLOCK_InitCfg_t clock_cfg;
 
     clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
     clock_cfg.hfclk_in  = CLOCK_HFCLK_IN_32M;
 #if (RC_32K)
     clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
 #endif //(RC_32K)
 
 #if (XTAL_32K)
     clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
 #endif // (XTAL_32K)
 
 #if (XTAL_32768K)
     clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
 #endif // (XTAL_32768K)
 #ifdef XC62XX
     clock_cb.lfclk_src  = CLOCK_LFCLK_SRC_RC;
     clock_cfg.lfclk_in  = CLOCK_LFCLK_IN_32K;
 #else
     if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
         clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
     } else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
         clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
     }
 #endif
     xc_clock_init_cfg(&clock_cfg);
 
     SysTick_Config(xc_clock_hfclk_in_get() / 100);
     SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
 }
#ifdef DEBUG_LOG
/**
 * @brief       RF 2.4g register information printing
 * @param       void
 * @retval      void
 */
void rf_2M_reg_info(void)
{
    /* Register information printing */
    LOGI("CFG_TOP:       0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
    LOGI("TXPROC_CFG:    0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
    LOGI("RXPROC_CFG_L:  0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
    LOGI("RF_CH:         0x%08x\r\n", XC_RF_2_4G->RF_CH);
    LOGI("rccal_reg_l:   0x%08x\r\n", XC_BT_RF->rccal_reg_l);
    LOGI("ana2_reg_l:    0x%08x\r\n", XC_BT_RF->ana2_reg_l);
    LOGI("ana3_reg_l:    0x%08x\r\n", XC_BT_RF->ana3_reg_l);
    LOGI("ana4_reg_l:    0x%08x\r\n", XC_BT_RF->ana4_reg_l);
    LOGI("ana5_reg_l:    0x%08x\r\n", XC_BT_RF->ana5_reg_l);
    LOGI("ana14_reg_l:   0x%08x\r\n", XC_BT_RF->ana14_reg_l);
    LOGI("ana15_reg_l:   0x%08x\r\n", XC_BT_RF->ana15_reg_l);
    LOGI("ana16_reg_l:   0x%08x\r\n", XC_BT_RF->ana16_reg_l);
    LOGI("ana17_reg_l:   0x%08x\r\n", XC_BT_RF->ana17_reg_l);
    LOGI("ana18_reg_l:   0x%08x\r\n", XC_BT_RF->ana18_reg_l);
    LOGI("ana21_reg_l:   0x%08x\r\n", XC_BT_RF->ana21_reg_l);
    LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
}

/**
 * @brief       Rf 2.4g dump log
 * @param       void
 *
 * @retval      void
 */
void rf_dump_log(void)
{
    LOGI("***************** 2.4G Param ******************\n");
    LOGI("CFG_TOP:       0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
    LOGI("EN_AA:         0x%08x\r\n", XC_RF_2_4G->EN_AA);
    LOGI("EN_RXADDR:     0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
    LOGI("SETUP_AW:	     0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
    LOGI("SETUP_RETR:    0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
    LOGI("RF_CH:         0x%08x\r\n", XC_RF_2_4G->RF_CH);
    LOGI("SETUP_RF:      0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
    LOGI("STATUS:        0x%08x\r\n", XC_RF_2_4G->STATUS);
    LOGI("OBSERVE_TX:    0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
    LOGI("RSSI:          0x%08x\r\n", XC_RF_2_4G->RSSI);
    LOGI("RX_ADDR_P0:    0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
    LOGI("RX_ADDR_P1:    0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
    LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
    LOGI("BER_RESULT:	 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
    LOGI("AGC_SETTING:   0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
    LOGI("PGA_SETTING:   0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
    LOGI("TX_ADDR:	     0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
    LOGI("RX_PW_PX:	     0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
    LOGI("STATUS_FIFO:   0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
    LOGI("RSSIREC:	     0x%08x\r\n", XC_RF_2_4G->RSSIREC);
    LOGI("TXPROC_CFG:    0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
    LOGI("RXPROC_CFG:    0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
    LOGI("DYNPD:  	     0x%08x\r\n", XC_RF_2_4G->DYNPD);
    LOGI("FEATURE:	     0x%08x\r\n", XC_RF_2_4G->FEATURE);
    LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
#ifdef XC62XX
    LOGI("HW_CONFIG:     0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
    LOGI("PBT_CONFIG:    0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
    LOGI("PBT_TIMER:     0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
    LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
    LOGI("PBT_TX_HEAD:   0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
    LOGI("PBT_RX_HEAD:   0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
    LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
#endif
    LOGI("TX_POWER       0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
    LOGI("ana11_reg_l:   0x%08x\r\n", XC_BT_RF->ana11_reg_l);
    LOGI("***********************************************\n");
    LOGI("\r\n");
}
#endif // DEBUG_LOG



void app_uart_init(void)
{
    GPIO_InitCfg_t gpio_cfg = {0};

    gpio_cfg.Mux            = GPIO_Mux0;
    gpio_cfg.Pull           = GPIO_PULLUP;
    gpio_cfg.Int            = NOT_INT;
    gpio_cfg.FunSel         = UART0_TX;

    gpio_cfg.Pin            = GPIO_18;
    gpio_cfg.Dir            = GPIO_DIR_OUTPUT;
    xc_gpio_init(&gpio_cfg);

    gpio_cfg.FunSel = UART0_RX;
    gpio_cfg.Pin    = GPIO_19;
    gpio_cfg.Dir    = GPIO_DIR_INPUT;
    xc_gpio_init(&gpio_cfg);

    UART_InitCfg_t uart_cfg      = {0};

    uart_cfg.Parity              = UART_PARITY_DISABLE;
    uart_cfg.StopBits            = UART_STOP_1_BITS;
    uart_cfg.WordLength          = UART_DATA_8_BITS;
    uart_cfg.BaudRate            = UART_BAUDRATE_115200;
    uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;

    xc_uart_init(UART0_IDX, &uart_cfg);
}


void rf_single_wave_static_demo()
{
	/* Set testing frequency points */
	rf_set_channel(XINCX_2_4G_CHANNEL_SINGLE);
	
	/* Set transmission power */
	set_rf_power(XINCX_POWER_SINGLE);
	
	rf_set_freq_dev(XINCX_2_4G_FREQ_DEV);

    LOGI("single channel:%d MHz\n", XC_RF_2_4G->RF_CH & 0x3fff);
	
    for (;;) {
        delay_ms(100);
    }
}

void rf_single_wave_sweep_demo()
{
	/* Set testing frequency points */
	rf_set_channel(XINCX_2_4G_CHANNEL_SINGLE);
	
	/* Set transmission power */
	set_rf_power(XINCX_POWER_SINGLE);
	
	rf_set_freq_dev(XINCX_2_4G_FREQ_DEV);
	
    uint16_t channel = RF_SINGLE_MIN;
	
    LOGI("channel sweep from:%d MHz to %d MHz\n", RF_SINGLE_MIN, RF_SINGLE_MAX - 1);
	
    for (;;) {
        delay_ms(100);
        rf_set_channel(channel);

//        channel += 1;
//        if (channel >= RF_SINGLE_MAX)
//            channel = RF_SINGLE_MIN;
    }
}

void main_loop(void)
{
	//rf_single_wave_static_demo();
	rf_single_wave_sweep_demo();
}

int main(void)
{
    /* Clock initialization */
    clock_init();

    /* Serial port initialization */
    app_uart_init();

    /* Single carrier initialization */
    rf_single_init();
	
	xc_system_param_check_rf24g();

	main_loop();

	while(true);
}