/*!
 * \file      main.c
 *
 * \brief     Target main implementation
 *
 * \copyright Revised BSD License, see section \ref LICENSE.
 *
 * \code
 *
 *            _  __ _       ________    _
 *           | |/ /(_)___  / ____/ /_  (_)___
 *           |   // / __ \/ /   / __ \/ / __ \
 *          /   |/ / / / / /___/ / / / / /_/ /
 *         /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
 *                                   /_/
 *           (C) 2022-2025 XinChip
 *
 * \endcode
 *
 * \author     ( XinChip ) Howl-C
 *
 * \author     ( XinChip )
 */

/*-----------------------------------------------------------------------------------
                                   INCLUDE HEADE FILES
 ------------------------------------------------------------------------------------*/
#include "main.h"

/*------------------------------------------------------------------------------------
                                         Macros
 -------------------------------------------------------------------------------------*/
 #define BLE_ADV_LEN		42

/*------------------------------------------------------------------------------------
                                     Static Variables
 -------------------------------------------------------------------------------------*/
static uint8_t	rx_buf[256]		= {0};
static uint16_t	rx_len			= 0;

static bool rf24g_rx_irq_flag = false;
static bool rf24g_tx_irq_flag = false;




/*------------------------------------------------------------------------------------
                                     Func Prototype
 -------------------------------------------------------------------------------------*/

/*------------------------------------------------------------------------------------
                                        Functions
 -------------------------------------------------------------------------------------*/

/**
 ****************************************************************************************
 * @brief      Clock Initialization
 *
 * @param[in]
 * @param[in]
 ****************************************************************************************
 */

 void clock_init(void)
 {
     CLOCK_InitCfg_t clock_cfg;
 
     clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
     clock_cfg.hfclk_in  = CLOCK_HFCLK_IN_32M;
 #if (RC_32K)
     clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
 #endif //(RC_32K)
 
 #if (XTAL_32K)
     clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
 #endif // (XTAL_32K)
 
 #if (XTAL_32768K)
     clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
 #endif // (XTAL_32768K)
 #ifdef XC62XX
     clock_cb.lfclk_src  = CLOCK_LFCLK_SRC_RC;
     clock_cfg.lfclk_in  = CLOCK_LFCLK_IN_32K;
 #else
     if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
         clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
     } else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
         clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
     }
 #endif
     xc_clock_init_cfg(&clock_cfg);
 
     SysTick_Config(xc_clock_hfclk_in_get() / 100);
     SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
 }
#ifdef DEBUG_LOG
/**
 * @brief       RF 2.4g register information printing
 * @param       void
 * @retval      void
 */
void rf_2M_reg_info(void)
{
    /* Register information printing */
    LOGI("CFG_TOP:       0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
    LOGI("TXPROC_CFG:    0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
    LOGI("RXPROC_CFG_L:  0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
    LOGI("RF_CH:         0x%08x\r\n", XC_RF_2_4G->RF_CH);
    LOGI("rccal_reg_l:   0x%08x\r\n", XC_BT_RF->rccal_reg_l);
    LOGI("ana2_reg_l:    0x%08x\r\n", XC_BT_RF->ana2_reg_l);
    LOGI("ana3_reg_l:    0x%08x\r\n", XC_BT_RF->ana3_reg_l);
    LOGI("ana4_reg_l:    0x%08x\r\n", XC_BT_RF->ana4_reg_l);
    LOGI("ana5_reg_l:    0x%08x\r\n", XC_BT_RF->ana5_reg_l);
    LOGI("ana14_reg_l:   0x%08x\r\n", XC_BT_RF->ana14_reg_l);
    LOGI("ana15_reg_l:   0x%08x\r\n", XC_BT_RF->ana15_reg_l);
    LOGI("ana16_reg_l:   0x%08x\r\n", XC_BT_RF->ana16_reg_l);
    LOGI("ana17_reg_l:   0x%08x\r\n", XC_BT_RF->ana17_reg_l);
    LOGI("ana18_reg_l:   0x%08x\r\n", XC_BT_RF->ana18_reg_l);
    LOGI("ana21_reg_l:   0x%08x\r\n", XC_BT_RF->ana21_reg_l);
    LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
}

/**
 * @brief       Rf 2.4g dump log
 * @param       void
 *
 * @retval      void
 */
void rf_dump_log(void)
{
    LOGI("***************** 2.4G Param ******************\n");
    LOGI("CFG_TOP:       0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
    LOGI("EN_AA:         0x%08x\r\n", XC_RF_2_4G->EN_AA);
    LOGI("EN_RXADDR:     0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
    LOGI("SETUP_AW:	     0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
    LOGI("SETUP_RETR:    0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
    LOGI("RF_CH:         0x%08x\r\n", XC_RF_2_4G->RF_CH);
    LOGI("SETUP_RF:      0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
    LOGI("STATUS:        0x%08x\r\n", XC_RF_2_4G->STATUS);
    LOGI("OBSERVE_TX:    0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
    LOGI("RSSI:          0x%08x\r\n", XC_RF_2_4G->RSSI);
    LOGI("RX_ADDR_P0:    0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
    LOGI("RX_ADDR_P1:    0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
    LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
    LOGI("BER_RESULT:	 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
    LOGI("AGC_SETTING:   0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
    LOGI("PGA_SETTING:   0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
    LOGI("TX_ADDR:	     0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
    LOGI("RX_PW_PX:	     0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
    LOGI("STATUS_FIFO:   0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
    LOGI("RSSIREC:	     0x%08x\r\n", XC_RF_2_4G->RSSIREC);
    LOGI("TXPROC_CFG:    0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
    LOGI("RXPROC_CFG:    0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
    LOGI("DYNPD:  	     0x%08x\r\n", XC_RF_2_4G->DYNPD);
    LOGI("FEATURE:	     0x%08x\r\n", XC_RF_2_4G->FEATURE);
    LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
#ifdef XC62XX
    LOGI("HW_CONFIG:     0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
    LOGI("PBT_CONFIG:    0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
    LOGI("PBT_TIMER:     0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
    LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
    LOGI("PBT_TX_HEAD:   0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
    LOGI("PBT_RX_HEAD:   0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
    LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
#endif
    LOGI("TX_POWER       0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
    LOGI("ana11_reg_l:   0x%08x\r\n", XC_BT_RF->ana11_reg_l);
    LOGI("***********************************************\n");
    LOGI("\r\n");
}
#endif // DEBUG_LOG



/**
 * @brief       RF 2.4g buff info
 * @param       uint8_t * - buff
 *              uint8_t len
 * @retval      void
 */
void rf_buff_info(uint8_t *buff, uint16_t len)
{
    for (uint16_t i = 0; i < len; i++)
        LOGI("%02x ", buff[i]);
    LOGI("\r\n");
}

void app_uart_init(void)
{
    GPIO_InitCfg_t gpio_cfg = {0};

    gpio_cfg.Mux            = GPIO_Mux0;
    gpio_cfg.Pull           = GPIO_PULLUP;
    gpio_cfg.Int            = NOT_INT;
    gpio_cfg.FunSel         = UART0_TX;

    gpio_cfg.Pin            = GPIO_18;
    gpio_cfg.Dir            = GPIO_DIR_OUTPUT;
    xc_gpio_init(&gpio_cfg);

    gpio_cfg.FunSel = UART0_RX;
    gpio_cfg.Pin    = GPIO_19;
    gpio_cfg.Dir    = GPIO_DIR_INPUT;
    xc_gpio_init(&gpio_cfg);

    UART_InitCfg_t uart_cfg      = {0};

    uart_cfg.Parity              = UART_PARITY_DISABLE;
    uart_cfg.StopBits            = UART_STOP_1_BITS;
    uart_cfg.WordLength          = UART_DATA_8_BITS;
    uart_cfg.BaudRate            = UART_BAUDRATE_115200;
    uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;

    xc_uart_init(UART0_IDX, &uart_cfg);
}

/* switch mode and set channel */
void rf_switch_mode(uint8_t mode, uint16_t channel)
{
    CE_CTL_LOW;

    switch (mode) {
        case TX_MODE:
        case RX_MODE:
            break;

        default:
            LOGI("The mode is set incorrectly\n");
            while(1);
    }
	
    set_rf_mode(mode);
    rf_set_channel(channel);
	
#ifdef XC62XX
    XC_RF_2_4G->STATUS = ((XC_RF_2_4G->CFG_TOP >> 30) & 0x3 << 7) | ((XC_RF_2_4G->CFG_TOP >> 4) & 0x7 << 4);
#else
    XC_RF_2_4G->STATUS = MASK_ALL_INTER;
#endif
	
	
    rf_wr_cmd(FLUSH_RX);
    rf_wr_cmd(FLUSH_TX);

    if (mode) {
        CE_CTL_HIGH;
    }
}

/* RF发送完成回调 */
void rf_24g_tx_ds_cb(void)
{
	/* set flag */
	rf24g_tx_irq_flag = true;
}


/* RF接收完成回调 */
void rf_24g_rx_dr_cb(void)
{
	/* stop RF */
	CE_CTL_LOW;
	
	/* set flag */
	rf24g_rx_irq_flag = true;
	
	/* recv data */
	rx_len = rf_rx_packet(rx_buf);
	
	/* start RF */
	CE_CTL_HIGH;
}


uint8_t rf24g_adv_packet_generate(uint8_t *buff)
{
    uint8_t l                  = 0;
    uint8_t rf_adv_data_complete_name[26]  = {"RF-ADV-TEST-123456789BLE52"};
	
	/* hearder */
    buff[l++]                  = 0x42;
    buff[l++]                  = 37;

    /* BLE MAC address */
	buff[l++]                     = MAC_ADDR_0;
	buff[l++]                     = MAC_ADDR_1;
	buff[l++]                     = MAC_ADDR_2;
	buff[l++]                     = MAC_ADDR_3;
	buff[l++]                     = MAC_ADDR_4;
	buff[l++]                     = MAC_ADDR_5;

	/* Flags */
    buff[l++]                     = 0x02;
    buff[l++]                     = 0x01;
    buff[l++]                     = 0x06;
	
	/* Complete Local Name */
    buff[l++]                     = 27;
    buff[l++]                     = 0x09;
    memcpy(&buff[l], rf_adv_data_complete_name, sizeof(rf_adv_data_complete_name));
    l         += sizeof(rf_adv_data_complete_name);

    /* CRC */
    buff[l++]  = 0x55;
    buff[l++]  = 0x55;
    buff[l++]  = 0x55;

    return l;
}

void rf24g_adv_tx_demo()
{
	uint32_t	tx_cnt      	= 0;
	uint16_t adv_len = 0;
    uint8_t adv_buff[BLE_ADV_LEN];
	uint16_t adv_channel = XINCX_2_4G_CHANNEL;
	
    /* Set the communication mode */
    rf_switch_mode( TX_MODE, adv_channel);
	
	/* genrate adv data */
    adv_len = rf24g_adv_packet_generate(adv_buff);
	
	/* CRC */
	ble_crc(adv_buff, adv_len - 3, adv_buff + adv_len - 3);

	/* whitening */
	ble_whiten(adv_buff, adv_len, bleWhitenStart(adv_channel));
    
    LOGI("************ADV Send Start**************\r\n");
	
	/* main loop */
    while(true)
    {
		/* Send data */
		rf_tx_packet(adv_buff, adv_len);
		
		tx_cnt += 1;
		LOGI("tx_cnt:%d\n", tx_cnt);
		
		delay_ms(10);
    }
}

void rf24g_adv_rx_demo()
{
	uint32_t	rx_cnt      	= 0;
	uint8_t adv_len = 0;
	uint16_t adv_channel = XINCX_2_4G_CHANNEL;
    uint32_t blecrc              = 0;
    uint8_t rf_adv_crc_stat      = CRC_IDLE;
	
	LOGI("************ADV Recv Start**************\r\n");
	
	/* Set the communication mode */
	rf_switch_mode( RX_MODE, adv_channel);
	
	/* main loop */
	while(true)
	{
		if (rf24g_rx_irq_flag) 
		{
			rf24g_rx_irq_flag = false;
			
			/* Whitening of packet software */
            blecrc            = rf_adv_unpacket( rx_buf, rx_len, &adv_len);

            /* Packet software CRC judgment */
            rf_adv_crc_stat   = rf_adv_crc( rx_buf, &adv_len, blecrc);
            if (rf_adv_crc_stat == CRC_OK) 
			{
				//rf_buff_info( rx_buf, rx_len);
				rx_cnt += 1;
				LOGI("rx_cnt:%d,len:%d\n", rx_cnt, adv_len);
                rf_adv_crc_stat = CRC_IDLE;
            }
		}
	}
}


int main(void)
{
    /* Clock initialization */
    clock_init();

    /* Serial port initialization */
    app_uart_init();

    /* Simulate broadcast initialization */
    rf24g_adv_init();

#if (XINCX_RF_NVIC_MODE)
    /* Enable RF2.4G interrupts */
    NVIC_EnableIRQ(RF24G_IRQn);
    /* Configure the RF2.4G interrupt priority */
    NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
	
	xc_system_param_check_rf24g();
	
#if XINCX_RF_MODE == TX_MODE
    rf24g_adv_tx_demo();
#elif XINCX_RF_MODE == RX_MODE
    rf24g_adv_rx_demo();
#endif

	while(true);
}