/* * @Descripttion: * @version: * @Author: sueRimn * @Date: 2024-05-09 11:45:27 * @LastEditors: sueRimn * @LastEditTime: 2024-07-24 15:18:52 */ #ifndef __APP_DATA_H__ #define __APP_DATA_H__ #include "rf_config.h" #include "xc6xxx_rf_2_4g.h" #include "xc_software_crc.h" #include #define BEKEN (0) #define PAN2416 (1) #ifdef TELINK_MODE #define COMPATILBE_MODE BEKEN #endif #ifdef BEKEN_MODE #define COMPATILBE_MODE BEKEN #endif #ifdef PANCHIP_MODE #define COMPATILBE_MODE PAN2416 #endif #define RF_CONFIRMED_VALUE (5U) /* 最大接收数据长度 */ #define BUFF_LEN_MAX (32U) #define RF_RECV_AMX_LEN (BUFF_LEN_MAX) #define RF_PRX_READ_RXFIFO_TIMER (RF_RECV_AMX_LEN) #define BIT7 0x80 #define BIT6 0x40 #define BIT5 0x20 #define BIT4 0x10 #define BIT3 0x08 #define BIT2 0x04 #define BIT1 0x02 #define BIT0 0x01 /* 动态包位移长度,单位bit */ #if (BEKEN == COMPATILBE_MODE) #define DATA_ANALYSIS_BIT_H (BIT7) #define DATA_ANALYSIS_BIT_L (BIT0) #define DATA_CONTROL_BIT (1U) #define DATA_CONTROL_NOACK (1U) // 1-ack 0-noack #elif (PAN2416 == COMPATILBE_MODE) #define DATA_ANALYSIS_BIT_H (BIT7 | BIT6) #define DATA_ANALYSIS_BIT_L (BIT0 | BIT1) #define DATA_CONTROL_BIT (2U) #define DATA_CONTROL_NOACK (0U) // 0-ack 1-noack #endif #define DATA_SPLICE_BIT (8U - DATA_CONTROL_BIT) /* 地址长度 */ #define RF_ADDR_LEN XINCX_RF_TX_ADDR_WIDTH // 5U /* 接收CRC+contorl字段长度 */ #define RF_RECV_EXTEN_LEN (3U) /* CRC初始值 */ #if (1 == XINCX_2_4G_CRC_BYTE) #define RF_CRC_INIT_VALUE (0xFF) // CRC8 0xFF CRC16 0xFFFF #elif (2 == XINCX_2_4G_CRC_BYTE) #define RF_CRC_INIT_VALUE (0xFFFF) // CRC8 0xFF CRC16 0xFFFF #endif /* 调制频偏 */ #if ((XINCX_RF_TRANS_RATE == DR_250K) && (PAN2416 == COMPATILBE_MODE)) #define RF_FREQ_DEV (0xb8) // 0x75 #define RF_FREQ_SEND_DEV (0x90) // 0xb8//0xa0 #define RF_FREQ_RECV_DEV (0x80) // 0x98//0xa0 #define ACK_DELAY (50) //(300) #elif ((XINCX_RF_TRANS_RATE == DR_1M) && (PAN2416 == COMPATILBE_MODE)) #define RF_FREQ_DEV (0xd0) // 0xb8//0xa0 #define RF_FREQ_SEND_DEV (0xe0) // 0xb8//0xa0 #define RF_FREQ_RECV_DEV (0x80) // 0x98//0xa0 #define ACK_DELAY (300) //(300) #elif ((XINCX_RF_TRANS_RATE == DR_1M) && (BEKEN == COMPATILBE_MODE)) #define RF_FREQ_DEV (0x80) // 0x75 #define RF_FREQ_SEND_DEV (0xd0) // 0xb8//0xa0 #define RF_FREQ_RECV_DEV (RF_FREQ_DEV) // 0x98//0xa0 #define ACK_DELAY (40) #elif ((XINCX_RF_TRANS_RATE == DR_250K) && (BEKEN == COMPATILBE_MODE)) #define RF_FREQ_DEV (0x80) // 0x75 #define RF_FREQ_SEND_DEV (0xd0) // 0xb8//0xa0 #define RF_FREQ_RECV_DEV (RF_FREQ_DEV) // 0x98//0xa0 #define ACK_DELAY (0) #endif /* 磐启白化初始值 */ #define PANCHIP_WHITEN_INIT_VAL (0x7F) /* ACK 长度 */ #define ACK_LEN (32U) // 32U /* */ #define USB_TEST (1U) /* 测试IO 使能 */ #define DEBUG_PIN (1U) #define TEST_PIN_NO_USB (1U) /* 测试IO */ #define TEST_PIN_1 GPIO_3 #define TEST_PIN_2 GPIO_6 #define TEST_PIN_3 GPIO_7 #define TEST_PIN_4 GPIO_8 #define TEST_PIN_5 GPIO_1 #define TEST_PIN_6 GPIO_4 #define TEST_PIN_7 GPIO_5 #define TEST_PIN_8 GPIO_0 /* ACK固定接收字节数 */ #define RF_RECV_TIMER \ (XINCX_2_4G_PREAMBLE_NUM + 1 + XINCX_RF_TX_ADDR_WIDTH + RF_PRX_READ_RXFIFO_TIMER + XINCX_2_4G_CRC_BYTE + 2 + 10) /* 速率-bit占用时间 */ #if (XINCX_RF_TRANS_RATE == DR_2M) #define BIT_TIMER (4U) #elif (XINCX_RF_TRANS_RATE == DR_1M) #define BIT_TIMER (8U) #elif (XINCX_RF_TRANS_RATE == DR_250K) #define BIT_TIMER (32U) #elif (XINCX_RF_TRANS_RATE == DR_125K) #define BIT_TIMER (64U) #endif extern uint8_t addr_buff[5]; extern uint8_t ack_buff[BUFF_LEN]; extern uint16_t rf_addr_crc; extern uint8_t panchip_addr_whiten; extern uint8_t panchip_contorl_whiten; extern uint8_t rf_send_ack_stat; void rf_enhanced_packet(uint8_t *buff, uint8_t buff_len); uint16_t rf_recv_dyn_crc(uint8_t *buff, uint8_t buff_len); uint16_t rf_enhanced_package_grouping(uint8_t *data_buff, uint8_t data_len); uint8_t read_addr_wid(uint8_t *addr_buff); void rf_addr_map(uint8_t *addr_buff); uint8_t rf_enhanced_recv_data(uint8_t *buff); #endif