/** **************************************************************************************** * * @file arch_main.c * * @brief Main loop of the application. * * Copyright (C) RivieraWaves 2009-2015 * * **************************************************************************************** */ /* * INCLUDES **************************************************************************************** */ #include "rwip_config.h" // RW SW configuration #include "arch.h" // architectural platform definitions #include "boot.h" // boot definition #include "rwip.h" // RW SW initialization #include "xc_drv_pwr.h" #include // boolean definition #include // standard definitions #include // standard integer definition #include // standard lib functions #if (BLE_TEST_MODE_SUPPORT) #include "uart.h" // UART initialization #endif // (BLE_TEST_MODE_SUPPORT) #if (BLE_EMB_PRESENT || BT_EMB_PRESENT) #include "rf.h" // RF initialization #endif // BLE_EMB_PRESENT || BT_EMB_PRESENT #if (BLE_APP_PRESENT) // #include "app.h" // application functions #endif // BLE_APP_PRESENT #if PLF_DMA #include "dma.h" // DMA initialization #endif // PLF_DMA #if (PLF_NVDS) #include "nvds.h" // NVDS definitions #endif // PLF_NVDS #include "reg_assert_mgr.h" #if (PLF_PROFILING || PLF_MEM_PROTECTION) #include "reg_sw_profiling.h" #endif // (PLF_PROFILING || PLF_MEM_PROTECTION) #include "platform.h" #include "xc6xxx.h" // CPU early wake-up time (unit:us) #define SLEEP_TIME_EARLY (3000) #define HS_TO_US(frame) (((frame) * SLOT_SIZE) >> 1) /** * @brief clock_init * @details * @param void * @retval void */ void clock_init(void) { CLOCK_InitCfg_t clock_cfg; clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL; clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M; #if (RC_32K) clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC; #endif //(RC_32K) #if (XTAL_32K) clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL; #endif // (XTAL_32K) #if (XTAL_32768K) clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL; #endif // (XTAL_32768K) if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) { clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768; } else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) { clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K; } xc_clock_init_cfg(&clock_cfg); SysTick_Config(xc_clock_hfclk_in_get() / 100); SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; } #if (SLEEP_ENABLE) void wakeup_timer_init(void) { TIMER_BaseInitTypeDef Timer_Init; Timer_Init.src_clk = TIMER_CLK_SRC_32K; Timer_Init.mode = TIMER_MODE_SINGLE_COUNT; Timer_Init.div_clk = TIMER_DIV_CLK_32000Hz; // Timer0 Config & Start TIMER_Base_Init(XC_TIMER0, &Timer_Init); PWR_InitTypeDef PWR_InitStruct = {0}; PWR_InitStruct.PWR_WakeITSrc = GPIO_IRQn_WAKE | TIMER0_IRQn_WAKE; PWR_InitStruct.PWR_SleepMode = LIGHT_SLEEP_MODE; PWR_SleepInit(&PWR_InitStruct); PWR_GPIO_SleepConfig(PWR_InitStruct.PWR_SleepMode); PWR_GPIO_LightSleepWakeConfig(GPIO_2, RIS_EDGE_INT); PWR_GPIO_LightSleepWakeConfig(GPIO_3, RIS_EDGE_INT); } void sleep_wkup() { PWR_InitTypeDef PWR_InitStruct = {0}; #if (USE_XIP != 1) SPI_InitCfg_t spi_cfg = {0}; spi_cfg.Mode = SPI_MODE_MASTER; spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT; spi_cfg.Direction = SSI_CTRL0_TMOD_WR; spi_cfg.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW; spi_cfg.CLKPhase = SPI_CPHA_LEAD; spi_cfg.FirstBit = SPI_FirstBit_MSB; xc_spi_init(XC_SPI0, &spi_cfg); SPI_Flash_PowerDown(XC_SPI0); #endif //(USE_XIP!=1) // PWR_InitStruct.PWR_WakeITSrc = GPIO_IRQn_WAKE | TIMER0_IRQn_WAKE ; // PWR_InitStruct.PWR_SleepMode = LIGHT_SLEEP_MODE; // PWR_SleepInit(&PWR_InitStruct); // PWR_GPIO_SleepConfig(PWR_InitStruct.PWR_SleepMode); sleep_init(); PWR_BLE_SleepEnter(); } void Turn_Off_PeripheralClk() { XC_CPR->SSI0_MCLK_CTL = (((0UL << CPR_SSI_MCLK_CTL_SSI_MCLK_DIV_Pos) | CPR_SSI_MCLK_CTL_SSI_MCLK_DIV_WE) | ((CPR_SSI_MCLK_CTL_SSI_MCLK_EN_DISABLE) | CPR_SSI_MCLK_CTL_SSI_MCLK_EN_WE)); XC_CPR->CTLAPBCLKEN_GRCTL = ((CPR_CTLAPBCLKEN_GRCTL_SSI0_PCLK_EN_DISABLE) | (CPR_CTLAPBCLKEN_GRCTL_SSI0_PCLK_EN_Msk << CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET)) << 0; XC_CPR->CTLAPBCLKEN_GRCTL = ((CPR_CTLAPBCLKEN_GRCTL_UART0_PCLK_EN_DISABLE) | (CPR_CTLAPBCLKEN_GRCTL_UART0_PCLK_EN_Msk << CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET)); XC_CPR->UART0_CLK_GRCTL = (((8UL << CPR_UART_CLK_GRCTL_UART0_CLK_GR_Pos) | CPR_UART_CLK_GRCTL_UART0_CLK_GR_WE) | ((CPR_UART_CLK_GRCTL_UART0_CLK_GR_UPD_DISABLE) | (CPR_UART_CLK_GRCTL_UART1_CLK_GR_UPD_WE))); XC_CPR->CTLAPBCLKEN_GRCTL = ((CPR_CTLAPBCLKEN_GRCTL_UART0_PCLK_EN_DISABLE) | (CPR_CTLAPBCLKEN_GRCTL_UART0_PCLK_EN_Msk << CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET)) << 1; // // XC_CPR->UART1_CLK_GRCTL = (((8UL << // CPR_UART_CLK_GRCTL_UART1_CLK_GR_Pos) | // CPR_UART_CLK_GRCTL_UART1_CLK_GR_WE) | // ((CPR_UART_CLK_GRCTL_UART1_CLK_GR_UPD_DISABLE) // | // (CPR_UART_CLK_GRCTL_UART1_CLK_GR_UPD_WE))); // XC_CPR->AHBCLKEN_GRCTL =0x1e001e; } void sleep_schedule() { // Checks for sleep have to be done with interrupt disabled GLOBAL_INT_DISABLE(); // Check if the processor clock can be gated uint32_t duration = 0; uint32_t duration_timer = 0; // switch(rwip_sleep(&duration, 2, \ // 0x7D00, RWIP_MINIMUM_SLEEP_TIME)){ switch (rwip_sleep(&duration, 1, 0x7D00, 20)) { case RWIP_DEEP_SLEEP: { duration_timer = (HS_TO_US(duration) - SLEEP_TIME_EARLY); TIMER_SetUs(XC_TIMER0, duration_timer); TIMER_Start_IT(XC_TIMER0); sleep_wkup(); __TIMER_Disable(XC_TIMER0); } // no break case RWIP_CPU_SLEEP: { // Wait for interrupt // Turn_Off_PeripheralClk(); // __PWR_SleepSrcMask_Set(0x1e000e); // __NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); // __WFI(); // __NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); // __PWR_SleepSrcMask_Set(0x1e001e); } break; case RWIP_ACTIVE: default: { // nothing to do. } break; } // Checks for sleep have to be done with interrupt disabled GLOBAL_INT_RESTORE(); } #endif // (SLEEP_ENABLE)