/*---------------------------------------------------------------------------------------------------- INCLUDE HEADE FILES ----------------------------------------------------------------------------------------------------*/ #include "Includes.h" #include "bsp_spi_master.h" #include "BootSecond.h" #include "bsp_2_4G.h" volatile uint8_t rf_intrrupt_flag = 0; volatile INFO_24G info_24g = { .DataStatus = STATUS_OK, .CheckStatus = STATUS_BUSY, .WriteAddr = FLASH_BIN_ADDR_OFFSET, .cPacketNo = 1, .cFrameNo = 1, .RevComplete = rFALSE, }; uint8_t __attribute__((aligned(4))) data_buffer[1200]; uint8_t __attribute__((aligned(4))) xc_buffer[32]; uint8_t __attribute__((aligned(4))) ack_pay_buf[32] = {0x01, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00}; // #define printf(...) (0) extern void makeCRC32table(unsigned int table[]); extern unsigned int crc32table[]; extern unsigned int get_crc32(unsigned int hash, unsigned char *data, unsigned int length); /** * Copyright (c) 2022 - 2025, XinChip * * All rights reserved. * * Author : * */ void dump_log(void) { printf("CFG_TOP: 0x%08x\r\n", *CFG_TOP); printf("EN_AA: 0x%08x\r\n", *EN_AA); printf("EN_RXADDR: 0x%08x\r\n", *EN_RXADDR); printf("SETUP_AW: 0x%08x\r\n", *SETUP_AW); printf("SETUP_RETR: 0x%08x\r\n", *SETUP_RETR); printf("RF_CH: 0x%08x\r\n", *RF_CH); printf("SETUP_RF: 0x%08x\r\n", *SETUP_RF); printf("STATUS: 0x%08x\r\n", *STATUS); printf("OBSERVE_TX: 0x%08x\r\n", *OBSERVE_TX); printf("RSSI: 0x%08x\r\n", *RSSI); printf("RX_ADDR_P0: 0x%02x%08x\r\n", 0xFF & (*RX_ADDR_P0_H), *RX_ADDR_P0_L); printf("RX_ADDR_P1: 0x%02x%08x\r\n", 0xFF & (*RX_ADDR_P1_H), *RX_ADDR_P1_L); printf("RX_ADDR_P2TOP5:0x%08x\r\n", *RX_ADDR_P2TOP5); printf("BER_RESULT: 0x%08x%08x\r\n", *BER_RESULT_H, *BER_RESULT_L); printf("AGC_SETTING: 0x%08x\r\n", *AGC_SETTING); printf("PGA_SETTING: 0x%02x%08x\r\n", ((*PGA_SETTING_H) & 0xFF00) >> 8, *PGA_SETTING_L); printf("TX_ADDR: 0x%02x%08x\r\n", ((*TX_ADDR_H) & 0xFF), *TX_ADDR_L); printf("RX_PW_PX: 0x%04x%08x\r\n", 0xFFFF & (*RX_PW_PX_H), *RX_PW_PX_L); printf("STATUS_FIFO: 0x%08x\r\n", *STATUS_FIFO); printf("RSSIREC: 0x%08x\r\n", *RSSIREC); printf("TXPROC_CFG: 0x%08x\r\n", *TXPROC_CFG); printf("RXPROC_CFG: 0x%02x%08x\r\n", 0xFF & (*RXPROC_CFG_H), *RXPROC_CFG_L); printf("DYNPD: 0x%08x\r\n", *DYNPD); printf("FEATURE: 0x%08x\r\n", *FEATURE); printf("PGA_SETTING_H: 0x%08x\r\n", *PGA_SETTING_H); printf("TX_ADDR_H: 0x%08x\r\n", *TX_ADDR_H); } /** * Copyright (c) 2022 - 2025, XinChip * * All rights reserved. * * Author : * */ void my_memcpy(uint8_t *des, uint8_t *src, uint16_t len) { for (int i = 0; i < len; i++) des[i] = src[i]; } void my_memset(uint8_t *s, uint8_t val, uint16_t len) { for (int i = 0; i < len; i++) s[i] = val; } /** * Copyright (c) 2022 - 2025, XinChip * * All rights reserved. * * Author : * */ __RAM_CODE void packet_24g(void) { static uint8_t xCount = 0; static uint16_t xPacketNo = 0; uint8_t packet_len = 0; // for (uint8_t idx=0; idx= 3) { xCount = 0; static uint8_t once_flag = 0; if (once_flag == 0) { once_flag = 1; info_24g.SoftVer = xc_buffer[5] + (xc_buffer[6] << 8); info_24g.RomVer = xc_buffer[7] + (xc_buffer[8] << 8); info_24g.Len = xc_buffer[9] + (xc_buffer[10] << 8) + (xc_buffer[11] << 16) + (xc_buffer[12] << 24); info_24g.CRC32 = xc_buffer[13] + (xc_buffer[14] << 8) + (xc_buffer[15] << 16) + (xc_buffer[16] << 24); info_24g.PacketNum = xc_buffer[17] + (xc_buffer[18] << 8); info_24g.AddrH = xc_buffer[24]; info_24g.AddrL = xc_buffer[20] + (xc_buffer[21] << 8) + (xc_buffer[22] << 16) + (xc_buffer[23] << 24); info_24g.Channel = 2400 + xc_buffer[19]; set_txaddr(info_24g.AddrL, info_24g.AddrH); set_pipe0_rxaddr(info_24g.AddrL, info_24g.AddrH); nop(); nop(); nop(); set_channel(info_24g.Channel); #ifdef DEBUG1 printf("[SoftVer:0x%08X]\n[RomVer:0x%08X]\n[Len:0x%08X]\n[CRC32:0x%08X]\n", info_24g.SoftVer, info_24g.RomVer, info_24g.Len, info_24g.CRC32); printf("[PacketNum:0x%08X]\n", info_24g.PacketNum); printf("[addr_H:0x%08X]\n[addr_L:0x%08X]\n[channel:%d]\n@@mathch ok@@\n", info_24g.AddrH, info_24g.AddrL, info_24g.Channel); #endif } } break; case 3: // bin info packet // printf("P %02x ",xc_buffer[5]); // info_24g.cPacketNo == (xc_buffer[5]+(xc_buffer[6]<<8)) xPacketNo = (xc_buffer[5] + (xc_buffer[6] << 8)); // packet No info_24g.FrameNum = xc_buffer[15] + (xc_buffer[16] << 8); info_24g.cFrameNo = 1; // printf("info_24g.FrameNum:%X\n",info_24g.FrameNum); break; case 5: // bin packet if (info_24g.cFrameNo == xc_buffer[0]) { my_memcpy(data_buffer + PACKET_LENGTH * (info_24g.cFrameNo - 1), xc_buffer + 3, PACKET_LENGTH); info_24g.cFrameNo++; } else { break; } if (xc_buffer[0] == info_24g.FrameNum) { if (info_24g.cPacketNo != xPacketNo) { info_24g.DataStatus = STATUS_FAIL; break; } #ifdef DEBUG2 for (int i = 0; i < 1024; i++) { printf("%02x ", data_buffer[i]); if ((i + 1) % 16 == 0) printf("\n"); } #endif #if 1 // exchange byte position for (int i = 0; i < 512; i++) { uint8_t t = data_buffer[2 * i]; data_buffer[2 * i] = data_buffer[2 * i + 1]; data_buffer[2 * i + 1] = t; } #endif // printf("F:%02x no:%x\n",info_24g.WriteAddr,info_24g.cPacketNo); info_24g.DataStatus = STATUS_BUSY; // spi_flash_write_sPages(info_24g.WriteAddr, data_buffer); my_memset(data_buffer, 0xff, PAGES_SIZE); if (info_24g.PacketNum == info_24g.cPacketNo) { info_24g.RevComplete = rTRUE; info_24g.DataStatus = STATUS_OK; #ifdef DEBUG1 printf("Receivev Complete Write Complete !\n"); #endif break; } info_24g.cPacketNo++; info_24g.WriteAddr = ((info_24g.cPacketNo - 1) * PAGES_SIZE) + FLASH_BIN_ADDR_OFFSET; // info_24g.WriteAddr+=PAGES_SIZE; info_24g.DataStatus = STATUS_OK; } // printf("F %02x ",xc_buffer[0]); break; case 6: // packet check result #ifdef DEBUG1 printf("request check result...\n"); #endif if (info_24g.RevComplete == rTRUE) { info_24g.RevComplete = rFALSE; uint32_t crc = 0; uint32_t PageCNT = (info_24g.Len) / FLASH_PAGE_SIZE; PageCNT = (((info_24g.Len) % FLASH_PAGE_SIZE) == 0) ? PageCNT : (PageCNT + 1); for (uint32_t i = 0; i < PageCNT; i++) { /*read a page*/ spi_flash_Read_Page(FLASH_BIN_ADDR_OFFSET + (i * FLASH_PAGE_SIZE), data_buffer); for (int j = 0; j < 128; j++) { uint8_t t = data_buffer[2 * j]; data_buffer[2 * j] = data_buffer[2 * j + 1]; data_buffer[2 * j + 1] = t; } crc = ((PageCNT - 1) == i) ? (get_crc32(crc, data_buffer, ((info_24g.Len) % FLASH_PAGE_SIZE))) : (get_crc32(crc, data_buffer, FLASH_PAGE_SIZE)); } #ifdef DEBUG1 printf("Check crc32:0x%08X\n", crc); #endif if (crc == info_24g.CRC32) { info_24g.CheckStatus = STATUS_OK; } else { info_24g.CheckStatus = STATUS_FAIL; } } else { info_24g.CheckStatus = STATUS_BUSY; } break; default: break; } #ifdef DEBUG2 for (int i = 0; i < 32; i++) { printf("%02x ", xc_buffer[i]); } printf("\r\n"); #endif } } /** * Copyright (c) 2022 - 2025, XinChip * * All rights reserved. * * Author : * */ __RAM_CODE void RF24G_Handler(void) { rf_intrrupt_flag |= (*STATUS & 0x70); __write_hw_reg32(STATUS, ALL_IRQ_STATUS); // clear all status inter // printf("RF24G_Handler stu=%x\n",rf_intrrupt_flag); } void erase_flash_chip(void) { spi_flash_write_enable(); // spi_flash_chip_erase(); while (spi_flash_wait_till_ready()) ; } static uint8_t __attribute__((aligned(4))) ParamBuff1[FLASH_PAGE_SIZE]; void rx_24g_ota(void) { sboot_message *ptrA = (sboot_message *)(&ParamBuff1[0]); spi_flash_Read_Page(2 * 4096, ParamBuff1); int num_1 = 0; init_24G(RX_MODE); set_channel(CHANNEL_24G); my_memset(data_buffer, 0xff, PAGES_SIZE); #ifdef DEBUG2 dump_log(); #endif CE_High; // ����RF���� while (1) { if (*STATUS & XC_RX_DR) { CE_Low; // ��ȡ����������ʱ��ֹRF���ա� packet_24g(); CE_High; } if (num_1 == 0x45500) { param_analy(&(ptrA->ParamUnit[0])); } num_1++; } } /** * Copyright (c) 2022 - 2025, XinChip * * All rights reserved. * * Author : * */