xushaoxiang
141 lines
4.2 KiB
C
141 lines
4.2 KiB
C
#include "Includes.h"
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// #define printf(...) (0)
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#ifdef XIP_JUMP
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#endif
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typedef void (*iapfun)(void); // 定义一个函数类型的参数.
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iapfun jump2app;
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__asm void MSR_MSP(uint32_t addr) // 设置栈顶地址 addr:栈顶地址
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{
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MSR MSP, r0 // set Main Stack value
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BX r14
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}
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void delay_wait(uint8_t cn)
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{
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for (int i = 0; i < cn; i++)
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for (int j = 0; j < 0x200; j++)
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;
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}
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void jump_app()
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{
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uint32_t pes=0x11001000;
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typedef void (*iapfun)(void); // 定义一个函数类型的参数static iapfun jump2app;
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jump2app = (iapfun) * (uint32_t *)(pes + 4);
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MSR_MSP(*(uint32_t *) (pes));
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jump2app ();
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while(1);
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}
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#define __write_hw_reg32(reg,val) ((*reg) = (val))
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#define __read_hw_reg32(reg, val) ((val) = (*reg))
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#define setbit(x,y) ((x) |= (1<<(y)))
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#define clrbit(x,y) ((x) &= ~(1<<(y)))
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#define CPR_BASE 0x40000000
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#define CPR_SPIx_MCLK_CTL(a) ((volatile unsigned *)(CPR_BASE + 0x050 + (a*0x04)))
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#define CPR_CTLAPBCLKEN_GRCTL ((volatile unsigned *)(CPR_BASE + 0x070))
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#define CPR_RSTCTL_SUBRST_SW ((volatile unsigned *)(CPR_BASE + 0x104))
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#define CPR_CTL_MUXCTL3 ((volatile unsigned *)(CPR_BASE + 0x19c))
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void close_ssi0(void)
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{
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__write_hw_reg32(CPR_SPIx_MCLK_CTL(0), 0x110000);//close ssi0 mclk
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__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000000)); //close ssi0 pclk
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__write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040000); //复位ssi0
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__write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040004); //复位ssi0
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}
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extern void gpio_mux_ctl_u(uint8_t num, uint8_t mux) //(num:32-34)
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{
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if (mux > 3)
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return;
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uint32_t tv = 0;
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__read_hw_reg32(CPR_CTL_MUXCTL3, tv);
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tv = (tv & (~(0x3 << ((num % 16) * 2)))) | (mux << ((num % 16) * 2));
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__write_hw_reg32(CPR_CTL_MUXCTL3, tv);
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}
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extern void init_xip(uint8_t mode)
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{
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#ifdef QUAD_ENABLE
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if (mode == QUAD_MODE)
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{
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if ((spi_flash_read_stat() & 0x02) == 0)
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{
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spi_flash_write_enable();
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spi_flash_quad_en();
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while (spi_flash_wait_till_ready())
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;
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}
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else
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{
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#ifdef DEBUG_PRINT
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printf("quad has been enabled !!!\n");
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#endif
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}
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}
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#endif
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close_ssi0(); // close ssi0
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// config fmc pin
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gpio_mux_ctl_u(33, 1); // d2
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gpio_mux_ctl_u(34, 1); // d3
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gpio_mux_ctl_u(35, 2); // clk
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gpio_mux_ctl_u(36, 2); // cs
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gpio_mux_ctl_u(37, 2); // d0 rx
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gpio_mux_ctl_u(38, 2); // d1 tx
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// open fmc clk
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__write_hw_reg32(FMC_CTL, 0x0503 | (0 << 11)); //
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delay_wait(1);
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__write_hw_reg32(FMC_CTL, 0x3503 | (0 << 11)); //
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delay_wait(1);
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// config cache
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__write_hw_reg32(CACHE_CCR, 0x00);
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delay_wait(6);
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__write_hw_reg32(CACHE_CCR, 0x21);
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delay_wait(6);
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// config fmc contrl
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__write_hw_reg32(FMC_EN, 0x00); // Disables DWC_ssi
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__write_hw_reg32(FMC_IE, 0x00);
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__write_hw_reg32(FMC_CTRL0, 0x1F); /* 32bit SPI data */
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__write_hw_reg32(FMC_SE, 0x01);
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__write_hw_reg32(FMC_RXFTL, 0x00);
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__write_hw_reg32(FMC_TXFTL, 0x00);
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__write_hw_reg32(FMC_XIP_SER, 0x01);
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__write_hw_reg32(FMC_XIP_CNT_TIME_OUT, 0xFF); // XIP time out
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__write_hw_reg32(FMC_BAUD, 0x2); // SSI Clock Divider= 2 --mclk/2
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if (mode == QUAD_MODE) // #ifdef QUAD_ENABLE //1 //quad
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{
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#ifdef DEBUG_PRINT
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uart_printf("xip quad cmd\n");
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#endif
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__write_hw_reg32(FMC_XIP_CTRL, (2) | (6 << 4) | (2 << 9) | (1 << 22) | (1 << 29) | (1 << 23) | (0 << 24) | (8 << 13));
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__write_hw_reg32(FMC_XIP_INCR_INST, 0x6b); // quad read cmd
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__write_hw_reg32(FMC_XIP_WRAP_INST, 0x6b); // quad read cmd
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}
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else // #else //dual
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{
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#ifdef DEBUG_PRINT
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// printf("xip dual cmd\n");
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#endif
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__write_hw_reg32(FMC_XIP_CTRL, (1) | (6 << 4) | (2 << 9) | (1 << 22) | (1 << 29) | (1 << 23) | (0) | (8 << 13));
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__write_hw_reg32(FMC_XIP_INCR_INST, 0x3b); // dual read cmd
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__write_hw_reg32(FMC_XIP_WRAP_INST, 0x3b); // dual read cmd
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} // #endif
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__write_hw_reg32(FMC_EN, 0x01); // Enables DWC_ssi
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__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x100000);
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__write_hw_reg32(CPR_RSTCTL_SUBRST_SW, 0x10000);
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}
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