xushaoxiang
238 lines
11 KiB
C
238 lines
11 KiB
C
/*!
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* \file xc6axx.h
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*
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* \brief The header of xc6axx chip
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __XC6AXX_H__
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#define __XC6AXX_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#define __RAM_CODE __attribute__((section("ram_code")))
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#define __WEAK __attribute__((weak))
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
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#endif
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#define __STATIC_INLINE static __inline
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#define QDEC_USE_P20_P21
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#define HFCLK_SRC_XTAL_IS_24M
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#define XC6AXX_TEST_CODE
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#define NEW_BLE_COMMON_BASE
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#define XC6AXX_ROM_DRIVER_ADDR
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#define NO_SUPPORT_ROM_FMC_SPI
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/* ------------------- Processor Exceptions Numbers ----------------------------- */
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NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /* 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
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BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
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SVCall_IRQn = -5, /* 11 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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/* ------------------- Processor Interrupt Numbers ------------------------------ */
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BLE_IRQn = 0, /*!< Device Interrupt */
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DMA_IRQn = 1,
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CPR_IRQn = 2,
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GPIO_IRQn = 3,
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RTC_IRQn = 4,
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TIMER0_IRQn = 5,
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TIMER1_IRQn = 6,
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TIMER2_IRQn = 7,
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TIMER3_IRQn = 8,
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WDT_IRQn = 9,
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I2C_IRQn = 10,
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UART0_IRQn = 11,
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UART1_IRQn = 12,
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SPI0_IRQn = 13,
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SPI1_IRQn = 14,
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KBS_IRQn = 15,
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QDEC_IRQn = 16,
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GADC_IRQn = 17,
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PWM_IRQn = 18,
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AES_IRQn = 19,
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USB_IRQn = 20,
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CDC_IRQn = 21,
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RF24G_IRQn = 22,
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SPI2_IRQn = 23,
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FPU_IRQn = 24,
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UART2_IRQn = 25,
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I2S_IRQn = 26,
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TIMER_AO0_IRQn = 27,
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TIMER_AO1_IRQn = 28,
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CMP_IRQn = 29,
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FMC_IRQn = 30,
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CAN_IRQn = 31,
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BT_IRQn = 32,
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BT_DM_IRQn = 33,
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BT_DBM_IRQn = 34,
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UNUSED_IRQn
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/* Interrupts 46 .. 63 are left out */
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M# Processor and Core Peripherals */
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/* ToDo: set the defines according your Device */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#if defined ( __CC_ARM )
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#if defined (__TARGET_FPU_VFP)
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#define __FPU_PRESENT 1 /*!< FPU present or not */
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#else
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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#endif
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#else
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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#endif
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/*@}*/ /* end of group <Device>_CMSIS */
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#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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#include "compiler.h"
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/* =========================================================================================================================== */
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/* ================ QDEC ================ */
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/* =========================================================================================================================== */
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/**
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* @brief Quadrature Decoder (QDEC)
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*/
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typedef struct { /*!< (@ 0x40016000UL) QDEC Structure */
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__IOM uint32_t QDEC_CTL; /*!< (@ 0x00000000) QDEC Control Register */
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__IOM uint32_t SAMP_CTL; /*!< (@ 0x00000004) QDEC Sample Control Register */
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__IM uint32_t SAMPLE; /*!< (@ 0x00000008) QDEC Sample State Register */
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__IM uint32_t ACC; /*!< (@ 0x0000000C) QDEC Acc Counter Now Register */
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__IM uint32_t ACC_R; /*!< (@ 0x00000010) QDEC Acc Counter Record Register */
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__IM uint32_t DB; /*!< (@ 0x00000014) QDEC Double Bounce Counter Now Register */
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__IM uint32_t DB_R; /*!< (@ 0x00000018) QDEC Double Bounce Counter Record Register */
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__IOM uint32_t INT; /*!< (@ 0x0000001C) QDEC Interrupt Register */
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__IOM uint32_t INT_MSK; /*!< (@ 0x00000020) QDEC Interrupt Mask Register */
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__IM uint32_t QDEC_STAT; /*!< (@ 0x00000024) QDEC Counter Busy State Register */
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} QDEC_TypeDef;
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/* =========================================================================================================================== */
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/* ================ 2.4G ================ */
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/* =========================================================================================================================== */
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/* RF 2.4G Module Register Typedef */
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typedef struct {
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__IOM uint32_t CFG_TOP; /*!< Top-level configuration (0x000) */
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__IOM uint32_t EN_AA; /*!< Auto-acknowledgement settings (0x004) */
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__IOM uint32_t EN_RXADDR; /*!< Enable RX addresses (0x008) */
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__IOM uint32_t SETUP_AW; /*!< Address width & timing stup (0x00C) */
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__IOM uint32_t SETUP_RETR; /*!< Automatic retransmission setup (0x010) */
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__IOM uint32_t RF_CH; /*!< RF channel (0x014) */
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__IOM uint32_t SETUP_RF; /*!< RF settings (0x018) */
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__IOM uint32_t STATUS; /*!< Status, SDO output may be adjusted (0x01C) */
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__IOM uint32_t OBSERVE_TX; /*!< Transmission observation (0x020) */
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__IOM uint32_t RSSI; /*!< TSSI and RSSI indicator/control (0x024) */
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__IOM uint32_t RX_ADDR_P0_L; /*!< RX address low 32bit for data pipe 0 (0x028) */
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__IOM uint32_t RX_ADDR_P0_H; /*!< RX address high 8bit for data pipe 0 (0x02C) */
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__IOM uint32_t RX_ADDR_P1_L; /*!< RX address low 32bit for data pipe 1 (0x030) */
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__IOM uint32_t RX_ADDR_P1_H; /*!< RX address high 8bit for data pipe 1 (0x034) */
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__IOM uint32_t RX_ADDR_P2TOP5; /*!< Only LSB are set, MSB use RX_ADDR_P1 (0x038) */
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__IOM uint32_t BER_RECV_CNT; /*!< Receive total Bit Counter for BER Test (0x03C) */
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__IOM uint32_t BER_ERR_CNT; /*!< Receive error Bit Counter for BER Test (0x040) */
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__IOM uint32_t AGC_SETTING; /*!< AGC setting (0x044) */
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__IOM uint32_t PGA_SETTING; /*!< PGA setting (0x048) */
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__IOM uint32_t TX_ADDR_L; /*!< TX address low 32bit (0x04C) */
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__IOM uint32_t TX_ADDR_H; /*!< TX address high 8bit (0x050) */
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__IOM uint32_t RX_PW_Px_L; /*!< Number of bytes in data pipe0~3 (0x054) */
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__IOM uint32_t RX_PW_Px_H; /*!< Number of bytes in data pipe4~5 (0x058) */
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__IOM uint32_t ANALOG_CFG0_L; /*!< Analog register 0 low 32bit (0x05C) */
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__IOM uint32_t ANALOG_CFG0_H; /*!< Analog register 0 high 32bit (0x060) */
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__IOM uint32_t ANALOG_CFG1_L; /*!< Analog register 1 low 32bit (0x064) */
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__IOM uint32_t ANALOG_CFG1_H; /*!< Analog register 1 high 32bit (0x068) */
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__IOM uint32_t ANALOG_CFG2_L; /*!< Analog register 2 low 32bit (0x06C) */
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__IOM uint32_t ANALOG_CFG2_H; /*!< Analog register 2 high 32bit (0x070) */
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__IOM uint32_t ANALOG_CFG3_L; /*!< Analog register 3 low 32bit (0x074) */
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__IOM uint32_t ANALOG_CFG3_H; /*!< Analog register 3 high 32bit (0x078) */
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__IM uint32_t Reserved1; /*!< Reserved1 (0x07C) */
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__IOM uint32_t STATUS_FIFO; /*!< FIFO status (0x080) */
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__IOM uint32_t RSSIREC; /*!< RSSI recorder feature (0x084) */
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__IOM uint32_t TXPROC_CFG; /*!< TX Process configuration (0x088) */
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__IOM uint32_t RXPROC_CFG_L; /*!< RX Process configuration (0x08C) */
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__IM uint32_t Reserved2; /*!< Reserved2 (0x090) */
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__IOM uint32_t DYNPD; /*!< Dynamic payload length (0x094) */
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__IOM uint32_t FEATURE; /*!< Features (0x098) */
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__IM uint32_t Reserved3[3]; /*!< Reserved3 (0x09C - 0x0A4) */
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__IOM uint32_t RXPROC_CFG_H; /*!< PA Ramp Configuration (0x0A8) */
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__IM uint32_t Reserved4[5]; /*!< Reserved4 (0x0AC - 0x0BC) */
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__IOM uint32_t CMD_CFG; /*!< Command Configuration (0x0C0) */
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__IOM uint32_t TX_FIFO_DATA; /*!< Tx Fifo Data (0x0C4) */
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__IOM uint32_t RX_FIFO_DATA; /*!< Rx Fifo Data (0x0C8) */
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__IOM uint32_t RX_FIFO_LEN; /*!< Tx Fifo Data Len (0x0CC) */
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} RF_2_4G_TypeDef;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __XC6AXX_H__ */
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