MARVEL/hpw421
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 1 Wiki Activity
Files
main
hpw421/component/xc6xx_drivers/Drivers/xc_driver/xc_drv_adc.h
T
xushaoxiang 2339bbfd1f hpw421初始版本
2026-06-06 16:49:48 +08:00

251 lines
8.3 KiB
C
Raw Permalink Blame History

/*!
* \file xc_drv_adc.h
*
* \brief The header of xc_drv_adc.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
#ifndef _XC_DRV_ADC_H_
#define _XC_DRV_ADC_H_
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdbool.h>
#include <stdio.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define ADC_FIFO_DOUT_LEN 0x10UL
#define ADC_TIMER 4
#define ADC_MAIN_CTL_AUTO_SW_ENABLE (0x01UL)
#define ADC_MAIN_CTL_AUTO_SW_DISABLE (0x00UL)
#define ADC_MAIN_CTL_ADC_EN_ENABLE (0x01UL)
#define ADC_MAIN_CTL_ADC_EN_DISABLE (0x00UL)
#define ADC_CHAN_CTL_CHAN_1_SET (0x01UL)
#define ADC_CHAN_CTL_CHAN_2_SET (0x02UL)
#define ADC_CHAN_CTL_CHAN_3_SET (0x04UL)
#define ADC_CHAN_CTL_CHAN_4_SET (0x08UL)
#define ADC_FIFO_CTL_FIFO_FLUSH_SET (0x01UL)
#define ADC_FIFO_CTL_FIFO_FLUSH_RESET (0x00UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_1 (0x01UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_2 (0x02UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_3 (0x03UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_4 (0x04UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_5 (0x05UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_6 (0x06UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_7 (0x07UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_8 (0x08UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_9 (0x09UL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_10 (0x0AUL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_11 (0x0BUL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_12 (0x0CUL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_13 (0x0DUL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_14 (0x0EUL)
#define ADC_FIFO_CTL_READ_REQ_THRESH_LEN_15 (0x0FUL)
#define ADC_INT_FIFO_ERROR_INT_SET (0x01UL<<0x01UL)
#define ADC_INT_READ_REQ_INT_SET (0x01UL<<0x00UL)
#define ADC_EXT_EDGE_SEL_INTER (0x00UL)
#define ADC_EXT_EDGE_SEL_EXTERN_RISE (0x01UL)
#define ADC_EXT_EDGE_SEL_EXTERN_FALL (0x02UL)
#define ADC_EXT_EDGE_SEL_EXTERN_BOTH (0x03UL)
#define ADC_EXT_TRIGGER_SEL_PWM0 (0x00UL)
#define ADC_EXT_TRIGGER_SEL_PWM1 (0x01UL)
#define ADC_EXT_TRIGGER_SEL_PWM2 (0x02UL)
#define ADC_EXT_TRIGGER_SEL_PWM3 (0x03UL)
#define ADC_EXT_TRIGGER_SEL_PWM4 (0x04UL)
#define ADC_EXT_TRIGGER_SEL_PWM5 (0x05UL)
#define ADC_EXT_TRIGGER_SEL_PWM_BRK1 (0x06UL)
#define ADC_EXT_TRIGGER_SEL_PWM_BRK2 (0x07UL)
#define ADC_EXT_DATA_MODE_32BIT (0x00UL)
#define ADC_EXT_DATA_MODE_LOW16BIT (0x01UL)
#define ADC_EXT_SAMPLE_NUM_1 (0x00UL)
#define ADC_EXT_SAMPLE_NUM_2 (0x01UL)
#define ADC_EXT_SAMPLE_NUM_3 (0x02UL)
#define ADC_EXT_SAMPLE_NUM_4 (0x03UL)
#define ADC_EXT_SAMPLE_NUM_5 (0x04UL)
#define ADC_EXT_SAMPLE_NUM_6 (0x05UL)
#define ADC_EXT_SAMPLE_NUM_7 (0x06UL)
#define ADC_EXT_SAMPLE_NUM_8 (0x07UL)
#define ADC_EXT_SAMPLE_NUM_9 (0x08UL)
#define ADC_EXT_SAMPLE_NUM_10 (0x09UL)
#define ADC_EXT_SAMPLE_NUM_11 (0x0AUL)
#define ADC_EXT_SAMPLE_NUM_12 (0x0BUL)
#define ADC_EXT_SAMPLE_NUM_13 (0x0CUL)
#define ADC_EXT_SAMPLE_NUM_14 (0x0DUL)
#define ADC_EXT_SAMPLE_NUM_15 (0x0EUL)
#define ADC_EXT_SAMPLE_NUM_16 (0x0FUL)
#define ADC_RF_CTL_PD_GADC_POWERDOWN (0x01UL)
#define ADC_RF_CTL_PD_GADC_WAKWUP (0x00UL)
#define ADC_RF_CTL_REFSEL_AVDD (0x01UL)
#define ADC_RF_CTL_REFSEL_2_4 (0x00UL)
#define ADC_RF_CTL_ADC_CTL_MUX_DIGITAL (0x01UL)
#define ADC_RF_CTL_ADC_CTL_MUX_SPI (0x00UL)
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
typedef struct
{
unsigned int value_2 : 12;
unsigned int chanel_2 : 4;
unsigned int value_1 : 12;
unsigned int chanel_1 : 4;
} ADC_FIFO_TypeDef_t;
typedef enum
{
ADC_CH0_PIN21 = 0,
ADC_CH1_PIN20 = 1,
ADC_CH2_PIN19 = 2,
ADC_CH3_PIN18 = 3,
ADC_CH4_PIN0 = 4,
ADC_CH5_PIN1 = 5,
ADC_CH6_PIN4 = 6,
ADC_CH7_PIN5 = 7,
ADC_CH8_NOPIN = 8, // cmp0
ADC_CH9_NOPIN = 9, // cmp1
ADC_CH10_NOPIN = 10, // cmp2
ADC_CH11_NOPIN = 11, // pga
ADC_CH12_PIN2 = 12,
ADC_CH13_PIN3 = 13,
ADC_CH14_PIN6 = 14,
ADC_CH15_PIN7 = 15,
} ADC_ChannelTypeDef_t;
typedef enum
{
ADC_REF_VOL_2_48V = 0,
ADC_REF_VOL_3_3V = 1,
} ADC_RefVolTypeDef_t;
typedef enum
{
ADC_FREQ_8M = 0x00,
ADC_FREQ_4M = 0x01,
ADC_FREQ_2M = 0x03,
ADC_FREQ_1M = 0x07,
ADC_FREQ_500K = 0x0f,
} ADC_FreqTypeDef_t;
typedef enum
{
// Single-ended mode. PSELN will be ignored, negative input to ADC shorted
// to GND.
ADC_SAMPMODE_SINGLE_ENDED = 0x00UL,
ADC_SAMPMODE_DIFFERENTIAL = 0x01UL // Differential mode.
} ADC_SampModeTypeDef_t;
typedef enum
{
ADC_SAMPEDGE_FALL = 0x00UL, ///< Single-ended mode. PSELN will be ignored,
///< negative input to ADC shorted to GND.
ADC_SAMPEDGE_RISE = 0x01UL ///< Differential mode.
} ADC_SampEdgeTypeDef_t;
typedef struct
{
ADC_RefVolTypeDef_t RefVol;
ADC_FreqTypeDef_t Freq;
ADC_SampEdgeTypeDef_t SampEdge;
uint32_t ExtSampleNum;
uint32_t ExtDataMode;
uint32_t ExtTriggerSel;
uint32_t ExtEdgeSel;
} ADC_InitCfg_t;
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Inline Functions
-------------------------------------------------------------------------------------*/
static __inline void xc_adc_fifo_flush(void)
{
adc_fifo_ctl__fifo_flush__setf(ADC_FIFO_CTL_FIFO_FLUSH_SET);
adc_fifo_ctl__fifo_flush__setf(ADC_FIFO_CTL_FIFO_FLUSH_RESET);
}
static __inline void xc_adc_refvol_set(uint8_t ref_vol)
{
adc_rf_ctl__pd_adc__setf(DISABLE);
if (ref_vol == ADC_REF_VOL_2_48V) {
adc_rf_ctl__gadc_vref_sel__setf(ADC_RF_CTL_REFSEL_2_4);
} else {
adc_rf_ctl__gadc_vref_sel__setf(ADC_RF_CTL_REFSEL_AVDD);
}
}
static __inline void xc_adc_freq_set(uint8_t freq)
{
adc_rf_ctl__adc_clkdiv__setf(freq);
adc_rf_ctl__adc_ctl_mux__setf(ADC_RF_CTL_ADC_CTL_MUX_DIGITAL);
}
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void xc_adc_init(ADC_InitCfg_t *adc_cfg);
void xc_adc_start_get_value(ADC_ChannelTypeDef_t Channel, uint16_t *adc_val);
void xc_adc_enable_it(uint8_t it);
void xc_adc_disable_it(uint8_t it);
void xc_adc_fifo_req_len_set(uint8_t len);
void xc_adc_wait_time_set(uint8_t timer0, uint16_t timer1);
void xc_adc_ch_auto_enable(void);
void xc_adc_ch_auto_disable(void);
void xc_adc_ch_auto_set(uint8_t ch);
void xc_adc_ch_not_auto_set(uint8_t ch);
void xc_adc_it_set(uint8_t it);
uint8_t xc_adc_it_get(void);
void xc_adc_ch_not_auto_set(uint8_t ch);
uint32_t xc_adc_data_get(void);
void xc_adc_enable(void);
void xc_adc_disable(void);
uint16_t xc_adc_it_collectval_get(void);
void xc_adc_channel_gpio_config(ADC_ChannelTypeDef_t Channel);
void adc_intr_callback(void);
#endif
Reference in New Issue View Git Blame Copy Permalink