xushaoxiang
227 lines
6.3 KiB
C
227 lines
6.3 KiB
C
/*!
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* \file xc_drv_pwr.h
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*
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* \brief The header of xc_drv_pwr.c
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __XC_DRV_PWR_H_
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#define __XC_DRV_PWR_H_
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "xc6xxx.h"
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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#define RST_READY_TIME 0x07
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#define OSC32_STABLE_TIME 80
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#define WAIT_BLE_EXIT_LOWpwr_TIME 20 // 15
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#define PRE_WAKEUP_TIME \
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(RST_READY_TIME + OSC32_STABLE_TIME + WAIT_BLE_EXIT_LOWpwr_TIME)
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#define DEEP_SLEEP_MODE 0
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#define LIGHT_SLEEP_MODE 1
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#define DEEP_SLEEP_GPIO_WAKE_HIGH_LEVEL 0
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#define DEEP_SLEEP_GPIO_WAKE_LOW_LEVEL 1
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#define BLE_IRQn_WAKE (1 << BLE_IRQn)
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#define GPIO_IRQn_WAKE (1 << GPIO_IRQn)
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#define RTC_IRQn_WAKE (1 << RTC_IRQn)
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#define TIMER0_IRQn_WAKE (1 << TIMER0_IRQn)
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#define TIMER1_IRQn_WAKE (1 << TIMER1_IRQn)
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#define TIMER2_IRQn_WAKE (1 << TIMER2_IRQn)
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#define TIMER3_IRQn_WAKE (1 << TIMER3_IRQn)
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#define TIMER_AO0_IRQn_WAKE (1 << TIMER_AO0_IRQn)
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#define TIMER_AO1_IRQn_WAKE (1 << TIMER_AO1_IRQn)
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#define pwr_GPIO_LightSleepConfig pwr_GPIO_SleepConfig
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#define pwr_GPIO_DeepSleepConfig pwr_GPIO_SleepConfig
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/*------------------------------------------------------------------------------------
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TypeDef
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-------------------------------------------------------------------------------------*/
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/* pwr Init structure definition */
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typedef struct
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{
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uint32_t pwr_wake_it_src;
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uint32_t pwr_sleep_mode;
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} PWR_InitCfg_t;
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/*------------------------------------------------------------------------------------
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Inline Functions
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-------------------------------------------------------------------------------------*/
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static __inline void xc_pwr_wake_it_set(uint32_t Val)
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{
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cprao_slpctl_int_mask_set(0xFFFFFFFF & (~Val));
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}
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static __inline void xc_pwr_usb_off(void) { cpr_rf_reg5_set(0x1C); }
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static __inline void xc_pwr_rc16m_off(void)
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{
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cpr_rf_reg0__rc_16m_disalbe__setf(ENABLE);
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}
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static __inline void xc_pwr_aotimer_src_set32k(void)
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{
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cprao_aon_reg1__timer_ao_sleep_clksw__setf(ENABLE);
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}
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static __inline void xc_pwr_aotimer_src_set32m(void)
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{
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cprao_aon_reg1__timer_ao_sleep_clksw__setf(DISABLE);
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}
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static __inline void xc_pwr_pd_lightsleep_set(void)
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{
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cprao_aon_slp_pd_mask_set(0x101);
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}
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static __inline void xc_pwr_pd_deepsleep_set(void)
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{
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cprao_aon_slp_pd_mask_set(0x0);
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}
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static __inline void xc_pwr_osc_off(void)
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{
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cprao_aon_slp_ctl_set(0x0);
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}
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static __inline void xc_pwr_modem_off(void)
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{
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cprao_aon_vdd_iso_en__vddmdm_en__setf(ENABLE);
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cprao_aon_vdd_switch_en__vddmdm_en__setf(DISABLE);
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}
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static __inline void xc_pwr_modem_on(void)
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{
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cprao_aon_vdd_iso_en__vddmdm_en__setf(DISABLE);
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cprao_aon_vdd_switch_en__vddmdm_en__setf(ENABLE);
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}
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__RAM_CODE static __inline void xc_pwr_rom_off(void)
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{
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cprao_aon_vdd_iso_en__vddrom_en__setf(ENABLE);
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cprao_aon_vdd_switch_en__vddrom_en__setf(DISABLE);
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}
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__RAM_CODE static __inline void xc_pwr_rom_on(void)
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{
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cprao_aon_vdd_iso_en__vddrom_en__setf(DISABLE);
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cprao_aon_vdd_switch_en__vddrom_en__setf(ENABLE);
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}
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static __inline void xc_pwr_rfdigital_off(void)
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{
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uint32_t val;
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val = cprao_aon_coreldo_en_get();
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val &= 0xFFFFFFFE;
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cprao_aon_coreldo_en_set(val);
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}
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static __inline void xc_pwr_rfdigital_on(void)
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{
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uint32_t val;
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val = cprao_aon_coreldo_en_get();
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val |= 1 << 0;
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cprao_aon_coreldo_en_set(val);
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}
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static __inline void xc_pwr_sleepsrc_mask_set(uint32_t val)
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{
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cpr_slp_src_mask_set(val);
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}
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static __inline void xc_pwr_opa_volr_off(void)
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{
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// OPA volr off
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uint32_t val;
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val = cpr_opa_ctrl_reg__volr__getf();
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val |= 1 << 2;
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cpr_opa_ctrl_reg__opa_ctrl__setf(val);
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}
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static __inline void xc_pwr_revddldo_off()
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{
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cprao_aon_reg4__bb_lpoldo_ibc__setf(4);
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}
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static __inline void xc_pwr_opa_tempsensor_off(void)
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{
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cpr_opa_ctrl_reg__en_temp_sensor__setf(DISABLE);
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}
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static __inline void xc_pwr_bor_on(void)
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{
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cprao_aon_bor_ctr_reg0__en_bor__setf(DISABLE);
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}
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static __inline void xc_pwr_bor_off(void)
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{
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cprao_aon_bor_ctr_reg0__en_bor__setf(DISABLE);
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}
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static __inline void xc_pwr_rc32k_calib_off() {}
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/*------------------------------------------------------------------------------------
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Exported Functions
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-------------------------------------------------------------------------------------*/
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void xc_pwr_sleep_init(PWR_InitCfg_t *pwr_cfg);
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void xc_pwr_ao_timer_pclk32m_Set(void);
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void xc_pwr_ao_timer_pclk32k_set(void);
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void xc_pwr_gpio_sleep_config(void);
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void pwr_cpu_sleep_init(void);
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__RAM_CODE void xc_pwr_cpu_sleep_enter(void);
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__RAM_CODE void xc_pwr_ble_sleep_enter(void);
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// void xc_sleep_init(void);
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// void xc_gpio_sleep_config(void);
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__RAM_CODE void xc_deep_sleep(void);
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__RAM_CODE void xc_sleep(void);
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void xc_pwr_gpio_lightsleep_wake_config(uint8_t pin, uint8_t edge_it);
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void xc_pwr_pwrkey_init(void);
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void xc_pwr_pwrkey_deepsleep_wake_config(uint8_t pin, uint8_t level);
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void pwr_gpio_sleep_wake_config(uint8_t sleep_mode, uint8_t pin, uint8_t it);
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void xc_pwr_dcdc_init(uint8_t vol_level);
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void xc_pwr_dcdc_close(void);
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void xc_pwr_dcdc_open(void);
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void xc_pwr_vol_set(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __XC6xxx_HAL_pwr_H_ */
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