xushaoxiang
200 lines
6.5 KiB
C
200 lines
6.5 KiB
C
/*!
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* \file xc6xxx_hal_uart.c
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*
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* \brief Target xc6xxx hal uart implementation
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "xc_drv_uart.h"
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Local Variables
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-------------------------------------------------------------------------------------*/
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uint8_t __attribute__((aligned(4))) uart_txdmabuff[UART_BUFF_LEN];
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uint8_t __attribute__((aligned(4))) uart_rxdmabuff[UART_BUFF_LEN];
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UART_Block_t uart_ctl_block;
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bool buffer_complet_flag = 0;
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/*------------------------------------------------------------------------------------
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Func Prototype
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Functions
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-------------------------------------------------------------------------------------*/
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void xc_uart_init(uint8_t reg_idx, UART_InitCfg_t *uart_cfg)
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{
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uint32_t val;
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uint32_t uart_clk = 0x00;
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uint32_t div, mul, clk_ctl, adj_div, m0_fclk_div;
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m0_fclk_div = cpr_m0_fclk_ctl__m0_fclk_div__getf();
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uart_clk = xc_clock_hfclk_in_get() * (m0_fclk_div + 1);
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mul = (uart_cfg->BaudRate >> 20) & 0xFFFF;
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div = (uart_cfg->BaudRate >> 4) & 0xFFFF;
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adj_div = uart_clk / 1000000;
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clk_ctl = (mul << 16) | (div * adj_div / 32);
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if (reg_idx == UART0_IDX) {
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cpr_rstctl_subrst_sw__uart0_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_subrst_sw__uart0_rstn__setf(RSTCTL_DISABLE);
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val = cpr_lp_ctl_get();
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val &= ~(UART0_CLK_OFF_PROTECT_EN_BIT);
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cpr_lp_ctl_set(val);
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cpr_ctlapbclken_grctl__uart0_pclk_en__setf(ENABLE);
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cpr_uart0_clk_grctl__uart0_clk_gr__setf(8);
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cpr_uart0_clk_grctl__uart0_clk_gr_upd__setf(ENABLE);
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cpr_uart0_clk_ctl_set(clk_ctl);
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}
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if (reg_idx == UART1_IDX) {
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cpr_rstctl_subrst_sw__uart1_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_subrst_sw__uart1_rstn__setf(RSTCTL_DISABLE);
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val = cpr_lp_ctl_get();
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val &= ~(UART1_CLK_OFF_PROTECT_EN_BIT);
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cpr_lp_ctl_set(val);
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cpr_ctlapbclken_grctl__uart1_pclk_en__setf(ENABLE);
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cpr_uart1_clk_grctl__uart1_clk_gr__setf(8);
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cpr_uart1_clk_grctl__uart1_clk_gr_upd__setf(ENABLE);
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cpr_uart1_clk_ctl_set(clk_ctl);
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}
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if (reg_idx == UART2_IDX) {
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cpr_rstctl_subrst_sw__uart2_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_subrst_sw__uart2_rstn__setf(RSTCTL_DISABLE);
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cpr_uart2_clk_grctl__uart2_pclk_en__setf(ENABLE);
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cpr_uart2_clk_grctl__uart2_clk_gr__setf(8);
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cpr_uart2_clk_grctl__uart2_clk_gr_upd__setf(ENABLE);
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cpr_uart2_clk_ctl_set(clk_ctl);
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}
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uart_tcr__dlab__setf(reg_idx, UART_TCR_DLAB_DLLH_ENABLE);
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uart_dll__dll__setf(reg_idx, (uart_cfg->BaudRate & 0xF));
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uart_ier_set(reg_idx, 0);
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uart_tcr__dlab__setf(reg_idx, UART_TCR_DLAB_DLLH_DISABLE);
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while (uart_usr_get(reg_idx) == 1) {
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};
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uart_tcr__eps__setf(reg_idx, uart_cfg->Parity);
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uart_tcr__stop__setf(reg_idx, uart_cfg->StopBits);
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uart_tcr__cls__setf(reg_idx, uart_cfg->WordLength);
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uart_mcr__afce__setf(reg_idx, uart_cfg->HardwareFlowControl);
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uart_fcr_pack(reg_idx, UART_FCR_RCVR_TRIGGER_FIFO_2_1, UART_FCR_TX_EMPTY_TRIGGER_FIFO_2_1,
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UART_FCR_XMIT_FIFO_RESET_CLEAR, UART_FCR_RCVR_FIFO_RESET_CLEAR, UART_FCR_FIFO_ENABLE_ENABLE);
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}
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void xc_uart_enable_rx_it(uint8_t reg_idx) { uart_ier__erdai__setf(reg_idx, UART_IER_ERDAI_ENABLE); }
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void xc_uart_disable_rx_it(uint8_t reg_idx) { uart_ier__erdai__setf(reg_idx, UART_IER_ERDAI_DISABLE); }
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void xc_uart_send_byte(uint8_t reg_idx, uint8_t byte)
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{
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while (1) {
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if (uart_tsr__thre__getf(reg_idx) & UART_TSR_THRE_VALID) {
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break;
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}
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}
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uart_thr__thr__setf(reg_idx, byte);
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}
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void xc_uart_send_data(uint8_t reg_idx, uint8_t *data, uint16_t len)
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{
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for (int i = 0; i < len; i++) {
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xc_uart_send_byte(reg_idx, data[i]);
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}
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}
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void xc_uart_ctl_block_reset(void)
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{
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memset(&uart_ctl_block, 0, sizeof(uart_ctl_block));
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uart_ctl_block.uart_receive_cb = NULL;
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}
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void xc_uart_register_receive_cb(uart_handler_callback uart_cb) { uart_ctl_block.uart_receive_cb = uart_cb; }
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__WEAK void uart_user_handler(uint8_t reg_idx)
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{
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uint8_t rx_val;
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uint32_t IIR, TSR;
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IIR = uart_iir__iid__getf(reg_idx);
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TSR = uart_tsr_get(reg_idx);
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if (((IIR & IID_MASK) == UART_IIR_IID_BUSY)) {
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uart_usr_get(reg_idx);
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}
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if (((IIR & IID_MASK) == UART_IIR_IID_ETSI)) {
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DEBUG("line=%d, error handle \n", __LINE__);
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}
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if (((IIR & IID_MASK) == UART_IIR_IID_ERDAI)) {
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TSR = uart_tsr_get(reg_idx);
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while ((TSR & UART_TSR_DR_VALID) == UART_TSR_DR_VALID) {
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rx_val = uart_rbr__rbr__getf(reg_idx);
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TSR = uart_tsr_get(reg_idx);
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if (uart_ctl_block.uart_receive_cb != NULL) {
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uart_ctl_block.uart_receive_cb(&rx_val, 1);
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}
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}
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}
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if ((IIR & IID_MASK) == UART_IIR_IID_TO) {
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TSR = uart_tsr_get(reg_idx);
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while ((TSR & UART_TSR_DR_VALID) == UART_TSR_DR_VALID) {
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rx_val = uart_rbr__rbr__getf(reg_idx);
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TSR = uart_tsr_get(reg_idx);
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if (uart_ctl_block.uart_receive_cb != NULL) {
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uart_ctl_block.uart_receive_cb(&rx_val, 1);
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}
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}
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}
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}
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void UART0_Handler(void) { uart_user_handler(UART0_IDX); }
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void UART1_Handler(void) { uart_user_handler(UART1_IDX); }
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void UART2_Handler(void) { uart_user_handler(UART2_IDX); }
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