xushaoxiang
313 lines
12 KiB
C
313 lines
12 KiB
C
/*!
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* \file xc_drv_i2c.h
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*
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* \brief The header of xc_drv_i2c.c
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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#ifndef _XC_DRV_I2C_H_
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#define _XC_DRV_I2C_H_
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include <stdbool.h>
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#include <stdio.h>
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#include "xc6xxx.h"
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#define I2C_FIFO_LEN 16
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/* I2C Init structure definition */
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typedef struct
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{
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uint32_t I2C_ClockSpeed;
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uint16_t I2C_Mode;
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uint16_t I2C_SlaveAddr;
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uint8_t DivClk;
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} I2C_InitCfg_t;
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enum
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{
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I2C_FREQUENCY_100K = 0,
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I2C_FREQUENCY_400K = 1,
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I2C_FREQUENCY_1M = 2,
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};
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typedef void (*i2c_write_callback)(void);
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typedef void (*i2c_read_callback)(uint8_t* buff, uint16_t len);
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typedef struct{
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i2c_read_callback i2c_read_cb;
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i2c_write_callback i2c_write_cb;
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} I2C_Block_t;
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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#define I2C_CON_MASTER_MODE_ENABLE (0x1UL)
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#define I2C_CON_MASTER_MODE_DISABLE (0x0UL)
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#define I2C_CON_SPEED_STANDARD_MODE (0x1UL)
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#define I2C_CON_SPEED_FAST_MODE (0x2UL)
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#define I2C_CON_10BITADDR_SLAVE_MODE (0x1UL)
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#define I2C_CON_7BITADDR_SLAVE_MODE (0x0UL)
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#define I2C_CON_10BITADDR_MASTER_MODE (0x1UL)
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#define I2C_CON_7BITADDR_MASTER_MODE (0x0UL)
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#define I2C_CON_RESTART_EN_ENABLE (0x1UL)
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#define I2C_CON_RESTART_EN_DISABLE (0x0UL)
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#define I2C_CON_SLAVE_DISABLE_ENABLE (0x0UL)
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#define I2C_CON_SLAVE_DISABLE_DISABLE (0x1UL)
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#define I2C_TAR_GC_OR_START_GC (0x0UL)
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#define I2C_TAR_GC_OR_START_Start (0x1UL)
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#define I2C_TAR_SPECIA_EXECUTE (0x1UL)
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#define I2C_TAR_SPECIA_IGNORE (0x0UL)
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#define I2C_TAR_I2C_10BITADDR_MODE (0x1UL)
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#define I2C_TAR_I2C_7BITADDR_MODE (0x0UL)
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#define I2C_DATA_CMD_CMD_READ (0x1UL << CMD_POS)
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#define I2C_DATA_CMD_CMD_WRITE (0x0UL << CMD_POS)
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#define I2C_DATA_CMD_STOP_SET (0x1UL << I2C_STOP_POS)
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#define I2C_DATA_CMD_STOP_RESET (0x0UL << I2C_STOP_POS)
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#define I2C_DATA_CMD_RESTART_SET (0x1UL << RESTART_POS)
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#define I2C_DATA_CMD_RESTART_RESET (0x0UL << RESTART_POS)
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#define I2C_DATA_CMD_DAT_SET (0x1UL << DAT_LSB)
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#define I2C_DATA_CMD_DAT_RESET (0x0UL << DAT_LSB)
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#define I2C_MLCK32M_FREQUENCY_HCNT_100K (0x8EUL)
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#define I2C_MLCK32M_FREQUENCY_LCNT_100K (0x9EUL)
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#define I2C_MLCK32M_FREQUENCY_HCNT_400K (0x18UL)
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#define I2C_MLCK32M_FREQUENCY_LCNT_400K (0x25UL)
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#define I2C_MLCK32M_FREQUENCY_HCNT_1M (0x07UL)
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#define I2C_MCLK32M_FREQUENCY_LCNT_1M (0x0AUL)
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#define I2C_MLCK48M_FREQUENCY_HCNT_100K (0xDBUL)
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#define I2C_MLCK48M_FREQUENCY_LCNT_100K (0xEBUL)
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#define I2C_MLCK48M_FREQUENCY_HCNT_400K (0x28UL)
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#define I2C_MLCK48M_FREQUENCY_LCNT_400K (0x38UL)
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#define I2C_MLCK48M_FREQUENCY_HCNT_1M (0x0DUL)
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#define I2C_MCLK48M_FREQUENCY_LCNT_1M (0x0FUL)
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#define I2C_MLCK64M_FREQUENCY_HCNT_100K (0x128UL)
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#define I2C_MLCK64M_FREQUENCY_LCNT_100K (0x138UL)
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#define I2C_MLCK64M_FREQUENCY_HCNT_400K (0x39UL)
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#define I2C_MLCK64M_FREQUENCY_LCNT_400K (0x49UL)
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#define I2C_MLCK64M_FREQUENCY_HCNT_1M (0x10UL)
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#define I2C_MCLK64M_FREQUENCY_LCNT_1M (0x14UL)
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#define I2C_INTR_STAT_RX_UNDER_RESET (0x0UL << R_RX_UNDER_POS)
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#define I2C_INTR_STAT_RX_UNDER_SET (0x1UL << R_RX_UNDER_POS)
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#define I2C_INTR_STAT_RX_OVER_RESET (0x0UL << R_RX_OVER_POS)
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#define I2C_INTR_STAT_RX_OVER_SET (0x1UL << R_RX_OVER_POS)
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#define I2C_INTR_STAT_RX_FULL_RESET (0x0UL << R_RX_FULL_POS)
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#define I2C_INTR_STAT_RX_FULL_SET (0x1UL << R_RX_FULL_POS)
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#define I2C_INTR_STAT_TX_OVER_RESET (0x0UL << R_TX_OVER_POS)
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#define I2C_INTR_STAT_TX_OVER_SET (0x1UL << R_TX_OVER_POS)
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#define I2C_INTR_STAT_TX_EMPTY_RESET (0x0UL << R_TX_EMPTY_POS)
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#define I2C_INTR_STAT_TX_EMPTY_SET (0x1UL << R_TX_EMPTY_POS)
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#define I2C_INTR_STAT_RD_REQ_RESET (0x0UL << R_RD_REQ_POS)
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#define I2C_INTR_STAT_RD_REQ_SET (0x1UL << R_RD_REQ_POS)
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#define I2C_INTR_STAT_TX_ABRT_RESET (0x0UL << R_TX_ABRT_POS)
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#define I2C_INTR_STAT_TX_ABRT_SET (0x1UL << R_TX_ABRT_POS)
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#define I2C_INTR_STAT_RX_DONE_RESET (0x0UL << R_RX_DONE_POS)
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#define I2C_INTR_STAT_RX_DONE_SET (0x1UL << R_RX_DONE_POS)
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#define I2C_INTR_STAT_ACTIVITY_RESET (0x0UL << R_ACTIVITY_POS)
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#define I2C_INTR_STAT_ACTIVITY_SET (0x1UL << R_ACTIVITY_POS)
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#define I2C_INTR_STAT_STOP_DET_RESET (0x0UL << R_STOP_DET_POS)
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#define I2C_INTR_STAT_STOP_DET_SET (0x1UL << R_STOP_DET_POS)
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#define I2C_INTR_STAT_START_DET_RESET (0x1UL << R_START_DET_POS)
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#define I2C_INTR_STAT_START_DET_SET (0x1UL << R_START_DET_POS)
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#define I2C_INTR_STAT_GEN_CALL_RESET (0x0UL << R_GEN_CALL_POS)
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#define I2C_INTR_STAT_GEN_CALL_SET (0x1UL << R_GEN_CALL_POS)
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#define I2C_INTR_EN_RX_UNDER_DISABLE (0x0UL << EN_RX_UNDER_POS)
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#define I2C_INTR_EN_RX_UNDER_ENABLE (0x1UL << EN_RX_UNDER_POS)
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#define I2C_INTR_EN_RX_OVER_DISABLE (0x0UL << EN_RX_OVER_POS)
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#define I2C_INTR_EN_RX_OVER_ENABLE (0x1UL << EN_RX_OVER_POS)
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#define I2C_INTR_EN_RX_FULL_DISABLE (0x0UL << EN_RX_FULL_POS)
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#define I2C_INTR_EN_RX_FULL_ENABLE (0x1UL << EN_RX_FULL_POS)
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#define I2C_INTR_EN_TX_OVER_DISABLE (0x0UL << EN_TX_OVER_POS)
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#define I2C_INTR_EN_TX_OVER_ENABLE (0x1UL << EN_TX_OVER_POS)
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#define I2C_INTR_EN_TX_EMPTY_DISABLE (0x0UL << EN_TX_EMPTY_POS)
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#define I2C_INTR_EN_TX_EMPTY_ENABLE (0x1UL << EN_TX_EMPTY_POS)
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#define I2C_INTR_EN_RD_REQ_DISABLE (0x0UL << EN_RD_REQ_POS)
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#define I2C_INTR_EN_RD_REQ_ENABLE (0x1UL << EN_RD_REQ_POS)
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#define I2C_INTR_EN_TX_ABRT_DISABLE (0x0UL << EN_TX_ABRT_POS)
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#define I2C_INTR_EN_TX_ABRT_ENABLE (0x1UL << EN_TX_ABRT_POS)
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#define I2C_INTR_EN_RX_DONE_DISABLE (0x0UL << EN_RX_DONE_POS)
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#define I2C_INTR_EN_RX_DONE_ENABLE (0x1UL << EN_RX_DONE_POS)
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#define I2C_INTR_EN_ACTIVITY_DISABLE (0x0UL << EN_ACTIVITY_POS)
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#define I2C_INTR_EN_ACTIVITY_ENABLE (0x1UL << EN_ACTIVITY_POS)
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#define I2C_INTR_EN_STOP_DET_DISABLE (0x0UL << EN_STOP_DET_POS)
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#define I2C_INTR_EN_STOP_DET_ENABLE (0x1UL << EN_STOP_DET_POS)
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#define I2C_INTR_EN_START_DET_DISABLE (0x0UL << EN_START_DET_POS)
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#define I2C_INTR_EN_START_DET_ENABLE (0x1UL << EN_START_DET_POS)
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#define I2C_INTR_EN_GEN_CALL_DISABLE (0x0UL << EN_GEN_CALL_POS)
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#define I2C_INTR_EN_GEN_CALL_ENABLE (0x1UL << EN_GEN_CALL_POS)
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#define I2C_RAW_INTR_STAT_RX_UNDER_RESET (0x0UL << RX_UNDER_POS)
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#define I2C_RAW_INTR_STAT_RX_UNDERL_SET (0x1UL << RX_UNDER_POS)
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#define I2C_RAW_INTR_STAT_RX_OVER_RESET (0x0UL << RX_OVER_POS)
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#define I2C_RAW_INTR_STAT_RX_OVER_SET (0x1UL << RX_OVER_POS)
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#define I2C_RAW_INTR_STAT_RX_FULL_RESET (0x0UL << RX_FULL_POS)
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#define I2C_RAW_INTR_STAT_RX_FULL_SET (0x1UL << RX_FULL_POS)
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#define I2C_RAW_INTR_STAT_TX_OVER_RESET (0x0UL << TX_OVER_POS)
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#define I2C_RAW_INTR_STAT_TX_OVER_SET (0x1UL << TX_OVER_POS)
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#define I2C_RAW_INTR_STAT_TX_EMPTY_RESET (0x0UL << TX_EMPTY_POS)
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#define I2C_RAW_INTR_STAT_TX_EMPTY_SET (0x1UL << TX_EMPTY_POS)
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#define I2C_RAW_INTR_STAT_RD_REQ_RESET (0x0UL << RD_REQ_POS)
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#define I2C_RAW_INTR_STAT_RD_REQ_SET (0x1UL << RD_REQ_POS)
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#define I2C_RAW_INTR_STAT_TX_ABRT_RESET (0x0UL << TX_ABRT_POS)
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#define I2C_RAW_INTR_STAT_TX_ABRT_SET (0x1UL << TX_ABRT_POS)
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#define I2C_RAW_INTR_STAT_RX_DONE_RESET (0x0UL << RX_DONE_POS)
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#define I2C_RAW_INTR_STAT_RX_DONE_SET (0x1UL << RX_DONE_POS)
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#define I2C_RAW_INTR_STAT_ACTIVITY_RESET (0x0UL << ACTIVITY_POS)
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#define I2C_RAW_INTR_STAT_ACTIVITY_SET (0x1UL << ACTIVITY_POS)
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#define I2C_RAW_INTR_STAT_STOP_DET_RESET (0x0UL << STOP_DET_POS)
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#define I2C_RAW_INTR_STAT_STOP_DET_SET (0x1UL << STOP_DET_POS)
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#define I2C_RAW_INTR_STAT_START_DET_RESET (0x0UL << START_DET_POS)
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#define I2C_RAW_INTR_STAT_START_DET_SET (0x1UL << START_DET_POS)
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#define I2C_RAW_INTR_STAT_GEN_CALL_RESET (0x0UL << GEN_CALL_POS)
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#define I2C_RAW_INTR_STAT_GEN_CALL_SET (0x1UL << GEN_CALL_POS)
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#define I2C_RX_TL_FIFO_1 (0x0UL)
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#define I2C_RX_TL_FIFO_2 (0x1UL)
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#define I2C_RX_TL_FIFO_3 (0x2UL)
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#define I2C_RX_TL_FIFO_4 (0x3UL)
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#define I2C_RX_TL_FIFO_5 (0x4UL)
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#define I2C_RX_TL_FIFO_6 (0x5UL)
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#define I2C_RX_TL_FIFO_7 (0x6UL)
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#define I2C_RX_TL_FIFO_8 (0x7UL)
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#define I2C_RX_TL_FIFO_9 (0x8UL)
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#define I2C_RX_TL_FIFO_10 (0x9UL)
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#define I2C_RX_TL_FIFO_11 (0xAUL)
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#define I2C_RX_TL_FIFO_12 (0xBUL)
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#define I2C_RX_TL_FIFO_13 (0xCUL)
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#define I2C_RX_TL_FIFO_14 (0xDUL)
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#define I2C_RX_TL_FIFO_15 (0xEUL)
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#define I2C_RX_TL_FIFO_16 (0xFUL)
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#define I2C_TX_TL_FIFO_0 (0x0UL)
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#define I2C_TX_TL_FIFO_1 (0x1UL)
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#define I2C_TX_TL_FIFO_2 (0x2UL)
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#define I2C_TX_TL_FIFO_3 (0x3UL)
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#define I2C_TX_TL_FIFO_4 (0x4UL)
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#define I2C_TX_TL_FIFO_5 (0x5UL)
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#define I2C_TX_TL_FIFO_6 (0x6UL)
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#define I2C_TX_TL_FIFO_7 (0x7UL)
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#define I2C_TX_TL_FIFO_8 (0x8UL)
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#define I2C_TX_TL_FIFO_9 (0x9UL)
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#define I2C_TX_TL_FIFO_10 (0xAUL)
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#define I2C_TX_TL_FIFO_11 (0xBUL)
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#define I2C_TX_TL_FIFO_12 (0xCUL)
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#define I2C_TX_TL_FIFO_13 (0xDUL)
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#define I2C_TX_TL_FIFO_14 (0xEUL)
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#define I2C_TX_TL_FIFO_15 (0xFUL)
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#define I2C_ENABLE_EN_DISABLE (0x0UL)
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#define I2C_ENABLE_EN_ENABLE (0x1UL)
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#define I2C_STATUS_ACTIVITY_RESET (0x0UL << I2C_ACTIVITY_POS)
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#define I2C_STATUS_ACTIVITY_SET (0x1UL << I2C_ACTIVITY_POS)
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#define I2C_STATUS_TFNF_RESET (0x0UL << TFNF_POS)
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#define I2C_STATUS_TFNF_SET (0x1UL << TFNF_POS)
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#define I2C_STATUS_TFE_RESET (0x0UL << TFE_POS)
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#define I2C_STATUS_TFE_SET (0x1UL << TFE_POS)
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#define I2C_STATUS_RFNE_RESET (0x0UL << RFNE_POS)
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#define I2C_STATUS_RFNE_SET (0x1UL << RFNE_POS)
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#define I2C_STATUS_RFF_RESET (0x0UL << RFF_POS)
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#define I2C_STATUS_RFF_SET (0x1UL << RFF_POS)
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#define I2C_STATUS_MST_ACTIVITY_RESET (0x0UL << 5)
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#define I2C_STATUS_MST_ACTIVITY_SET (0x1UL << 5)
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#define I2C_MODE_MASTER I2C_CON_MASTER_MODE_ENABLE
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#define I2C_MODE_SLAVE I2C_CON_SLAVE_DISABLE_ENABLE
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#define I2C_CLOCK_SPEED_100K I2C_FREQUENCY_100K
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#define I2C_CLOCK_SPEED_400K I2C_FREQUENCY_400K
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#define I2C_CLOCK_SPEED_1M I2C_FREQUENCY_1M
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void xc_i2c_init(I2C_InitCfg_t *i2c_cfg);
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void xc_i2c_enable_it(uint32_t val);
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void xc_i2c_fifo_rxtl_set(uint32_t val);
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void xc_i2c_fifo_txtl_set(uint32_t val);
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FlagStatus i2c_flag_status_get(uint32_t i2c_flag);
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void xc_i2c_register_read_cb(i2c_read_callback i2c_cb);
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void xc_i2c_register_write_cb(i2c_write_callback i2c_cb);
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uint32_t xc_i2c_write_block(uint8_t dev_addr, uint8_t *src, size_t len, uint16_t reset, uint16_t stop);
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uint32_t xc_i2c_read_block(uint8_t dev_addr, uint8_t *dst, size_t len, uint16_t reset, uint16_t stop);
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#endif
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