xushaoxiang
436 lines
14 KiB
C
436 lines
14 KiB
C
/*!
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* \file xc_drv_pwm.c
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*
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* \brief Target xc pwm driver implementation
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/*------------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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-------------------------------------------------------------------------------------*/
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#include "xc_drv_pwm.h"
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#include "xc_drv_gpio.h"
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Global Variables
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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TypeDef
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-------------------------------------------------------------------------------------*/
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typedef enum
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{
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STATE_UNINITIALIZED,
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STATE_INITIALIZED,
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} xincx_drv_state_t;
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pwm_handler_callback pwm_n_callback[3] = {
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pwm_capture_ch0_callback,
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pwm_capture_ch1_callback,
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pwm_capture_ch2_callback,
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};
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/*------------------------------------------------------------------------------------
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Local Variables
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-------------------------------------------------------------------------------------*/
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static uint32_t pwm_clk_init_state = STATE_UNINITIALIZED;
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static uint16_t pwm_freq_to_period(PWM_InitCfg_t *pwm_cfg, PWM_ClkDiv_TypeDef div_clk);
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double period;
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/*------------------------------------------------------------------------------------
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Func Prototype
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Functions
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-------------------------------------------------------------------------------------*/
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void xc_pwm_init(uint8_t reg_idx, PWM_InitCfg_t *init_cfg)
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{
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if (pwm_clk_init_state == STATE_UNINITIALIZED) {
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cpr_ctlapbclken_grctl__pwm_pclk_en__setf(ENABLE);
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cpr_rstctl_ctlapb_sw__pwm_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_ctlapb_sw__pwm_rstn__setf(RSTCTL_DISABLE);
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cpr_pwm_clk_ctl__pwm_clk_en__setf(ENABLE);
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cpr_pwm_clk_ctl__pwm_clksel__setf(init_cfg->SrcClk);
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cpr_pwm_clk_ctl__pwm_clk0_div__setf(init_cfg->DivClk);
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cpr_pwm_clk_ctl__pwm_clk1_div__setf(init_cfg->DivClk);
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pwm_clk_init_state = STATE_INITIALIZED;
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}
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pwm_pin_set(reg_idx, init_cfg);
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pwm_en__en__setf(reg_idx, DISABLE);
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pwm_en__en_sel__setf(reg_idx, init_cfg->SrcEnable);
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xc_pwm_dutycycle_set(reg_idx, init_cfg->DutyCycleAcc, init_cfg->DutyCycle);
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pwm_period__period__setf(reg_idx, pwm_freq_to_period(init_cfg, PWM_CLK_DIV0));
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pwm_compen__pwmcompen__setf(reg_idx, init_cfg->InvertEnable);
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pwm_comptime__comptime__setf(reg_idx, init_cfg->InvertDelay);
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}
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void xc_pwm_start(uint8_t reg_idx) { pwm_en__en__setf(reg_idx, PWM_EN_ENABLE); }
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void xc_pwm_stop(uint8_t reg_idx) { pwm_en__en__setf(reg_idx, PWM_EN_DISABLE); }
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void pwm_src_enable_set(uint8_t reg_idx, uint8_t src_enable) { pwm_en__en_sel__setf(reg_idx, src_enable); }
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void xc_pwm_start_all(void) { pwm_en__pwm_en_all__setf(PWM0_IDX, PWM_EN_ALL_ENABLE); }
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void xc_pwm_stop_all(void) { pwm_en__pwm_en_all__setf(PWM0_IDX, PWM_EN_ALL_DISABLE); }
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void pwm_pin_set(uint8_t reg_idx, PWM_InitCfg_t *pwm_cfg)
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{
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GPIO_InitCfg_t gpio_cfg;
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if(pwm_cfg->OutputPin==GPIO_11||pwm_cfg->OutputPin==GPIO_12||pwm_cfg->OutputPin==GPIO_13){
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gpio_cfg.Mux = GPIO_Mux1;
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}else
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{
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gpio_cfg.Mux = GPIO_Mux0;
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}
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gpio_cfg.Dir = GPIO_DIR_OUTPUT;
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gpio_cfg.Pull = GPIO_PULLDOWN;
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gpio_cfg.Int = NOT_INT;
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gpio_cfg.Pin = pwm_cfg->OutputPin;
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if (reg_idx == PWM0_IDX || reg_idx == PWM1_IDX) {
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gpio_cfg.FunSel = (reg_idx == PWM0_IDX) ? PWM0 : PWM1;
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xc_gpio_init(&gpio_cfg);
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if (pwm_cfg->InvertEnable) {
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gpio_cfg.FunSel = (reg_idx == PWM0_IDX) ? PWM0_INV : PWM1_INV;
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gpio_cfg.Pin = pwm_cfg->OutputInvertPin;
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xc_gpio_init(&gpio_cfg);
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}
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} else if (reg_idx == PWM2_IDX) {
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gpio_cfg.Mux = GPIO_Mux3;
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if (pwm_cfg->OutputPin == GPIO_12) {
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xc_gpio_init(&gpio_cfg);
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}
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} else if (reg_idx == PWM3_IDX) {
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gpio_cfg.Mux = GPIO_Mux3;
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if (pwm_cfg->OutputPin == GPIO_13) {
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xc_gpio_init(&gpio_cfg);
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}
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} else if (reg_idx == PWM4_IDX) {
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gpio_cfg.Mux = GPIO_Mux2;
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if (pwm_cfg->OutputPin == GPIO_0) {
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xc_gpio_init(&gpio_cfg);
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}
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} else if (reg_idx == PWM5_IDX) {
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gpio_cfg.Mux = GPIO_Mux2;
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if (pwm_cfg->OutputPin == GPIO_1) {
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xc_gpio_init(&gpio_cfg);
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}
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}
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}
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static uint16_t pwm_freq_to_period(PWM_InitCfg_t *pwm_cfg, PWM_ClkDiv_TypeDef div_clk)
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{
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uint32_t pwm_clk;
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switch (pwm_cfg->SrcClk) {
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case PWM_CLK_SRC_32M_DIV: {
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pwm_clk = xc_clock_hfclk_in_get() / PWM_CLK_DIV_CAL(div_clk);
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} break;
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case PWM_CLK_SRC_32K_DIV: {
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pwm_clk = xc_clock_lfclk_in_get() / PWM_CLK_DIV_CAL(div_clk);
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} break;
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case PWM_CLK_SRC_32K: {
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pwm_clk = CLOCK_LFCLK_IN_32K;
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} break;
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default:
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break;
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}
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uint32_t freq_max = PWM_FREQ_MAX_CAL(pwm_clk, pwm_cfg->DutyCycleAcc);
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uint32_t freq = PWM_FREQ_CAL(pwm_clk, pwm_cfg->DutyCycleAcc, pwm_cfg->Period);
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if (freq > freq_max) {
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DEBUG("%s,line=%d,set freq=%d,The maximum configurable frequency %d hz "
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"has been exceeded.\n",
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__func__, __LINE__, freq, freq_max);
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} else {
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DEBUG("%s,line=%d,set freq=%d,maximum configurable frequency %d hz\n", __func__, __LINE__, freq, freq_max);
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}
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return pwm_cfg->Period;
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}
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void xc_pwm_dutycycle_set(uint8_t reg_idx, uint32_t dutycycle_acc, uint32_t dutycycle)
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{
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pwm_en__mode__setf(reg_idx, PWM_EN_MODE_EDGE_ALIGNED);
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pwm_ocpy__ocpy_ratio_config__setf(reg_idx, (dutycycle_acc - 1));
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pwm_ocpy__ocpy_ratio__setf(reg_idx, dutycycle_acc - dutycycle);
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pwm_up__update__setf(reg_idx, PWM_UP_UPDATE_ENABLE);
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}
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void xc_pwm_lowpower_enable(uint8_t reg_idx) { pwm_en__sleep_en__setf(reg_idx, PWM_EN_SLEEP_EN_ENABLE); }
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void xc_pwm_lowpower_disable(uint8_t reg_idx) { pwm_en__sleep_en__setf(reg_idx, PWM_EN_SLEEP_EN_DISABLE); }
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void xc_pwm_lowpower_countdirection_set(uint8_t reg_idx, uint32_t direction)
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{
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pwm_en__sleep_incr__setf(reg_idx, direction);
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}
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void xc_pwm_brake_enable(uint8_t reg_idx)
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{
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uint32_t val;
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val = pwm_break_ctl__pwm_brk_enable__getf(PWM0_IDX);
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if (reg_idx == PWM0_IDX || reg_idx == PWM1_IDX) {
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val &= ~(PWM_BRK0_ENABLE_ENABLE);
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val |= (PWM_BRK0_ENABLE_ENABLE);
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} else if (reg_idx == PWM2_IDX || reg_idx == PWM3_IDX) {
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val &= ~(PWM_BRK1_ENABLE_ENABLE);
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val |= (PWM_BRK1_ENABLE_ENABLE);
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} else if (reg_idx == PWM4_IDX || reg_idx == PWM5_IDX) {
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val &= ~(PWM_BRK2_ENABLE_ENABLE);
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val |= (PWM_BRK2_ENABLE_ENABLE);
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}
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pwm_break_ctl__pwm_brk_enable__setf(PWM0_IDX, val);
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}
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void xc_pwm_brake_disable(uint8_t reg_idx)
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{
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uint32_t val;
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val = pwm_break_ctl__pwm_brk_enable__getf(PWM0_IDX);
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if (reg_idx == PWM0_IDX || reg_idx == PWM1_IDX) {
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val &= ~(PWM_BRK0_ENABLE_ENABLE);
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} else if (reg_idx == PWM2_IDX || reg_idx == PWM3_IDX) {
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val &= ~(PWM_BRK1_ENABLE_ENABLE);
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} else if (reg_idx == PWM4_IDX || reg_idx == PWM5_IDX) {
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val &= ~(PWM_BRK2_ENABLE_ENABLE);
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}
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pwm_break_ctl__pwm_brk_enable__setf(PWM0_IDX, val);
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}
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uint8_t xc_pwm_brake_signal_valid_get(void) { return pwm_break_ctl__pwm_brk_sync__getf(PWM0_IDX); }
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void xc_pwm_brake_signal_mask_set(uint32_t mask) { pwm_break_ctl__pwm_brk_mask__setf(PWM0_IDX, mask); }
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void xc_pwm_brake_signal_trigger_level_set(uint32_t level) { pwm_break_ctl__pwm_brk_inv__setf(PWM0_IDX, level); }
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void xc_pwm_brake_recovery_mode_set(uint32_t mode) { pwm_break_ctl__brk_mode__setf(PWM0_IDX, mode); }
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uint8_t xc_pwm_brake_recovery_mode_get(void) { return (pwm_break_ctl__brk_mode__getf(PWM0_IDX)); }
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void xc_pwm_brake_debounce_set(uint32_t debounce, uint32_t step)
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{
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pwm_break_ctl__brk_dbc_en__setf(PWM0_IDX, debounce);
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pwm_break_ctl__brk_dbc_step__setf(PWM0_IDX, step);
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}
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void xc_pwm_brake_clear() { pwm_break_ctl__clear__setf(PWM0_IDX, PWM_BRK_BRK_CLEAR_EXIT); }
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void xc_pwm_capture_enable(uint8_t ch) { cap_tim_ctl__capture_enable__setf(ch, PWM_CAPTURE_ENABLE); }
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void xc_pwm_capture_disable(uint8_t ch) { cap_tim_ctl__capture_enable__setf(ch, PWM_CAPTURE_DISABLE); }
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void xc_pwm_capture_enable_it(uint8_t ch)
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{
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if (ch == 0) {
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pwm_cap_tim_int_en__capture_upd_0_en__setf(ENABLE);
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} else if (ch == 1) {
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pwm_cap_tim_int_en__capture_upd_1_en__setf(ENABLE);
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} else if (ch == 2) {
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pwm_cap_tim_int_en__capture_upd_2_en__setf(ENABLE);
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}
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}
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void xc_pwm_capture_disable_it(uint8_t ch)
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{
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if (ch == PWM_IC_CH0) {
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pwm_cap_tim_int_en__capture_upd_0_en__setf(DISABLE);
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} else if (ch == PWM_IC_CH1) {
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pwm_cap_tim_int_en__capture_upd_1_en__setf(DISABLE);
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} else if (ch == PWM_IC_CH2) {
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pwm_cap_tim_int_en__capture_upd_2_en__setf(DISABLE);
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}
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}
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void xc_pwm_capture_signal_set(uint8_t ch, uint32_t signal) { cap_tim_ctl__capture_sig_sel__setf(ch, signal); }
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void xc_pwm_capture_debounce_enable(uint8_t ch, uint32_t step)
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{
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cap_tim_ctl__dbc_en__setf(ch, PWM_CAPTURE_DBC_ENABLE);
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cap_tim_ctl__dbc_step__setf(ch, step);
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}
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void xc_pwm_capture_debounce_disable(uint8_t ch, uint32_t step)
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{
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cap_tim_ctl__dbc_en__setf(ch, PWM_CAPTURE_DBC_DISABLE);
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cap_tim_ctl__dbc_step__setf(ch, step);
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}
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void xc_pwm_capture_edge_set(uint8_t ch, uint32_t edge) { cap_tim_ctl__capture_mode__setf(ch, edge); }
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void xc_pwm_capture_psc_set(uint8_t ch, uint32_t psc) { cap_tim_ctl__capture_psc__setf(ch, psc); }
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void xc_pwm_capture_counter_enable(uint8_t ch)
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{
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cap_tim_ctl__common_cnt_enable__setf(ch, PWM_CAPTURE_COMMON_CNT_ENABLE);
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}
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void xc_pwm_capture_counter_disable(uint8_t ch)
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{
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cap_tim_ctl__common_cnt_enable__setf(ch, PWM_CAPTURE_COMMON_CNT_DISABLE);
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}
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uint16_t xc_pwm_capture_val_get(uint8_t ch) { return cap_tim_val__capture_value__getf(ch); }
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/*
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*-----------------------------------------------------------------------------------------------
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* PWM Timer
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*-----------------------------------------------------------------------------------------------
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*/
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/**
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****************************************************************************************
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* @brief
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void xc_pwm_timer_init(uint8_t reg_idx, PWM_Timer_InitCfg_t *init_cfg)
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{
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if (reg_idx > PWM_TIMER5_IDX)
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return;
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if (pwm_clk_init_state == STATE_UNINITIALIZED) {
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cpr_ctlapbclken_grctl__pwm_pclk_en__setf(ENABLE);
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cpr_rstctl_ctlapb_sw__pwm_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_ctlapb_sw__pwm_rstn__setf(RSTCTL_DISABLE);
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cpr_pwm_clk_ctl__pwm_clk_en__setf(ENABLE);
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cpr_pwm_clk_ctl__pwm_clksel__setf(init_cfg->src_clk);
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cpr_pwm_clk_ctl__pwm_clk0_div__setf(init_cfg->clk_div);
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cpr_pwm_clk_ctl__pwm_clk1_div__setf(init_cfg->clk_div);
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pwm_clk_init_state = STATE_INITIALIZED;
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}
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uint32_t ctl_reg = (init_cfg->timer_mode << TIMER_MODE_POS) | (init_cfg->timer_int_mask_en << TIMER_INT_MASK_POS) |
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(init_cfg->timer_pwm_en << TIMER_PWM_POS) |
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(init_cfg->timer_0to100_pwm_en << TIMER_ON10OPWM_EN_POS);
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pwm_timer_controlreg_set(reg_idx, ctl_reg);
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}
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void xc_pwm_timer_deinit(uint8_t reg_idx)
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{
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pwm_clk_init_state = STATE_UNINITIALIZED;
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cpr_ctlapbclken_grctl__pwm_pclk_en__setf(DISABLE);
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}
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/**
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****************************************************************************************
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* @brief
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void xc_pwm_timer_set_freq(uint8_t reg_idx, uint32_t freq) { period = xc_clock_hfclk_in_get() / 2 / freq; }
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void xc_pwm_timer_set_dutycycle(uint8_t reg_idx, double dutycycle)
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{
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uint16_t high_cnt = ((uint32_t)(period * dutycycle) / 100);
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uint16_t low_cnt = (uint32_t)(period - high_cnt);
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pwm_timer_loadcount__timer_lc__setf(reg_idx, low_cnt);
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pwm_timer_loadcount2__timer_lc2__setf(reg_idx, high_cnt);
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}
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void xc_pwm_timer_set_high_cnt(uint8_t reg_idx, uint16_t high_cnt)
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{
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pwm_timer_loadcount2__timer_lc2__setf(reg_idx, high_cnt);
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}
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void xc_pwm_timer_set_low_cnt(uint8_t reg_idx, uint16_t low_cnt)
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{
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pwm_timer_loadcount__timer_lc__setf(reg_idx, low_cnt);
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}
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/**
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****************************************************************************************
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* @brief
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void xc_pwm_timer_start(uint8_t reg_idx) { pwm_timer_controlreg__timer_en__setf(reg_idx, ENABLE); }
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void xc_pwm_timer_stop(uint8_t reg_idx) { pwm_timer_controlreg__timer_en__setf(reg_idx, DISABLE); }
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/*-----------------------------------------------------------------------------------------------*/
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void PWM_Handler(void)
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{
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uint32_t cap_tim_int;
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cap_tim_int = pwm_cap_tim_int_get();
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pwm_cap_tim_int_set(cap_tim_int); // clear inter
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if ((cap_tim_int & PWM_CAPTURE_UPD0_EN_ENABLE) == PWM_CAPTURE_UPD0_EN_ENABLE) {
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pwm_capture_ch0_callback(NULL);
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}
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if ((cap_tim_int & PWM_CAPTURE_UPD1_EN_ENABLE) == PWM_CAPTURE_UPD1_EN_ENABLE) {
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pwm_capture_ch1_callback(NULL);
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}
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if ((cap_tim_int & PWM_CAPTURE_UPD2_EN_ENABLE) == PWM_CAPTURE_UPD2_EN_ENABLE) {
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pwm_capture_ch2_callback(NULL);
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}
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}
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__WEAK uint8_t pwm_capture_ch0_callback(void *context) { return 0; }
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__WEAK uint8_t pwm_capture_ch1_callback(void *context) { return 0; }
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__WEAK uint8_t pwm_capture_ch2_callback(void *context) { return 0; }
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