xushaoxiang
238 lines
7.3 KiB
C
238 lines
7.3 KiB
C
#ifndef _BSP_2_4_G_H_
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#define _BSP_2_4_G_H_
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#include "Includes.h"
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#define _2_4G_BASE 0x50003000
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#define CFG_TOP ((volatile unsigned *)(_2_4G_BASE + 0x00))
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#define EN_AA ((volatile unsigned *)(_2_4G_BASE + 0x04))
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#define EN_RXADDR ((volatile unsigned *)(_2_4G_BASE + 0x08))
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#define SETUP_AW ((volatile unsigned *)(_2_4G_BASE + 0x0C))
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#define SETUP_RETR ((volatile unsigned *)(_2_4G_BASE + 0x10))
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#define RF_CH ((volatile unsigned *)(_2_4G_BASE + 0x14))
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#define SETUP_RF ((volatile unsigned *)(_2_4G_BASE + 0x18))
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#define STATUS ((volatile unsigned *)(_2_4G_BASE + 0x1C))
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#define OBSERVE_TX ((volatile unsigned *)(_2_4G_BASE + 0x20))
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#define RSSI ((volatile unsigned *)(_2_4G_BASE + 0x24))
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#define RX_ADDR_P0_L ((volatile unsigned *)(_2_4G_BASE + 0x28))
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#define RX_ADDR_P0_H ((volatile unsigned *)(_2_4G_BASE + 0x2C))
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#define RX_ADDR_P1_L ((volatile unsigned *)(_2_4G_BASE + 0x30))
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#define RX_ADDR_P1_H ((volatile unsigned *)(_2_4G_BASE + 0x34))
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#define RX_ADDR_P2TOP5 ((volatile unsigned *)(_2_4G_BASE + 0x38))
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#define BER_RESULT_L ((volatile unsigned *)(_2_4G_BASE + 0x3C))
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#define BER_RESULT_H ((volatile unsigned *)(_2_4G_BASE + 0x40))
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#define AGC_SETTING ((volatile unsigned *)(_2_4G_BASE + 0x44))
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#define PGA_SETTING_L ((volatile unsigned *)(_2_4G_BASE + 0x48))
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#define PGA_SETTING_H ((volatile unsigned *)(_2_4G_BASE + 0x50))
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#define TX_ADDR_L ((volatile unsigned *)(_2_4G_BASE + 0x4C))
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#define TX_ADDR_H ((volatile unsigned *)(_2_4G_BASE + 0x50))
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#define RX_PW_PX_L ((volatile unsigned *)(_2_4G_BASE + 0x54))
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#define RX_PW_PX_H ((volatile unsigned *)(_2_4G_BASE + 0x58))
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#define STATUS_FIFO ((volatile unsigned *)(_2_4G_BASE + 0x80))
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#define RSSIREC ((volatile unsigned *)(_2_4G_BASE + 0x84))
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#define TXPROC_CFG ((volatile unsigned *)(_2_4G_BASE + 0x88))
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#define RXPROC_CFG_L ((volatile unsigned *)(_2_4G_BASE + 0x8C))
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#define RXPROC_CFG_H ((volatile unsigned *)(_2_4G_BASE + 0xA8))
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#define DYNPD ((volatile unsigned *)(_2_4G_BASE + 0x94))
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#define FEATURE ((volatile unsigned *)(_2_4G_BASE + 0x98))
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#define CMD_BYTE ((volatile unsigned *)(_2_4G_BASE + 0xC0))
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#define TXFIFO_WDATA ((volatile unsigned *)(_2_4G_BASE + 0xC4))
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#define RXFIFO_RDTA ((volatile unsigned *)(_2_4G_BASE + 0xC8))
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#define RXFIFO_LEN ((volatile unsigned *)(_2_4G_BASE + 0xCC))
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#define R_REG 0x00
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#define W_REG 0x20
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#define R_RX_PLOAD 0x61
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#define W_TX_PLOAD 0xA0
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#define FLUSH_TX 0xE1
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#define FLUSH_RX 0xE2
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#define REUSE_TX_PL 0xE3
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#define R_RX_PL_WID 0x60
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#define W_ACK_PLOAD 0xA8
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#define W_TX_PLOAD_NOACK 0xB0
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#define CMD_NOP 0xFF
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#define CMD_DONE 0x100
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#define TX_REUSE (0x1 << 6)
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#define TX_FULL (0x1 << 5)
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#define TX_EMPTY (0x1 << 4)
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#define RX_FULL (0x2)
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#define RX_EMPTY (0x1)
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/* STATUS Interrupt status */
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#define XC_RX_DR (0x1 << 6)//@
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#define XC_TX_DS (0x1 << 5)//@
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#define XC_MAX_RT (0x1 << 4)//@
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#define ALL_IRQ_STATUS (0x70)//@
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//
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#define EN_LONG_PLD 1
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#define EN_FEC 1
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#define EN_WHITEN 1
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#define EN_DPL 1
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#define EN_ACK_PAY 1
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#define DIS_LONG_PLD 0
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#define DIS_FEC 0
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#define DIS_WHITEN 0
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#define DIS_DPL 0
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#define DIS_ACK_PAY 0
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#define EN_CRC 1
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#define DIS_CRC 0
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#define CRC_1BIT 1
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#define CRC_2BIT 2
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#define setbit_array(x,y) (setbit((x)[(y)/8],(y)%8))
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#define clrbit_array(x,y) (clrbit((x)[(y)/8],(y)%8))
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#define CE_High *CFG_TOP |=0x4000
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#define CE_Low *CFG_TOP &=(~0x4000)
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#define TX_MODE 0x0
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#define RX_MODE 0x1
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#define nop() __NOP();\
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__NOP();\
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__NOP();\
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__NOP()
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extern void send_cmd(uint8_t cmd);
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extern void BLEcrc(const uint8_t* data, uint8_t dataLen, uint8_t* outputCRC);
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extern void bleWhiten(uint8_t* data, uint8_t len, uint8_t whitenCoeff);
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extern uint8_t bleWhitenStart(uint16_t Fre);
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extern uint8_t reverseBits(uint8_t input);
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extern uint8_t XC_RxPacket(uint8_t en_ack_pay,uint8_t *ack_buf,uint8_t ack_len,uint8_t *rxbuf);
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extern void XC_TxPacket(uint8_t *txbuf, uint8_t len);
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extern void init_24G(uint8_t mode);
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extern void init_adv(uint8_t mode);
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extern void set_channel(uint16_t channel);
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extern void config_2_4g_rf(void);
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extern void set_power(uint8_t gc);
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void set_txaddr(uint32_t txaddr_l,uint32_t txaddr_h);
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void set_pipe0_rxaddr(uint32_t rxaddr_l,uint32_t rxaddr_h);
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void set_trx_addr_len(uint8_t len);
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void set_rate(uint8_t rate);
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void set_feature(uint8_t long_pld,uint8_t fec,uint8_t whiten,uint8_t dpl,uint8_t ack_pay);
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void set_mode(uint8_t mode);
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void set_crc(uint8_t enable,uint8_t crc_bit);
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void set_p012345_revlen(uint32_t p0123len,uint32_t p45len);
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void set_pipe0_revlen(uint8_t p0len);
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void rf_rccalib(void);
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void go_tx(uint16_t ch);
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void go_rx(uint16_t ch);
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void rx_24g_ota(void);
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uint8_t wait_ack(uint8_t *ack_pay_buf,uint8_t *len,uint32_t timeout);
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void set_retry_cnt(uint8_t ch);
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/////////////////////////////////////////////////////////
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#define CLK_BBPLL64M 0
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#define CLK_BBPLL96M 1
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#define _24G_CLK_SOURCE CLK_BBPLL96M
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/////////////////////////////////////////////////////////
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#define BUFF_ADV_LENGTH 15
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#define BUFF_24G_LENGTH 32
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#define BUFF_24G_ACK_PAY_LENGTH 7
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/////////////////////////////////////////////////////////
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#define RF_ADV_CHANNELS_37 2402
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#define RF_ADV_CHANNELS_38 2426
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#define RF_ADV_CHANNELS_39 2480
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#define RF_ADV_CHANNELS RF_ADV_CHANNELS_38
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#define CHANNEL_24G 2402
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/////////////////////////////////////////////////////////
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#define RATE_2M 0x0A
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#define RATE_1M 0x02
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#define RATE_250K 0x22
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#define RATE_125K 0x2A
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//#define TRANS_RATE RATE_250K
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//#define TRANS_RATE RATE_1M
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#define TRANS_RATE RATE_1M //RATE_250K RATE_125K RATE_1M
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/////////////////////////////////////////////////////////
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#define POWER_LEVEL 0x10 /////tip:1M Max Power 0x2c(6.8dbm)
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/////////////////////////////////////////////////////////
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//#define USE_24G_IRQ
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/////////////////////////////////////////////////////////
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#define ACK_TOMEOUT 0x10000 //4550
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/////////////////////////////////////////////////////////
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#define TEST_SINGLE 0
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#define TEST_24G 1
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#define TEST_ADV 0
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#define TEST_SWITCH_24G 0
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/////////////////////////////////////////////////////////
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#define DEBUG1
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//#define DEBUG2
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#define FLASH_BIN_ADDR_OFFSET (0x3000)
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#define PACKET_LENGTH (29)
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enum{
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STATUS_OK=0,
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STATUS_FAIL=1,
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STATUS_BUSY=2,
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STATUS_READY=3,
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};
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enum{
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rFALSE=0,//false
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rTRUE=1, //true
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};
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typedef struct{
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uint32_t SoftVer;/**/
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uint32_t RomVer;
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uint32_t Len;/*file len*/
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uint32_t CRC32;/*crc32*/
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uint32_t PacketNum;
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uint32_t cPacketNo;
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uint32_t Channel;
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uint32_t AddrH;
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uint32_t AddrL;
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uint32_t FrameNum;
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uint32_t cFrameNo;
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uint32_t WriteAddr;
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uint32_t DataStatus:8;
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uint32_t CheckStatus:8;
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uint32_t RevComplete:8;
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uint32_t ResStatus1:8;
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}INFO_24G;
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extern volatile INFO_24G info_24g;
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#endif
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