xushaoxiang
512 lines
14 KiB
C
512 lines
14 KiB
C
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/*----------------------------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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----------------------------------------------------------------------------------------------------*/
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#include "Includes.h"
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/*----------------------------------------------------------------------------------------------------
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SPI COMMAND
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-----------------------------------------------------------------------------------------------------*/
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#define CMD_RDID 0x9F
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#define CMD_PAGE_ERASE 0x81
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#define CMD_READ_STATUS2 0x35
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#define CMD_WRITE_STATUS 0x01
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#define CMD_READ_DATA 0x03
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#define CMD_READ_STATUS 0x05
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#define CMD_CHIP_ERASE 0xc7
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#define CMD_WRITE_ENABLE 0x06
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#define CMD_PAGE_PROGRAM 0x02
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#define CMD_BLOCK_ERASE 0xD8
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#define CMD_SECTOR_ERASE 0x20
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#define CMD_RELEASE_PWRDWN 0xAB
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#define CMD_PWRDWN 0xB9
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#define CMD_ID 0x4B
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#define PACKET_FULL_LEN FLASH_PAGE_SIZE
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static uint8_t __attribute__((aligned(4))) txbuff[(PACKET_FULL_LEN+4)];
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static uint8_t __attribute__((aligned(4))) rxbuff[(PACKET_FULL_LEN+4)];
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/* ---------------------------------------------------------------------------------------------------
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- 函数名称: Init_spi_master
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- 函数功能: 初始化spi主模式
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- 创建日期: 2015-09-14
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----------------------------------------------------------------------------------------------------*/
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void Init_spi_master(uint32_t ch, uint32_t freq)
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{
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uint32_t val;
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__write_hw_reg32(CPR_SPIx_MCLK_CTL(ch), 0x110010);//1分频 //- spi(x)_mclk = 32Mhz(When TXCO=32Mhz).
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__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000100<<ch)); //- 打开spi(x) pclk.
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__read_hw_reg32(CPR_SSI_CTRL, val);
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val |= (ch==0)? 0x01: 0x30;
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__write_hw_reg32(CPR_SSI_CTRL, val);
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__write_hw_reg32(SSIx_EN(ch), 0x00);
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__write_hw_reg32(SSIx_IE(ch), 0x00);
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__write_hw_reg32(SSIx_CTRL0(ch) , 0x7); /* 16bit SPI data */
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__write_hw_reg32(SSIx_SE(ch), 0x01);
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__write_hw_reg32(SSIx_BAUD(ch), freq); //- spix_mclk 分频.
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__write_hw_reg32(SSIx_RXFTL(ch), 0x00);
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__write_hw_reg32(SSIx_TXFTL(ch), 0x00);
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}
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void close_ssi0(void)
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{
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__write_hw_reg32(CPR_SPIx_MCLK_CTL(0), 0x110000);//close ssi0 mclk
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__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , (0x1000000)); //close ssi0 pclk
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__write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040000); //复位ssi0
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__write_hw_reg32(CPR_RSTCTL_SUBRST_SW , 0x040004); //复位ssi0
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}
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#ifdef QUAD_ENABLE
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void spi_flash_quad_en(void)
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{
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uint32_t bWk, cWk;
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__read_hw_reg32(SSI0_CTRL0 , bWk);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN , 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_WRITE_STATUS);
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__write_hw_reg32(SSI0_DATA, 0);
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__write_hw_reg32(SSI0_DATA, 0x02);
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do {
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__read_hw_reg32(SSI0_STS, cWk);
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}while((cWk&0x05) != 0x04);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , bWk);
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}
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uint8_t spi_flash_read_stat(void)
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{
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uint32_t bWk, cWk;
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uint8_t s8_15;
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__read_hw_reg32(SSI0_CTRL0 , bWk);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN , 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_READ_STATUS2);
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__write_hw_reg32(SSI0_DATA, 0xff);
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do {
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__read_hw_reg32(SSI0_STS, cWk);
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}while((cWk&0x05) != 0x04);
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cWk=*SSI0_DATA;//no use
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s8_15=*SSI0_DATA;
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , bWk);
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return s8_15;
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}
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#endif
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uint32_t spi_flash_read_identific(void)
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{
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uint32_t bWk, cWk;
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uint8_t manufact,memory_type,capacity;
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__read_hw_reg32(SSI0_CTRL0 , bWk);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN , 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_RDID);
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__write_hw_reg32(SSI0_DATA, 0xff);
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__write_hw_reg32(SSI0_DATA, 0xff);
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__write_hw_reg32(SSI0_DATA, 0xff);
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do {
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__read_hw_reg32(SSI0_STS, cWk);
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}while((cWk&0x05) != 0x04);
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cWk=*SSI0_DATA;//no use
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manufact=*SSI0_DATA;
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memory_type=*SSI0_DATA;
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capacity=*SSI0_DATA;
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , bWk);
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return (CMD_RDID<<24)|(manufact<<16)|(memory_type<<8)|(capacity<<0);
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}
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/* ---------------------------------------------------------------------------------------------------
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- 函数名称: spi_flash_write_Sector
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- 函数功能: 向SPI FLASH指定扇区写入数据
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- 创建日期: 2019.04.08
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- 作 者:陈俊伟
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---------------------------------------------------------------*/
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extern void spi_flash_write_sPages(uint32_t WriteAddR, uint8_t *buff)
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{
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uint8_t i=0,j=PAGES_SIZE/FLASH_PAGE_SIZE;
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uint8_t buf;
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for (int k = 0; k < 1024; k += 4)
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{
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// printf("i:%d\n",i);
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buf = buff[k];
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buff[k] = buff[k + 3];
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buff[k + 3] = buf;
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buf = buff[k + 1];
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buff[k + 1] = buff[k + 2];
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buff[k + 2] = buf;
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}
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for(i=0;i<j;i++)
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{
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spi_flash_write_enable();
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spi_flash_write_page(WriteAddR,buff);
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while(spi_flash_wait_till_ready());
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WriteAddR+=FLASH_PAGE_SIZE;
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buff+=FLASH_PAGE_SIZE;
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}
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}
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/* ---------------------------------------------------------------------------------------------------
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- 函数名称: spi_flash_chip_erase
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- 函数功能: 擦除整个芯片的内容
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- 创建日期: 2015-09-16
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----------------------------------------------------------------------------------------------------*/
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extern void spi_flash_chip_erase(void)
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{
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uint32_t bWk, cWk;
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__read_hw_reg32(SSI0_CTRL0 , bWk);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN , 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_CHIP_ERASE);
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do {
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__read_hw_reg32(SSI0_STS, cWk);
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}while((cWk&0x05) != 0x04);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , bWk);
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}
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__RAM_CODE void spi_flash_Read_Page(uint32_t addr, uint8_t *buff)
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{
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uint32_t iWK = 0;
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txbuff[1] = (uint8_t)(addr>>16);
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txbuff[0] = CMD_READ_DATA;
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txbuff[3] = (uint8_t)(addr);
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txbuff[2] = (uint8_t)(addr>>8);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x03);
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__write_hw_reg32(SSI0_DMATDL, 0x4); //-
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__write_hw_reg32(SSI0_DMARDL, 0x4); //- 1/4 FIFO
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__write_hw_reg32(SSI0_EN , 0x01);
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//- RX Channel
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__write_hw_reg32(DMAS_CHx_SAR(10) , 0x40013060);
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__write_hw_reg32(DMAS_CHx_DAR(10) , (uint32_t)rxbuff);
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__write_hw_reg32(DMAS_CHx_CTL1(10) ,((2 << 8)| 0));
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__write_hw_reg32(DMAS_CHx_CTL0(10) ,(PACKET_FULL_LEN+4));
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__write_hw_reg32(DMAS_EN , 10);
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//- TX Channel
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__write_hw_reg32(DMAS_CHx_SAR(2) , (uint32_t)txbuff);
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__write_hw_reg32(DMAS_CHx_DAR(2) , 0x40013060);
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__write_hw_reg32(DMAS_CHx_CTL1(2) ,((2 << 8)| 0));
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__write_hw_reg32(DMAS_CHx_CTL0(2) ,(PACKET_FULL_LEN+4));
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__write_hw_reg32(DMAS_EN , 2);
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do {
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__read_hw_reg32(DMAS_INT_RAW , iWK);
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}while((iWK&0x404) != 0x404);
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__write_hw_reg32(DMAS_INT_RAW, 0x404);
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__write_hw_reg32(DMAS_CLR , 10);
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__write_hw_reg32(DMAS_CLR , 2);
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__write_hw_reg32(SSI0_EN , 0x00);
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for(int i=0;i<PACKET_FULL_LEN;i++){
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buff[i]=rxbuff[i+4];
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}
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}
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void spi_flash_write_page(uint32_t PageAddR, uint8_t *buff)
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{
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uint32_t addr = PageAddR;
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uint32_t iWK = 0;
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uint32_t i;
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for(i=0; i<PACKET_FULL_LEN; i++){
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txbuff[i+4] = buff[i];
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}
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txbuff[1] = (uint8_t)(addr>>16);
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txbuff[0] = CMD_PAGE_PROGRAM;
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txbuff[3] = (uint8_t)(addr);
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txbuff[2] = (uint8_t)(addr>>8);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x03);
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__write_hw_reg32(SSI0_DMATDL, 0x4); //-
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__write_hw_reg32(SSI0_DMARDL, 0x4); //- 1/2FIFO
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__write_hw_reg32(SSI0_EN , 0x01);
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//- RX Channel
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__write_hw_reg32(DMAS_CHx_SAR(10), 0x40013060);
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__write_hw_reg32(DMAS_CHx_DAR(10), (uint32_t)rxbuff);
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__write_hw_reg32(DMAS_CHx_CTL1(10),((2 << 8)| 0));
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__write_hw_reg32(DMAS_CHx_CTL0(10),(PACKET_FULL_LEN+4));
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__write_hw_reg32(DMAS_EN, 10);
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//- TX Channel
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__write_hw_reg32(DMAS_CHx_SAR(2), (uint32_t)txbuff);
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__write_hw_reg32(DMAS_CHx_DAR(2), 0x40013060);
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__write_hw_reg32(DMAS_CHx_CTL1(2),((2 << 8)| 0));
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__write_hw_reg32(DMAS_CHx_CTL0(2),(PACKET_FULL_LEN+4));
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__write_hw_reg32(DMAS_EN, 2);
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do {
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__read_hw_reg32(DMAS_INT_RAW , iWK);
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}while((iWK&0x404) != 0x404);
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__write_hw_reg32(DMAS_INT_RAW, 0x404);
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__write_hw_reg32(DMAS_CLR , 10);
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__write_hw_reg32(DMAS_CLR , 2);
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__write_hw_reg32(SSI0_EN , 0x00);
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}
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//void spi_flash_page_erase(uint32_t addr)
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//{
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// uint32_t bWk, cWk;
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// __read_hw_reg32(SSI0_CTRL0 , bWk);
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// __write_hw_reg32(SSI0_EN , 0x00);
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// __write_hw_reg32(SSI0_DMAS , 0x00);
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// __write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
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// __write_hw_reg32(SSI0_EN , 0x01);
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// __write_hw_reg32(SSI0_DATA, CMD_PAGE_ERASE);
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// __write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>16));
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// __write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>8));
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// __write_hw_reg32(SSI0_DATA, (uint8_t)(addr));
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// do {
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// __read_hw_reg32(SSI0_STS, cWk);
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// }while((cWk&0x05) != 0x04);
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// __write_hw_reg32(SSI0_EN , 0x00);
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// __write_hw_reg32(SSI0_CTRL0 , bWk);
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//}
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void spi_flash_sector_erase(uint32_t addr)
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{
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// if((addr>=(4096+param_backup_addr))&&(addr<(8192+param_backup_addr))) return; //forbid erase the calibration parameter area
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uint32_t bWk, cWk;
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__read_hw_reg32(SSI0_CTRL0 , bWk);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN , 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_SECTOR_ERASE);
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__write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>16));
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__write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>8));
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__write_hw_reg32(SSI0_DATA, (uint8_t)(addr));
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do {
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__read_hw_reg32(SSI0_STS, cWk);
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}while((cWk&0x05) != 0x04);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , bWk);
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}
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void spi_flash_block_erase(uint32_t addr)
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{
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uint32_t bWk, cWk;
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__read_hw_reg32(SSI0_CTRL0 , bWk);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN , 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_BLOCK_ERASE);
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__write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>16));
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__write_hw_reg32(SSI0_DATA, (uint8_t)(addr>>8));
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__write_hw_reg32(SSI0_DATA, (uint8_t)(addr));
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do {
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__read_hw_reg32(SSI0_STS, cWk);
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}while((cWk&0x05) != 0x04);
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__write_hw_reg32(SSI0_EN , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , bWk);
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}
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void spi_flash_write_enable(void)
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{
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uint32_t bWk, cWk;
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__read_hw_reg32(SSI0_CTRL0 , bWk);
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__write_hw_reg32(SSI0_EN, 0x00);
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__write_hw_reg32(SSI0_DMAS , 0x00);
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__write_hw_reg32(SSI0_CTRL0 , 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN, 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_WRITE_ENABLE);
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do {
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__read_hw_reg32(SSI0_STS, cWk);
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}while((cWk&0x05) != 0x04);
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__write_hw_reg32(SSI0_EN, 0x00);
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__write_hw_reg32(SSI0_CTRL0, bWk);
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}
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void spi_flash_Release_powerdown(void)
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{
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uint32_t bWk, cWk;
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__read_hw_reg32(SSI0_CTRL0, bWk);
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__write_hw_reg32(SSI0_EN, 0x00);
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__write_hw_reg32(SSI0_DMAS, 0x00);
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__write_hw_reg32(SSI0_CTRL0, 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN, 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_RELEASE_PWRDWN);
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do {
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__read_hw_reg32(SSI0_STS, cWk);
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}while((cWk&0x05) != 0x04);
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__write_hw_reg32(SSI0_EN, 0x00);
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__write_hw_reg32(SSI0_CTRL0, bWk);
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}
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void spi_flash_Enter_powerdown(void)
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{
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uint32_t bWk, cWk;
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__read_hw_reg32(SSI0_CTRL0, bWk);
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__write_hw_reg32(SSI0_EN, 0x00);
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__write_hw_reg32(SSI0_DMAS, 0x00);
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__write_hw_reg32(SSI0_CTRL0, 0x07); /* 8bit SPI data */
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__write_hw_reg32(SSI0_EN, 0x01);
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__write_hw_reg32(SSI0_DATA, CMD_PWRDWN);
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do {
|
|
__read_hw_reg32(SSI0_STS, cWk);
|
|
}while((cWk&0x05) != 0x04);
|
|
|
|
|
|
__write_hw_reg32(SSI0_EN, 0x00);
|
|
__write_hw_reg32(SSI0_CTRL0, bWk);
|
|
|
|
}
|
|
|
|
uint8_t spi_flash_wait_till_ready (void)
|
|
{
|
|
uint16_t cmd = (CMD_READ_STATUS<<8);
|
|
uint32_t iWK,bWk;
|
|
uint16_t dWK = 0;
|
|
|
|
__read_hw_reg32(SSI0_CTRL0 , bWk);
|
|
|
|
__write_hw_reg32(SSI0_EN , 0x00);
|
|
__write_hw_reg32(SSI0_CTRL0 , 0x0F); /* 16bit SPI data */
|
|
__write_hw_reg32(SSI0_DMAS , 0x00); /* turn off dma*/
|
|
__write_hw_reg32(SSI0_DMATDL, 0x0); //-
|
|
__write_hw_reg32(SSI0_DMARDL, 0x0); //-
|
|
__write_hw_reg32(SSI0_EN , 0x01);
|
|
|
|
__write_hw_reg32(SSI0_DATA , cmd);
|
|
|
|
do {
|
|
__read_hw_reg32(SSI0_STS, iWK);
|
|
}while((iWK&0x05) != 0x04);
|
|
|
|
__read_hw_reg32(SSI0_DATA , dWK);
|
|
|
|
__write_hw_reg32(SSI0_EN , 0x00);
|
|
__write_hw_reg32(SSI0_CTRL0 , bWk);
|
|
return (uint8_t)(dWK&0x01);
|
|
}
|
|
|
|
#ifdef TEST_SPI_FLASH
|
|
void test_spi_master(void)
|
|
{
|
|
|
|
spi_flash_Release_powerdown();
|
|
#ifdef QUAD_ENABLE
|
|
if((spi_flash_read_stat()&0x02)==0)
|
|
{
|
|
printf("\n@@ QUAD ENABLE @@\n");
|
|
spi_flash_write_enable();
|
|
spi_flash_quad_en();
|
|
while(spi_flash_wait_till_ready());
|
|
}
|
|
printf("s15_8=%#X\n",spi_flash_read_stat());
|
|
#endif
|
|
uint8_t tx_arr[256];
|
|
uint8_t rx_arr[256];
|
|
static uint8_t flag=0;
|
|
printf("capacity=%#X\n",spi_flash_read_identific());
|
|
/*read a page*/
|
|
spi_flash_Read_Page(0*4096,rx_arr);
|
|
for(int i=0;i<256;i++) printf("%02x ",rx_arr[i]);
|
|
|
|
printf("\n*****************#*******************\n");
|
|
if(flag){
|
|
flag=0;
|
|
for(int i=0; i<256; i++) tx_arr[i]=i;
|
|
}else{
|
|
for(int i=0; i<256; i++) tx_arr[i]=255-i;
|
|
flag=1;
|
|
}
|
|
/*erase a page/sector*/
|
|
spi_flash_write_enable();
|
|
spi_flash_sector_erase(31*4096); //spi_flash_page_erase(31*4096);
|
|
while(spi_flash_wait_till_ready());
|
|
|
|
/*write a page*/
|
|
spi_flash_write_enable();
|
|
spi_flash_write_page(31*4096,tx_arr);
|
|
while(spi_flash_wait_till_ready());
|
|
/*read a page*/
|
|
spi_flash_Read_Page(31*4096,rx_arr);
|
|
for(int i=0;i<256;i++) printf("%02x ",rx_arr[i]);
|
|
printf("\n*****************@*******************\n");
|
|
|
|
//
|
|
spi_flash_Enter_powerdown();
|
|
|
|
}
|
|
#endif
|
|
|