xushaoxiang
173 lines
4.5 KiB
C
173 lines
4.5 KiB
C
#include "Includes.h"
|
|
|
|
|
|
|
|
void xc_timer_init(uint8_t tn,uint32_t us)
|
|
{
|
|
__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL,0x80008); //TIMER_PCLK enable
|
|
__write_hw_reg32(CPR_TIMER_CLK_CTL(tn),0x0B);//TIMERx_CLK mclk_in(24MHz)/(2*(0x0B + 0x1))
|
|
__write_hw_reg32(TIMERx_TCR(tn),0x0);
|
|
__write_hw_reg32(TIMERx_TCR(tn),0x2);
|
|
__write_hw_reg32(TIMERx_TLC(tn),us);
|
|
__write_hw_reg32(TIMERx_TCR(tn),0x3);
|
|
NVIC_EnableIRQ(TIMER0_IRQn+tn);
|
|
}
|
|
|
|
|
|
extern void Init_Timer(uint32_t ch, uint32_t msTick)
|
|
{
|
|
uint32_t val;
|
|
__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL , 0x80008);
|
|
//__write_hw_reg32(CPR_TIMER_CLK_CTL(ch) , 0x10000000); //- TIMER (32K/2) 16Khz
|
|
__write_hw_reg32(CPR_TIMER_CLK_CTL(ch) , 0x30000000); //- TIMER 32Khz
|
|
__read_hw_reg32(CPR_LP_CTL , val);
|
|
val |= (1<<2);
|
|
__write_hw_reg32(CPR_LP_CTL , val);
|
|
|
|
__read_hw_reg32(TIMERx_TIC(ch) , val);
|
|
__write_hw_reg32(TIMERx_TCR(ch) , 0x00);
|
|
//val = (msTick * 32000)/1000;
|
|
val = msTick;
|
|
__write_hw_reg32(TIMERx_TLC(ch) , val);
|
|
__write_hw_reg32(TIMERx_TCR(ch) , 0x03);
|
|
|
|
val = TIMER0_IRQn + ch;
|
|
NVIC_EnableIRQ((IRQn_Type)val);
|
|
}
|
|
|
|
|
|
void TIMER0_Handler(void)
|
|
{
|
|
uint32_t val=0;
|
|
__read_hw_reg32(TIMER0_TIC , val);
|
|
//printf("TIMER0_Handler \n");
|
|
gpio_output_low(0);
|
|
gpio_output_high(0);
|
|
|
|
}
|
|
|
|
void TIMER1_Handler(void)
|
|
{
|
|
uint32_t val=0;
|
|
__read_hw_reg32(TIMER1_TIC , val);
|
|
//printf("TIMER1_Handler\n");
|
|
gpio_output_low(1);
|
|
gpio_output_high(1);
|
|
}
|
|
|
|
void TIMER2_Handler(void)
|
|
{
|
|
uint32_t val=0;
|
|
__read_hw_reg32(TIMER2_TIC , val);
|
|
//printf("TIMER2_Handler\n");
|
|
gpio_output_low(2);
|
|
gpio_output_high(2);
|
|
|
|
}
|
|
|
|
void TIMER3_Handler(void)
|
|
{
|
|
uint32_t val=0;
|
|
__read_hw_reg32(TIMER3_TIC , val);
|
|
//printf("TIMER3_Handler\n");
|
|
gpio_output_low(3);
|
|
gpio_output_high(3);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/////////////////////////////////////////AO TIMER///////////////////////////////////////
|
|
#define TIMER_AO_BASE 0x40002800
|
|
#define TIMERx_AO_TLC(a) ((volatile unsigned *)(TIMER_AO_BASE + 0x00 + (a * 0x14)))
|
|
#define TIMERx_AO_TCV(a) ((volatile unsigned *)(TIMER_AO_BASE + 0x04 + (a * 0x14)))
|
|
#define TIMERx_AO_TCR(a) ((volatile unsigned *)(TIMER_AO_BASE + 0x08 + (a * 0x14)))
|
|
#define TIMERx_AO_TIC(a) ((volatile unsigned *)(TIMER_AO_BASE + 0x0C + (a * 0x14)))
|
|
#define TIMERx_AO_TIS(a) ((volatile unsigned *)(TIMER_AO_BASE + 0x10 + (a * 0x14)))
|
|
|
|
void aotimer_clk_conf(void)
|
|
{
|
|
uint32_t val=0;
|
|
__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x100000);// rest ao timer
|
|
__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x100010);// rest ao timer
|
|
__read_hw_reg32(CPR_AOCLKEN_GRCTL, val);
|
|
__write_hw_reg32(CPR_AOCLKEN_GRCTL, val|0xFF001d);// enable ao timer 0 1 clk and pclk
|
|
|
|
}
|
|
void aotimer_init(uint8_t tn,uint32_t tick)
|
|
{
|
|
|
|
__write_hw_reg32(TIMERx_AO_TCR(tn),0x0);
|
|
__write_hw_reg32(TIMERx_AO_TCR(tn),0x2);
|
|
__write_hw_reg32(TIMERx_AO_TLC(tn),tick);
|
|
__write_hw_reg32(TIMERx_AO_TCR(tn),0x3);
|
|
NVIC_EnableIRQ(AOTIMER0_IRQn+tn);
|
|
|
|
// //timer pclk switch to clk32k when sleep
|
|
// uint32_t val=0;
|
|
// __read_hw_reg32(CPR_AO_REG1, val);
|
|
// __write_hw_reg32(CPR_AO_REG1,val|(1<<19));//bit 19, 1: sleep timer pclk switch
|
|
|
|
}
|
|
|
|
|
|
void AOTIMER0_Handler(void)
|
|
{
|
|
uint32_t val=0;
|
|
// *CPR_AO_REG1 &=(~(1<<19));//timer pclk switch to pclk when wake up (if no set ,so it is intering)
|
|
__read_hw_reg32(TIMERx_AO_TIC(0) , val);
|
|
// printf("AOTIMER0_Handler \n");
|
|
gpio_output_low(2);
|
|
gpio_output_high(2);
|
|
|
|
}
|
|
void AOTIMER1_Handler(void)
|
|
{
|
|
uint32_t val=0;
|
|
// *CPR_AO_REG1 &=(~(1<<19));//timer pclk switch to pclk when wake up (if no set ,so it is intering)
|
|
__read_hw_reg32(TIMERx_AO_TIC(1) , val);
|
|
// printf("AOTIMER1_Handler \n");
|
|
gpio_output_low(3);
|
|
gpio_output_high(3);
|
|
|
|
|
|
|
|
}
|
|
void aotimer_disable(uint32_t ch)
|
|
{
|
|
__write_hw_reg32(TIMERx_AO_TCR(ch) , 0x00);
|
|
NVIC_DisableIRQ(AOTIMER0_IRQn+ch);
|
|
}
|
|
|
|
|
|
|
|
extern void test_timer(void)
|
|
{
|
|
//fpga clk fix 12M (no div)
|
|
gpio_mux_ctl(0,0);gpio_fun_inter(0,0);gpio_fun_sel(0,0);gpio_direction_output(0);
|
|
gpio_mux_ctl(1,0);gpio_fun_inter(1,0);gpio_fun_sel(1,0);gpio_direction_output(1);
|
|
gpio_mux_ctl(2,0);gpio_fun_inter(2,0);gpio_fun_sel(2,0);gpio_direction_output(2);
|
|
gpio_mux_ctl(3,0);gpio_fun_inter(3,0);gpio_fun_sel(3,0);gpio_direction_output(3);
|
|
#if 0
|
|
//Init_Timer(0,12000);
|
|
xc_timer_init(0,12000);//
|
|
xc_timer_init(1,24000);
|
|
|
|
//Init_Timer(2,12);
|
|
//Init_Timer(3,24);
|
|
xc_timer_init(2,12000);
|
|
xc_timer_init(3,12000);
|
|
#endif
|
|
|
|
#if 1
|
|
aotimer_clk_conf();
|
|
aotimer_init(0,12);
|
|
aotimer_init(1,2400);
|
|
while(1);
|
|
{
|
|
printf("%#X ",*TIMERx_AO_TCV(0));
|
|
}
|
|
#endif
|
|
}
|
|
|