xushaoxiang
125 lines
4.5 KiB
C
125 lines
4.5 KiB
C
#ifndef __XINC_M0_H__
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#define __XINC_M0_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/******************************************************************************/
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/* Processor and Core Peripherals */
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/******************************************************************************/
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/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
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Configuration of the Cortex-M# Processor and Core Peripherals
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@{
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*/
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
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/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
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/****** Device Specific Interrupt Numbers ********************************************************/
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/* ToDo: add here your device specific external interrupt numbers
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according the interrupt handlers defined in startup_Device.s
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eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
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BLUETOOTH_IRQn = 0, /*!< Device Interrupt */
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DMAS_IRQn = 1,
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CPR_IRQn = 2,
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GPIO_IRQn = 3,
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RTC_IRQn = 4,
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TIMER0_IRQn = 5,
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TIMER1_IRQn = 6,
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TIMER2_IRQn = 7,
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TIMER3_IRQn = 8,
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WDT_IRQn = 9,
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I2C_IRQn = 10,
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UART0_IRQn = 11,
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UART1_IRQn = 12,
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SPI0_IRQn = 13,
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SPI1_IRQn = 14,
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KBS_IRQn = 15,
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QDEC_IRQn = 16,
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GADC_IRQn = 17,
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SIM_IRQn = 18,
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AES_IRQn = 19,
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USB_IRQn = 20,
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RESV0_IRQn = 21,
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SUB1G_IRQn = 22,
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RESV1_IRQn = 23,
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BOR = 24,
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RESV2_IRQn = 25,
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RESV3_IRQn = 26,
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AOTIMER0_IRQn = 27,
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AOTIMER1_IRQn = 28,
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CMP_IRQn = 29,
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FMC_IRQn = 30,
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CAN_IRQn = 31,
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M# Processor and Core Peripherals */
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/* ToDo: set the defines according your Device */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#if defined ( __CC_ARM )
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#if defined (__TARGET_FPU_VFP)
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#define __FPU_PRESENT 1 /*!< FPU present or not */
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#else
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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#endif
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#else
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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#endif
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/*@}*/ /* end of group <Device>_CMSIS */
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#include "core_cm0.h"
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/******************************************************************************/
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/* Device Specific Peripheral registers structures */
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/******************************************************************************/
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/** @addtogroup <Device>_Peripherals <Device> Peripherals
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<Device> Device Specific Peripheral registers structures
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@{
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*/
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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#include "xinc_reg.h"
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif // __<Device>_H__
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