xushaoxiang
287 lines
9.7 KiB
C
287 lines
9.7 KiB
C
/*!
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* \file xc_drv_dma.h
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*
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* \brief The header of xc_drv_dma.c
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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#ifndef _XC_DRV_DMA_H_
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#define _XC_DRV_DMA_H_
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include <stdbool.h>
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#include <stdio.h>
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#include "xc6xxx.h"
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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// Macro definitions for DMA operation return code
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#define DMA_OK 0 // operation normal
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#define DMA_EPERM 1 // operation not permitted
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#define DMA_EIO 5 // I/O error
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#define DMA_ENXIO 6 // no such device or address
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#define DMA_ENOMEM 12 // out of memory
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#define DMA_EACCES 13 // permission denied
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#define DMA_EBUSY 16 // device or resource busy
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#define DMA_ENODEV 19 // no such device
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#define DMA_EINVAL 22 // invalid argument
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#define DMA_ENOSPC 28 // no space left on device
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#define DMA_ENOSYS 38 // function not implemented/supported
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#define DMA_ECHRNG 44 // channel number out of range
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#define DMA_ENODATA 61 // no data available
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#define DMA_ETIME 62 // timer expired
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#define DMA_EPROTO 71 // protocol error
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// Macro definitions for DMA controller limits
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#define DMA_MAX_CHANNELS 4U //5A 2 CH; 5B 4 CH
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#define DMA_MAX_INTERRUPTS 5U
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/*------------------------------------------------------------------------------------
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TypeDef
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-------------------------------------------------------------------------------------*/
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typedef void (*DMA_Callback)(uint8_t eCode);
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typedef enum dmac_channel_number
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{
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// 4 channel configuration
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DMA_NO_CHANNEL = 0x0000,
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DMA_CHANNEL0 = 0x0101,
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DMA_CHANNEL1 = 0x0202,
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DMA_CHANNEL2 = 0x0404,
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DMA_CHANNEL3 = 0x0808,
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DMA_ALL_CHANNELS = 0x0f0f
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} eDMA_Ch_Num;
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typedef enum dmac_src_dst_select
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{
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DMA_SRC = 0x1,
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DMA_DST = 0x2,
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DMA_SRC_DST = 0x3
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} eDMA_Src_Dst_Select;
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typedef enum dmac_ch_state
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{
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DMA_IDLE = 0x0,
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DMA_SINGLE_REGION = 0x1,
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DMA_BURST_REGION = 0x2
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} eDMA_CH_State;
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typedef enum dmac_transfer_type
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{
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DMA_TRANSFER_ROW1 = 0x1, /* single block or last multi-block */
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/* no write back */
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DMA_TRANSFER_ROW2 = 0x2, /* multi-block auto-reload DAR */
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/* contiguous SAR no write back */
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DMA_TRANSFER_ROW3 = 0x3, /* multi-block auto reload SAR */
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/* contiguous DAR no write back */
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DMA_TRANSFER_ROW4 = 0x4, /* multi-block auto-reload SAR DAR */
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/* no write back */
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DMA_TRANSFER_ROW5 = 0x5, /* single block or last multi-block */
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/* with write back */
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DMA_TRANSFER_ROW6 = 0x6, /* multi-block linked list DAR */
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/* contiguous SAR with write back */
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DMA_TRANSFER_ROW7 = 0x7, /* multi-block linked list DAR auto */
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/* reload SAR with write back */
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DMA_TRANSFER_ROW8 = 0x8, /* multi-block linked list SAR */
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/* contiguous DAR with write back */
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DMA_TRANSFER_ROW9 = 0x9, /* multi-block linked list SAR auto */
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/* reload DAR with write back */
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DMA_TRANSFER_ROW10 = 0xa /* multi-block linked list SAR DAR */
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/* with write back */
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} eDMA_Trans_Type;
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typedef enum dw_dmac_irq
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{
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DMA_IRQ_NONE = 0x00, // no interrupts
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DMA_IRQ_TRF = 0x01, // transfer complete
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DMA_IRQ_BLOCK = 0x02, // block transfer complete
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DMA_IRQ_SRCTRAN = 0x04, // source transaction complete
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DMA_IRQ_DSTTRAN = 0x08, // destination transaction complete
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DMA_IRQ_ERR = 0x10, // error
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DMA_IRQ_ALL = 0x1f // all interrupts
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} eDMA_Irq;
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typedef enum dmac_burst_trans_length
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{
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DMA_MSIZE_1 = 0x0,
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DMA_MSIZE_4 = 0x1,
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DMA_MSIZE_8 = 0x2,
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DMA_MSIZE_16 = 0x3,
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DMA_MSIZE_32 = 0x4,
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DMA_MSIZE_64 = 0x5,
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DMA_MSIZE_128 = 0x6,
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DMA_MSIZE_256 = 0x7
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} eDMA_Burst_Trans_Len;
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typedef enum dmac_address_increment
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{
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DMA_ADDR_INCREMENT = 0x0,
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DMA_ADDR_DECREMENT = 0x1,
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DMA_ADDR_NOCHANGE = 0x2
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} eDMA_Addr_Increment;
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typedef enum dmac_transfer_width
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{
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DMA_TRANS_WIDTH_8 = 0x0,
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DMA_TRANS_WIDTH_16 = 0x1,
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DMA_TRANS_WIDTH_32 = 0x2,
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DMA_TRANS_WIDTH_64 = 0x3,
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DMA_TRANS_WIDTH_128 = 0x4,
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DMA_TRANS_WIDTH_256 = 0x5
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} eDMA_Trans_Width;
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typedef enum dw_dmac_sw_hw_hs_select
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{
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DMA_HS_HARDWARE = 0x0,
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DMA_HS_SOFTWARE = 0x1
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} eDMA_SW_HW_HS_Select;
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typedef enum dmac_hs_interface
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{
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UART0_DMA_TX_HS_IF0 = 0x0,
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UART1_DMA_TX_HS_IF1 = 0x1,
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SSI0_DMA_TX_HS_IF2 = 0x2,
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SSI1_DMA_TX_HS_IF3 = 0x3,
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SSI2_DMA_TX_HS_IF4 = 0x4,
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I2S_DMA_TX_HS_IF5 = 0x5,
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CDC_DMA_TX_HS_IF6 = 0x6,
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DMA_HS_IF7 = 0x7,
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UART0_DMA_RX_HS_IF8 = 0x8,
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UART1_DMA_RX_HS_IF9 = 0x9,
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SSI0_DMA_RX_HS_IF10 = 0xa,
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SSI1_DMA_RX_HS_IF11 = 0xb,
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GPADC_DMA_RX_HS_IF12 = 0xc,
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CDC_DMA_RX_HS_IF13 = 0xd,
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SSI2_DMA_RX_HS_IF14 = 0xe,
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I2S_DMA_RX_HS_IF15 = 0xf
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} eDMA_HS_Interface;
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typedef enum dmac_transfer_flow
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{
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DMA_MEM2MEM_DMA = 0x0, /* mem to mem - DMA flow ctlr */
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DMA_MEM2PRF_DMA = 0x1, /* mem to prf - DMA flow ctlr */
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DMA_PRF2MEM_DMA = 0x2, /* prf to mem - DMA flow ctlr */
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DMA_PRF2PRF_DMA = 0x3, /* prf to prf - DMA flow ctlr */
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DMA_PRF2MEM_PRF = 0x4, /* prf to mem - periph flow ctlr */
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DMA_PRF2PRF_SRCPRF = 0x5, /* prf to prf - source flow ctlr */
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DMA_MEM2PRF_PRF = 0x6, /* mem to prf - periph flow ctlr */
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DMA_PRF2PRF_DSTPRF = 0x7 /* prf to prf - dest flow ctlr */
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} eDMA_Trans_Flow;
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typedef enum dmac_fifo_mode
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{
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DMA_FIFO_MODE_SINGLE = 0x0,
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DMA_FIFO_MODE_HALF = 0x1
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} eDMA_Fifo_Mode;
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typedef enum dw_dmac_channel_priority
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{
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DMA_PRIORITY_0 = 0x0,
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DMA_PRIORITY_1 = 0x1,
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DMA_PRIORITY_2 = 0x2,
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DMA_PRIORITY_3 = 0x3,
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DMA_PRIORITY_4 = 0x4,
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DMA_PRIORITY_5 = 0x5,
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DMA_PRIORITY_6 = 0x6,
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DMA_PRIORITY_7 = 0x7
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} eDMA_CH_Priority;
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typedef struct dmac_channel_config
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{
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uint32_t sar;
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uint32_t dar;
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eDMA_Burst_Trans_Len ctl_src_msize;
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eDMA_Burst_Trans_Len ctl_dst_msize;
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eDMA_Addr_Increment ctl_sinc;
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eDMA_Addr_Increment ctl_dinc;
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eDMA_Trans_Width ctl_src_tr_width;
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eDMA_Trans_Width ctl_dst_tr_width;
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eDMA_HS_Interface cfg_dst_per;
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eDMA_HS_Interface cfg_src_per;
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uint32_t ctl_block_ts;
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eDMA_Trans_Flow ctl_tt_fc;
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eDMA_Fifo_Mode cfg_fifo_mode;
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eDMA_SW_HW_HS_Select cfg_hs_sel_src;
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eDMA_SW_HW_HS_Select cfg_hs_sel_dst;
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eDMA_CH_Priority cfg_ch_prior;
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} DMA_Chx_Cfg_t;
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typedef struct dmac_param_s
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{
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bool encoded_params; /* include encoded hardware parameters */
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uint8_t num_channels; /* number of DMA channels */
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uint8_t num_hs_int; /* number of handshaking interfaces */
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uint8_t intr_io; /* individual or combined interrupts */
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bool big_endian; /* big or little endian 1=big */
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uint16_t s_hdata_width; /* AHB slave data bus width */
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} DMA_Params_t;
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typedef struct dma_instance_s
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{
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struct
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{
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eDMA_Ch_Num ch_num; // channel number
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DMA_Callback userCallback; // callback functon for IRQ handler
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DMA_Callback userListener; // listener functon for IRQ handler
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} Ch[DMA_MAX_CHANNELS];
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uint8_t Ch_Order[DMA_MAX_CHANNELS];
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} DMA_Instance_t;
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/*------------------------------------------------------------------------------------
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Global Variables
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-------------------------------------------------------------------------------------*/
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extern DMA_Instance_t DMA_Instance;
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/*------------------------------------------------------------------------------------
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Exported Functions
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-------------------------------------------------------------------------------------*/
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uint8_t xc_dma_init(void);
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void xc_dma_enable(void);
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uint8_t xc_dma_disable(void);
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bool xc_dma_is_enable(void);
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uint8_t xc_dma_enable_channel(eDMA_Ch_Num ch_num);
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uint8_t xc_dma_disable_channel(eDMA_Ch_Num ch_num);
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bool xc_dma_is_channel_enabled(eDMA_Ch_Num ch_num);
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uint8_t xc_dma_enable_channel_irq(eDMA_Ch_Num ch_num);
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uint8_t xc_dma_set_channel_config(eDMA_Ch_Num ch_num, DMA_Chx_Cfg_t *ch);
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bool xc_dma_set_listener(eDMA_Ch_Num ch_num, DMA_Callback userFunction);
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uint8_t xc_dma_start_transfer(eDMA_Ch_Num ch_num, DMA_Callback cb_func);
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void xc_dma_set_test_mode(uint8_t mode);
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void xc_dma_set_channel_priority_order(DMA_Instance_t *inst);
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void xc_dma_reset_instance(DMA_Instance_t *inst);
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uint8_t xc_dma_check_channel_range(eDMA_Ch_Num ch_num);
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uint8_t xc_dma_check_channel_range(eDMA_Ch_Num ch_num);
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uint8_t xc_dma_get_channel_index(eDMA_Ch_Num ch_num);
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bool dma_irq_handler(DMA_Instance_t *inst);
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#endif /* _XC_DRV_DMA_H_ */
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