xushaoxiang
1059 lines
59 KiB
C
1059 lines
59 KiB
C
/*!
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* \file xc20xx.h
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*
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* \brief The header of xc20xx chip
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __XC20XX_H__
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#define __XC20XX_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#define __RAM_CODE __attribute__((section("ram_code")))
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#define __WEAK __attribute__((weak))
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
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#endif
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#define __STATIC_INLINE static __inline
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#define I2S_OFF
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#define CAN_OFF
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#define USB_OFF
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#define AES_OFF
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#define QDEC_USE_P20_P21
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#define HFCLK_SRC_XTAL_IS_24M
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#define LORA_CLOCK_PLL_CONFIG
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#define M0_LORA_RF_ANALOG_REG26_REG27
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#define NO_SUPPORT_HFCLK_BBPLL_128M
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#define NO_SUPPORT_HFCLK_RC_16M
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#define NO_SUPPORT_SPI2
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#define NO_SUPPORT_ROM_FMC_SPI
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/**
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* ==========================================================================
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* ------------------- Interrupt Number Definition --------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
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/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
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/****** Device Specific Interrupt Numbers ********************************************************/
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/* ToDo: add here your device specific external interrupt numbers
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according the interrupt handlers defined in startup_Device.s
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eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
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BLE_IRQn = 0, /*!< Device Interrupt */
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DMA_IRQn = 1,
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CPR_IRQn = 2,
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GPIO_IRQn = 3,
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RTC_IRQn = 4,
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TIMER0_IRQn = 5,
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TIMER1_IRQn = 6,
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TIMER2_IRQn = 7,
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TIMER3_IRQn = 8,
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WDT_IRQn = 9,
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I2C_IRQn = 10,
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UART0_IRQn = 11,
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UART1_IRQn = 12,
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SPI0_IRQn = 13,
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SPI1_IRQn = 14,
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KBS_IRQn = 15,
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QDEC_IRQn = 16,
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GADC_IRQn = 17,
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PWM_IRQn = 18,
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AUDIO_IRQn = 21,
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RF24G_IRQn = 22,
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MPU_IRQn = 24,
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UART2_IRQn = 25,
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TIMER_AO0_IRQn = 27,
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TIMER_AO1_IRQn = 28,
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CMP_IRQn = 29,
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FMC_IRQn = 30,
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M# Processor and Core Peripherals */
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/* ToDo: set the defines according your Device */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#if defined ( __CC_ARM )
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#if defined (__TARGET_FPU_VFP)
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#define __FPU_PRESENT 1 /*!< FPU present or not */
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#else
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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#endif
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#else
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#define __FPU_PRESENT 0 /*!< FPU present or not */
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#endif
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/*@}*/ /* end of group <Device>_CMSIS */
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#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
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/* =========================================================================================================================== */
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/* ================ DMAS ================ */
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/* =========================================================================================================================== */
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/**
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* @brief 精简直接存储器存取控制器（DMAS） (DMAS)
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*/
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typedef struct { /*!< (@ 0x50001000) DMAS Structure */
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__OM uint32_t DMAs_EN; /*!< (@ 0x50001000) DMA 通道使能寄存器 */
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__OM uint32_t DMAs_CLR; /*!< (@ 0x50001004) DMA 通道清除寄存器 */
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__IM uint32_t DMAs_STA; /*!< (@ 0x50001008) DMA 通道清除寄存器 */
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__IOM uint32_t DMAs_INT_RAW; /*!< (@ 0x5000100C) DMA 中断原始状态寄存器 */
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__IOM uint32_t DMAs_INT_EN0; /*!< (@ 0x50001010) DMA 中断使能寄存器 0 */
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__IM uint32_t RESERVED0[2];
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__IOM uint32_t DMAs_INT0; /*!< (@ 0x5000101C) DMA 中断状态寄存器 0 */
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__IM uint32_t RESERVED1[2];
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__OM uint32_t DMAs_INT_CLR; /*!< (@ 0x50001028) DMA 中断清除寄存器 */
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__IOM uint32_t DMAs_INTV_UNIT; /*!< (@ 0x5000102C) DMA 定时单位寄存器 */
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__IM uint32_t RESERVED2[4];
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__IOM uint32_t DMAs_CH0_SAR; /*!< (@ 0x50001040) 发送通道 0 源起始地址 */
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__IOM uint32_t DMAs_CH0_DAR; /*!< (@ 0x50001044) 发送通道 0 目的起始地址 */
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__IOM uint32_t DMAs_CH0_CTL0; /*!< (@ 0x50001048) 发送通道 0 控制寄存器 0 */
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__IOM uint32_t DMAs_CH0_CTL1; /*!< (@ 0x5000104C) 发送通道 0 控制寄存器 1*/
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__IM uint32_t DMAs_CH0_CA; /*!< (@ 0x50001050) 发送通道 0 当前源地址寄存器 */
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__IM uint32_t RESERVED3[3];
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__IOM uint32_t DMAs_CH1_SAR; /*!< (@ 0x50001060) 发送通道 1 源起始地址 */
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__IOM uint32_t DMAs_CH1_DAR; /*!< (@ 0x50001064) 发送通道 1 目的起始地址 */
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__IOM uint32_t DMAs_CH1_CTL0; /*!< (@ 0x50001068) 发送通道 1 控制寄存器 0 */
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__IOM uint32_t DMAs_CH1_CTL1; /*!< (@ 0x5000106C) 发送通道 1 控制寄存器 1*/
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__IM uint32_t DMAs_CH1_CA; /*!< (@ 0x50001070) 发送通道 1 当前源地址寄存器 */
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__IM uint32_t RESERVED4[3];
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__IOM uint32_t DMAs_CH2_SAR; /*!< (@ 0x50001080) 发送通道 2 源起始地址 */
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__IOM uint32_t DMAs_CH2_DAR; /*!< (@ 0x50001084) 发送通道 2 目的起始地址 */
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__IOM uint32_t DMAs_CH2_CTL0; /*!< (@ 0x50001088) 发送通道 2 控制寄存器 0 */
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__IOM uint32_t DMAs_CH2_CTL1; /*!< (@ 0x5000108C) 发送通道 2 控制寄存器 1*/
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__IM uint32_t DMAs_CH2_CA; /*!< (@ 0x50001090) 发送通道 2 当前源地址寄存器 */
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__IM uint32_t RESERVED5[3];
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__IOM uint32_t DMAs_CH3_SAR; /*!< (@ 0x500010A0) 发送通道 3 源起始地址 */
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__IOM uint32_t DMAs_CH3_DAR; /*!< (@ 0x500010A4) 发送通道 3 目的起始地址 */
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__IOM uint32_t DMAs_CH3_CTL0; /*!< (@ 0x500010A8) 发送通道 3 控制寄存器 0 */
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__IOM uint32_t DMAs_CH3_CTL1; /*!< (@ 0x500010AC) 发送通道 3 控制寄存器 1*/
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__IM uint32_t DMAs_CH3_CA; /*!< (@ 0x500010B0) 发送通道 3 当前源地址寄存器 */
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__IM uint32_t RESERVED7[35]; //(@ 0x500010B4) -->/(@ 0x5000113C)
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__IOM uint32_t DMAs_CH8_SAR; /*!< (@ 0x50001140) 接收通道 8 源起始地址 */
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__IOM uint32_t DMAs_CH8_DAR; /*!< (@ 0x50001144) 接收通道 8 目的起始地址 */
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__IOM uint32_t DMAs_CH8_CTL0; /*!< (@ 0x50001148) 接收通道 8 控制寄存器 0 */
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__IOM uint32_t DMAs_CH8_CTL1; /*!< (@ 0x5000114C) 接收通道 8 控制寄存器 1*/
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__IM uint32_t DMAs_CH8_CA; /*!< (@ 0x50001150) 接收通道 8 当前源地址寄存器 */
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__IM uint32_t RESERVED8[3];
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__IOM uint32_t DMAs_CH9_SAR; /*!< (@ 0x50001160) 接收通道 9 源起始地址 */
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__IOM uint32_t DMAs_CH9_DAR; /*!< (@ 0x50001164) 接收通道 9 目的起始地址 */
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__IOM uint32_t DMAs_CH9_CTL0; /*!< (@ 0x50001168) 接收通道 9 控制寄存器 0 */
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__IOM uint32_t DMAs_CH9_CTL1; /*!< (@ 0x5000116C) 接收通道 9 控制寄存器 1*/
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__IM uint32_t DMAs_CH9_CA; /*!< (@ 0x50001170) 接收通道 9 当前源地址寄存器 */
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__IM uint32_t RESERVED9[3];
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__IOM uint32_t DMAs_CH10_SAR; /*!< (@ 0x50001180) 接收通道 10 源起始地址 */
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__IOM uint32_t DMAs_CH10_DAR; /*!< (@ 0x50001184) 接收通道 10 目的起始地址 */
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__IOM uint32_t DMAs_CH10_CTL0; /*!< (@ 0x50001188) 接收通道 10 控制寄存器 0 */
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__IOM uint32_t DMAs_CH10_CTL1; /*!< (@ 0x5000118C) 接收通道 10 控制寄存器 1*/
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__IM uint32_t DMAs_CH10_CA; /*!< (@ 0x50001190) 接收通道 10 当前源地址寄存器 */
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__IM uint32_t RESERVED10[3];
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__IOM uint32_t DMAs_CH11_SAR; /*!< (@ 0x500011A0) 接收通道 11 源起始地址 */
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__IOM uint32_t DMAs_CH11_DAR; /*!< (@ 0x500011A4) 接收通道 11 目的起始地址 */
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__IOM uint32_t DMAs_CH11_CTL0; /*!< (@ 0x500011A8) 接收通道 11 控制寄存器 0 */
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__IOM uint32_t DMAs_CH11_CTL1; /*!< (@ 0x500011AC) 接收通道 11 控制寄存器 1*/
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__IM uint32_t DMAs_CH11_CA; /*!< (@ 0x500011B0) 接收通道 11 当前源地址寄存器 */
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__IM uint32_t RESERVED11[3];
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__IOM uint32_t DMAs_CH12_SAR; /*!< (@ 0x500011C0) 接收通道 12 源起始地址 */
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__IOM uint32_t DMAs_CH12_DAR; /*!< (@ 0x500011C4) 接收通道 12 目的起始地址 */
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__IOM uint32_t DMAs_CH12_CTL0; /*!< (@ 0x500011C8) 接收通道 12 控制寄存器 0 */
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__IOM uint32_t DMAs_CH12_CTL1; /*!< (@ 0x500011CC) 接收通道 12 控制寄存器 1*/
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__IM uint32_t DMAs_CH12_CA; /*!< (@ 0x500011D0) 接收通道 12 当前源地址寄存器 */
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__IM uint32_t RESERVED12[27]; //(@ 0x500011D4) -->/(@ 0x5000123C)
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__IOM uint32_t DMAs_CH0_WD; /*!< (@ 0x50001240) 发送通道 0 缺省写入数据 */
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__IOM uint32_t DMAs_CH1_WD; /*!< (@ 0x50001244) 发送通道 0 缺省写入数据 */
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__IOM uint32_t DMAs_CH2_WD; /*!< (@ 0x50001248) 发送通道 0 缺省写入数据 */
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__IOM uint32_t DMAs_CH3_WD; /*!< (@ 0x5000124C) 发送通道 0 缺省写入数据 */
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__IM uint32_t RESERVED14[107];//(@ 0x50001250) -->/(@ 0x500013F8)
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__IOM uint32_t DMAs_LP_CTL; /*!< (@ 0x500013FC) DMA 低功耗控制寄存器 */
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}DMA_TypeDef; /*!< Size = 1024 (0x400) */
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/* =========================================================================================================================== */
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/* ================ CPR ================ */
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/* =========================================================================================================================== */
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typedef struct { /*!< (@ 0x40000000) CPR PD 域寄存器地址映射 Structure */
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__IOM uint32_t SLP_SRC_MASK; /*!< (@ 0x40000000) 睡眠源屏蔽寄存器 */
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__IM uint32_t RESERVED[3];
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__IOM uint32_t SLP_CNT_LIMIT; /*!< (@ 0x40000010) 睡眠进入阈值寄存器 */
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__IOM uint32_t SLP_ST; /*!< (@ 0x40000014) 睡眠启动寄存器 */
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__IOM uint32_t SLP_FSM_STATE; /*!< (@ 0x40000018) 睡眠状态机状态寄存器 */
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__IM uint32_t RESERVED01[1];
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__IOM uint32_t M0_FCLK_CTL; /*!< (@ 0x40000020) M0 fclk 时钟控制寄存器 */
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__IOM uint32_t CTL_PCLK_GRCTL; /*!< (@ 0x00000024) CTL_PCLK 时钟控制寄存器 GR */
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__IOM uint32_t SIM_CLK_GRCTL; /*!< (@ 0x00000028) SIM_CLK时钟GR控制寄存器 */
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__IOM uint32_t SIM_CLK_CTLL; /*!< (@ 0x0000002C) SIM_CLK 时钟控制寄存器 */
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__IOM uint32_t UART0_CLK_GRCTL; /*!< (@ 0x00000030) UART0 CLK GR */
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__IOM uint32_t UART0_CLK_CTL; /*!< (@ 0x00000034) UART0 CLK CTL */
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__IOM uint32_t UART1_CLK_GRCTL; /*!< (@ 0x00000038) UART1 CLK GR */
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__IOM uint32_t UART1_CLK_CTL; /*!< (@ 0x0000003C) UART1 CLK CTL */
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__IOM uint32_t BT_CLK_CTL; /*!< (@ 0x00000040) BT_CLK 时钟控制寄存器 */
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__IM uint32_t RESERVED02;
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__IOM uint32_t BT_MODEM_CTL; /*!< (@ 0x00000048) BT_MODEM_CLK时钟控制寄存器 */
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__IOM uint32_t QDEC_CLK_CTL; /*!< (@ 0x0000004C) QDEC 时钟控制寄存器 */
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__IOM uint32_t SSI0_MCLK_CTL; /*!< (@ 0x00000050) SSI0_MCLK CTL */
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__IOM uint32_t SSI1_MCLK_CTL; /*!< (@ 0x00000054) SSI1_MCLK CTL */
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__IOM uint32_t TIMER0_CLK_CTL; /*!< (@ 0x00000058) TIMER0 CLK CTL */
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__IOM uint32_t TIMER1_CLK_CTL; /*!< (@ 0x0000005C) TIMER1 CLK CTL */
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__IOM uint32_t TIMER2_CLK_CTL; /*!< (@ 0x00000060) TIMER2 CLK CTL */
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__IOM uint32_t TIMER3_CLK_CTL; /*!< (@ 0x00000064) TIMER2 CLK CTL */
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__IOM uint32_t PWM_CLK_CTL; /*!< (@ 0x00000068) PWM CLK CTL */
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__IOM uint32_t AHBCLKEN_GRCTL; /*!< (@ 0x0000006C) AHBCLKEN_GRCTL */
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__IOM uint32_t CTLAPBCLKEN_GRCTL; /*!< (@ 0x00000070) CTLAPBCLKEN_GRCTL */
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__IOM uint32_t OTHERCLKEN_GRCTL; /*!< (@ 0x00000074) OTHERCLKEN_GRCTL */
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__IOM uint32_t I2C_CLK_CTL; /*!< (@ 0x00000078) I2C_CLK_CTL */
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__IM uint32_t RESERVED03[9];
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__IOM uint32_t INT; /*!< (@ 0x000000A0) M0 的 CPR 中断状态寄存器 */
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__IOM uint32_t INT_EN; /*!< (@ 0x000000A4) M0 的 CPR 中断状态寄存器 */
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__IOM uint32_t INT_RAW; /*!< (@ 0x000000A8) M0 的 CPR 中断状态寄存器 */
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__IM uint32_t RESERVED04[5];
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__IOM uint32_t GPIO_FUN_SELx[8]; /*!< (@ 0x000000C0) gpio_fun_sel0..7 */
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__IM uint32_t RESERVED05[8];
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__IOM uint32_t RSTCTL_CTLAPB_SW; /*!< (@ 0x00000100) CTLAPB 模块软复位寄存器 */
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__IOM uint32_t RSTCTL_SUBRST_SW; /*!< (@ 0x00000104) SUB 模块软复位寄存器 */
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__IOM uint32_t RSTCTL_M0RST_SW; /*!< (@ 0x00000108) M0 相关软复位寄存器 */
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__IOM uint32_t RSTCTL_M0RST_MASK; /*!< (@ 0x0000010C) M0 复位屏蔽寄存器 */
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__IOM uint32_t RSTCTL_LOCKUP_STATE; /*!< (@ 0x00000110) M0 死锁状态指示寄存器 */
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__IOM uint32_t RSTCTL_WDTRST_MASK; /*!< (@ 0x00000114) WDT 复位屏蔽寄存 */
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__IOM uint32_t LP_CTL; /*!< (@ 0x00000118) 低功耗控制寄存器 */
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__IM uint32_t RESERVED06[1];
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__IOM uint32_t CTL_SHRAM_ICM_PRIORITY; /*!< (@ 0x00000120) SHRAM 的 ICM 优先级配置寄存器 */
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__IOM uint32_t CTL_CTLAPB_ICM_PRIORITY; /*!< (@ 0x00000124) CTL_APB 桥的 ICM优先级配置寄存器 */
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__IOM uint32_t CTL_MUXCTL1_2[2]; /*!< (@ 0x00000128) MUXPIN 控制寄存器1 2 */
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__IOM uint32_t RF_REG3; /*!< (@ 0x00000130) CRP 通用寄存器3 */
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__IOM uint32_t RF_REG4; /*!< (@ 0x00000134) CRP 通用寄存器4 */
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__IM uint32_t RESERVED07[1];
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__IOM uint32_t REMAP_CTRL; /*!< (@ 0x0000013C) REMAP 控制寄存器 */
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__IOM uint32_t CTL_BOOTCTL; /*!< (@ 0x00000140) BOOTCTL 指示寄存器 */
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__IOM uint32_t CTL_M0_STCALIB; /*!< (@ 0x00000144) M0 配置寄存器 */
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__IOM uint32_t CTL_M0_IRQLATENCY; /*!< (@ 0x00000148) M0 IRQ 延迟寄存器 */
|
|
__IM uint32_t RESERVED08[5];
|
|
|
|
// SSI 控制寄存器
|
|
__IOM uint32_t SSI_CTRL; /*!< (@ 0x00000160) SSI 控制寄存器 */
|
|
__IM uint32_t RESERVED09[3];
|
|
|
|
__IOM uint32_t TESTCTRL0; /*!< (@ 0x00000170) 测试控制寄存器 0 */
|
|
__IOM uint32_t TESTCTRL1; /*!< (@ 0x00000174) 测试控制寄存器 1 */
|
|
__IOM uint32_t TESTCTRL2; /*!< (@ 0x00000178) 测试控制寄存器 2 */
|
|
__IOM uint32_t TESTCTRL3; /*!< (@ 0x0000017C) 测试控制寄存器 3 */
|
|
|
|
__IOM uint32_t TESTCTRL4; /*!< (@ 0x00000180) 测试控制寄存器 4 */
|
|
__IOM uint32_t TESTCTRL5; /*!< (@ 0x00000184) 测试控制寄存器 5 */
|
|
__IOM uint32_t TESTCTRL6; /*!< (@ 0x00000188) 测试控制寄存器 6 */
|
|
__IOM uint32_t TESTCTRL7; /*!< (@ 0x0000018C) 测试控制寄存器 7 */
|
|
|
|
__IOM uint32_t TESTCTRL8; /*!< (@ 0x00000190) 测试控制寄存器 8 */
|
|
__IOM uint32_t TESTCTRL9; /*!< (@ 0x00000194) 测试控制寄存器 9 */
|
|
__IM uint32_t RESERVED10[1];
|
|
__IOM uint32_t CTL_MUXCTL3[1]; /*!< (@ 0x0000019C) MUXPIN 控制寄存器 3 */
|
|
|
|
__IOM uint32_t RF_REG5; /*!< (@ 0x000001A0) 管脚上下拉配置寄存 3 */
|
|
__IM uint32_t RESERVED11[3];
|
|
|
|
__IOM uint32_t RF_REG0; /*!< (@ 0x000001b0) CRP 通用寄存器 */
|
|
__IOM uint32_t RF_REG1; /*!< (@ 0x000001b4) USB、2.4G、ADUDIO_ADC控制寄存器 */
|
|
__IOM uint32_t RF_REG2; /*!< (@ 0x000001b8) ADUDIO_ADC控制寄存器 2 */
|
|
__IOM uint32_t OPA_CTRL_REG; /*!< (@ 0x000001bc) OPA 控制寄存器 */
|
|
|
|
__IM uint32_t RESERVED13[36]; //0x000001c0 - 0x0000024C
|
|
|
|
__IOM uint32_t UART2_CLK_GRCTL; /*!< (@ 0x00000250) UART2 CLK GR */
|
|
__IOM uint32_t UART2_CLK_CTL; /*!< (@ 0x00000254) UART2 CLK CTL */
|
|
__IOM uint32_t I2S_CLK_CTL; /*!< (@ 0x00000258) I2S CLK CTL */
|
|
__IOM uint32_t CAN_CLK_CTL; /*!< (@ 0x0000025C) CAN CLK CTL */
|
|
__IOM uint32_t CMP_CTL; /*!< (@ 0x00000260) CMP CTL */
|
|
__IOM uint32_t CMP_INT; /*!< (@ 0x00000264) CMP INT */
|
|
__IOM uint32_t CMP_INT_RAW; /*!< (@ 0x00000268) CMP INT RAW */
|
|
__IOM uint32_t CMP_INT_EN; /*!< (@ 0x0000026C) CMP INT EN */
|
|
__IOM uint32_t FMC_CTL; /*!< (@ 0x00000270) FMC_CTL */
|
|
__IOM uint32_t OTP_CTL; /*!< (@ 0x00000274) CMP EM */
|
|
}CPR_CTL_TypeDef;
|
|
|
|
typedef struct { /*!< (@ 0x40002400) CPR AO Structure */
|
|
__IM uint32_t RESERVED00;
|
|
__IOM uint32_t SLP_CTL; /*!< (@ 0x00000004) 睡眠控制寄存器 */
|
|
__IOM uint32_t SLPCTL_INT_MASK; /*!< (@ 0x00000008) 睡眠唤醒 M0 中断屏蔽寄存器 */
|
|
__IOM uint32_t SLP_PD_MASK; /*!< (@ 0x0000000C) 睡眠断电屏蔽寄存器 */
|
|
|
|
__IOM uint32_t MCLK_DIV_CLK_CTL; /*!< (@ 0x00000010) MCLK_DIV_CLK(32K)分频控制寄存器 */
|
|
__IOM uint32_t RFPMU_SPI_CTL; /*!< (@ 0x00000014) SPI 控制寄存器 */
|
|
__IM uint32_t RESERVED01;
|
|
__IOM uint32_t SYS_TIME; /*!< (@ 0x0000001C) SPI 控制寄存器 */
|
|
|
|
__IOM uint32_t BBLDO_ADJ; /*!< (@ 0x00000020) */
|
|
__IM uint32_t RESERVED02[3]; /*!< (@ 0x00000024) */
|
|
|
|
__IOM uint32_t RF_AON_REG; /*!< (@ 0x00000030) */
|
|
__IOM uint32_t PE_CTRLx[2]; /*!< (@ 0x00000034) CPR AO GPIO PE Ctrl1..2 */
|
|
__IOM uint32_t PU_CTRLx[1]; /*!< (@ 0x0000003C) CPR AO GPIO PU Ctrl1 */
|
|
|
|
__IOM uint32_t AON_VDD_SWITCH_EN; /*!< (@ 0x00000040) */
|
|
__IOM uint32_t AON_VDD_ISO_EN; /*!< (@ 0x00000044) */
|
|
|
|
__IOM uint32_t LPOLDO_ADJ; /*!< (@ 0x00000048) */
|
|
__IM uint32_t RESERVED05[1]; /*!< (@ 0x0000004C) */
|
|
|
|
|
|
__IOM uint32_t AON_CORERFLDO_EN; /*!< (@ 0x00000050) */
|
|
__IOM uint32_t DCDC_CTRL[2]; /*!< (@ 0x00000054) CPR AO DCDC CTRL */
|
|
__IOM uint32_t RESERVED04[1];/*!< (@ 0x0000005C) */
|
|
|
|
|
|
__IM uint32_t RESERVED06[7]; /*!< (@ 0x00000060) */
|
|
__IOM uint32_t AOCLKEN_GRCTL; /*!< (@ 0x0000007C) AO 域时钟使能寄存器 */
|
|
|
|
__IM uint32_t RESERVED07[51];
|
|
__IOM uint32_t CTL_CLK32K; /*!< (@ 0x0000014C) 32K 时钟配置寄存器 */
|
|
|
|
__IM uint32_t RESERVED08[1];
|
|
__IOM uint32_t ALWAYS_ON_REG0; /*!< (@ 0x00000154) AO 通用器 0 */
|
|
__IOM uint32_t ALWAYS_ON_REG1; /*!< (@ 0x00000158) AO 通用器 1 */
|
|
__IOM uint32_t AO_CTRL; /*!< (@ 0x0000015C) AO 控制寄存器 */
|
|
|
|
__IOM uint32_t ALWAYS_ON_REG2; /*!< (@ 0x00000160) AO 通用器 2 */
|
|
__IM uint32_t RESERVED09[2];
|
|
__IOM uint32_t ALWAYS_ON_REG3; /*!< (@ 0x0000016C) AO 通用器 3 */
|
|
|
|
}CPR_AO_CTL_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ TIMER0 ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Timer/Counter 0 (TIMER0)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40003000) TIMER0 Structure */
|
|
__IOM uint32_t TLC; /*!< (@ 0x00000000) Load count value into register */
|
|
__IOM uint32_t TCV; /*!< (@ 0x00000004) current count value register */
|
|
__IOM uint32_t TCR; /*!< (@ 0x00000008) control register */
|
|
__IOM uint32_t TIC; /*!< (@ 0x0000000C) interrupt clear register */
|
|
__IOM uint32_t TIS; /*!< (@ 0x00000010) Interrupt Status Register */
|
|
|
|
}TIMER_TypeDef;
|
|
|
|
|
|
typedef struct { /*!< (@ 0x40003000) TIMER0 Structure */
|
|
|
|
__IOM uint32_t GLOBAL_TIS; /*!< (@ 0x000000A0) Global Interrupt Status Register */
|
|
__IOM uint32_t GLOBAL_TIC; /*!< (@ 0x000000A4) Global interrupt clear register */
|
|
__IOM uint32_t GLOBAL_RTIS; /*!< (@ 0x000000A8) Global Raw Interrupt Status register */
|
|
|
|
}TIMER_GLOBAL_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ RTC0 ================ */
|
|
/* =========================================================================================================================== */
|
|
/**
|
|
* @brief Real time counter 0 (RTC0)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */
|
|
__IM uint32_t CCVR; /*!< (@ 0x00000000) current count value register */
|
|
__IOM uint32_t CLR; /*!< (@ 0x00000004) Counter initial value setting register */
|
|
__IOM uint32_t CMR_ONE; /*!< (@ 0x00000008) Timing Match Register 1 */
|
|
__IOM uint32_t CMR_TWO; /*!< (@ 0x0000000C) Timing Match Register 2 */
|
|
__IOM uint32_t CMR_THREE; /*!< (@ 0x00000010) Timing Match Register 3 */
|
|
__IOM uint32_t ICR; /*!< (@ 0x00000014) Interrupt Control Register */
|
|
__IOM uint32_t ISR_EOI; /*!< (@ 0x00000018) The interrupt status register and the interrupt clear register share one */
|
|
__IM uint32_t WVR; /*!< (@ 0x0000001C) Current Week Counter Value Register */
|
|
__IOM uint32_t WLR; /*!< (@ 0x00000020) Week counter initial value setting register */
|
|
__IOM uint32_t RAW_LIMIT; /*!< (@ 0x00000024) Counting frequency setting register */
|
|
__IOM uint32_t SECOND_LIMIT; /*!< (@ 0x00000028) Second count upper limit control register */
|
|
__IOM uint32_t MINUTE_LIMIT; /*!< (@ 0x0000002C) Minute count upper limit control register */
|
|
__IOM uint32_t HOUR_LIMIT; /*!< (@ 0x00000030) hour count upper limit control register */
|
|
__IM uint32_t ISR_RAW; /*!< (@ 0x00000034) interrupt raw status register */
|
|
__IM uint32_t RVR; /*!< (@ 0x00000038) Current second count value register */
|
|
__IOM uint32_t RESERVED0;
|
|
__IOM uint32_t AO_TIMER_CTL; /*!< (@ 0x00000040) 16-bit Counter Control Register */
|
|
__IOM uint32_t AO_GPIO_MODE; /*!< (@ 0x00000044) GPIO Mode Configuration Register */
|
|
__IOM uint32_t AO_GPIO_CTL; /*!< (@ 0x00000048) GPIO Control Register */
|
|
__IOM uint32_t ALL_INTR_AO; /*!< (@ 0x0000004C) AO Interrupt Register */
|
|
__IM uint32_t FREQ_32K_TIMER_VAL; /*!< (@ 0x00000050) FREQ_TIMER value register */
|
|
__IOM uint32_t RTC_CALI_CONFIG; /*!< (@ 0x00000054) */
|
|
__IOM uint32_t RTC_CALI_RESULT; /*!< (@ 0x00000058) */
|
|
__IOM uint32_t PWRKEY_CTRL0; /*!< (@ 0x0000005C) */
|
|
__IOM uint32_t PWRKEY_CTRL1; /*!< (@ 0x00000060) */
|
|
__IOM uint32_t PWRKEY_CTRL2; /*!< (@ 0x00000064) */
|
|
__IOM uint32_t PWRKEY_SOFT_CTRL0; /*!< (@ 0x00000068) */
|
|
__IOM uint32_t PWRKEY_SOFT_CTRL1; /*!< (@ 0x0000006C) */
|
|
__IOM uint32_t RCCAL_EN; /*!< (@ 0x00000070) */
|
|
__IOM uint32_t RCCAL_LFCFG; /*!< (@ 0x00000074) */
|
|
__IOM uint32_t RCCAL_HFCFG; /*!< (@ 0x00000078) */
|
|
__IOM uint32_t RCCAL_LIM1; /*!< (@ 0x0000007C) */
|
|
__IOM uint32_t RCCAL_LIM2; /*!< (@ 0x00000080) */
|
|
__IOM uint32_t RCCAL_ADJ_CFG; /*!< (@ 0x00000084) */
|
|
__IOM uint32_t RCCAL_ADJ_STEP; /*!< (@ 0x00000088) */
|
|
__IOM uint32_t RCCAL_HFCNT_VAL; /*!< (@ 0x0000008C) */
|
|
__IOM uint32_t RCCAL_ADJ_VAL; /*!< (@ 0x00000090) */
|
|
__IOM uint32_t RCCAL_STATUS; /*!< (@ 0x00000094) */
|
|
__IOM uint32_t RCCAL_INTEN; /*!< (@ 0x00000098) */
|
|
__IOM uint32_t RCCAL_INTSTA; /*!< (@ 0x0000009C) */
|
|
__IOM uint32_t RCCAL_INTRAW; /*!< (@ 0x000000A0) */
|
|
|
|
}RTC_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Device Specific Peripheral Address Map ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/**
|
|
* @brief GPIO Port 1 (P0)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40001000) P0 Structure */
|
|
__IOM uint32_t PORT_DR[2]; /*!< (@ 0x40001000) GPIO_PORT_DRx */
|
|
__IM uint32_t RESERVED[6];
|
|
__IOM uint32_t PORT_DDR[2]; /*!< (@ 0x40001020) GPIO_PORT_DATA DRx */
|
|
__IM uint32_t RESERVED1[6];
|
|
__IOM uint32_t EXT_PORT[2]; /*!< (@ 0x40001040) Read GPIO port */
|
|
__IM uint32_t RESERVED2[46];
|
|
__IOM uint32_t INTR_CTRL[8]; /*!< (@ 0x40001100) Intr ctr GPIO port */
|
|
__IM uint32_t RESERVED3[24];
|
|
__IOM uint32_t DEBOUNCE[2]; /*!< (@ 0x40001180) Set individual bits in GPIO port */
|
|
__IM uint32_t RESERVED4[6];
|
|
__IM uint32_t INTR_RAW[1]; /*!< (@ 0x400011A0) Intr RAW */
|
|
__IM uint32_t RESERVED5[3];
|
|
__IOM uint32_t INTR_CLR[2]; /*!< (@ 0x400011B0) Intr Clear */
|
|
__IM uint32_t RESERVED6[18];
|
|
__IOM uint32_t INTR_MASK_C0[2]; /*!< (@ 0x40001200) DIR set register */
|
|
__IM uint32_t RESERVED7[6];
|
|
__IM uint32_t INTR_STATUS_C0[1]; /*!< (@ 0x40001220) 中断状态寄存器 */
|
|
|
|
}GPIO_TypeDef;//XC_GPIO_Type; /*!< Size = 548 (0x224) */
|
|
|
|
|
|
typedef union
|
|
{
|
|
__IM uint32_t RBR;
|
|
__OM uint32_t THR;
|
|
__IOM uint32_t DLL;
|
|
} REG0;
|
|
|
|
typedef union
|
|
{
|
|
__IOM uint32_t IER;
|
|
__IOM uint32_t DLH;
|
|
} REG1;
|
|
|
|
typedef union
|
|
{
|
|
__IM uint32_t IIR;
|
|
__OM uint32_t FCR;
|
|
} REG2;
|
|
|
|
typedef struct { /*!< (@ 0x40011000) UART1 Structure */
|
|
REG0 RBR_THR_DLL;
|
|
REG1 IER_DLH;
|
|
REG2 IIR_FCR;
|
|
__IOM uint32_t TCR;
|
|
__IOM uint32_t MCR;
|
|
__IM uint32_t TSR;
|
|
__IM uint32_t MSR;
|
|
__IM uint32_t RESERVED4[24];
|
|
__IM uint32_t USR;
|
|
|
|
}UART_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ SPIM0_NS ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS)
|
|
*/
|
|
|
|
|
|
|
|
typedef struct { /*!< (@ 0x40014000) SPIM1_NS Structure */
|
|
__IOM uint32_t CTRL0; /*!< (@ 0x00000000) */
|
|
__IOM uint32_t CTRL1; /*!< (@ 0x00000004) */
|
|
__IOM uint32_t EN; /*!< (@ 0x00000008) */
|
|
__IM uint32_t RESERVED0;
|
|
__IOM uint32_t SE; /*!< (@ 0x00000010) */
|
|
__IOM uint32_t BAUD; /*!< (@ 0x00000014) */
|
|
__IOM uint32_t TXFTL; /*!< (@ 0x00000018) */
|
|
__IOM uint32_t RXFTL; /*!< (@ 0x0000001C) */
|
|
__IM uint32_t TXFL; /*!< (@ 0x00000020) */
|
|
__IM uint32_t RXFL; /*!< (@ 0x00000024) */
|
|
__IM uint32_t STS; /*!< (@ 0x00000028) */
|
|
__IOM uint32_t IE; /*!< (@ 0x0000002C) */
|
|
__IM uint32_t IS; /*!< (@ 0x00000030) */
|
|
__IM uint32_t RIS; /*!< (@ 0x00000034) */
|
|
__IM uint32_t TXOIC; /*!< (@ 0x00000038) */
|
|
__IM uint32_t RXOIC; /*!< (@ 0x0000003C) */
|
|
__IM uint32_t RXUIC; /*!< (@ 0x00000040) */
|
|
__IM uint32_t RESERVED1;
|
|
__IM uint32_t IC; /*!< (@ 0x00000048) */
|
|
__IOM uint32_t DMAS; /*!< (@ 0x0000004C) */
|
|
__IOM uint32_t DMATDL; /*!< (@ 0x00000050) */
|
|
__IOM uint32_t DMARDL; /*!< (@ 0x00000054) */
|
|
__IM uint32_t RESERVED2[2];
|
|
__IOM uint32_t DATA; /*!< (@ 0x00000060) */
|
|
__IM uint32_t RESERVED3[36];
|
|
__IOM uint32_t SSI2_SPI_CTRLR0; /*!< (@ 0x000000F4) */
|
|
} SPI_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ I2C ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/**
|
|
* @brief I2C compatible Two-Wire Interface 0 (I2C0)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40006000) I2C Structure */
|
|
__IOM uint32_t I2C_CON; /*!< (@ 0x00000000) */
|
|
__IOM uint32_t I2C_TAR; /*!< (@ 0x00000004) */
|
|
__IOM uint32_t I2C_SAR; /*!< (@ 0x00000008) */
|
|
__IM uint32_t RESERVED0;
|
|
|
|
__IOM uint32_t I2C_DATA_CMD; /*!< (@ 0x00000010) */
|
|
__IOM uint32_t I2C_SS_SCL_HCNT; /*!< (@ 0x00000014) */
|
|
__IOM uint32_t I2C_SS_SCL_LCNT; /*!< (@ 0x00000018) */
|
|
__IOM uint32_t I2C_FS_SCL_HCNT; /*!< (@ 0x0000001c) */
|
|
|
|
__IOM uint32_t I2C_FS_SCL_LCNT; /*!< (@ 0x00000020) */
|
|
__IM uint32_t RESERVED1[2];
|
|
__IOM uint32_t I2C_INTR_STAT; /*!< (@ 0x0000002C) */
|
|
|
|
__IOM uint32_t I2C_INTR_EN; /*!< (@ 0x00000030) */
|
|
__IOM uint32_t I2C_RAW_INTR_STAT; /*!< (@ 0x00000034) */
|
|
__IOM uint32_t I2C_RX_TL; /*!< (@ 0x00000038) */
|
|
__IOM uint32_t I2C_TX_TL; /*!< (@ 0x0000003c) */
|
|
|
|
__IM uint32_t I2C_CLR_INTR; /*!< (@ 0x00000040) */
|
|
__IM uint32_t I2C_CLR_RX_UNDER; /*!< (@ 0x00000044) */
|
|
__IM uint32_t I2C_CLR_RX_OVER; /*!< (@ 0x00000048) */
|
|
__IM uint32_t I2C_CLR_TX_OVER; /*!< (@ 0x0000004c) */
|
|
|
|
__IM uint32_t I2C_CLR_RD_REQ; /*!< (@ 0x00000050) */
|
|
__IM uint32_t I2C_CLR_TX_ABRT; /*!< (@ 0x00000054) */
|
|
__IM uint32_t I2C_CLR_RX_DONE; /*!< (@ 0x00000058) */
|
|
__IM uint32_t I2C_CLR_ACTIVITY; /*!< (@ 0x0000005c) */
|
|
|
|
__IM uint32_t I2C_CLR_STOP_DET; /*!< (@ 0x00000060) */
|
|
__IM uint32_t I2C_CLR_START_DET; /*!< (@ 0x00000064) */
|
|
__IM uint32_t I2C_CLR_GEN_CALL; /*!< (@ 0x00000068) */
|
|
__IOM uint32_t I2C_ENABLE; /*!< (@ 0x0000006c) */
|
|
|
|
__IM uint32_t I2C_STATUS; /*!< (@ 0x00000070) */
|
|
__IM uint32_t I2C_TXFLR; /*!< (@ 0x00000074) */
|
|
__IM uint32_t I2C_RXFLR; /*!< (@ 0x00000078) */
|
|
__IOM uint32_t I2C_SDA_HOLD; /*!< (@ 0x0000007c) */
|
|
|
|
__IOM uint32_t I2C_TX_ABRT_SOURCE; /*!< (@ 0x00000080) */
|
|
|
|
} I2C_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ WDT ================ */
|
|
/* =========================================================================================================================== */
|
|
/**
|
|
* @brief Watchdog Timer (WDT)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40010000) WDT Structure */
|
|
__IOM uint32_t CR; /*!< (@ 0x00000000) control register */
|
|
__IOM uint32_t TORR; /*!< (@ 0x00000004) Timeout Range Register */
|
|
__IOM uint32_t CCVR; /*!< (@ 0x00000008) current count value register */
|
|
__OM uint32_t CRR; /*!< (@ 0x0000000c) Counter restart register */
|
|
__IM uint32_t STAT; /*!< (@ 0x00000010) Interrupt Status Register */
|
|
__IM uint32_t ICR; /*!< (@ 0x00000014) interrupt clear register */
|
|
|
|
} WDT_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ SAADC ================ */
|
|
/* =========================================================================================================================== */
|
|
/**
|
|
* @brief Successive approximation register (SAR) analog-to-digital converter (SAADC)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40018000) SAADC Structure */
|
|
__IOM uint32_t MAIN_CTL; /*!< (@ 0x00000000) */
|
|
__IOM uint32_t CHAN_CTL; /*!< (@ 0x00000004) */
|
|
__IOM uint32_t FIFO_CTL; /*!< (@ 0x00000008) */
|
|
__IOM uint32_t TIMER0; /*!< (@ 0x0000000C) */
|
|
__IOM uint32_t TIMER1 ; /*!< (@ 0x00000010) */
|
|
__IOM uint32_t INT ; /*!< (@ 0x00000014) */
|
|
__IM uint32_t INT_RAW; /*!< (@ 0x00000018) */
|
|
__IOM uint32_t INT_EN; /*!< (@ 0x0000001C) */
|
|
__IM uint32_t FIFO; /*!< (@ 0x00000020) */
|
|
__IOM uint32_t RF_CTL; /*!< (@ 0x00000024) */
|
|
|
|
} ADC_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ PWM ================ */
|
|
/* =========================================================================================================================== */
|
|
/**
|
|
* @brief Pulse width modulation unit (PWM)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40017000UL) PWM Structure */
|
|
__IOM uint32_t EN; /*!< (@ 0x00000000) PWM EN Register */
|
|
__IOM uint32_t UP; /*!< (@ 0x00000004) PWM UPDATE Register */
|
|
__IOM uint32_t RST; /*!< (@ 0x00000008) PWM RST Register */
|
|
__IOM uint32_t PERIOD; /*!< (@ 0x0000000c) PWM Period Register */
|
|
__IOM uint32_t OCPY; /*!< (@ 0x00000010) PWM OCPY Register */
|
|
__IM uint32_t RESERVED[2];
|
|
__IOM uint32_t PWMCOMPEN; /*!< (@ 0x0000001C) PWM COMP EN Register */
|
|
__IOM uint32_t PWMCOMPTIME; /*!< (@ 0x00000020) PWM OCPYCOMP TIME Register */
|
|
} PWM_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CAN ================ */
|
|
/* =========================================================================================================================== */
|
|
typedef struct {
|
|
|
|
__IOM uint32_t Frame_Information;
|
|
__IOM uint32_t ID[2];
|
|
__IOM uint32_t DATA[8];
|
|
|
|
} CAN_SFF_TypeDef;
|
|
|
|
typedef struct {
|
|
|
|
__IOM uint32_t Frame_Information;
|
|
__IOM uint32_t ID[4];
|
|
__IOM uint32_t DATA[8];
|
|
|
|
} CAN_EFF_TypeDef;
|
|
|
|
typedef struct {
|
|
|
|
__IOM uint32_t ACR[4];
|
|
__IOM uint32_t AMR[4];
|
|
|
|
} CAN_Filter_TypeDef;
|
|
|
|
typedef union
|
|
{
|
|
CAN_SFF_TypeDef CAN_SFF;
|
|
CAN_EFF_TypeDef CAN_EFF;
|
|
CAN_Filter_TypeDef CAN_Filter;
|
|
} CAN_FRAME_TypeDef;
|
|
|
|
typedef struct {
|
|
|
|
__IOM uint32_t MOD; /*!< (@ 0x00000000) */
|
|
__IOM uint32_t CMR; /*!< (@ 0x00000004) */
|
|
__IOM uint32_t SR; /*!< (@ 0x00000008) */
|
|
__IOM uint32_t IR; /*!< (@ 0x0000000C) */
|
|
__IOM uint32_t IER; /*!< (@ 0x00000010) */
|
|
__IM uint32_t RESERVED0[1]; /*!< (@ 0x00000014) */
|
|
__IOM uint32_t BTR0; /*!< (@ 0x00000018) */
|
|
__IOM uint32_t BTR1; /*!< (@ 0x0000001C) */
|
|
__IOM uint32_t OCR ; /*!< (@ 0x00000020) */
|
|
__IM uint32_t RESERVED1[2]; /*!< (@ 0x00000024) */
|
|
__IOM uint32_t ALC; /*!< (@ 0x0000002C) */
|
|
__IOM uint32_t ECC; /*!< (@ 0x00000030) */
|
|
__IOM uint32_t EWLR; /*!< (@ 0x00000034) */
|
|
__IOM uint32_t RXERR; /*!< (@ 0x00000038) */
|
|
__IOM uint32_t TXERR; /*!< (@ 0x0000003C) */
|
|
CAN_FRAME_TypeDef CAN_FRAME; /*!< (@ 0x00000040) */
|
|
__IOM uint32_t RMC; /*!< (@ 0x00000074) */
|
|
__IOM uint32_t RBSA; /*!< (@ 0x00000078) */
|
|
__IOM uint32_t CDR; /*!< (@ 0x0000007C) */
|
|
|
|
} CAN_TypeDef;
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Sub 1G ================ */
|
|
/* =========================================================================================================================== */
|
|
/* Sub 1G Module Register Typedef */
|
|
typedef struct
|
|
{
|
|
__IOM uint32_t SUBG_CLK_CTL; /*!< (@ 0x00000000) */
|
|
__IOM uint32_t SUBG_RST_CTL; /*!< (@ 0x00000004) */
|
|
__IOM uint32_t SUBG_WORK_CTL; /*!< (@ 0x00000008) */
|
|
__IM uint32_t SUBG_STA; /*!< (@ 0x0000000C) */
|
|
__IOM uint32_t SUBG_GLB_CTL; /*!< (@ 0x00000010) */
|
|
__IM uint32_t RESERVED0[59]; /*!< (@ 0x00000014)
|
|
-->/(@ 0x000000FC) */
|
|
__IOM uint32_t MAC_PREAM; /*!< (@ 0x00000100) */
|
|
__IOM uint32_t MAC_SYNC1; /*!< (@ 0x00000104) */
|
|
__IOM uint32_t MAC_SYNC2; /*!< (@ 0x00000108) */
|
|
__IOM uint32_t MAC_SYNC3; /*!< (@ 0x0000010C) */
|
|
__IOM uint32_t MAC_SYNC4; /*!< (@ 0x00000110) */
|
|
__IOM uint32_t MAC_PKT; /*!< (@ 0x00000114) */
|
|
__IOM uint32_t MAC_NID1; /*!< (@ 0x00000118) */
|
|
__IOM uint32_t MAC_NID2; /*!< (@ 0x0000011C) */
|
|
__IOM uint32_t MAC_CRC; /*!< (@ 0x00000120) */
|
|
__IOM uint32_t MAC_CDC; /*!< (@ 0x00000124) */
|
|
__IOM uint32_t MAC_TX_CTL; /*!< (@ 0x00000128) */
|
|
__IOM uint32_t MAC_RX_CTL; /*!< (@ 0x0000012C) */
|
|
__IM uint32_t MAC_RX_ERR_STA; /*!< (@ 0x00000130) */
|
|
__IOM uint32_t MAC_FIFO_CTL; /*!< (@ 0x00000134) */
|
|
__OM uint32_t MAC_FIFO_CLR; /*!< (@ 0x00000138) */
|
|
__IM uint32_t MAC_FIFO_STA; /*!< (@ 0x0000013C) */
|
|
__IOM uint32_t MAC_FIFO_DATA_TX; /*!< (@ 0x00000140) */
|
|
__IM uint32_t MAC_FIFO_DATA_RX; /*!< (@ 0x00000144) */
|
|
__IOM uint32_t MAC_ASK; /*!< (@ 0x00000148) */
|
|
__IOM uint32_t MDM_RX_ASK; /*!< (@ 0x0000014C) */
|
|
__IOM uint32_t MAC_ASK_1527; /*!< (@ 0x00000150) */
|
|
__IM uint32_t RESERVED1[43]; /*!< (@ 0x00000154)
|
|
-->/(@ 0x000001FC) */
|
|
__IOM uint32_t MDM_TRX_CTL; /*!< (@ 0x00000200) */
|
|
__IOM uint32_t MDM_SPREAD; /*!< (@ 0x00000204) */
|
|
__IOM uint32_t MDM_AGC_CTL1; /*!< (@ 0x00000208) */
|
|
__IOM uint32_t MDM_AGC_CTL2; /*!< (@ 0x0000020C) */
|
|
__IOM uint32_t MDM_AGC_CTL3; /*!< (@ 0x00000210) */
|
|
__IOM uint32_t MDM_AGC_CTL4; /*!< (@ 0x00000214) */
|
|
__IOM uint32_t MDM_AGC_CTL5; /*!< (@ 0x00000218) */
|
|
__IM uint32_t RESERVED2; /*!< (@ 0x0000021C) */
|
|
__IOM uint32_t MDM_AGC_CTL6; /*!< (@ 0x00000220) */
|
|
__IOM uint32_t MDM_AGC_CTL7; /*!< (@ 0x00000224) */
|
|
__IOM uint32_t MDM_AGC_CTL8; /*!< (@ 0x00000228) */
|
|
__IOM uint32_t MDM_AGC_CTL9; /*!< (@ 0x0000022C) */
|
|
__IOM uint32_t MDM_AGC_CTL10; /*!< (@ 0x00000230) */
|
|
__IM uint32_t MDM_AGC_RSSI1; /*!< (@ 0x00000234) */
|
|
__IM uint32_t MDM_AGC_RSSI2; /*!< (@ 0x00000238) */
|
|
__IM uint32_t MDM_AGC_RSSI3; /*!< (@ 0x0000023C) */
|
|
__IM uint32_t MDM_AGC_RSSI4; /*!< (@ 0x00000240) */
|
|
__IM uint32_t RESERVED3; /*!< (@ 0x00000244) */
|
|
__IM uint32_t MDM_DEBUG; /*!< (@ 0x00000248) */
|
|
__IM uint32_t RESERVED4[45]; /*!< (@ 0x0000024C)
|
|
-->/(@ 0x000002FC) */
|
|
__IOM uint32_t RF_RAMP_CTL1; /*!< (@ 0x00000300) */
|
|
__IOM uint32_t RF_RAMP_CTL2; /*!< (@ 0x00000304) */
|
|
__IOM uint32_t RF_RAMP_CTL3; /*!< (@ 0x00000308) */
|
|
__IOM uint32_t RF_RAMP_CTL4; /*!< (@ 0x0000030C) */
|
|
__IOM uint32_t RF_CH; /*!< (@ 0x00000310) */
|
|
__IOM uint32_t RF_TIMING; /*!< (@ 0x00000314) */
|
|
__IM uint32_t RESERVED5[58]; /*!< (@ 0x00000318)
|
|
-->/(@ 0x000003FC) */
|
|
__IOM uint32_t SUBG_DEBUG_PROB; /*!< (@ 0x00000400) */
|
|
__IOM uint32_t SUBG_DEBUG_PROB2; /*!< (@ 0x00000404) */
|
|
__IM uint32_t RESERVED6[702]; /*!< (@ 0x00000408)
|
|
-->/(@ 0x00000EFC) */
|
|
__IM uint32_t SUB1G_INT_STS; /*!< (@ 0x00000F00) */
|
|
__IOM uint32_t SUB1G_INT_EN; /*!< (@ 0x00000F04) */
|
|
__IM uint32_t SUB1G_INT_MSK; /*!< (@ 0x00000F08) */
|
|
__IOM uint32_t SUB1G_INT_CLR; /*!< (@ 0x00000F0C) */
|
|
} SUB_1G_TypeDef;
|
|
|
|
/* Lora RF Register Typedef */
|
|
typedef struct
|
|
{
|
|
__IOM uint16_t ana0_reg_l; /* RF analog0 Reg (0x000) */
|
|
__IM uint16_t ana0_reg_h;
|
|
__IOM uint16_t ana1_reg_l; /* RF analog1 Reg (0x004) */
|
|
__IM uint16_t ana1_reg_h;
|
|
__IOM uint16_t ana2_reg_l; /* RF analog2 Reg (0x008) */
|
|
__IM uint16_t ana2_reg_h;
|
|
__IOM uint16_t ana3_reg_l; /* RF analog3 Reg (0x00C) */
|
|
__IM uint16_t ana3_reg_h;
|
|
__IOM uint16_t ana4_reg_l; /* RF analog4 Reg (0x010) */
|
|
__IM uint16_t ana4_reg_h;
|
|
__IOM uint16_t ana5_reg_l; /* RF analog5 Reg (0x014) */
|
|
__IM uint16_t ana5_reg_h;
|
|
__IOM uint16_t ana6_reg_l; /* RF analog6 Reg (0x018) */
|
|
__IM uint16_t ana6_reg_h;
|
|
__IOM uint16_t ana7_reg_l; /* RF analog7 Reg (0x01C) */
|
|
__IM uint16_t ana7_reg_h;
|
|
__IOM uint16_t ana8_reg_l; /* RF analog8 Reg (0x020) */
|
|
__IM uint16_t ana8_reg_h;
|
|
__IOM uint16_t ana9_reg_l; /* RF analog9 Reg (0x024) */
|
|
__IM uint16_t ana9_reg_h;
|
|
__IOM uint16_t ana10_reg_l; /* RF analog10 Reg (0x028) */
|
|
__IM uint16_t ana10_reg_h;
|
|
__IOM uint16_t ana11_reg_l; /* RF analog11 Reg (0x02C) */
|
|
__IM uint16_t ana11_reg_h;
|
|
__IOM uint16_t ana12_reg_l; /* RF analog12 Reg (0x030) */
|
|
__IM uint16_t ana12_reg_h;
|
|
__IOM uint16_t ana13_reg_l; /* RF analog13 Reg (0x034) */
|
|
__IM uint16_t ana13_reg_h;
|
|
__IOM uint16_t ana14_reg_l; /* RF analog14 Reg (0x038) */
|
|
__IM uint16_t ana14_reg_h;
|
|
__IOM uint16_t ana15_reg_l; /* RF analog15 Reg (0x03C) */
|
|
__IM uint16_t ana15_reg_h;
|
|
__IOM uint16_t ana16_reg_l; /* RF analog16 Reg (0x040) */
|
|
__IM uint16_t ana16_reg_h;
|
|
__IOM uint16_t ana17_reg_l; /* RF analog17 Reg (0x044) */
|
|
__IM uint16_t ana17_reg_h;
|
|
__IOM uint16_t ana18_reg_l; /* RF analog18 Reg (0x048) */
|
|
__IM uint16_t ana18_reg_h;
|
|
__IOM uint16_t ana19_reg_l; /* RF analog19 Reg (0x04C) */
|
|
__IM uint16_t ana19_reg_h;
|
|
__IOM uint16_t ana20_reg_l; /* RF analog20 Reg (0x050) */
|
|
__IM uint16_t ana20_reg_h;
|
|
__IOM uint16_t ana21_reg_l; /* RF analog21 Reg (0x054) */
|
|
__IM uint16_t ana21_reg_h;
|
|
__IOM uint16_t ana22_reg_l; /* RF analog22 Reg (0x058) */
|
|
__IM uint16_t ana22_reg_h;
|
|
__IOM uint16_t ana23_reg_l; /* RF analog23 Reg (0x05C) */
|
|
__IM uint16_t ana23_reg_h;
|
|
__IOM uint16_t ana24_reg_l; /* RF analog24 Reg (0x060) */
|
|
__IM uint16_t ana24_reg_h;
|
|
__IOM uint16_t ana25_reg_l; /* RF analog25 Reg (0x064) */
|
|
__IM uint16_t ana25_reg_h;
|
|
__IOM uint16_t ana26_reg_l; /* RF analog26 Reg (0x068) */
|
|
__IM uint16_t ana26_reg_h;
|
|
__IOM uint16_t ana27_reg_l; /* RF analog27 Reg (0x06C) */
|
|
__IM uint16_t ana27_reg_h;
|
|
__IOM uint16_t ana28_reg_l; /* RF analog28 Reg (0x070) */
|
|
__IM uint16_t ana28_reg_h;
|
|
__IOM uint16_t ana29_reg_l; /* RF analog29 Reg (0x074) */
|
|
__IM uint16_t ana29_reg_h;
|
|
__IOM uint16_t ana30_reg_l; /* RF analog30 Reg (0x078) */
|
|
__IM uint16_t ana30_reg_h;
|
|
__IOM uint16_t ana31_reg_l; /* RF analog31 Reg (0x07C) */
|
|
__IM uint16_t ana31_reg_h;
|
|
__IOM uint16_t rccal_reg_l; /* RF rccal Reg (0x080) */
|
|
__IM uint16_t rccal_reg_h;
|
|
__IOM uint16_t rccal_rslt_l; /* RF rccal result Reg (0x084) */
|
|
__IM uint16_t rccal_rslt_h;
|
|
__IOM uint16_t rf_rx_lna_map0_l; /* Lora rx lna map Reg0 (0x088) */
|
|
__IM uint16_t rf_rx_lna_map0_h;
|
|
__IOM uint16_t rf_rx_lna_map1_l; /* Lora rx lna map Reg1 (0x08C) */
|
|
__IM uint16_t rf_rx_lna_map1_h;
|
|
__IOM uint16_t rf_rx_vga_map0_l; /* Lora rx vga map Reg0 (0x090) */
|
|
__IM uint16_t rf_rx_vga_map0_h;
|
|
__IOM uint16_t rf_rx_vga_map1_l; /* Lora rx vga map Reg1 (0x094) */
|
|
__IM uint16_t rf_rx_vga_map1_h;
|
|
__IOM uint16_t rf_rx_vga_map2_l; /* Lora rx vga map Reg2 (0x098) */
|
|
__IM uint16_t rf_rx_vga_map2_h;
|
|
__IOM uint16_t rf_rx_vga_map3_l; /* Lora rx vga map Reg3 (0x09C) */
|
|
__IM uint16_t rf_rx_vga_map3_h;
|
|
__IOM uint16_t rf_rx_vga_map4_l; /* Lora rx vga map Reg4 (0x0A0) */
|
|
__IM uint16_t rf_rx_vga_map4_h;
|
|
__IOM uint16_t rf_rx_vga_map5_l; /* Lora rx vga map Reg5 (0x0A4) */
|
|
__IM uint16_t rf_rx_vga_map5_h;
|
|
__IOM uint16_t rf_rx_vga_map6_l; /* Lora rx vga map Reg6 (0x0A8) */
|
|
__IM uint16_t rf_rx_vga_map6_h;
|
|
__IOM uint16_t rf_rx_vga_map7_l; /* Lora rx vga map Reg7 (0x0AC) */
|
|
__IM uint16_t rf_rx_vga_map7_h;
|
|
__IOM uint16_t bt_rf_pm_reg_l; /* BT rf pm Reg (0x0B0) */
|
|
__IM uint16_t bt_rf_pm_reg_h;
|
|
__IOM uint16_t bt_rf_chan_reg_l; /* BT rf chan Reg (0x0B4) */
|
|
__IM uint16_t bt_rf_chan_reg_h;
|
|
__IOM uint16_t bt_rf_ctrl_sel_l; /* BT rf control select Reg (0x0B8) */
|
|
__IM uint16_t bt_rf_ctrl_sel_h;
|
|
__IOM uint16_t rf_ctrl_lora_l; /* Lora rf control select Reg (0x0BC) */
|
|
__IM uint16_t rf_ctrl_lora_h;
|
|
__IOM uint16_t rf_chan_lora0_l; /* RF channel config Reg0 (0x0C0) */
|
|
__IM uint16_t rf_chan_lora0_h;
|
|
__IOM uint16_t rf_chan_lora1_l; /* RF channel config Reg0 (0x0C4) */
|
|
__IM uint16_t rf_chan_lora1_h;
|
|
} LORA_RF_TypeDef;
|
|
|
|
/** @addtogroup Device_Peripheral_peripheralAddr
|
|
* @{
|
|
*/
|
|
#define XC_CPR_BASE 0x40000000UL
|
|
#define XC_CPR_AO_BASE 0x40002400UL
|
|
|
|
#define XC_GPIO0_BASE 0x40001000UL
|
|
|
|
#define XC_WDT0_BASE 0x40004000UL
|
|
#define XC_I2C0_BASE 0x40006000UL
|
|
|
|
#define XC_UART0_BASE 0x40010000UL
|
|
#define XC_UART1_BASE 0x40011000UL
|
|
|
|
#define XC_CAN0_BASE 0x40011C00UL
|
|
|
|
#define XC_SPI0_BASE 0x40013000UL
|
|
#define XC_SPI1_BASE 0x40014000UL
|
|
|
|
#define XC_PWM0_BASE 0x40017000UL
|
|
#define XC_PWM1_BASE 0x40017400UL
|
|
#define XC_PWM2_BASE 0x40017800UL
|
|
|
|
#define XC_ADC_BASE 0x40018000UL
|
|
|
|
#define XC_TIMER0_BASE 0x40003000UL
|
|
#define XC_TIMER1_BASE 0x40003014UL
|
|
#define XC_TIMER2_BASE 0x40003028UL
|
|
#define XC_TIMER3_BASE 0x4000303CUL
|
|
|
|
#define XC_AOTIMER0_BASE 0x40002800UL
|
|
#define XC_AOTIMER1_BASE 0x40002814UL
|
|
|
|
#define XC_RTC0_BASE 0x40002000UL
|
|
|
|
#define XC_DMA_BASE 0x50001000UL
|
|
|
|
#define XC_LORA_BB_BASE 0x50003000UL
|
|
#define XC_LORA_RF_BASE 0x4002F000UL
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Peripheral declaration ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/** @addtogroup Device_Peripheral_declaration
|
|
* @{
|
|
*/
|
|
#define XC_CPR ((CPR_CTL_TypeDef*) XC_CPR_BASE)
|
|
#define XC_CPR_AO ((CPR_AO_CTL_TypeDef*) XC_CPR_AO_BASE)
|
|
#define XC_DMA0 ((DMA_TypeDef*) XC_DMA_BASE)
|
|
|
|
#define XC_GPIO0 ((GPIO_TypeDef*) XC_GPIO0_BASE)
|
|
|
|
#define XC_UART0 ((UART_TypeDef*) XC_UART0_BASE)
|
|
#define XC_UART1 ((UART_TypeDef*) XC_UART1_BASE)
|
|
|
|
#define XC_CAN0 ((CAN_TypeDef*) XC_CAN0_BASE)
|
|
|
|
#define XC_SPI0 ((SPI_TypeDef*) XC_SPI0_BASE)
|
|
#define XC_SPI1 ((SPI_TypeDef*) XC_SPI1_BASE)
|
|
|
|
#define XC_I2C0 ((I2C_TypeDef*) XC_I2C0_BASE)
|
|
|
|
#define XC_WDT0 ((WDT_TypeDef*) XC_WDT0_BASE)
|
|
|
|
#define XC_ADC0 ((ADC_TypeDef*) XC_ADC_BASE)
|
|
|
|
#define XC_PWM0 ((PWM_TypeDef*) XC_PWM0_BASE)
|
|
#define XC_PWM1 ((PWM_TypeDef*) XC_PWM1_BASE)
|
|
#define XC_PWM2 ((PWM_TypeDef*) XC_PWM2_BASE)
|
|
|
|
#define XC_TIMER0 ((TIMER_TypeDef*) XC_TIMER0_BASE)
|
|
#define XC_TIMER1 ((TIMER_TypeDef*) XC_TIMER1_BASE)
|
|
#define XC_TIMER2 ((TIMER_TypeDef*) XC_TIMER2_BASE)
|
|
#define XC_TIMER3 ((TIMER_TypeDef*) XC_TIMER3_BASE)
|
|
|
|
#define XC_AOTIMER0 ((TIMER_TypeDef*) XC_AOTIMER0_BASE)
|
|
#define XC_AOTIMER1 ((TIMER_TypeDef*) XC_AOTIMER1_BASE)
|
|
|
|
#define XC_RTC0 ((RTC_TypeDef*) XC_RTC0_BASE)
|
|
|
|
#define XC_SUB_1G ((SUB_1G_TypeDef*) XC_LORA_BB_BASE)
|
|
#define XC_SUB1G_RF ((LORA_RF_TypeDef*) XC_LORA_RF_BASE)
|
|
|
|
/** @addtogroup Driver_Bitfields_Included
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
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#endif /* __XC20XX_H__ */
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