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b140b47ceb2f65a5fbf9520e08e848466d69aa35
hpw421/component/xc6xx_drivers/Drivers/xc_driver/xc_drv_clock.c
T
xushaoxiang 945a5a5b0b hpw422移植新的sdk
2026-07-03 18:08:25 +08:00

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/*!
* \file xc_drv_clock.c
*
* \brief Target xinchip clock driver implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc_drv_clock.h"
#include "xc_romaddr_define.h"
#if XC_CHECK(XC_CLOCK_ENABLED)
/*------------------------------------------------------------------------------------
Local Variables
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
CLOCK_InitCfg_t clock_cb;
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
#ifdef XC62XX_RFANA2_BIT13_SET
void rf_ana2_bit13_enable(void)
{
cpr_bt_clk_ctl__bt_clk_en__setf(ENABLE);
rf_ana2_bit13_setf(0x01);
}
void rf_ana2_bit13_disable(void)
{
cpr_bt_clk_ctl__bt_clk_en__setf(ENABLE);
rf_ana2_bit13_setf(0x00);
}
#endif // XC62XX_RFANA2_BIT13_SET
/**
****************************************************************************************
* @brief xc_clock_bbpll_common_cfg
* @details Common Settings for frequency doubling
* @param[in] void
* @param[in] void
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_bbpll_common_cfg(void)
{
#if defined(LORA_CLOCK_PLL_CONFIG)
xc_lora_clock_bbpll_common_cfg();
#else
cpr_bt_clk_ctl__bt_clk_en__setf(ENABLE);
cpr_ctlapbclken_grctl__bt_pclk_en__setf(ENABLE);
bt_rf_pm_reg__bt_en_pm__setf(ENABLE);
cprao_aon_coreldo_en_set(ENABLE);
#ifdef XC62XX_RFANA2_BIT13_SET
rf_ana2_bit13_enable();
#endif // XC62XX_RFANA2_BIT13_SET
#endif // LORA_CLOCK_PLL_CONFIG
}
/**
****************************************************************************************
* @brief xc_clock_bbpll_freq_cfg
* @details Initializes the frequency doubling clock
* @param[in] hfclk_src :Source clock
* @param[in] loopdiv :clock multiplier factor
* @param[in] clk_div :Frequency division coefficient
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_bbpll_freq_cfg(CLOCK_HFCLK_Src_Typedef hfclk_src, uint16_t loopdiv,
uint8_t clk_div)
{
#if !defined(NO_SUPPORT_HFCLK_RC_16M)
if (CLOCK_HFCLK_SRC_RC == hfclk_src)
{
cprao_aon_rf_aonreg__da_ldo_en__setf(0);
/* delay than 10us */
delay_us(AON_RF_AONREG_DA_LDO_EN_DELAY);
cprao_aon_rf_aonreg__da_ldo_en__setf(1);
rf_ana27__bbpll_16m_sel__setf(ENABLE);
}
else
#endif
{
rf_ana27__bbpll_16m_sel__setf(DISABLE);
}
/* 2 div, must be opened */
rf_ana27__bbpll_core_96m_en__setf(ENABLE);
#if !defined(XC62XX_CLOCK_CONFIG)
#else
rf_ana25_bit11_12_setf(3);/* Enhance the driving capability of bbpll */
#endif
rf_ana26__bbpll_loopdiv__setf(loopdiv);
rf_ana26__clk_bbpll_en__setf(ENABLE);
rf_ana26__clk_bbpll_rstn__setf(ENABLE);
rf_ana26__bbpll_en__setf(ENABLE);
rf_ana26__bbpll_core_64m_en__setf(ENABLE);
switch (loopdiv)
{
case LOOPDIV_BBPLL_RES_LEVEL_0:
rf_ana26__bbpll_res__setf(0);
break;
case LOOPDIV_BBPLL_RES_LEVEL_1:
rf_ana26__bbpll_res__setf(1);
break;
case LOOPDIV_BBPLL_RES_LEVEL_2:
rf_ana26__bbpll_res__setf(2);
break;
case LOOPDIV_BBPLL_RES_LEVEL_3:
rf_ana26__bbpll_res__setf(3);
break;
case LOOPDIV_BBPLL_RES_LEVEL_4:
rf_ana26__bbpll_res__setf(4);
break;
case LOOPDIV_BBPLL_RES_LEVEL_5:
rf_ana26__bbpll_res__setf(4);
break;
case LOOPDIV_BBPLL_RES_LEVEL_6:
rf_ana26__bbpll_res__setf(5);
break;
default:
rf_ana26__bbpll_res__setf(0);
break;
}
cpr_rf_reg4__bbpll_clk_div__setf(clk_div);
cpr_rf_reg4__bbpll_clk_en__setf(ENABLE);
}
#if !defined(NO_SUPPORT_HFCLK_RC_16M)
/**
****************************************************************************************
* @brief xc_clock_set_rc16m
* @details The clock is set to RC16M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_rc16m(CLOCK_InitCfg_t *cb)
{
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_RC16M);
cb->hfclk_in = CLOCK_HFCLK_IN_16M;
cb->systick_unit = SYSTICK_UNIT_IN_16M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_rc16m_bbpll_32m
* @details RC16M clock overclocked to 32M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_rc16m_bbpll_32m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x08, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_32M;
cb->systick_unit = SYSTICK_UNIT_IN_32M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_rc16m_bbpll_48m
* @details RC16M clock overclocked to 48M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_rc16m_bbpll_48m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x0C, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_48M;
cb->systick_unit = SYSTICK_UNIT_IN_48M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_rc16m_bbpll_64m
* @details RC16M clock overclocked to 64M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_rc16m_bbpll_64m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x08, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL);
cb->hfclk_in = CLOCK_HFCLK_IN_64M;
cb->systick_unit = SYSTICK_UNIT_IN_64M;
delay_us(BBPLL_LOCK_DELAY);
}
#if !defined(NO_SUPPORT_HFCLK_BBPLL_96M)
/**
****************************************************************************************
* @brief xc_clock_set_rc16m_bbpll_96m
* @details RC16M clock overclocked to 96M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_rc16m_bbpll_96m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x0C, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL);
cb->hfclk_in = CLOCK_HFCLK_IN_96M;
cb->systick_unit = SYSTICK_UNIT_IN_96M;
delay_us(BBPLL_LOCK_DELAY);
}
#endif
#endif
#if defined(HFCLK_SRC_XTAL_IS_32M)
/**
****************************************************************************************
* @brief xc_clock_set_osc32m_bbpll_16m
* @details osc32M Clock overclocked to 64M and hflck is 16M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc32m_bbpll_16m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x04, 0x03);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_16M;
cb->systick_unit = SYSTICK_UNIT_IN_16M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_osc32m_div_16m
* @details osc32M Clock divided into 16M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc32m_div_16m(CLOCK_InitCfg_t *cb)
{
//M0_FCLK
cpr_m0_fclk_ctl__m0_fclk_div_p__setf(0x1);
cpr_m0_fclk_ctl__m0_fclk_direct_sw__setf(0x1);
//CTL_PCLK
cpr_ctl_pclk_grctl__ctl_pclk_gr__setf(0x8);
cpr_ctl_pclk_grctl__ctl_pclk_gr_upd__setf(0x1);
cprao_aon_bbldo_adj_set(0x3c);
/* The value needs to be configured to 7,
otherwise the current drop will be slower during sleep
and the clock accuracy of the rc32k will be affected.
*/
cprao_aon_lpoldo_adj_set(0x7);
cb->hfclk_in = CLOCK_HFCLK_IN_16M;
cb->systick_unit = SYSTICK_UNIT_IN_16M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_osc32m_bbpll_24m
* @details osc32M Clock overclocked to 96M and hflck is 24M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc32m_bbpll_24m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x06, 0x03);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_24M;
cb->systick_unit = SYSTICK_UNIT_IN_24M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_osc32m
* @details The clock is set to osc32M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc32m(CLOCK_InitCfg_t *cb)
{
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_OSC32M);
#ifdef XC62XX_RFANA2_BIT13_SET
rf_ana2_bit13_disable();
#endif // XC62XX_RFANA2_BIT13_SET
cb->hfclk_in = CLOCK_HFCLK_IN_32M;
cb->systick_unit = SYSTICK_UNIT_IN_32M;
delay_us(BBPLL_LOCK_DELAY);
}
#if (CONFIG_HFCLK_IS_OSC32M_PLL_32M)
/**
****************************************************************************************
* @brief xc_clock_set_osc32m_bbpll_32m
* @details osc32M Clock overclocked to 64M and hflck is 32M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc32m_bbpll_32m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x04, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_32M;
cb->systick_unit = SYSTICK_UNIT_IN_32M;
delay_us(BBPLL_LOCK_DELAY);
}
#endif
/**
****************************************************************************************
* @brief xc_clock_set_osc32m_bbpll_48m
* @details osc32M Clock overclocked to 48M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc32m_bbpll_48m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x06, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_48M;
cb->systick_unit = SYSTICK_UNIT_IN_48M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_osc32m_bbpll_64m
* @details osc32M Clock overclocked to 64M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc32m_bbpll_64m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x04, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL);
cb->hfclk_in = CLOCK_HFCLK_IN_64M;
cb->systick_unit = SYSTICK_UNIT_IN_64M;
delay_us(BBPLL_LOCK_DELAY);
}
#if !defined(NO_SUPPORT_HFCLK_BBPLL_96M)
/**
****************************************************************************************
* @brief xc_clock_set_osc32m_bbpll_96m
* @details osc32M Clock overclocked to 96M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc32m_bbpll_96m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x06, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL);
cb->hfclk_in = CLOCK_HFCLK_IN_96M;
cb->systick_unit = SYSTICK_UNIT_IN_96M;
delay_us(BBPLL_LOCK_DELAY);
}
#endif
#elif defined(HFCLK_SRC_XTAL_IS_24M)
/**
****************************************************************************************
* @brief xc_clock_set_osc24m_bbpll_16m
* @details osc24M Clock overclocked to 48M and hflck is 16M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc24m_bbpll_16m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x4, 0x02);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_16M;
cb->systick_unit = SYSTICK_UNIT_IN_16M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_osc24m
* @details The clock is set to osc24M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc24m(CLOCK_InitCfg_t *cb)
{
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_OSC32M);
cb->hfclk_in = CLOCK_HFCLK_IN_24M;
cb->systick_unit = SYSTICK_UNIT_IN_24M;
delay_us(BBPLL_LOCK_DELAY);
}
#if (CONFIG_HFCLK_IS_OSC24M_PLL_24M)
/**
****************************************************************************************
* @brief xc_clock_set_osc24m_bbpll_24m
* @details osc24M Clock overclocked to 48M and hflck is 24M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc24m_bbpll_24m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x04, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_24M;
cb->systick_unit = SYSTICK_UNIT_IN_24M;
delay_us(BBPLL_LOCK_DELAY);
}
#endif
/**
****************************************************************************************
* @brief xc_clock_set_osc24m_bbpll_32m
* @details osc24M Clock overclocked to 96M and hflck is 32M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc24m_bbpll_32m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x08, 0x02);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_32M;
cb->systick_unit = SYSTICK_UNIT_IN_32M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_osc24m_bbpll_48m
* @details osc24M Clock overclocked to 48M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc24m_bbpll_48m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x04, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL);
cb->hfclk_in = CLOCK_HFCLK_IN_48M;
cb->systick_unit = SYSTICK_UNIT_IN_48M;
delay_us(BBPLL_LOCK_DELAY);
}
/**
****************************************************************************************
* @brief xc_clock_set_osc24m_bbpll_64m
* @details osc24M Clock overclocked to 192M and hflck is 64M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc24m_bbpll_64m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x10, 0x02);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL_DIV);
cb->hfclk_in = CLOCK_HFCLK_IN_64M;
cb->systick_unit = SYSTICK_UNIT_IN_64M;
delay_us(BBPLL_LOCK_DELAY);
}
#if !defined(NO_SUPPORT_HFCLK_BBPLL_96M)
/**
****************************************************************************************
* @brief xc_clock_set_osc24m_bbpll_96m
* @details osc24M Clock overclocked to 96M
* @param[in] CLOCK_InitCfg_t *cb
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_set_osc24m_bbpll_96m(CLOCK_InitCfg_t *cb)
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(cb->hfclk_src, 0x08, 0x01);
cpr_rf_reg3__mclk_src_sel__setf(CLOCK_SRC_BBPLL);
cb->hfclk_in = CLOCK_HFCLK_IN_96M;
cb->systick_unit = SYSTICK_UNIT_IN_96M;
delay_us(BBPLL_LOCK_DELAY);
}
#endif
#endif
/**
****************************************************************************************
* @brief xc_hfclk_set
* @details Configure the system hfclock
* @param[in] Hfclk_InitCfg_t *hfclk_cfg
* @param[in]
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_hfclk_set(Hfclk_InitCfg_t hfclk_cfg)
{
if ((hfclk_cfg.mclk_src == CLOCK_SRC_BBPLL) || (hfclk_cfg.mclk_src == CLOCK_SRC_BBPLL_DIV))
{
xc_clock_bbpll_common_cfg();
xc_clock_bbpll_freq_cfg(hfclk_cfg.cb->hfclk_src, hfclk_cfg.bbpll_loopdiv, hfclk_cfg.bbpll_clkdiv);
}
cpr_rf_reg3__mclk_src_sel__setf(hfclk_cfg.mclk_src);
delay_us(BBPLL_LOCK_DELAY);
xc_pwr_vol_set();
}
/**
****************************************************************************************
* @brief xc_clock_hfclk_set
* @details High speed clock setting, Will modify all peripheral clock.
* @param[in] CLOCK_HFCLK_Src_Typedef hfclk_src
* @param[in] CLOCK_HFCLK_In_Typedef hfclk_in
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_hfclk_set(CLOCK_HFCLK_Src_Typedef hfclk_src,
CLOCK_HFCLK_In_Typedef hfclk_in)
{
Hfclk_InitCfg_t hfclk_param;
hfclk_param.cb = &clock_cb;
hfclk_param.cb->hfclk_src = hfclk_src;
hfclk_param.cb->hfclk_in = hfclk_in;
hfclk_param.cb->systick_unit = (Systick_Unit_Typedef)(hfclk_in / 1000000);
switch (hfclk_src) {
#if !defined(NO_SUPPORT_HFCLK_RC_16M)
case CLOCK_HFCLK_SRC_RC: {
if (CLOCK_HFCLK_IN_16M == hfclk_in) {
hfclk_param.mclk_src = CLOCK_SRC_RC16M;
} else if (CLOCK_HFCLK_IN_32M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x08;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
} else if (CLOCK_HFCLK_IN_48M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x0C;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
} else if (CLOCK_HFCLK_IN_64M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x08;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL;
}
#if !defined(NO_SUPPORT_HFCLK_BBPLL_96M)
else if (CLOCK_HFCLK_IN_96M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x0C;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL;
}
#endif
} break;
#endif
case CLOCK_HFCLK_SRC_XTAL: {
#if defined(HFCLK_SRC_XTAL_IS_32M)
if (CLOCK_HFCLK_IN_16M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x04;
hfclk_param.bbpll_clkdiv = 0x03;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
} else if (CLOCK_HFCLK_IN_24M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x06;
hfclk_param.bbpll_clkdiv = 0x03;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
}else if (CLOCK_HFCLK_IN_32M == hfclk_in) {
#if (CONFIG_HFCLK_IS_OSC32M_PLL_32M)
hfclk_param.bbpll_loopdiv = 0x04;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
#else
hfclk_param.mclk_src = CLOCK_SRC_OSC;
#endif
} else if (CLOCK_HFCLK_IN_48M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x06;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
} else if (CLOCK_HFCLK_IN_64M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x04;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL;
}
#if !defined(NO_SUPPORT_HFCLK_BBPLL_96M)
else if (CLOCK_HFCLK_IN_96M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x06;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL;
}
#endif
#elif defined(HFCLK_SRC_XTAL_IS_24M)
if (CLOCK_HFCLK_IN_16M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x04;
hfclk_param.bbpll_clkdiv = 0x02;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
} else if (CLOCK_HFCLK_IN_24M == hfclk_in) {
#if (CONFIG_HFCLK_IS_OSC24M_PLL_24M)
hfclk_param.bbpll_loopdiv = 0x04;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
#else
hfclk_param.mclk_src = CLOCK_SRC_OSC;
#endif
} else if (CLOCK_HFCLK_IN_32M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x08;
hfclk_param.bbpll_clkdiv = 0x02;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
} else if (CLOCK_HFCLK_IN_48M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x04;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL;
} else if (CLOCK_HFCLK_IN_64M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x10;
hfclk_param.bbpll_clkdiv = 0x02;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL_DIV;
}
#if !defined(NO_SUPPORT_HFCLK_BBPLL_96M)
else if (CLOCK_HFCLK_IN_96M == hfclk_in) {
hfclk_param.bbpll_loopdiv = 0x08;
hfclk_param.bbpll_clkdiv = 0x01;
hfclk_param.mclk_src = CLOCK_SRC_BBPLL;
}
#endif
#endif
} break;
}
xc_hfclk_set(hfclk_param);
}
/**
****************************************************************************************
* @brief xc_clock_lfclk_set
* @details Low speed clock setting
* @param[in] CLOCK_LFCLK_Src_Typedef lfclk_src
* @param[in] CLOCK_LFCLK_In_Typedef lfclk_in
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_lfclk_set(CLOCK_LFCLK_Src_Typedef lfclk_src,
CLOCK_LFCLK_In_Typedef lfclk_in)
{
clock_cb.lfclk_src = lfclk_src;
clock_cb.lfclk_in = lfclk_in;
#if !defined(NO_SUPPORT_LFCLK_XTAL_32768)
if (lfclk_src == CLOCK_LFCLK_SRC_XTAL)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.FunSel = GPIO_Dx;
gpio_cfg.Dir = GPIO_DIR_INPUT;
gpio_cfg.Pull = GPIO_NOPULL;
gpio_cfg.Int = NOT_INT;
gpio_cfg.Pin = 20;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = 21;
xc_gpio_init(&gpio_cfg);
cprao_aon_xtl32k_val__xtl32k_v__setf(0x01);
cprao_aon_xtl32k_val__xtl32k_en__setf(ENABLE);
cprao_aon_ctl_clk32k__osc32k_sel__setf(2);
}
else if (lfclk_src == CLOCK_LFCLK_SRC_RC)
{
}
#endif
}
/**
****************************************************************************************
* @brief xc_clock_init_cfg
* @details Configure the clock initially
* @param[in] CLOCK_InitCfg_t *clock_cfg
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_clock_init_cfg(CLOCK_InitCfg_t *clock_cfg)
{
xc_clock_hfclk_set(clock_cfg->hfclk_src, clock_cfg->hfclk_in);
xc_clock_lfclk_set(clock_cfg->lfclk_src, clock_cfg->lfclk_in);
}
/**
****************************************************************************************
* @brief xc_clock_hfclk_in_get
* @details Gets the current high speed clock ( system clock )
* @param[in]
* @param[out] void
* @retval clock_cb.hfclk_in
****************************************************************************************
*/
CLOCK_HFCLK_In_Typedef xc_clock_hfclk_in_get(void) { return clock_cb.hfclk_in; }
/**
****************************************************************************************
* @brief xc_clock_lfclk_in_get
* @details Gets the current low speed clock ( Low power clock )
* @param[in]
* @param[out] void
* @retval clock_cb.lfclk_in
****************************************************************************************
*/
CLOCK_LFCLK_In_Typedef xc_clock_lfclk_in_get(void) { return clock_cb.lfclk_in; }
/**
****************************************************************************************
* @brief xc_clock_hfclk_src_get
* @details Obtain the current high-speed source clock
* @param[in]
* @param[out] void
* @retval clock_cb.hfclk_src
****************************************************************************************
*/
CLOCK_HFCLK_Src_Typedef xc_clock_hfclk_src_get(void) { return clock_cb.hfclk_src; }
/**
****************************************************************************************
* @brief xc_clock_lfclk_src_get
* @details Obtain the current low-speed source clock
* @param[in]
* @param[out] void
* @retval clock_cb.lfclk_src
****************************************************************************************
*/
CLOCK_LFCLK_Src_Typedef xc_clock_lfclk_src_get(void) { return clock_cb.lfclk_src; }
/**
****************************************************************************************
* @brief xc_systick_unit_get
* @details Obtain the current systick unit
* @param[in]
* @param[out] void
* @retval clock_cb.lfclk_src
****************************************************************************************
*/
Systick_Unit_Typedef xc_systick_unit_get(void) { return clock_cb.systick_unit; }
#if defined(LORA_CLOCK_PLL_CONFIG)
void xc_lora_clock_bbpll_common_cfg()
{
cpr_rf_reg1__rf24g_rstn_reg__setf(DISABLE);
cpr_rf_reg1__rf24g_rstn_reg__setf(ENABLE);
// cpr_rf_reg1__rf24g_mclk_div__setf(1);
cpr_rf_reg1__rf24g_hclk_en__setf(ENABLE);
cpr_rf_reg1__rf24g_mclk_en__setf(ENABLE);
cprao_aon_coreldo_en_set(ENABLE);
}
#endif // defined(LORA_CLOCK_PLL_CONFIG)
#if !defined(NO_SUPPORT_ROM_FMC_SPI)
__RAM_CODE void fmc_status_wait_idle_rom(void)
{
typedef void (*rom_function)(void);
rom_function xc_fmc_status_wait_idle_rom = (rom_function)(XC_FMC_STATUS_WAIT_IDLE);
xc_fmc_status_wait_idle_rom();
}
__RAM_CODE void fmc_spi_write_nbyte_rom(uint8_t *txdata, uint16_t size)
{
typedef void (*rom_function)(uint8_t *rom_txdata, uint16_t rom_size);
rom_function xc_fmc_spi_write_nbyte_rom = (rom_function)(XC_FMC_SPI_WRITE_NBYTE);
xc_fmc_spi_write_nbyte_rom(txdata, size);
}
__RAM_CODE void fmc_spi_read_nbyte_rom(uint8_t *rxdata, uint16_t size)
{
typedef void (*rom_function)(uint8_t *rom_rxdata, uint16_t rom_size);
rom_function xc_fmc_spi_read_nbyte_rom = (rom_function)(XC_FMC_SPI_READ_NBYTE);
xc_fmc_spi_read_nbyte_rom(rxdata, size);
}
__RAM_CODE void fmc_spi_enable_rom(uint8_t dfs)
{
typedef void (*rom_function)(uint8_t rom_dfs);
rom_function xc_fmc_spi_enable_rom = (rom_function)(XC_FMC_SPI_ENABLE);
xc_fmc_spi_enable_rom(dfs);
}
__RAM_CODE void fmc_spi_disable_rom(void)
{
typedef void (*rom_function)(void);
rom_function xc_fmc_spi_disable_rom = (rom_function)(XC_FMC_SPI_DISABLE);
xc_fmc_spi_disable_rom();
}
__RAM_CODE void fmc_spi_init_oprt_rom(void)
{
typedef void (*rom_function)(void);
rom_function xc_fmc_spi_init_oprt_rom = (rom_function)(XC_FMC_SPI_INIT_OPRT);
xc_fmc_spi_init_oprt_rom();
}
__RAM_CODE void fmc_spi_flash_power_down_rom(void)
{
typedef void (*rom_function)(void);
rom_function xc_fmc_spi_flash_power_down_rom = (rom_function)(XC_FMC_SPI_FLASH_POWER_DOWN);
xc_fmc_spi_flash_power_down_rom();
}
__RAM_CODE void fmc_spi_flash_wake_up_rom(void)
{
typedef void (*rom_function)(void);
rom_function xc_fmc_spi_flash_wake_up_rom = (rom_function)(xc_fmc_SPI_FLASH_WAKE_UP);
xc_fmc_spi_flash_wake_up_rom();
}
__RAM_CODE void fmc_spi_flash_erase_sector_rom(uint32_t addr)
{
typedef void (*rom_function)(uint32_t rom_addr);
rom_function xc_fmc_spi_flash_erase_sector_rom = (rom_function)(XC_FMC_SPI_FLASH_ERASE_SECTOR);
xc_fmc_spi_flash_erase_sector_rom(addr);
}
__RAM_CODE void fmc_spi_flash_erase_page_rom(uint32_t addr)
{
typedef void (*rom_function)(uint32_t rom_addr);
rom_function xc_fmc_spi_flash_erase_page_rom = (rom_function)(XC_FMC_SPI_FLASH_ERASE_PAGE);
xc_fmc_spi_flash_erase_page_rom(addr);
}
#ifndef FAST_SPI
__RAM_CODE void fmc_spi_flash_write_page_rom(uint32_t addr, uint8_t *data, uint16_t size)
{
typedef void (*rom_function)(uint32_t rom_addr, uint8_t *rom_data, uint16_t rom_size);
rom_function xc_fmc_spi_flash_write_page_rom = (rom_function)(XC_FMC_SPI_FLASH_WRITE_PAGE);
xc_fmc_spi_flash_write_page_rom(addr, data, size);
}
#else
__RAM_CODE void fmc_spi_flash_write_page_rom(uint32_t addr, uint8_t *data, uint16_t size)
{
typedef void (*rom_function)(uint32_t rom_addr, uint8_t *rom_data, uint16_t rom_size);
rom_function xc_fmc_spi_flash_write_page_rom = (rom_function)(XC_FMC_FAST_SPI_FLASH_WRITE_PAGE);
xc_fmc_spi_flash_write_page_rom(addr, data, size);
}
#endif
__RAM_CODE void fmc_spi_otp_read_page_rom(uint32_t addr, uint8_t *data, uint16_t size)
{
typedef void (*rom_function)(uint32_t rom_addr, uint8_t *rom_data, uint16_t rom_size);
rom_function xc_fmc_spi_otp_read_page_rom = (rom_function)(XC_FMC_SPI_OTP_READ_PAGE);
xc_fmc_spi_otp_read_page_rom(addr, data, size);
}
__RAM_CODE void fmc_spi_flash_read_page_rom(uint32_t addr, uint8_t *data, uint16_t size)
{
typedef void (*rom_function)(uint32_t rom_addr, uint8_t *rom_data, uint16_t rom_size);
rom_function xc_fmc_spi_flash_read_page_rom = (rom_function)(XC_FMC_SPI_FLASH_READ_PAGE);
xc_fmc_spi_flash_read_page_rom(addr, data, size);
}
__RAM_CODE uint8_t fmc_spi_flash_write_rom(uint32_t addr, uint8_t *buff, uint16_t size)
{
typedef uint8_t (*rom_function)(uint32_t rom_addr, uint8_t *rom_buff, uint16_t rom_size);
rom_function xc_fmc_spi_flash_write_rom = (rom_function)(XC_FMC_SPI_FLASH_WRITE);
xc_fmc_spi_flash_write_rom(addr, buff, size);
return 0;
}
__RAM_CODE uint8_t fmc_spi_flash_read_rom(uint32_t addr, uint8_t *buff, uint16_t size)
{
typedef uint8_t (*rom_function)(uint32_t rom_addr, uint8_t *rom_buff, uint16_t rom_size);
rom_function xc_fmc_spi_flash_read_rom = (rom_function)(XC_FMC_SPI_FLASH_READ);
xc_fmc_spi_flash_read_rom(addr, buff, size);
return 0;
}
__RAM_CODE void fmc_spi_flash_ruid_rom(uint8_t *ruid)
{
typedef void (*rom_function)(uint8_t *rom_ruid);
rom_function xc_fmc_spi_flash_ruid_rom = (rom_function)(XC_FMC_SPI_FLASH_RUID);
xc_fmc_spi_flash_ruid_rom(ruid);
}
__RAM_CODE void fmc_spi_flash_rdid_rom(uint8_t *rdid)
{
typedef void (*rom_function)(uint8_t *rom_rdid);
rom_function xc_fmc_spi_flash_rdid_rom = (rom_function)(XC_FMC_SPI_FLASH_RDID);
xc_fmc_spi_flash_rdid_rom(rdid);
}
#endif // NO_SUPPORT_ROM_FMC_SPI
#if defined(XC62XX_ADC_CALI_PARA)
extern uint16_t extract32_16(uint32_t val);
bool adc_2v4_calibrate_read(uint16_t * adc_calibrate)
{
uint16_t high ;
uint16_t low;
uint32_t spi_buff[32];
GLOBAL_INT_DISABLE();
xc_fmc_spi_init_oprt();
xc_fmc_spi_flash_wake_up();
xc_fmc_spi_otp_read_page(OTP_PROGRAM_PAGE_1,(uint8_t *)spi_buff,16);
high = spi_buff[0] >> 16;
low = spi_buff[0] & 0xFFFF;
high = (high << 8) | (high >> 8);
low = (low << 8) | (low >> 8);
GLOBAL_INT_RESTORE();
if(high == ((~low)&0x0000ffff))
{
*adc_calibrate = extract32_16(spi_buff[0] << 16);
DEBUG("%s,%d\n",__func__,__LINE__);
return true;
}else
{
DEBUG("%s,%d\n",__func__,__LINE__);
return false;
}
}
void adc_channel_gpio_config(ADC_ChannelTypeDef_t Channel)
{
if (Channel >= ADC_CH_NUM)
return;
GPIO_InitCfg_t GPIO_InitCfg;
GPIO_InitCfg.Mux = GPIO_Mux0;
GPIO_InitCfg.FunSel = GPIO_Dx;
GPIO_InitCfg.Dir = GPIO_DIR_INPUT;
GPIO_InitCfg.Pull = GPIO_NOPULL;
GPIO_InitCfg.Int = NOT_INT;
switch (Channel) {
case ADC_CH0_PIN10:
GPIO_InitCfg.Pin = GPIO_10;
break;
case ADC_CH1_PIN9:
GPIO_InitCfg.Pin = GPIO_9;
break;
case ADC_CH2_PIN19:
GPIO_InitCfg.Pin = GPIO_19;
break;
case ADC_CH3_PIN18:
GPIO_InitCfg.Pin = GPIO_18;
break;
case ADC_CH4_PIN0:
GPIO_InitCfg.Pin = GPIO_0;
break;
case ADC_CH5_PIN1:
GPIO_InitCfg.Pin = GPIO_1;
break;
case ADC_CH6_PIN4:
GPIO_InitCfg.Pin = GPIO_4;
break;
case ADC_CH7_PIN5:
GPIO_InitCfg.Pin = GPIO_5;
break;
case ADC_CH8_PIN2:
GPIO_InitCfg.Pin = GPIO_2;
break;
case ADC_CH9_PIN3:
GPIO_InitCfg.Pin = GPIO_3;
break;
case ADC_CH10_PIN6:
GPIO_InitCfg.Pin = GPIO_6;
break;
case ADC_CH11_PIN7:
GPIO_InitCfg.Pin = GPIO_7;
break;
case ADC_CH13_TEMP:
cpr_opa_ctrl_reg__en_temp_sensor__setf(ENABLE);
return;
default:
return;
}
xc_gpio_init(&GPIO_InitCfg);
}
#endif // XC62XX_ADC_CALI_PARA
/**
****************************************************************************************
* @brief xc_system_param_check
* @details Check the configuration of bbpldo, bor, rf and wdt parameters.
* @param[in] void
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_system_param_check(void)
{
uint32_t hf_clk = xc_clock_hfclk_in_get();
uint8_t expected_bbldo;
uint8_t bbldo_adj = cprao_aon_bbldo_adj_get() & 0xf;
uint8_t lpoldo_adj = cprao_aon_lpoldo_adj_get() & 0xf;
uint32_t temp_ana2 = ANA2_REG;
uint32_t temp_ana17 = ANA17_REG;
uint32_t temp_ana24 = ANA24_REG;
uint8_t errors = 0;
/* rf param check */
if (((temp_ana17 >> 8) & 0xff) != 0xee) {
printf("Err:ana17[8:15] must be 0xee\n");
errors |= 0x01;
}
if (((temp_ana24 >> 3) & 0x7) != 0x5) {
printf("Err:ana24[3:5] must be 0x5\n");
errors |= 0x02;
}
#if defined(XC62XX)
if ((temp_ana2 & 0xE1E0) != 0xe0c0) {
printf("Err:ana2[5:8] must be 0x6,ana2[13:15] must be 0x7\n");
errors |= 0x01;
}
#endif
/* wdt param check */
if (cpr_lp_ctl__wdt_tclk_en__getf() == DISABLE) {
printf("Err:wdt disabled, must be enabled\n");
errors |= 0x04;
}
if (cpr_lp_ctl__wdt_pclk_sel__getf() != WDT_WORK_32K) {
printf("Err:wdt clk is not 32K, must be 32K\n");
errors |= 0x08;
}
/* bor param check */
#if (defined(BOR_VERSION_IS_V2) || defined(XC62XX))
if ((cprao_aon_bor_ctr_reg0__bor_rstn_mask__getf() != 0) ||
(cprao_aon_bor_ctr_reg0__bor_intr_mask__getf() != 1) ||
(cprao_aon_bor_ctr_reg0__en_bor__getf() != 1))
{
printf("Err:bor cfg err\n");
errors |= 0x10;
}
#else
if ((cprao_aon_bor_ctr_reg0__bor_rstn_mask__getf() != 1) ||
(cprao_aon_bor_ctr_reg0__bor_intr_mask__getf() != 0) ||
(cprao_aon_bor_ctr_reg0__en_bor__getf() != 1))
{
printf("Err:bor cfg err\n");
errors |= 0x10;
}
if (!(NVIC->ISER[0] & (1UL << (uint8_t)MPU_IRQn)))
{
printf("Err:MPU interrupt is not enabled, must be enabled\n");
errors |= 0x10;
}
#endif
/* bblpo param check */
if (hf_clk <= 32000000) {
expected_bbldo = 0xc;
} else if (hf_clk <= 64000000) {
expected_bbldo = 0xd;
} else {
expected_bbldo = 0xf;
}
if (bbldo_adj != expected_bbldo) {
printf("Err:bbldo!=0x%x\n", expected_bbldo);
errors |= 0x20;
}
/* lpoldo param check */
if (lpoldo_adj != 0x7) {
printf("Err:lpoldo must be 0x7\n");
errors |= 0x40;
}
if (errors == 0) {
printf("system param check: OK\n");
}
}
/**
****************************************************************************************
* @brief xc_system_param_check_rf24g
* @details Check the configuration of bbpldo, bor, rf and wdt parameters in the 2.4G SDK.
* @param[in] void
* @param[out] void
* @retval void
****************************************************************************************
*/
void xc_system_param_check_rf24g(void)
{
uint32_t hf_clk = xc_clock_hfclk_in_get();
uint8_t bbldo_adj = cprao_aon_bbldo_adj_get() & 0xf;
uint8_t lpoldo_adj = cprao_aon_lpoldo_adj_get() & 0xf;
uint32_t temp_ana2 = ANA2_REG;
uint32_t temp_ana17 = ANA17_REG;
uint32_t temp_ana24 = ANA24_REG;
uint8_t errors = 0;
/* rf param check */
if (((temp_ana17 >> 8) & 0xff) != 0xee) {
printf("Err:ana17[8:15] must be 0xee\n");
errors |= 0x01;
}
if (((temp_ana24 >> 3) & 0x7) != 0x5) {
printf("Err:ana24[3:5] must be 0x5\n");
errors |= 0x02;
}
#if defined(XC62XX)
if ((temp_ana2 & 0xE1E0) != 0xe0c0) {
printf("Err:ana2[5:8] must be 0x6,ana2[13:15] must be 0x7\n");
errors |= 0x01;
}
#endif
/* wdt param check */
if (cpr_lp_ctl__wdt_tclk_en__getf() == DISABLE) {
printf("Err:wdt disabled, must be enabled\n");
errors |= 0x04;
}
if (cpr_lp_ctl__wdt_pclk_sel__getf() != WDT_WORK_32K) {
printf("Err:wdt clk is not 32K, must be 32K\n");
errors |= 0x08;
}
/* bor param check */
#if (defined(BOR_VERSION_IS_V2) || defined(XC62XX))
if ((cprao_aon_bor_ctr_reg0__bor_rstn_mask__getf() != 0) ||
(cprao_aon_bor_ctr_reg0__bor_intr_mask__getf() != 1) ||
(cprao_aon_bor_ctr_reg0__en_bor__getf() != 1))
{
printf("Err:bor cfg err\n");
errors |= 0x10;
}
#else
if ((cprao_aon_bor_ctr_reg0__bor_rstn_mask__getf() != 1) ||
(cprao_aon_bor_ctr_reg0__bor_intr_mask__getf() != 0) ||
(cprao_aon_bor_ctr_reg0__en_bor__getf() != 1))
{
printf("Err:bor cfg err\n");
errors |= 0x10;
}
if (!(NVIC->ISER[0] & (1UL << (uint8_t)MPU_IRQn)))
{
printf("Err:MPU interrupt is not enabled, must be enabled\n");
errors |= 0x10;
}
#endif
/* bblpo param check */
if ((bbldo_adj != 0x0e) && (bbldo_adj != 0x0f) ) {
printf("Err:bbldo must be 0x0e or 0x0f\n");
errors |= 0x20;
}
/* lpoldo param check */
if (lpoldo_adj != 0x7) {
printf("Err:lpoldo must be 0x7\n");
errors |= 0x40;
}
if (errors == 0) {
printf("system param check: OK\n");
}
}
#endif // XC_CHECK(XC_CLOCK_ENABLED)
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