xushaoxiang
240 lines
8.6 KiB
C
240 lines
8.6 KiB
C
#ifndef _XC_DRV_CODEC_H_
|
|
#define _XC_DRV_CODEC_H_
|
|
#if 1
|
|
#include "xc6xxx.h"
|
|
|
|
#define CODEC_ADC_FIFO_LEN (3)
|
|
#define CODEC_DAC_FIFO_LEN (8)
|
|
|
|
typedef void (*codec_finish_callback)(uint8_t);
|
|
typedef struct
|
|
{
|
|
codec_finish_callback codec_adc_receive_finish_callback;
|
|
codec_finish_callback codec_dac_trans_finish_callback;
|
|
} codec_finish_callback_t;
|
|
|
|
#define ADINSEL_SINGLE_ENDED 0x01
|
|
#define ADINSEL_DIFFERENTIAL_ENDED 0x03
|
|
#define ADINSEL_FM 0x04
|
|
#define ADINSEL_MIC 0x08
|
|
|
|
#define JACK_DET_EN 0x40
|
|
#define TXFIFO_UNDERFLOW_EN 0x20
|
|
#define TXFIFO_OVERFLOW_EN 0x10
|
|
#define TXFIFO_DATA_READY_EN 0x08
|
|
#define RXFIFO_UNDERFLOW_EN 0x04
|
|
#define RXFIFO_OVERFLOW_EN 0x02
|
|
#define RXFIFO_DATA_READY_EN 0x01
|
|
|
|
#define CODEC_DMA_TX_EN 0x20000
|
|
#define CODEC_DMA_RX_EN 0x10000
|
|
|
|
|
|
#define __write_hw_reg32(reg,val) ((*reg) = (val))
|
|
#define __read_hw_reg32(reg, val) ((val) = (*reg))
|
|
|
|
#define CPR_M4_NEW_REG1 ((volatile unsigned *)(0x40000000 +0x1B4))
|
|
#define CPR_M4_NEW_REG2 ((volatile unsigned *)(0x40000000 +0x1B8))
|
|
|
|
#define CODEC_BASE 0x50004000
|
|
#define CDC_ANA_REG0 ((volatile unsigned *)(CODEC_BASE +0))
|
|
#define CDC_ANA_REG1 ((volatile unsigned *)(CODEC_BASE + 0x04))
|
|
#define CDC_ANA_REG2 ((volatile unsigned *)(CODEC_BASE + 0x08))
|
|
#define CDC_ANA_REG3 ((volatile unsigned *)(CODEC_BASE + 0x0c))
|
|
#define CDC_ANA_REG4 ((volatile unsigned *)(CODEC_BASE + 0x10))
|
|
#define CDC_ANA_REG5 ((volatile unsigned *)(CODEC_BASE + 0x14))
|
|
#define CDC_ANA_REG6 ((volatile unsigned *)(CODEC_BASE + 0x18))
|
|
#define CDC_ANA_REG7 ((volatile unsigned *)(CODEC_BASE + 0x1c))
|
|
#define CDC_RXFIFO_DATA ((volatile unsigned *)(CODEC_BASE +0x20))
|
|
#define CDC_FIFO_STATUS ((volatile unsigned *)(CODEC_BASE +0x24))
|
|
#define CDC_DMA_CONFIG ((volatile unsigned *)(CODEC_BASE +0x28))
|
|
#define CDC_INT ((volatile unsigned *)(CODEC_BASE +0x2C))
|
|
#define CDC_INT_RAW ((volatile unsigned *)(CODEC_BASE +0x30))
|
|
#define CDC_INT_EN ((volatile unsigned *)(CODEC_BASE +0x34))
|
|
#define CDC_TXFIFO_DATA ((volatile unsigned *)(CODEC_BASE +0x38))
|
|
|
|
#define buff_UNIT_type_t uint32_t
|
|
#define LENGTH_BUFFER 16//256
|
|
#define BUFFER_UNIT (sizeof(buff_UNIT_type_t))
|
|
#define BUFF_NUM 20
|
|
|
|
|
|
|
|
/*60seconds contain 3000 frames of 20ms, and every 20ms will be encoded into 20bytes so 1min=60000bytes */
|
|
#define ENCODED_FRAME_SIZE 32
|
|
#define FRAME_SIZE (32/4)
|
|
#define _1MIN_SIZE 60000
|
|
#define _1MIN_NB_OF_FRAMES (_1MIN_SIZE/ENCODED_FRAME_SIZE)
|
|
|
|
#define MIC_SAMPLING_DEBUG 1
|
|
#define USER_KEY_EN 0 // KEY
|
|
#define PCM_DATA_DEBUG_EN 1 // uart DEBUG pcm data
|
|
|
|
#define CODEC_DEBUG(fmt, ...) //printf(fmt, ##__VA_ARGS__)
|
|
|
|
#define CODEC_DAC_DMA_CHANNEL (DMA_CHANNEL0)
|
|
#define CODEC_ADC_DMA_CHANNEL (DMA_CHANNEL1)
|
|
|
|
typedef enum
|
|
{
|
|
CODEC_MCLK_12M = 0U,
|
|
CODEC_MCLK_13M = 1U,
|
|
} Codec_clk_e;
|
|
|
|
typedef enum
|
|
{
|
|
STEREO_MONO = 0U, /* Stereo Data Input */
|
|
LEFT_MONO = 1U, /* L Mono */
|
|
RIGHT_MONO = 2U, /* R Mono */
|
|
L_R_AVE_MONO = 3U, /* (L+R)/2 Mono */
|
|
} Codec_Mono_e;
|
|
|
|
typedef enum {
|
|
LRCK_8KHZ = 0U,
|
|
LRCK_11_025KHZ = 1U,
|
|
LRCK_12KHZ = 2U,
|
|
LRCK_16KHZ = 3U,
|
|
LRCK_22_05KHZ = 4U,
|
|
LRCK_24KHZ = 5U,
|
|
LRCK_32KHZ = 6U,
|
|
LRCK_44_1KHZ = 7U,
|
|
LRCK_48KHZ = 8U,
|
|
LRCK_96KHZ = 9U,
|
|
}Codec_SampleRate_e;
|
|
|
|
typedef enum
|
|
{
|
|
RATE_44_1KHZ = 0U,
|
|
RATE_48KHZ = 1U,
|
|
RATE_96KHZ = 2U,
|
|
RATE_OTHERS = 3U, /* Others */
|
|
} Codec_Filter_e;
|
|
typedef enum
|
|
{
|
|
SINGLE_LINE_INPUT = 1, // Single Ended Line Input Selection
|
|
DIFF_INPUT = 3, // Differential Line Input Selection(Default)
|
|
FM_INPUT = 4, // FM Input Selection
|
|
MIC_INPUT = 8, // MIC Input Selection
|
|
} Input_Select_e;
|
|
typedef enum
|
|
{
|
|
MIC1 = 0, // use Mic 0
|
|
MIC2 = 1, // use Mic 1
|
|
} Mic_INDEX_e;
|
|
typedef enum
|
|
{
|
|
MIC_PGA_GAIN_0DB = 0,
|
|
MIC_PGA_GAIN_20DB = 1,
|
|
} Mic_PGA_Gain_e;
|
|
typedef enum
|
|
{
|
|
STO_PGA_GAIN_0DB = 0,
|
|
STO_PGA_GAIN_1_6DB,
|
|
STO_PGA_GAIN_3_2DB,
|
|
STO_PGA_GAIN_4_8DB,
|
|
STO_PGA_GAIN_6_4DB,
|
|
STO_PGA_GAIN_8_0DB,
|
|
STO_PGA_GAIN_9_6DB,
|
|
STO_PGA_GAIN_11_2DB,
|
|
STO_PGA_GAIN_12_8DB,
|
|
STO_PGA_GAIN_14_4DB,
|
|
STO_PGA_GAIN_16_0DB,
|
|
STO_PGA_GAIN_17_6DB,
|
|
STO_PGA_GAIN_19_2DB,
|
|
STO_PGA_GAIN_20_8DB,
|
|
STO_PGA_GAIN_22_4DB,
|
|
STO_PGA_GAIN_MUTE,
|
|
} STO_PGA_Gain_e;
|
|
typedef enum
|
|
{
|
|
ADC_ANALOG_VOL_0DB = 0,
|
|
ADC_ANALOG_VOL_1_6DB,
|
|
ADC_ANALOG_VOL_3_2DB,
|
|
ADC_ANALOG_VOL_4_8DB,
|
|
ADC_ANALOG_VOL_6_4DB,
|
|
ADC_ANALOG_VOL_8_0DB,
|
|
ADC_ANALOG_VOL_9_6DB,
|
|
ADC_ANALOG_VOL_11_2DB,
|
|
ADC_ANALOG_VOL_12_8DB,
|
|
ADC_ANALOG_VOL_14_4DB,
|
|
ADC_ANALOG_VOL_16_0DB,
|
|
ADC_ANALOG_VOL_17_6DB,
|
|
ADC_ANALOG_VOL_19_2DB,
|
|
ADC_ANALOG_VOL_20_8DB,
|
|
ADC_ANALOG_VOL_22_4DB,
|
|
ADC_ANALOG_VOL_MUTE,
|
|
} ADC_Analog_Vol_e;
|
|
typedef enum
|
|
{
|
|
DAC_ANALOG_VOL_6DB = 0, /* 6DB */
|
|
DAC_ANALOG_VOL_4DB, /* 4DB */
|
|
DAC_ANALOG_VOL_2DB, /* 2DB */
|
|
DAC_ANALOG_VOL_0DB, /* 0DB */
|
|
DAC_ANALOG_VOL_2NDB, /* -2DB */
|
|
DAC_ANALOG_VOL_4NDB, /* -4DB */
|
|
DAC_ANALOG_VOL_6NDB, /* -6DB */
|
|
DAC_ANALOG_VOL_8NDB, /* -8DB */
|
|
DAC_ANALOG_VOL_10NDB, /* -10DB */
|
|
DAC_ANALOG_VOL_12NDB, /* -12DB */
|
|
DAC_ANALOG_VOL_14NDB, /* -14DB */
|
|
DAC_ANALOG_VOL_16NDB, /* -16DB */
|
|
DAC_ANALOG_VOL_18NDB, /* -18DB */
|
|
DAC_ANALOG_VOL_20NDB, /* -20DB */
|
|
DAC_ANALOG_VOL_22NDB, /* -22DB */
|
|
DAC_ANALOG_VOL_24NDB, /* -24DB */
|
|
DAC_ANALOG_VOL_26NDB, /* -26DB */
|
|
DAC_ANALOG_VOL_28NDB, /* -28DB */
|
|
DAC_ANALOG_VOL_30NDB, /* -30DB */
|
|
DAC_ANALOG_VOL_32NDB, /* -32DB */
|
|
DAC_ANALOG_VOL_34NDB, /* -34DB */
|
|
DAC_ANALOG_VOL_36NDB, /* -36DB */
|
|
DAC_ANALOG_VOL_38NDB, /* -38DB */
|
|
DAC_ANALOG_VOL_40NDB, /* -40DB */
|
|
DAC_ANALOG_VOL_42NDB, /* -42DB */
|
|
DAC_ANALOG_VOL_44NDB, /* -44DB */
|
|
DAC_ANALOG_VOL_46NDB, /* -46DB */
|
|
DAC_ANALOG_VOL_48NDB, /* -48DB */
|
|
DAC_ANALOG_VOL_50NDB, /* -50DB */
|
|
DAC_ANALOG_VOL_52NDB, /* -52DB */
|
|
DAC_ANALOG_VOL_54NDB, /* -54DB */
|
|
DAC_ANALOG_VOL_MUTE, /* MUTE */
|
|
} DAC_Analog_Vol_e;
|
|
typedef struct
|
|
{
|
|
Codec_clk_e codec_clk; /* codec clk set*/
|
|
Input_Select_e input_mode; /* ADC Channel Input Selection */
|
|
Codec_SampleRate_e sampleRate; /* ADC sampleRate set */
|
|
uint8_t digital_vol; /* ADC Right and Left Channel digital Gain Control:3FH: Max Volume (Step -1.5dB) (0x00: 0dB) */
|
|
ADC_Analog_Vol_e analog_vol_r; /* ADC Right Channel PGA Gain Control */
|
|
ADC_Analog_Vol_e analog_vol_l; /* ADC Left Channel PGA Gain Control */
|
|
Mic_PGA_Gain_e mic_pga_gain; /* ADC Mic-phone Input PGA Gain Control */
|
|
STO_PGA_Gain_e sto_pga_gain; /* ADC Sidetone PGA Gain Control */
|
|
#ifdef USE_DMA
|
|
uint32_t transf_size;
|
|
uint32_t *voice_buffer;
|
|
#endif
|
|
} codec_adc_config_t;
|
|
typedef struct
|
|
{
|
|
Codec_clk_e codec_clk; /* codec clk set*/
|
|
Codec_Mono_e mono_mode; /* DAC Digital Input Control Signal */
|
|
Codec_SampleRate_e sampleRate; /* DAC sampleRate set*/
|
|
uint8_t digital_vol_r; /* DAC Right Channel digital Gain Control:80H: Max Volume (Step 1/128) (0x00: 0 * VFS) VFS=AVDD_DA/3.3v, AVDD_DA=2.5v(typ), VFS=2.5/3.3=0.757575...(v) */
|
|
uint8_t digital_vol_l; /* DAC Left Channel digital Gain Control:80H: Max Volume (Step 1/128) (0x00: 0 * VFS) VFS=AVDD_DA/3.3v, AVDD_DA=2.5v(typ), VFS=2.5/3.3=0.757575...(v) */
|
|
DAC_Analog_Vol_e analog_vol_r; /* DAC Right Channel analog Gain Control:1FH: Max Volume (Step -2dB) (0x00: +6dB) */
|
|
DAC_Analog_Vol_e analog_vol_l; /* DAC Left Channel analog Gain Control:1FH: Max Volume (Step -2dB) (0x00: +6dB) */
|
|
#ifdef USE_DMA
|
|
uint32_t transf_size;
|
|
uint32_t *voice_buffer;
|
|
#endif
|
|
} codec_dac_config_t;
|
|
|
|
void xc_codec_clk_disable(uint8_t clk);
|
|
void xc_codec_adc_init(codec_adc_config_t *cfg);
|
|
void xc_codec_adc_start(void* cb);
|
|
void xc_codec_dac_init(codec_dac_config_t *cfg);
|
|
void xc_codec_dac_start(void* cb);
|
|
void xc_codec_dac_stop(void);
|
|
#endif
|
|
#endif
|