xushaoxiang
824 lines
20 KiB
C
824 lines
20 KiB
C
/*!
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* \file xc_drv_dma.c
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*
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* \brief Target xinchip dma driver implementation
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "xc_drv_dma.h"
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#if XC_CHECK(XC_DMA_ENABLED)
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/*------------------------------------------------------------------------------------
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Global Variables
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-------------------------------------------------------------------------------------*/
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DMA_Instance_t DMA_Instance;
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/*------------------------------------------------------------------------------------
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Functions
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-------------------------------------------------------------------------------------*/
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/**
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* @brief xc_dma_set_test_mode
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* @details DMAC test mode set
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*
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* @param uint8_t - mode
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE void xc_dma_set_test_mode(uint8_t mode)
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{
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dma_test_reg_set(mode);
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}
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/**
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* @brief xc_dma_set_channel_priority_order
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE void xc_dma_set_channel_priority_order(DMA_Instance_t *inst)
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{
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uint8_t priority[DMA_MAX_CHANNELS];
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uint8_t i, ch_priority, order;
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for (i = 0; i < DMA_MAX_CHANNELS; i++) {
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priority[i] = 0;
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inst->Ch_Order[i] = i;
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}
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for (uint8_t ch_num = 0; ch_num < DMA_MAX_CHANNELS; ch_num++) {
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// read the priority of the current channel
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ch_priority = dma_cfg_l__ch_prior__getf(ch_num);
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// Check the channel order array to see what position
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// this channel comes in the priority list.
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for (i = 0; i <= DMA_MAX_CHANNELS; i++) {
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if (A_MAXEQ_B(ch_priority, priority[i]) || i == DMA_MAX_CHANNELS) {
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order = i;
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break;
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}
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}
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// Now we know the order for this channel insert in the correct
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// array position and shift current priority ordering to suite.
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for (i = ch_num; i > order; i--) {
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priority[i] = priority[i - 1];
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inst->Ch_Order[i] = inst->Ch_Order[i - 1];
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}
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priority[order] = ch_priority;
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inst->Ch_Order[order] = ch_num;
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}
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}
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/**
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* @brief xc_dma_reset_instance
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE void xc_dma_reset_instance(DMA_Instance_t *inst)
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{
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for (uint8_t i = 0; i < DMA_MAX_CHANNELS; i++) {
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switch (i) {
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case 0:
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inst->Ch[i].ch_num = DMA_CHANNEL0;
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break;
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case 1:
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inst->Ch[i].ch_num = DMA_CHANNEL1;
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break;
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case 2:
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inst->Ch[i].ch_num = DMA_CHANNEL2;
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break;
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case 3:
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inst->Ch[i].ch_num = DMA_CHANNEL3;
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break;
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}
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inst->Ch[i].userCallback = NULL;
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inst->Ch[i].userListener = NULL;
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}
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// Set the channel priority order
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xc_dma_set_channel_priority_order(inst);
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}
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/**
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* @brief xc_dma_check_channel_range
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_check_channel_range(eDMA_Ch_Num ch_num)
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{
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uint8_t errorCode = DMA_OK;
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if (ch_num == DMA_NO_CHANNEL || ch_num > DMA_ALL_CHANNELS) {
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errorCode = DMA_ECHRNG;
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_check_channel_busy
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_check_channel_busy(eDMA_Ch_Num ch_num)
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{
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uint8_t errorCode = DMA_OK;
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if (ch_num == DMA_NO_CHANNEL || ch_num & (~DMA_ALL_CHANNELS)) {
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errorCode = DMA_ECHRNG;
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} else {
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if (((uint16_t)dma_ch_en_reg_get( )) & ch_num) {
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errorCode = DMA_EBUSY;
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}
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_get_channel_index
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_get_channel_index(eDMA_Ch_Num ch_num)
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{
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uint8_t ch_enum = 1;
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uint8_t ch_index = 0;
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ch_num &= (DMA_ALL_CHANNELS >> 8);
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while (ch_index < DMA_MAX_CHANNELS) {
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if (ch_enum == ch_num) {
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break;
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}
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ch_enum *= 2;
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ch_index++;
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}
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return ch_index;
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}
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/**
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* @brief xc_dma_enable
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE void xc_dma_enable(void) { dma_cfg_reg_set(ENABLE); }
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/**
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* @brief xc_dma_disable
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_disable(void)
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{
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uint8_t errorCode = 0;
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uint8_t dma_en = dma_cfg_reg__dma_en__getf( );
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if (dma_en != 0) {
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dma_cfg_reg_set(DISABLE);
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// Ensure that the DMA was disabled
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// May not disable due to split response on one
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// of the DMA channels
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if (dma_cfg_reg_get( )) {
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errorCode = DMA_EBUSY;
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}
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_is_enable
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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bool xc_dma_is_enable(void)
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{
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bool ret;
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ret = (bool)dma_cfg_reg__dma_en__getf( );
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return ret;
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}
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/**
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* @brief xc_dma_enable_channel
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_enable_channel(eDMA_Ch_Num ch_num)
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{
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uint8_t errorCode = 0;
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// Check for valid channel number and not busy
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errorCode = xc_dma_check_channel_busy(ch_num);
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if (errorCode == 0) {
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// The dw_dmac_channel_number enum is declared such that
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// the enumerated value maps exactly to the value that
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// needs to be written into the ChEnReg for enabling.
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dma_ch_en_reg_set(ch_num);
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_disable_channel
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_disable_channel(eDMA_Ch_Num ch_num)
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{
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uint8_t errorCode = 0;
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uint32_t enabled_ch;
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// Check for valid channel number
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errorCode = xc_dma_check_channel_range(ch_num);
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if (errorCode == 0) {
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enabled_ch = (dma_ch_en_reg_get( ) & ch_num);
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if (enabled_ch != 0) {
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dma_ch_en_reg_set((ch_num & (DMA_ALL_CHANNELS << 8)));
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// Ensure that the channel(s) was disabled.
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// Channel may not disable due to a split response.
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if (dma_ch_en_reg_get( ) & ch_num) {
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errorCode = DMA_EBUSY;
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}
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}
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_is_channel_enabled
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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bool xc_dma_is_channel_enabled(eDMA_Ch_Num ch_num)
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{
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uint8_t ch_index;
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bool ret;
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ch_index = xc_dma_get_channel_index(ch_num);
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// Allow only ONE channel to be specified
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if (ch_index == DMA_MAX_CHANNELS)
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return false;
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// Check that the specified channel is in range
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if (ch_num & (~DMA_ALL_CHANNELS))
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return false;
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ret = (bool)REG_BIT_VAL_GET(dma_ch_en_reg__ch_en__getf( ), 1 << ch_index, ch_index);
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return ret;
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}
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/**
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* @brief xc_dma_enable_channel_irq
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_enable_channel_irq(eDMA_Ch_Num ch_num)
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{
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uint8_t errorCode = DMA_OK;
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// Check for valid channel number and not busy
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errorCode = xc_dma_check_channel_busy(ch_num);
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if (errorCode == 0) {
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// Loop through each channel in turn and disable
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// the channel Irq for the selected channels.
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for (uint8_t x = 0; x < DMA_MAX_CHANNELS; x++) {
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if (ch_num & (1 << x)) {
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if (dma_ctl_l__int_en__getf(x) != 0x1) {
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dma_ctl_l__int_en__setf(x, ENABLE);
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}
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}
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}
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_disable_channel_irq
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_disable_channel_irq(eDMA_Ch_Num ch_num)
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{
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uint8_t errorCode = DMA_OK;
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// Check for valid channel number and not busy
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errorCode = xc_dma_check_channel_busy(ch_num);
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if (errorCode == 0) {
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// Loop through each channel in turn and disable
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// the channel Irq for the selected channels.
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for (uint8_t x = 0; x < DMA_MAX_CHANNELS; x++) {
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if (ch_num & (1 << x)) {
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if (dma_ctl_l__int_en__getf(x) != 0x0) {
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dma_ctl_l__int_en__setf(x, DISABLE);
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}
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}
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}
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_mask_irq
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_mask_irq(eDMA_Ch_Num ch_num, eDMA_Irq ch_irq)
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{
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uint8_t errorCode = DMA_OK;
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uint16_t reg;
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// Check for valid channel number
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errorCode = xc_dma_check_channel_range(ch_num);
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if (errorCode == 0) {
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// Loop through and clear the selected channel Irq
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// for the targeted channels.
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reg = (ch_num & (DMA_ALL_CHANNELS << 8));
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for (uint8_t x = 0; x < DMA_MAX_INTERRUPTS; x++) {
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if (ch_irq & (1 << x)) {
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if(x == 0){
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dma_mask_tfr_set(reg);
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}else if(x == 1){
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dma_mask_block_set(reg);
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}else if(x == 2){
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dma_mask_src_tran_set(reg);
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}else if(x == 3){
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dma_mask_dst_tran_set(reg);
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}else if(x == 4){
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dma_mask_err_set(reg);
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}
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}
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}
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_unmask_irq
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_unmask_irq(eDMA_Ch_Num ch_num, eDMA_Irq ch_irq)
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{
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uint8_t errorCode = DMA_OK;
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uint16_t reg;
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// Check for valid channel number
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errorCode = xc_dma_check_channel_range(ch_num);
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if (errorCode == 0) {
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// Loop through and clear the selected channel Irq
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// for the targeted channels.
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reg = ch_num;
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for (uint8_t x = 0; x < DMA_MAX_INTERRUPTS; x++) {
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if (ch_irq & (1 << x)) {
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if(x == 0){
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dma_mask_tfr_set(reg);
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}else if(x == 1){
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dma_mask_block_set(reg);
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}else if(x == 2){
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dma_mask_src_tran_set(reg);
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}else if(x == 3){
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dma_mask_dst_tran_set(reg);
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}else if(x == 4){
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dma_mask_err_set(reg);
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}
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}
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}
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}
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return errorCode;
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}
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/**
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* @brief xc_dma_clear_irq
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_clear_irq(eDMA_Ch_Num ch_num, eDMA_Irq ch_irq)
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{
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uint8_t errorCode = DMA_OK;
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uint16_t reg;
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// Check for valid channel number
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errorCode = xc_dma_check_channel_range(ch_num);
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if (errorCode == 0) {
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// Loop through and clear the selected channel Irq
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// for the targeted channels.
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reg = (ch_num & (DMA_ALL_CHANNELS >> 8));
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for (uint8_t x = 0; x < DMA_MAX_INTERRUPTS; x++) {
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if (ch_irq & (1 << x)) {
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if(x == 0){
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dma_clear_tfr_set(reg);
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}else if(x == 1){
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dma_clear_block_set(reg);
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}else if(x == 2){
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dma_clear_src_tran_set(reg);
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}else if(x == 3){
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dma_clear_dst_tran_set(reg);
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}else if(x == 4){
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dma_clear_err_set(reg);
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}
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}
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}
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}
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return errorCode;
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}
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|
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/**
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* @brief xc_dma_init
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* @details
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*
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* @param
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* @param
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* @return void
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* @retval void
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* @retval void
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* @note
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*/
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__RAM_CODE uint8_t xc_dma_init(void)
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{
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// Remove from test mode
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xc_dma_set_test_mode(DISABLE);
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// Reset the DMA instance structure
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xc_dma_reset_instance(&DMA_Instance);
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// Disable the DMA controller
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uint8_t errorCode = xc_dma_disable( );
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if (errorCode == 0) {
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// Disable all DMA channels
|
|
errorCode = xc_dma_disable_channel(DMA_ALL_CHANNELS);
|
|
}
|
|
|
|
if (errorCode == 0) {
|
|
// Disable all channel interrupts
|
|
errorCode = xc_dma_disable_channel_irq(DMA_ALL_CHANNELS);
|
|
}
|
|
|
|
if (errorCode == 0) {
|
|
// Mask all channel interrupts
|
|
errorCode = xc_dma_mask_irq(DMA_ALL_CHANNELS, DMA_IRQ_ALL);
|
|
}
|
|
|
|
if (errorCode == 0) {
|
|
// Clear any pending interrupts
|
|
errorCode = xc_dma_clear_irq(DMA_ALL_CHANNELS, DMA_IRQ_ALL);
|
|
}
|
|
|
|
return errorCode;
|
|
}
|
|
|
|
/**
|
|
* @brief xc_dma_set_channel_config
|
|
* @details
|
|
*
|
|
* @param
|
|
* @param
|
|
* @return void
|
|
* @retval void
|
|
* @retval void
|
|
* @note
|
|
*/
|
|
__RAM_CODE uint8_t xc_dma_set_channel_config(eDMA_Ch_Num ch_num,
|
|
DMA_Chx_Cfg_t *ch)
|
|
{
|
|
uint8_t errorCode;
|
|
uint8_t ch_index;
|
|
|
|
ch_index = xc_dma_get_channel_index(ch_num);
|
|
|
|
// Check for valid channel number and not busy
|
|
errorCode = xc_dma_check_channel_busy(ch_num);
|
|
if (errorCode == 0) {
|
|
// Set the control register
|
|
dma_ctl_l_pack(ch_index, ch->ctl_tt_fc, ch->ctl_src_msize, ch->ctl_dst_msize,
|
|
ch->ctl_sinc, ch->ctl_dinc, ch->ctl_src_tr_width, ch->ctl_dst_tr_width,
|
|
0);
|
|
|
|
dma_ctl_h__block_ts__setf(ch_index, ch->ctl_block_ts);
|
|
|
|
// Set the config register
|
|
dma_cfg_l__hs_sel_src__setf(ch_index, ch->cfg_hs_sel_src);
|
|
dma_cfg_l__hs_sel_dst__setf(ch_index, ch->cfg_hs_sel_dst);
|
|
|
|
dma_cfg_h_pack(ch_index, (ch->cfg_dst_per & 0xf), (ch->cfg_src_per & 0xf), (ch->cfg_fifo_mode & 0x1));
|
|
|
|
// set the SAR/DAR registers
|
|
dma_sar_set(ch_index, ch->sar);
|
|
dma_dar_set(ch_index, ch->dar);
|
|
};
|
|
|
|
return errorCode;
|
|
}
|
|
|
|
/**
|
|
* @brief xc_dma_set_listener
|
|
* @details
|
|
*
|
|
* @param
|
|
* @param
|
|
* @return void
|
|
* @retval void
|
|
* @retval void
|
|
* @note
|
|
*/
|
|
__RAM_CODE bool xc_dma_set_listener(eDMA_Ch_Num ch_num,
|
|
DMA_Callback userFunction)
|
|
{
|
|
uint8_t ch_index;
|
|
DMA_Instance_t *inst = &DMA_Instance;
|
|
|
|
ch_index = xc_dma_get_channel_index(ch_num);
|
|
|
|
// Allow only ONE channel to be specified
|
|
if (ch_index == DMA_MAX_CHANNELS)
|
|
return false;
|
|
|
|
// Check that the specified channel is in range
|
|
if (ch_num & (~DMA_ALL_CHANNELS))
|
|
return false;
|
|
|
|
inst->Ch[ch_index].userListener = userFunction;
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* @brief xc_dma_start_transfer
|
|
* @details
|
|
*
|
|
* @param
|
|
* @param
|
|
* @return void
|
|
* @retval void
|
|
* @retval void
|
|
* @note
|
|
*/
|
|
__RAM_CODE uint8_t xc_dma_start_transfer(eDMA_Ch_Num ch_num, DMA_Callback cb_func)
|
|
{
|
|
uint8_t errorCode;
|
|
uint8_t ch_index;
|
|
|
|
DMA_Instance_t *inst = &DMA_Instance;
|
|
// Update the channel instance
|
|
ch_index = xc_dma_get_channel_index(ch_num);
|
|
|
|
// Allow only ONE channel to be specified
|
|
if (ch_index == DMA_MAX_CHANNELS) {
|
|
errorCode = DMA_ECHRNG;
|
|
} else {
|
|
// Check for valid channel number and not busy
|
|
errorCode = xc_dma_check_channel_busy(ch_num);
|
|
}
|
|
|
|
if (errorCode == 0) {
|
|
// Disable the channels interrupts
|
|
errorCode = xc_dma_disable_channel_irq(ch_num);
|
|
}
|
|
|
|
if (errorCode == 0) {
|
|
// set the call back function, the number of blocks
|
|
// in the transfer and the source and destination states.
|
|
inst->Ch[ch_index].userCallback = cb_func;
|
|
|
|
// always want to unmask the tfr, block and err interrupts
|
|
xc_dma_unmask_irq(ch_num, DMA_IRQ_TRF);
|
|
xc_dma_unmask_irq(ch_num, DMA_IRQ_ERR);
|
|
|
|
// Enable the channel interrupts for the type of transfer
|
|
errorCode = xc_dma_enable_channel_irq(ch_num);
|
|
|
|
if (errorCode == 0) {
|
|
// Enable the DMA channel
|
|
errorCode = xc_dma_enable_channel(ch_num);
|
|
}
|
|
}
|
|
|
|
return errorCode;
|
|
}
|
|
|
|
/**
|
|
* @brief dma_irq_handler
|
|
* @details
|
|
*
|
|
* @param
|
|
* @param
|
|
* @return void
|
|
* @retval void
|
|
* @retval void
|
|
* @note
|
|
*/
|
|
__RAM_CODE bool dma_irq_handler(DMA_Instance_t *inst)
|
|
{
|
|
bool retval;
|
|
uint8_t i, ch_index, callbackArg;
|
|
uint32_t reg, mask;
|
|
DMA_Callback userCallback;
|
|
|
|
// Assume an interrupt will be processed. The return value will be
|
|
// set to false if an active interrupt is not found.
|
|
retval = true;
|
|
|
|
// ERR INTERRUPT
|
|
if (dma_status_int__err__getf( )) {
|
|
reg = dma_status_err_get( );
|
|
|
|
// Loop through the channels until we find
|
|
// active interrupt. We start at the highest priority
|
|
// channel and work down to the lowest priority.
|
|
for (i = 0; i < DMA_MAX_CHANNELS; i++) {
|
|
mask = 1 << inst->Ch_Order[i];
|
|
if (reg & mask) {
|
|
ch_index = inst->Ch_Order[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
// run the listener function
|
|
if (inst->Ch[ch_index].userListener != NULL) {
|
|
userCallback = inst->Ch[ch_index].userListener;
|
|
callbackArg = DMA_IRQ_ERR;
|
|
userCallback(callbackArg);
|
|
}
|
|
|
|
// clear the interrupt
|
|
dma_clear_err_set(mask);
|
|
}
|
|
// TFR INTERRUPT
|
|
else if (dma_status_int__tfr__getf( )) {
|
|
reg = dma_status_tfr_get( );
|
|
|
|
// Loop through the channels until we find
|
|
// active interrupt. We start at the highest priority
|
|
// channel and work down to the lowest priority.
|
|
for (i = 0; i < DMA_MAX_CHANNELS; i++) {
|
|
mask = 1 << inst->Ch_Order[i];
|
|
if (reg & mask) {
|
|
ch_index = inst->Ch_Order[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Disable all channel interrupts
|
|
xc_dma_disable_channel_irq(inst->Ch[ch_index].ch_num);
|
|
|
|
// clear any pending block/srcTran/dstTran interrupts
|
|
dma_clear_block_set(mask);
|
|
dma_clear_src_tran_set(mask);
|
|
dma_clear_dst_tran_set(mask);
|
|
xc_dma_clear_irq(inst->Ch[ch_index].ch_num, DMA_IRQ_TRF);
|
|
|
|
// Mask all channel interrupts
|
|
xc_dma_mask_irq(inst->Ch[ch_index].ch_num, DMA_IRQ_ALL);
|
|
|
|
// run the callback function
|
|
if (inst->Ch[ch_index].userCallback != NULL) {
|
|
userCallback = inst->Ch[ch_index].userCallback;
|
|
callbackArg = 0;
|
|
userCallback(callbackArg);
|
|
}
|
|
|
|
} else {
|
|
// If we've reached this point, either the enabling and
|
|
// disabling of DW_ahb_dmac interrupts is not being handled
|
|
// properly or this function is being called unnecessarily.
|
|
retval = false;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
__RAM_CODE void DMA_Handler(void) { dma_irq_handler(&DMA_Instance); }
|
|
|
|
#endif // XC_CHECK(XC_DMA_ENABLED)
|