xushaoxiang
674 lines
19 KiB
C
674 lines
19 KiB
C
/*!
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* \file xc6xxx_hal_spi.c
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*
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* \brief Target xc6xxx hal spi implementation
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "xc6xxx.h"
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#if XC_CHECK(XC_SPI_ENABLED)
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/*------------------------------------------------------------------------------------
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Global Variables
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-------------------------------------------------------------------------------------*/
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typedef struct
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{
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bool SPI_DMA_IT_Enable_Flag[3];
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uint8_t SPI_Mode[3];
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} SPI_CtrlBlock_Typedef;
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SPI_CtrlBlock_Typedef m_spi_cb;
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/*------------------------------------------------------------------------------------
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Func Prototype
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-------------------------------------------------------------------------------------*/
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eXC_RESULT xc_spi_write_bytes(uint8_t reg_idx, uint8_t *txdata, uint16_t len);
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eXC_RESULT xc_spi_read_bytes(uint8_t reg_idx, uint8_t *rxdata, uint16_t len);
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/*------------------------------------------------------------------------------------
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Functions
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-------------------------------------------------------------------------------------*/
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void xc_spi_init(uint8_t reg_idx, SPI_InitCfg_t *init_cfg)
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{
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#if (USE_XIP == 0)
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if (SPI0_IDX == reg_idx) {
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cpr_rstctl_subrst_sw__ssi0_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_subrst_sw__ssi0_rstn__setf(RSTCTL_DISABLE);
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cpr_ctlapbclken_grctl__ssi0_pclk_en__setf(ENABLE);
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cpr_ssi0_mclk_ctl__ssi_mclk_div__setf(0);
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cpr_ssi0_mclk_ctl__ssi_mclk_en__setf(1);
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cpr_ssi_ctrl__ssi0_protocol__setf(SSI_CTRL0_FRF_MOTOROLA);
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}
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#endif
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if (SPI1_IDX == reg_idx) {
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cpr_rstctl_subrst_sw__ssi1_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_subrst_sw__ssi1_rstn__setf(RSTCTL_DISABLE);
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cpr_ssi1_mclk_ctl__ssi_mclk_div__setf(0);
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cpr_ssi1_mclk_ctl__ssi_mclk_en__setf(1);
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cpr_ctlapbclken_grctl__ssi1_pclk_en__setf(ENABLE);
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if (init_cfg->Mode == SPI_MODE_MASTER) {
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cpr_ssi_ctrl__ssi1_master_en__setf(ENABLE);
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} else if (init_cfg->Mode == SPI_MODE_SLAVE) {
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cpr_ssi_ctrl__ssi1_master_en__setf(DISABLE);
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}
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cpr_ssi_ctrl__ssi1_protocol__setf(SSI_CTRL0_FRF_MOTOROLA);
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} else if (SPI2_IDX == reg_idx) {
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cpr_rstctl_subrst_sw__ssi2_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_subrst_sw__ssi2_rstn__setf(RSTCTL_DISABLE);
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cpr_ssi1_mclk_ctl__ssi2_mclk_div__setf(0);
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cpr_ssi1_mclk_ctl__ssi2_mclk_en__setf(1);
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cpr_ctlapbclken_grctl__ssi2_pclk_en__setf(ENABLE);
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cpr_ssi_ctrl__ssi2_protocol__setf(SSI_CTRL0_FRF_MOTOROLA);
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}
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spi_en_set(reg_idx, DISABLE);
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// sste is automatically set to 1 when spi slave is initialized.
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// therefor, manually clear this bit to 0 here.
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spi_ctrl0__ssi_sste__setf(reg_idx, DISABLE);
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spi_ctrl0__ssi_tmod__setf(reg_idx, init_cfg->Direction);
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spi_ctrl0__ssi_scpol__setf(reg_idx, init_cfg->CLKPolarity);
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spi_ctrl0__ssi_scpha__setf(reg_idx, init_cfg->CLKPhase);
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spi_ctrl0__ssi_dfs__setf(reg_idx, init_cfg->DataSize);
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spi_ie_set(reg_idx, DISABLE);
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spi_se_set(reg_idx, ENABLE);
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spi_baud__ssi_sckdv__setf(reg_idx, init_cfg->BaudRatePrescaler);
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spi_txftl__ssi_tft__setf(reg_idx, SSI_TXFTL_FIFO_1);
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spi_rxftl__ssi_rft__setf(reg_idx, SSI_RXFTL_FIFO_1);
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}
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static void xc_spi_enable(uint8_t reg_idx, uint8_t dfs)
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{
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spi_en__ssi_sen__setf(reg_idx, DISABLE);
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spi_dmas_set(reg_idx, DISABLE);
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spi_ctrl0__ssi_dfs__setf(reg_idx, dfs);
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spi_en__ssi_sen__setf(reg_idx, ENABLE);
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}
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static void xc_spi_disable(uint8_t reg_idx) { spi_en__ssi_sen__setf(reg_idx, DISABLE); }
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void xc_spi_rxftl_fifo_set(uint8_t reg_idx, uint8_t val)
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{
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spi_rxftl__ssi_rft__setf(reg_idx, val);
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}
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void xc_spi_txftl_fifo_set(uint8_t reg_idx, uint8_t val)
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{
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spi_txftl__ssi_tft__setf(reg_idx, val);
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}
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void xc_spi_enable_it(uint8_t reg_idx, uint8_t val) { spi_ie_set(reg_idx, val); }
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void xc_spi_disable_it(uint8_t reg_idx, uint8_t val) { spi_ie_set(reg_idx, val); }
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void xc_spi_flash_power_down(uint8_t reg_idx)
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{
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uint8_t txbuff[2] = {0};
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txbuff[1] = CMD_PWRDWN;
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_8BIT);
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xc_spi_write_bytes(reg_idx, txbuff, sizeof(txbuff));
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xc_spi_disable(reg_idx);
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}
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void xc_spi_flash_wake_up(uint8_t reg_idx)
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{
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uint8_t txbuff[2] = {0};
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txbuff[1] = CMD_RELEASE_PWRDWN;
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_8BIT);
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xc_spi_write_bytes(reg_idx, txbuff, sizeof(txbuff));
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xc_spi_disable(reg_idx);
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}
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static uint8_t xc_spi_flash_wait_busy(uint8_t reg_idx)
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{
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uint8_t cmd[2] = {0};
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uint8_t sta[2] = {0xff, 0xff};
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cmd[0] = CMD_READ_STATUS;
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cmd[1] = 0xff;
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
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xc_spi_write_bytes(reg_idx, cmd, sizeof(cmd));
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xc_spi_read_bytes(reg_idx, sta, sizeof(sta));
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xc_spi_disable(reg_idx);
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return (sta[1] & 0x01);
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}
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static void xc_spi_flash_write_enable(uint8_t reg_idx)
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{
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uint8_t txbuff[2] = {0};
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txbuff[1] = CMD_WRITE_ENABLE;
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_8BIT);
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xc_spi_write_bytes(reg_idx, txbuff, sizeof(txbuff));
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xc_spi_disable(reg_idx);
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}
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eXC_RESULT xc_spi_flash_erase_sector(uint8_t reg_idx, uint32_t Dst_Addr)
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{
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uint8_t cmd[4];
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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xc_spi_flash_write_enable(reg_idx);
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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cmd[0] = CMD_SECTOR_ERASE;
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cmd[1] = Dst_Addr >> 16;
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cmd[2] = Dst_Addr >> 8;
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cmd[3] = Dst_Addr;
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
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#ifndef FAST_SPI
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xc_spi_write_bytes(reg_idx, cmd, sizeof(cmd));
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#else
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xc_spi_write_2bytes(reg_idx, cmd, sizeof(cmd));
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#endif
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xc_spi_disable(reg_idx);
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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return XR_OK;
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}
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#if (USE_INTEGRATED_FlASH == USE_PUYA_FlASH)
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void xc_spi_flash_erase_page(uint8_t reg_idx, uint32_t Dst_Addr)
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{
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uint8_t cmd[4];
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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xc_spi_flash_write_enable(reg_idx);
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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cmd[0] = CMD_PAGE_ERASE;
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cmd[1] = Dst_Addr >> 16;
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cmd[2] = Dst_Addr >> 8;
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cmd[3] = Dst_Addr;
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
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#ifndef FAST_SPI
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xc_spi_write_bytes(reg_idx, cmd, sizeof(cmd));
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#else
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xc_spi_write_2bytes(reg_idx, cmd, sizeof(cmd));
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#endif
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xc_spi_disable(reg_idx);
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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}
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#endif
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#ifndef FAST_SPI
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void xc_spi_flash_write_page(uint8_t reg_idx, uint32_t WriteAddr, uint8_t *pBuffer)
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{
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uint32_t addr = WriteAddr;
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uint8_t cmd[16 + 4] = {0};
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for (uint8_t i = 0; i < 16; i++) {
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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xc_spi_flash_write_enable(reg_idx);
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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cmd[0] = CMD_PAGE_PROGRAM;
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cmd[1] = addr >> 16;
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cmd[2] = addr >> 8;
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cmd[3] = addr;
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memcpy(&cmd[4], pBuffer + i * 16, 16);
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
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xc_spi_write_bytes(reg_idx, cmd, sizeof(cmd));
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addr += 16;
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}
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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xc_spi_disable(reg_idx);
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}
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#else
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void xc_spi_flash_write_page(uint8_t reg_idx, uint32_t WriteAddr, uint8_t *pBuffer)
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{
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uint8_t cmd[256 + 4] = {0};
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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xc_spi_flash_write_enable(reg_idx);
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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cmd[0] = CMD_PAGE_PROGRAM;
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cmd[1] = WriteAddr >> 16;
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cmd[2] = WriteAddr >> 8;
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cmd[3] = WriteAddr;
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memcpy(&cmd[4], pBuffer, FLASH_PAGE_SIZE);
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xc_spi_write_2bytes(reg_idx, cmd, sizeof(cmd));
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while (xc_spi_flash_wait_busy(reg_idx))
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;
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xc_spi_disable(reg_idx);
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}
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#endif
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void xc_spi_flash_read_page(uint8_t reg_idx, uint32_t ReadAddr, uint8_t *pBuffer)
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{
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uint8_t cmd[16 + 4] = {0};
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uint8_t mid[16 + 4] = {0};
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uint16_t rx_idx = 0;
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uint32_t addr = ReadAddr;
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for (uint8_t i = 0; i < 16; i++) {
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cmd[0] = CMD_READ_DATA;
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cmd[1] = addr >> 16;
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cmd[2] = addr >> 8;
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cmd[3] = addr;
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
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xc_spi_write_bytes(reg_idx, cmd, sizeof(cmd));
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xc_spi_read_bytes(reg_idx, mid, sizeof(cmd));
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memcpy(&pBuffer[rx_idx], mid + 4, 16);
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addr += 16;
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rx_idx += 16;
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}
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xc_spi_disable(reg_idx);
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}
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/**
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****************************************************************************************
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* @brief
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*
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* @param[in]
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* @param[in]
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* @return[out]
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*
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****************************************************************************************
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*/
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eXC_RESULT xc_spi_flash_write(uint8_t reg_idx, uint32_t addr, uint8_t *buff,
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uint16_t size)
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{
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eXC_RESULT ret = XR_OK;
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uint32_t cur_addr = addr;
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uint32_t end_addr = addr + size;
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uint16_t wt_len = 0;
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// The current page number occupied by this data storage
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// The position occupied by this address on the current page
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uint32_t cur_start_psr = 0;
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uint16_t cur_size;
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#ifndef GD_FlASH_INTEGRATION
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uint16_t cur_page_num = 0;
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uint8_t temp_buff[FLASH_PAGE_SIZE];
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while (cur_addr != end_addr) {
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/* code */
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cur_page_num = CUR_PAGE_NUM(cur_addr);
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cur_start_psr = CUR_START_PSR(cur_addr);
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xc_spi_flash_read_page(reg_idx, cur_page_num * FLASH_PAGE_SIZE, temp_buff);
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xc_spi_flash_erase_page(reg_idx, cur_page_num * FLASH_PAGE_SIZE);
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if (cur_start_psr) {
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cur_size = MIN(FLASH_PAGE_SIZE - cur_start_psr, size - wt_len);
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} else {
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cur_size = MIN(FLASH_PAGE_SIZE, size - wt_len);
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}
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memcpy(&temp_buff[cur_start_psr], buff + wt_len, cur_size);
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wt_len += cur_size;
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cur_addr += cur_size;
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xc_spi_flash_write_page(reg_idx, cur_page_num * FLASH_PAGE_SIZE, temp_buff);
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}
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#else
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uint16_t cur_sector_num = 0;
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uint8_t temp_buff[FLASH_SECTOR_SIZE] = {0};
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while (cur_addr != end_addr) {
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/* code */
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cur_sector_num = CUR_SECTOR_NUM(cur_addr);
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cur_start_psr = CUR_START_PSR(cur_addr);
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for(int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
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xc_spi_flash_read_page(reg_idx, CUR_SECTOR_PAGE_ADDR(cur_sector_num, i), temp_buff+i*FLASH_PAGE_SIZE);
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}
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xc_spi_flash_erase_sector(reg_idx, cur_sector_num * FLASH_SECTOR_SIZE);
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if (cur_start_psr) {
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cur_size = MIN(FLASH_SECTOR_SIZE - cur_start_psr, size - wt_len);
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} else {
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cur_size = MIN(FLASH_SECTOR_SIZE, size - wt_len);
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}
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memcpy(&temp_buff[cur_start_psr], buff + wt_len, cur_size);
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wt_len += cur_size;
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cur_addr += cur_size;
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for(int i=0;i<FLASH_SECTOR_SIZE/FLASH_PAGE_SIZE;i++){
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xc_spi_flash_write_page(reg_idx, CUR_SECTOR_PAGE_ADDR(cur_sector_num, i), temp_buff+i*FLASH_PAGE_SIZE);
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}
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}
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#endif
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return ret;
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}
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/**
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****************************************************************************************
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* @brief
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*
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* @param[in]
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* @param[in]
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* @return[out]
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*
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****************************************************************************************
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*/
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eXC_RESULT xc_spi_flash_read(uint8_t reg_idx, uint32_t addr, uint8_t *buff,
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uint16_t size)
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{
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eXC_RESULT ret = XR_OK;
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uint32_t cur_addr = addr;
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uint32_t end_addr = addr + size;
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uint16_t rd_len = 0;
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uint16_t cur_page_num = 0;
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uint32_t cur_start_psr = 0;
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uint8_t temp_buff[FLASH_PAGE_SIZE] = {0};
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uint16_t cur_size;
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while (cur_addr != end_addr) {
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cur_page_num = CUR_PAGE_NUM(cur_addr);
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cur_start_psr = CUR_START_PSR(cur_addr);
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xc_spi_flash_read_page(reg_idx, cur_page_num * FLASH_PAGE_SIZE, temp_buff);
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if (cur_start_psr) {
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cur_size = MIN(FLASH_PAGE_SIZE - cur_start_psr, size - rd_len);
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} else {
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cur_size = MIN(FLASH_PAGE_SIZE, size - rd_len);
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}
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memcpy(buff + rd_len, &temp_buff[cur_start_psr], cur_size);
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cur_addr += cur_size;
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rd_len += cur_size;
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}
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return ret;
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}
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void xc_spi_flash_read_128bit_uid(uint8_t reg_idx, uint8_t *buff)
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{
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while (xc_spi_flash_wait_busy(reg_idx)) {
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DEBUG("line=%d,status=%d\n", __LINE__, xc_spi_flash_wait_busy(reg_idx));
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};
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uint8_t cmd[21] = {0};
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uint8_t id[21] = {0};
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cmd[0] = CMD_RUID;
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cmd[1] = 0x00;
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cmd[2] = 0x00;
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cmd[3] = 0x00;
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cmd[4] = 0x00;
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xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
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xc_spi_write_bytes(reg_idx, cmd, sizeof(cmd));
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xc_spi_read_bytes(reg_idx, id, sizeof(id));
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xc_spi_disable(reg_idx);
|
|
|
|
memcpy(buff, &id[5], 16);
|
|
}
|
|
|
|
eXC_RESULT xc_spi_flash_rdid(uint8_t reg_idx, uint8_t *buff)
|
|
{
|
|
while (xc_spi_flash_wait_busy(reg_idx)) {
|
|
DEBUG("line=%d,status=%d\n", __LINE__, xc_spi_flash_wait_busy(reg_idx));
|
|
};
|
|
|
|
uint8_t cmd[4] = {0};
|
|
uint8_t id[4] = {0};
|
|
|
|
cmd[0] = CMD_RDID;
|
|
cmd[1] = 0xff;
|
|
cmd[2] = 0xff;
|
|
cmd[3] = 0xff;
|
|
|
|
xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
|
|
xc_spi_write_bytes(reg_idx, cmd, sizeof(cmd));
|
|
|
|
xc_spi_read_bytes(reg_idx, id, sizeof(id));
|
|
xc_spi_disable(reg_idx);
|
|
|
|
memcpy(buff, &id[1], 3);
|
|
|
|
return XR_OK;
|
|
}
|
|
|
|
/*---------------------------------- SPI1 Master & Slave API
|
|
* ---------------------------------------*/
|
|
|
|
/**
|
|
****************************************************************************************
|
|
* @brief Only Master & Slave
|
|
*
|
|
* @param[in]
|
|
* @param[in]
|
|
****************************************************************************************
|
|
*/
|
|
static void xc_spi_datasize_set(uint8_t reg_idx, uint8_t dfs)
|
|
{
|
|
|
|
spi_en_set(reg_idx, DISABLE);
|
|
spi_ctrl0__ssi_dfs__setf(reg_idx, dfs);
|
|
spi_en_set(reg_idx, ENABLE);
|
|
}
|
|
|
|
/**
|
|
****************************************************************************************
|
|
* @brief Only applicable Master & Slave communication
|
|
*
|
|
* @param[in]
|
|
* @param[in]
|
|
****************************************************************************************
|
|
*/
|
|
eXC_RESULT xc_spi_write_bytes(uint8_t reg_idx, uint8_t *txdata, uint16_t len)
|
|
{
|
|
if (len == 0)
|
|
return XR_ERROR;
|
|
uint16_t n;
|
|
uint8_t remain = len % 2;
|
|
uint16_t cnt = len / 2;
|
|
uint16_t mid_data[128 + 1] = {0};
|
|
uint32_t i = 0;
|
|
|
|
while (spi_sts__ssi_tfe__getf(reg_idx) == RESET) {
|
|
i++;
|
|
if (i >= SPI_WAIT_TIMEOUT) {
|
|
DEBUG("func=%s,line=%d,timeout\n", __func__, __LINE__);
|
|
return XR_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
if (cnt != 0) {
|
|
for (n = 0; n < cnt; n++) {
|
|
mid_data[n] = ((txdata[n * 2] << 8) | txdata[n * 2 + 1]);
|
|
}
|
|
}
|
|
|
|
if (remain != 0) {
|
|
for (n = 0; n < remain; n++) {
|
|
mid_data[cnt] |= (txdata[cnt * 2 + n] << (16 - 8 * n));
|
|
}
|
|
}
|
|
|
|
if (cnt != 0) {
|
|
if (remain != 0)
|
|
cnt = cnt + 1;
|
|
for (n = 0; n < cnt; n++)
|
|
spi_data_set(reg_idx, mid_data[n]);
|
|
} else {
|
|
spi_data_set(reg_idx, mid_data[0]);
|
|
}
|
|
|
|
while ((spi_sts__ssi_rfne__getf(reg_idx) == RESET) ||
|
|
(spi_sts__ssi_tfe__getf(reg_idx) == RESET)) {
|
|
i++;
|
|
if (i >= SPI_WAIT_TIMEOUT) {
|
|
// DEBUG("func=%s,line=%d,timeout\n", __func__, __LINE__);
|
|
return XR_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
return XR_OK;
|
|
}
|
|
#if FAST_SPI
|
|
eXC_RESULT xc_spi_write_2bytes(uint8_t reg_idx, uint8_t *txdata, uint16_t size)
|
|
{
|
|
uint32_t time_out;
|
|
uint32_t temp_data;
|
|
uint16_t idx_8bit = 0;
|
|
uint16_t idx_16bit = 0;
|
|
uint8_t remain_size = size % 2;
|
|
uint16_t allign_16bit_size = size >> 1;
|
|
|
|
if (size == 0)
|
|
return XR_ERROR;
|
|
xc_spi_enable(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
|
|
while(!(spi_sts_get(reg_idx)&(1<<SSI_TFE_POS)));
|
|
while(idx_16bit < allign_16bit_size)
|
|
{
|
|
temp_data = ((txdata[idx_8bit] << 8) | txdata[idx_8bit+1]);
|
|
spi_data_set(reg_idx, temp_data);
|
|
idx_16bit++;
|
|
idx_8bit+=2;
|
|
}
|
|
if (remain_size != 0 ){
|
|
for (uint8_t i = 0; i < remain_size; i++){
|
|
temp_data |= (txdata[idx_8bit + i] << (8 - 8 * i));
|
|
}
|
|
while (!(spi_sts_get(reg_idx) & (1<<SSI_TFNF_POS)));
|
|
spi_data_set(reg_idx, temp_data);
|
|
}
|
|
while (!(spi_sts_get(reg_idx) & (1<<SSI_TFE_POS)) ||
|
|
(spi_sts_get(reg_idx) & (1<<SSI_BUSY_POS)))
|
|
{
|
|
time_out++;
|
|
if (time_out >= SPI_WAIT_TIMEOUT) {
|
|
DEBUG("func=%s,line=%d,timeout\n", __func__, __LINE__);
|
|
return XR_TIMEOUT;
|
|
}
|
|
}
|
|
return XR_OK;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
****************************************************************************************
|
|
* @brief Only applicable Master & Slave communication
|
|
*
|
|
* @param[in]
|
|
* @param[in]
|
|
****************************************************************************************
|
|
*/
|
|
eXC_RESULT xc_spi_read_bytes(uint8_t reg_idx, uint8_t *rxdata, uint16_t len)
|
|
{
|
|
if (len == 0)
|
|
return XR_ERROR;
|
|
|
|
uint16_t n;
|
|
uint8_t remain = len % 2;
|
|
uint16_t cnt = len / 2;
|
|
uint16_t mid_data = 0;
|
|
|
|
if (cnt != 0) {
|
|
for (n = 0; n < cnt; n++) {
|
|
|
|
mid_data = spi_data_get(reg_idx);
|
|
rxdata[n * 2] = mid_data >> 8;
|
|
rxdata[n * 2 + 1] = mid_data;
|
|
}
|
|
}
|
|
|
|
if (remain != 0) {
|
|
|
|
mid_data = spi_data_get(reg_idx);
|
|
for (n = 0; n < remain; n++) {
|
|
rxdata[cnt * 2 + n] = mid_data >> 8;
|
|
rxdata[cnt * 2 + 1 + n] = mid_data;
|
|
}
|
|
}
|
|
|
|
return XR_OK;
|
|
}
|
|
|
|
/**
|
|
****************************************************************************************
|
|
* @brief Only applicable Master & Slave communication
|
|
*
|
|
* @param[in]
|
|
* @param[in]
|
|
****************************************************************************************
|
|
*/
|
|
void xc_spi_write_and_read_data(uint8_t reg_idx, uint8_t *w_data, uint16_t w_size,
|
|
uint8_t *r_data, uint16_t r_size)
|
|
{
|
|
if (w_size != (spi_rxftl_get(reg_idx) + 1) * 2)
|
|
return;
|
|
xc_spi_datasize_set(reg_idx, SSI_CTRL0_DFS_LEN_16BIT);
|
|
xc_spi_write_bytes(reg_idx, w_data, w_size);
|
|
|
|
while (!(spi_is_get(reg_idx) == SSI_IS_RXFIS_SET))
|
|
;
|
|
xc_spi_read_bytes(reg_idx, r_data, r_size);
|
|
xc_spi_disable(reg_idx);
|
|
}
|
|
|
|
#endif // XC_CHECK(XC_SPI_ENABLED)
|