xushaoxiang
151 lines
4.5 KiB
C
151 lines
4.5 KiB
C
/*!
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* \file xc6xxx_hal_wdt.c
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*
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* \brief Target xc6xxx hal wdt implementation
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/*------------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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--------------------------------------------------------------------------------------*/
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#include "xc_drv_wdt.h"
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#if XC_CHECK(XC_WDT_ENABLED)
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/*------------------------------------------------------------------------------------
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Local Variables
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Func Prototype
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Functions
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-------------------------------------------------------------------------------------*/
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void xc_wdt_init(WDT_InitCfg_t *wdt_cfg)
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{
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cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
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cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
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/*
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SYS_DISABLE | M0_ENABLE : SYS RST, for low-power reset or quick system reset;
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SYS_ENABLE | M0_DISABLE: M0 RST, only for m0 reset;
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SYS_DISABLE | M0_DISABLE: M0 RST, m0 reset and low-power reset;
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*/
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cpr_rstctl_wdtrst_mask_set(
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(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
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cpr_lp_ctl__wdt_pclk_sel__setf(wdt_cfg->PclkSel);
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cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
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wdt_cr__wdt_rmod__setf(wdt_cfg->WorkMode);
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wdt_torr__wdt_top__setf(wdt_cfg->ReloadValue);
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}
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void xc_wdt_start(void)
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{
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wdt_cr__wdt_rpl__setf(WDT_CR_RPL_4PCLK);
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wdt_cr__wdt_en__setf(ENABLE);
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wdt_crr__setf(WDT_CRR_CRR_ENABLE);
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cpr_ctlapbclken_grctl__wdt_pclk_en__setf(DISABLE);
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}
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void xc_ext32k_wdt_init(WDT_InitCfg_t *wdt_cfg)
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{
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cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
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cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
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/*
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SYS_DISABLE | M0_ENABLE : SYS RST, for low-power reset or quick system reset;
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SYS_ENABLE | M0_DISABLE: M0 RST, only for m0 reset;
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SYS_DISABLE | M0_DISABLE: M0 RST, m0 reset and low-power reset;
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*/
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cpr_rstctl_wdtrst_mask_set(
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(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
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// cpr_rstctl_wdtrst_mask_set(
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// (WDT_SYS_RSTN_MASK_ENABLE | WDT_M0_RSTN_MASK_DISABLE));
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cpr_lp_ctl__wdt_pclk_sel__setf(wdt_cfg->PclkSel);
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cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
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wdt_cr__wdt_rmod__setf(wdt_cfg->WorkMode);
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wdt_torr__wdt_top__setf(wdt_cfg->ReloadValue);
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}
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void xc_ext32k_wdt_start(void)
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{
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wdt_cr__wdt_rpl__setf(WDT_CR_RPL_4PCLK);
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wdt_cr__wdt_en__setf(ENABLE);
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wdt_crr__setf(WDT_CRR_CRR_ENABLE);
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}
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void xc_wdt_stop(void)
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{
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wdt_cr__wdt_en__setf(DISABLE);
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}
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void xc_wdt_refresh(void)
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{
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GLOBAL_INT_DISABLE();
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cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
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uint8_t val = wdt_icr_get();
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val = wdt_torr__wdt_top__getf();
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wdt_torr__wdt_top__setf(val);
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cpr_ctlapbclken_grctl__wdt_pclk_en__setf(DISABLE);
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GLOBAL_INT_RESTORE();
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}
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void xc_wdt_reload(void)
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{
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GLOBAL_INT_DISABLE();
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cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
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uint8_t val = wdt_icr_get();
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val = wdt_torr__wdt_top__getf();
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wdt_torr__wdt_top__setf(val);
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wdt_crr__setf(WDT_CRR_CRR_ENABLE);
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cpr_ctlapbclken_grctl__wdt_pclk_en__setf(DISABLE);
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GLOBAL_INT_RESTORE();
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}
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void WDT_Handler()
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{
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DEBUG("WDT_Handler\n");
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#if ((XTAL_32K) && (!defined(NO_SUPPORT_LFCLK_XTAL_32768)))
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cprao_aon_ctl_clk32k_set(0x109);
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WDT_InitCfg_t wdt_cfg ;
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wdt_cfg.WorkMode = WDT_WORK_MODE0;
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wdt_cfg.ReloadValue = WDT_CLK_32M_RESET_MODE0_4096US;
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wdt_cfg.PclkSel = WDT_WORK_32M;
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xc_wdt_init(&wdt_cfg);
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xc_wdt_start();
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while(1);
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#endif
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xc_wdt_refresh();
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}
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#endif // XC_CHECK(XC_WDT_ENABLED)
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