MARVEL/pwm32e_pro
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

V1.0

Browse Source
This commit is contained in:
moyuhai
2026-06-09 16:39:17 +08:00
commit 41a602f89c
3057 changed files with 771495 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
component/xc6xx_drivers/test_case/SPI/spi_master.c
+208
View File
@@ -0,0 +1,208 @@
/*!
* \file spi_master.c
*
* \brief Target spi master device implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "spi_master.h"
#include "xc6xxx_hal_spi.h"
#include "xc6xxx_hal_spi_dmac.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define MS_BUFFER_LEN 64U
#define MS_NODMA_BUFFER_LEN 16U
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
volatile uint8_t m_wr_buff[MS_BUFFER_LEN] = {0};
volatile uint8_t m_rd_buff[MS_BUFFER_LEN] = {0};
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
* @return[out]
*
****************************************************************************************
*/
void spi_dma_master_demo(void) {
DEBUG("__SPI_DMA_MASTER_DEMO__\n");
GPIO_InitTypeDef gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
gpio_cfg.FunSel = SSI1_CLK;
gpio_cfg.Int = NOT_INT;
gpio_cfg.Pull = GPIO_PULLDOWN;
gpio_cfg.Pin = GPIO_5; // GPIO_24; //GPIO_14;
GPIO_Init(&gpio_cfg);
gpio_cfg.FunSel = SSI1_SSN;
gpio_cfg.Pin = GPIO_15; // GPIO_15;
GPIO_Init(&gpio_cfg);
gpio_cfg.FunSel = SSI1_TX;
gpio_cfg.Pin = GPIO_16;
GPIO_Init(&gpio_cfg);
gpio_cfg.FunSel = SSI1_RX;
gpio_cfg.Pin = GPIO_17;
GPIO_Init(&gpio_cfg);
SPI_TypeDef *spi_idx = XC_SPI1; // XC_SPI0;//XC_SPI1;
SPI_InitCfg_t spi_cfg = {0};
spi_cfg.Mode = SPI_MODE_MASTER;
spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
spi_cfg.BaudRatePrescaler =
SPI_BAUDRATEPRESCALER_4; // SPI_BAUDRATEPRESCALER_2;
spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
spi_cfg.CLKPhase = SSI_CTRL0_SCPHA_TRAIL;
spi_cfg.FirstBit = SPI_FirstBit_MSB;
xc_spi_init(spi_idx, &spi_cfg);
NVIC_EnableIRQ(DMA_IRQn);
memset((uint8_t *)m_wr_buff, 0x55, sizeof(m_wr_buff));
DEBUG("Write buffer: \n");
for (uint16_t i = 0; i < sizeof(m_wr_buff); i++) {
PRINT("%02x ", m_wr_buff[i]);
}
PRINT("\n");
SPI_DMA_WriteAndReadData(spi_idx, (uint8_t *)m_wr_buff, sizeof(m_wr_buff),
(uint8_t *)m_rd_buff, sizeof(m_rd_buff));
DEBUG("__SPI_READ_END__\n");
for (uint16_t i = 0; i < sizeof(m_rd_buff); i++) {
PRINT("%02x ", m_rd_buff[i]);
}
PRINT("\n");
memset((uint8_t *)m_wr_buff, 0xaa, sizeof(m_wr_buff));
SPI_DMA_WriteAndReadData(spi_idx, (uint8_t *)m_wr_buff, sizeof(m_wr_buff),
(uint8_t *)m_rd_buff, sizeof(m_rd_buff));
DEBUG("__SPI_READ_END2__\n");
for (uint16_t i = 0; i < sizeof(m_rd_buff); i++) {
PRINT("%02x ", m_rd_buff[i]);
}
PRINT("\n");
}
/**
* @brief spi_master_demo
* @details
* @param void
* @retval void
*/
void spi_master_demo(void) {
DEBUG("__SPI_MASTER_DEMO__\r");
SPI_InitCfg_t spi_cfg = {0};
GPIO_InitTypeDef gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
gpio_cfg.FunSel = SSI1_CLK;
gpio_cfg.Int = NOT_INT;
gpio_cfg.Pull = GPIO_PULLDOWN;
gpio_cfg.Pin = GPIO_5;
GPIO_Init(&gpio_cfg);
gpio_cfg.FunSel = SSI1_SSN;
gpio_cfg.Pin = GPIO_15;
GPIO_Init(&gpio_cfg);
gpio_cfg.FunSel = SSI1_TX;
gpio_cfg.Pin = GPIO_16;
GPIO_Init(&gpio_cfg);
gpio_cfg.FunSel = SSI1_RX;
gpio_cfg.Pin = GPIO_17;
GPIO_Init(&gpio_cfg);
spi_cfg.Mode = SPI_MODE_MASTER;
spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
spi_cfg.BaudRatePrescaler = SSI_BAUD_DIV_8;
spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
spi_cfg.CLKPhase = SSI_CTRL0_SCPHA_TRAIL;
spi_cfg.FirstBit = SPI_FirstBit_MSB;
SPI_TypeDef *spi_handle = XC_SPI1;
xc_spi_init(spi_handle, &spi_cfg);
uint8_t txbuff[MS_NODMA_BUFFER_LEN];
uint8_t rxbuff[MS_NODMA_BUFFER_LEN];
SPI_RXFTL_Set(XC_SPI1, 0x07);
SPI_IE_Enable(XC_SPI1, SSI_IE_RXFIE_ENABLE);
DEBUG("Write buffer: \n");
memset((uint8_t *)txbuff, 0xaa, sizeof(txbuff));
for (int i = 0; i < sizeof(txbuff); i++) {
PRINT("%02x ", txbuff[i]);
}
PRINT("\n");
spi_write_and_read_data(spi_handle, (uint8_t *)txbuff, sizeof(txbuff),
(uint8_t *)rxbuff, sizeof(rxbuff));
DEBUG("Read buffer:\n");
for (int i = 0; i < sizeof(rxbuff); i++) {
PRINT("%02x ", rxbuff[i]);
}
PRINT("\n");
DEBUG("__SPI_END__\n");
DEBUG("Write buffer: \n");
memset((uint8_t *)txbuff, 0x55, sizeof(txbuff));
for (int i = 0; i < sizeof(txbuff); i++) {
PRINT("%02x ", txbuff[i]);
}
PRINT("\n");
spi_write_and_read_data(spi_handle, (uint8_t *)txbuff, sizeof(txbuff),
(uint8_t *)rxbuff, sizeof(rxbuff));
DEBUG("Read buffer:\n");
for (int i = 0; i < sizeof(rxbuff); i++) {
PRINT("%02x ", rxbuff[i]);
}
PRINT("\n");
DEBUG("__SPI_END2__\n");
}