/***************************************************************************************** * * @file rf_extrc.c * * @brief External Radio Controller initialization and specific functions * * Copyright (C) RivieraWaves 2009-2017 * * *****************************************************************************************/ /***************************************************************************************** * @addtogroup RF_EXTRC * @ingroup RF * @brief External Radio Controller Driver * * This is the driver block for external radio controller * @{ *****************************************************************************************/ /***************************************************************************************** * INCLUDE FILES ****************************************************************************************/ #include "rwip_config.h" // RW SW configuration #include "co_math.h" // common math functions #include "co_utils.h" // common utility definition #include "em_map.h" // exchange table #include "plf.h" // Platform functions #include "rf.h" // RF interface #include "rwip.h" // for RF API structure definition #include // for memcpy #include "reg_ipcore.h" // DM core registers #include "xc_drv_gpio.h" #if (BLE_EMB_PRESENT) #include "reg_blecore.h" // ble core registers #include "reg_em_ble_cs.h" // control structure definitions #endif //(BLE_EMB_PRESENT) #if (BT_EMB_PRESENT) #include "reg_btcore.h" // bt core registers #include "reg_em_bt_cs.h" // control structure definitions #endif //(BT_EMB_PRESENT) /***************************************************************************************** * DEFINES ****************************************************************************************/ #define RF_GAIN_TBL_SIZE (8) #define RF_PWR_TBL_SIZE (8) #define RF_RSSI_20dB_THRHLD -20 #define RF_RSSI_40dB_THRHLD -40 #define RF_RSSI_45dB_THRHLD -45 #define RF_RSSI_48dB_THRHLD -48 #define RF_RSSI_55dB_THRHLD -55 #define RF_RSSI_60dB_THRHLD -60 #define RF_RSSI_70dB_THRHLD -70 // TX max power #define RF_POWER_MAX 7 #define RF_POWER_MIN 1 #define RF_POWER_MSK 0x07 /***************************************************************************************** * GLOBAL VARIABLE DEFINITIONS ****************************************************************************************/ // Power table __STATIC const int8_t RF_TX_PW_CONV_TBL[RF_PWR_TBL_SIZE] = { [0] = -23, [1] = -20, [2] = -17, [3] = -14, [4] = -11, [5] = -8, [6] = -5, [7] = -2}; /***************************************************************************************** * FUNCTION DEFINITIONS ****************************************************************************************/ /***************************************************************************************** * @brief Read access * * @param[in] addr register address * * @return uint32_t value ****************************************************************************************/ __STATIC uint32_t rf_reg_rd(uint32_t addr) { return 0; } /***************************************************************************************** * @brief Write access * * @param[in] addr register address * @param[in] value value to write ****************************************************************************************/ __STATIC void rf_reg_wr(uint32_t addr, uint32_t value) { return; } /***************************************************************************************** * @brief Initialize frequency table in the exchange memory ****************************************************************************************/ __STATIC void rf_em_init(void) { uint8_t idx = 0; uint8_t temp_freq_tbl[EM_RF_FREQ_TABLE_LEN]; #if (BT_EMB_PRESENT) // First half part of frequency table is for the even frequencies while (idx < (EM_RF_FREQ_TABLE_LEN / 2)) { temp_freq_tbl[idx] = 2 * idx; idx++; } while (idx < EM_RF_FREQ_TABLE_LEN) { temp_freq_tbl[idx] = 2 * (idx - (EM_RF_FREQ_TABLE_LEN / 2)) + 1; idx++; } em_wr(&temp_freq_tbl[0], EM_FT_OFFSET, EM_RF_FREQ_TABLE_LEN); #elif (BLE_EMB_PRESENT) while (idx < EM_RF_FREQ_TABLE_LEN) { temp_freq_tbl[idx] = 2 * idx; idx++; } em_wr(&temp_freq_tbl[0], EM_FT_OFFSET, EM_RF_FREQ_TABLE_LEN); #endif //(BT_EMB_PRESENT/BLE_EMB_PRESENT) } /** ***************************************************************************************** * @brief Convert RSSI to dBm * * @param[in] rssi_reg RSSI read from the HW registers * * @return The converted RSSI ***************************************************************************************** */ extern volatile uint8_t evt_start; __RAM_CODE __STATIC int8_t rf_rssi_convert(uint8_t rssi_reg) { int8_t rssi_dbm; // uint16_t power_modem; if (rssi_reg < 128) { rssi_dbm = rssi_reg - 50; } else { rssi_dbm = rssi_reg - 256 - 50; } #if (CONN_RSSI_DEBUG) if(evt_start){ printf("con rssi %d\n", rssi_dbm); } #endif return (rssi_dbm); } /** ***************************************************************************************** * @brief Get the TX power as control structure TX power field from a value in *dBm. * * @param[in] txpwr_dbm TX power in dBm * @param[in] option If TXPWR_CS_LOWER, return index equal to or lower than *requested If TXPWR_CS_HIGHER, return index equal to or higher than requested * If TXPWR_CS_NEAREST, return index nearest to the *desired value * * @return The index of the TX power * ***************************************************************************************** */ __STATIC uint8_t rf_txpwr_cs_get(int8_t txpwr_dbm, uint8_t option) { ASSERT_ERR(option <= TXPWR_CS_NEAREST); uint8_t i; for (i = RF_POWER_MIN; i < RF_POWER_MAX; i++) { // Loop until we find a power higher than or equal to the requested one if (RF_TX_PW_CONV_TBL[i] >= txpwr_dbm) break; } if ((RF_TX_PW_CONV_TBL[i] > txpwr_dbm) && (i > RF_POWER_MIN)) { if ((option == TXPWR_CS_LOWER) || ((option == TXPWR_CS_NEAREST) && (co_abs(txpwr_dbm - RF_TX_PW_CONV_TBL[i - 1]) < co_abs(txpwr_dbm - RF_TX_PW_CONV_TBL[i])))) { i--; } } return (i); } /** ***************************************************************************************** * @brief Init RF sequence after reset. ***************************************************************************************** */ __STATIC void rf_reset(void) { return; } #if (BT_EMB_PRESENT) /** ***************************************************************************************** * @brief Decrease the TX power by one step * * @param[in] link_id Link ID for which the TX power has to be decreased * * @return true when minimum power is reached, false otherwise ***************************************************************************************** */ __STATIC bool rf_txpwr_dec(uint8_t link_id) { // Get current TX power value uint8_t tx_pwr = em_bt_pwrcntl_txpwr_getf(EM_BT_CS_ACL_INDEX(link_id)) & RF_POWER_MSK; // Check if value can be decreased if (tx_pwr > RF_POWER_MIN) { // Decrease the TX power value em_bt_pwrcntl_txpwr_setf(EM_BT_CS_ACL_INDEX(link_id), tx_pwr - 1); } return (tx_pwr > RF_POWER_MIN); } /** ***************************************************************************************** * @brief Increase the TX power by one step * * @param[in] link_id Link ID for which the TX power has to be increased * * @return true when maximum power is reached, false otherwise ***************************************************************************************** */ __STATIC bool rf_txpwr_inc(uint8_t link_id) { // Get current TX power value uint8_t tx_pwr = em_bt_pwrcntl_txpwr_getf(EM_BT_CS_ACL_INDEX(link_id)) & RF_POWER_MSK; // Check if value can be increased if (tx_pwr < RF_POWER_MAX) { // Increase the TX power value em_bt_pwrcntl_txpwr_setf(EM_BT_CS_ACL_INDEX(link_id), tx_pwr + 1); } return (tx_pwr < RF_POWER_MAX); } /** **************************************************************************************** * @brief Set the TX power to max * * @param[in] link_id Link Identifier **************************************************************************************** */ __STATIC void rf_txpwr_max_set(uint8_t link_id) { // Set max TX power value em_bt_pwrcntl_txpwr_setf(EM_BT_CS_ACL_INDEX(link_id), RF_POWER_MAX); } #endif //(BT_EMB_PRESENT) #if (BLE_EMB_PRESENT) /** ***************************************************************************************** * @brief Enable/disable force AGC mechanism * * @param[in] True: Enable / False: disable ***************************************************************************************** */ __STATIC void rf_force_agc_enable(bool en) { return; } #endif //(BLE_EMB_PRESENT) /** ***************************************************************************************** * @brief Get TX power in dBm from the index in the control structure * * @param[in] txpwr_idx Index of the TX power in the control structure * @param[in] modulation Modulation: 1 or 2 or 3 MBPS * * @return The TX power in dBm ***************************************************************************************** */ __STATIC int8_t rf_txpwr_dbm_get(uint8_t txpwr_idx, uint8_t modulation) { // power table is the same for BR and EDR return (RF_TX_PW_CONV_TBL[txpwr_idx]); } /** ***************************************************************************************** * @brief Sleep function for the RF. ***************************************************************************************** */ __STATIC void rf_sleep(void) { ip_deepslcntl_set((ip_deepslcntl_get() & (~IP_EXTWKUPDSB_BIT)) | IP_DEEP_SLEEP_ON_BIT | // RW BT Core sleep IP_RADIO_SLEEP_EN_BIT | // Radio sleep IP_OSC_SLEEP_EN_BIT); // Oscillator sleep } #if 0 void rf_test_pin_init(void) { // writel(0x53022040, 6<<4| 6); writel(0x53022040, 6<<4| 0); // writel(0x53022040, 0); xc_gpio_fun_sel(3,0); xc_gpio_mux_ctl(3,3); // en test_pin[0] *((uint32_t volatile*)0x40000170) = 0; xc_gpio_fun_sel(4,0); xc_gpio_mux_ctl(4,3); // en test_pin[1] *((uint32_t volatile*)0x40000174) = 1; // xc_gpio_fun_sel(5,0); // xc_gpio_mux_ctl(5,3); // en test_pin[2] // *((uint32_t volatile*)0x40000178) = 2; xc_gpio_fun_sel(6,0); xc_gpio_mux_ctl(6,3); // en test_pin[3] *((uint32_t volatile*)0x4000017c) = 2; // xc_gpio_fun_sel(7,0); // xc_gpio_mux_ctl(7,3); // en test_pin[4] // *((uint32_t volatile*)0x40000180) = 3; xc_gpio_fun_sel(8,0); xc_gpio_mux_ctl(8,3); // en test_pin[5] *((uint32_t volatile*)0x40000184) = 3; // xc_gpio_fun_sel(9,0); // xc_gpio_mux_ctl(9,3); // en test_pin[6] // *((uint32_t volatile*)0x40000188) = 5; xc_gpio_fun_sel(23, GPIO_Dx); xc_gpio_mux_ctl(23, GPIO_Mux3); // en test_pin[7] *((uint32_t volatile*)0x4000018c) = 4; xc_gpio_fun_sel(24, GPIO_Dx); xc_gpio_mux_ctl(24, GPIO_Mux3); // en test_pin[8] *((uint32_t volatile*)0x40000190) = 5; xc_gpio_fun_sel(22,0); xc_gpio_mux_ctl(22,3); // en test_pin[6] *((uint32_t volatile*)0x40000188) = 6; uint32_t val = (*(volatile unsigned *)(0x40000000 + 0x134)); (*(volatile unsigned *)(0x40000000 + 0x134)) = val | (0x1<<28); xc_gpio_fun_sel(15,0); xc_gpio_mux_ctl(15,3); // en test_pin[0] xc_gpio_fun_sel(16,0); xc_gpio_mux_ctl(16,3); // en test_pin[1] xc_gpio_fun_sel(5,0); xc_gpio_mux_ctl(5,3); // en test_pin[3] xc_gpio_fun_sel(26,0); xc_gpio_mux_ctl(26,3); // en test_pin[4] xc_gpio_fun_sel(27,0); xc_gpio_mux_ctl(27,3); // en test_pin[5] xc_gpio_fun_sel(28,0); xc_gpio_mux_ctl(28,3); // en test_pin[6] // xc_gpio_fun_sel(29,0); // xc_gpio_mux_ctl(29,3); // en test_pin[7] // xc_gpio_fun_sel(30,0); // xc_gpio_mux_ctl(30,3); // en test_pin[8] } #endif /**************************************************************************************** * MODEM FUNCTION INTERFACE ***************************************************************************************/ void delay_ms_test() { for (volatile int i = 0; i < 1000; i++) { } } #define RF_BASE (0x53021000) #define rf_ana0 (RF_BASE + 0 * 0x4) // 0x53021000 #define rf_ana1 (RF_BASE + 1 * 0x4) // 0x53021004 #define rf_ana2 (RF_BASE + 2 * 0x4) // 0x53021008 #define rf_ana3 (RF_BASE + 3 * 0x4) // 0x5302100c #define rf_ana4 (RF_BASE + 4 * 0x4) // 0x53021010 #define rf_ana5 (RF_BASE + 5 * 0x4) // 0x53021014 #define rf_ana6 (RF_BASE + 6 * 0x4) // 0x53021018 #define rf_ana7 (RF_BASE + 7 * 0x4) // 0x5302101C #define rf_ana8 (RF_BASE + 8 * 0x4) // 0x53021020 #define rf_ana9 (RF_BASE + 9 * 0x4) // 0x53021024 #define rf_ana10 (RF_BASE + 10 * 0x4) // 0x53021028 #define rf_ana11 (RF_BASE + 11 * 0x4) // 0x5302102c #define rf_ana12 (RF_BASE + 12 * 0x4) // 0x53021030 #define rf_ana13 (RF_BASE + 13 * 0x4) // 0x53021034 #define rf_ana14 (RF_BASE + 14 * 0x4) // 0x53021038 #define rf_ana15 (RF_BASE + 15 * 0x4) // 0x5302103c #define rf_ana16 (RF_BASE + 16 * 0x4) // 0x53021040 #define rf_ana17 (RF_BASE + 17 * 0x4) // 0x53021044 #define rf_ana18 (RF_BASE + 18 * 0x4) // 0x53021048 #define rf_ana19 (RF_BASE + 19 * 0x4) // 0x5302104c #define rf_ana20 (RF_BASE + 20 * 0x4) // 0x53021050 #define rf_ana21 (RF_BASE + 21 * 0x4) // 0x53021054 #define rf_ana22 (RF_BASE + 22 * 0x4) // 0x53021058 #define rf_ana23 (RF_BASE + 23 * 0x4) // 0x5302105c #define rf_ana24 (RF_BASE + 24 * 0x4) // 0x53021060 #define rf_ana25 (RF_BASE + 25 * 0x4) // 0x53021064 #define rf_ana26 (RF_BASE + 26 * 0x4) // 0x53021068 #define rf_ana27 (RF_BASE + 27 * 0x4) // 0x5302106c #define rf_ana28 (RF_BASE + 28 * 0x4) // 0x53021070 #define rf_ana29 (RF_BASE + 29 * 0x4) // 0x53021074 #define rf_ana30 (RF_BASE + 30 * 0x4) // 0x53021078 #define rf_ana31 (RF_BASE + 31 * 0x4) // 0x5302107c //--- chip realated setting // Rx Parameter Configuration #define EXTRC_RXPWRUP (87) // #define RF_RX_ON_DELAY (70) // #define MODEM_RXON_DELAY (75) #define RF_RX_ON_DELAY (64) #define MODEM_RXON_DELAY (68) #define SYNC_ERR_BIT (7) ////Tx Parameter Configuration // #define EXTRC_TXPWRUP (80) // #define RF_TX_ON_DELAY (70) // #define MODEM_TXON_DELAY (10) // //2M test // #define EXTRC_RXPWRUP (80) // #define RF_RX_ON_DELAY (10) // #define MODEM_RXON_DELAY (15) // #define SYNC_ERR_BIT (6) // Tx Parameter Configuration #define EXTRC_TXPWRUP (87) #define RF_TX_ON_DELAY (75) #define MODEM_TXON_DELAY (32) // //ble1m // #define EXTRC_RFRXTMDA0 8 #define EXTRC_RFRXTMDA0 16 // #define EXTRC_RXPATHDLY0 6 #define EXTRC_RXPATHDLY0 4 // ble2m #define EXTRC_RFRXTMDA1 8 #define EXTRC_RXPATHDLY1 5 // bles8 #define EXTRC_RXFLUSHPATHDLY2 0 #define EXTRC_RFRXTMDA2 136 #define EXTRC_RXPATHDLY2 45 // bles2 #define EXTRC_RXFLUSHPATHDLY3 0 #define EXTRC_RFRXTMDA3 40 #define setbit(x, y) ((x) |= (1 << (y))) #define clrbit(x, y) ((x) &= ~(1 << (y))) static void wbit(uint16_t reg_addr, int end, int start, char *bit_str) { uint16_t reg_val = 0; char ch = 0; uint16_t i = 0; uint16_t s_len = 0; while (*(bit_str + s_len)) s_len++; if (s_len != (end - start + 1)) while (1) ; reg_val = *(uint16_t *)(0x53021000 + reg_addr); // 0X4002F000 for (i = start; i <= end; i++) { int bit_idx = i - start; ch = bit_str[(end - start) - bit_idx] - '0'; if (ch == 1) setbit(reg_val, i); else if (ch == 0) clrbit(reg_val, i); } *(uint16_t *)(0x53021000 + reg_addr) = reg_val; } /*! ******************************************************** * @name wbit * @desc wbit * *********************************************************/ static uint16_t rbit(uint16_t reg_addr) { return *(uint16_t *)(0x53021000 + reg_addr); } void rf_rccalib(void) { static uint8_t rccalib_flag = 0; if (rccalib_flag) return; uint32_t timeout = 0; uint16_t val = 0; wbit(0x0080, 10, 8, "111"); // RG_RCCAL_CTRL(Rccal �����ֵ����) def"100" delay_ms_test(); wbit(0x0080, 5, 5, "1"); // RG_RCCAL_RESETN=1 delay_ms_test(); wbit(0x0080, 3, 3, "0"); // RG_RCCAL_SEL =0 delay_ms_test(); wbit(0x0080, 2, 2, "1"); // RG_RCCAL_EN=1 delay_ms_test(); wbit(0x0080, 4, 4, "1"); // RG_RCCAL_START=1 delay_ms_test(); while (!(rbit(0x0084) & 0x8000)) { // �ȴ�AD_RCCAL_FINISH���� �ó�У׼ֵ // AD_RCCAL_CTRIM if ((timeout++) > 0x10000) break; } val = rbit(0x0084); val = (val & 0x7FFF) >> 10; // ��У׼ֵAD_RCCAL_CTRIM���� wbit(0x0080, 3, 3, "1"); // RG_RCCAL_SEL =1 wbit(0x0080, 2, 2, "0"); // RG_RCCAL_EN=0 wbit(0x0080, 4, 4, "0"); // RG_RCCAL_START=0 char tb[6] = {0}; // �������У׼ֵת�����ַ��� tb[4] = ((val & 0x01) ? '1' : '0'); tb[3] = ((val & 0x02) ? '1' : '0'); tb[2] = ((val & 0x04) ? '1' : '0'); tb[1] = ((val & 0x08) ? '1' : '0'); tb[0] = ((val & 0x10) ? '1' : '0'); wbit(0x0080, 15, 11, tb); rccalib_flag = 1; printf("\nRG_RCCAL_CC:%X \n", rbit(0x80)); } #if 0 void send_Tone(void) { printf("send_Tone \n"); uint32_t value = 0; //ana30<13> 默认0改成1;shdn_tx mux writel(rf_ana30, readl(rf_ana30) | (0x1 << 13)); //ana30<7:0> 默认00000000改成11111111;shdn writel(rf_ana30, readl(rf_ana30) | (0xff )); // ana29<5:4>默认11改成00；sxrstn mux value = readl(rf_ana29) & ~(0x3 << 4); writel(rf_ana29, value); // ana29<2>默认0改成1；dsmrstnspi writel(rf_ana29, readl(rf_ana29) | (0x01 << 2)); // ana27<0>默认0改成1；afcrstnspi writel(rf_ana27, readl(rf_ana27) | (0x01)); //手动开tx_en（5A,5B共用）: //ana29<3>默认0改成1；dacrstnspi writel(rf_ana29, readl(rf_ana29) | (0x01 << 3)); //ana30<14> 默认0改成1;en_tx mux writel(rf_ana30, readl(rf_ana30) | (0x01 << 14)); //ana31<7:2>默认000000改成111111;tx_en writel(rf_ana31, readl(rf_ana31) | (0x3f << 2)); // 发送单载波 writel(rf_ana29, readl(rf_ana29) | (0x01 << 1)); // 手动afc mux开关ana29<1>默认0改成1， writel(rf_ana28, readl(rf_ana28) | (0x01)); // ana28<0> 拉高 delay_ms_test(); value = readl(0x53022064) & ~(0x1FFFFFFF << 4);writel(0x53022064, value | 0x896A << 16); // 2410 writel(rf_ana28, readl(rf_ana28) & ~(0x01)); // ana28<0> 默认0 //value = readl(0x53022064) & ~(0x1FFFFFFF << 4);writel(0x53022064, value | 0x8962 << 16| 0xa4000); // 2402 delay_ms_test(); writel(rf_ana28, readl(rf_ana28) | (0x01)); // ana28<0> 拉高 while (1){ // value = readl(0x53022064) & ~(0x1FFFFFFF<<4); writel(0x53022064, value | 0x8970<<16|0x28f); //2416 tone +10k // delay_ms_test(); // value = readl(0x53022064) & ~(0x1FFFFFFF<<4); writel(0x53022064, value | 0x8960<<16|0xffd70); //2416 tone -10k // delay_ms_test(); value = readl(0x53022064) & ~(0x1FFFFFFF<<4); writel(0x53022064, value | 0x8960<<16|0xe028f); //2416 tone +10k delay_ms_test(); value = readl(0x53022064) & ~(0x1FFFFFFF<<4); writel(0x53022064, value | 0x8960<<16|0xdfd70); //2416 tone -10k delay_ms_test(); }; } #endif void auto_agc_init() { *((uint32_t volatile *)0x5302109c) = ((0x0) << 10 | (0x0) << 4); // bt_rx_vga_map6/7 *((uint32_t volatile *)0x530210A0) = ((0x0) << 10 | (0x4) << 4); // bt_rx_vga_map8/9 *((uint32_t volatile *)0x530210A4) = ((0x8) << 10 | (0xc) << 4); // bt_rx_vga_map10/11 *((uint32_t volatile *)0x530210A8) = ((0x10) << 10 | (0x14) << 4); // bt_rx_vga_map12/13 *((uint32_t volatile *)0x530210Ac) = ((0x18) << 10 | (0x1c) << 4); // bt_rx_vga_map14/15 // w4 0x53022000 0x97a0 *((uint32_t volatile *)0x53022018) = (0x0 << 24) | (0x0 << 16) | (0x0 << 8) | (0x0); // hw_cfg_rf_abb_gain0-3 *((uint32_t volatile *)0x5302201c) = (0x0 << 24) | (0x0 << 16) | (0x0 << 8) | (0x0); *((uint32_t volatile *)0x53022020) = (0x8 << 24) | (0x4 << 16) | (0x2 << 8) | (0x0); *((uint32_t volatile *)0x53022024) = (0xe << 24) | (0xc << 16) | (0xa << 8) | (0x8); // *((uint32_t volatile*)0x530210A0) = ((8<<2)<<10 | (9<<2)<<4); // //bt_rx_vga_map8/9 // *((uint32_t volatile*)0x530210A4) = ((9<<2)<<10 | (9<<2)<<4); // //bt_rx_vga_map10/11 // *((uint32_t volatile*)0x530210A8) = ((9<<2)<<10 | (9<<2)<<4); // //bt_rx_vga_map12/13 // *((uint32_t volatile*)0x530210Ac) = ((9<<2)<<10 | (9<<2)<<4); // //bt_rx_vga_map14/15 *((uint32_t volatile *)0x53022000) = ( // 0<<0 | //0 enable // 1<<1 | //1 hw_agc_sel 0 << 1 | // agc_en_mode 0 << 4 | // 16 agc_adc_en_sw 1 << 5 | // 17 hw_agc_ctrl_enable 0 << 6 | // 18 cfg_cci_gain_mode 1 << 7 | // rw rssi sel 7 << 8 | // 23:20 cfg_LNA_init 9 << 12); // 27:24 cfg_ABB_init *((uint32_t volatile *)0x5302200c) = 25; // cfg_turner_gain } void rf_xtal_cal_set(uint8_t set_value) { uint32_t value; value = readl(CPRAO_AON_RF_AONREG_ADDR) & ~(0x3F << 20); writel(CPRAO_AON_RF_AONREG_ADDR, value | (set_value << 20)); } void modem_init(void) { uint32_t value = 0; // open bt clock writel(0x40000040, readl(0x40000040) | (0x01 << 4) | 0xFFFF0000); // 0x40[4] bt_clk_en writel(0x40000048, readl(0x40000048) | (0x01 << 4) | 0xFFFF0000); // 0x48[4] bt_modem_clk_en writel(0x40000070, readl(0x40000070) | (0x01 << 10) | 0xFFFF0000); // 0x70[10]bt_pclk_en writel(0x40000074, readl(0x40000074) | (0x01 << 2) | 0xFFFF0000); // 0x74[2] bt32k_clk_en writel(0x4000247c, 0x200020); // bt32k_clk_ao_en writel(0x53022048, ((MODEM_TXON_DELAY << 8) | MODEM_RXON_DELAY)); writel(0x53020368, readl(0x53020368) | (0x01 << 31)); // EXT_CORRCODE_EN[31] writel(0x53020204, readl(0x53020204) | (0x01 << 2)); // int_rx_cfg_sel = 1 writel(0x53022044, readl(0x53022044) & ~(0x1 << 13)); // neg sample adc writel(0x530210B0, readl(0x530210B0) & 0xFFFF | (1 << 14)); // bt_en_pm = 1 writel(0x40002450, 1); // CPR_AO BB_CORELDORF_EN writel(0x53020244, readl(0x53020244) & 0xFFFF | (0x1e00 << 16)); // int_fe_ifshift1[12:0] 512->1M IF writel(0x5302204C, RF_TX_ON_DELAY << 8 | RF_RX_ON_DELAY); // rf_delay_ctrl writel(0x530210B8, (0x1 << 0x1) | (0x1 << 0x2)); // 正常工作 writel(0x53020214, 0x1); // SYNC_ERR_BLE value = readl(0x53020368) & ~(0x7 << 8); writel(0x53020368, value | (SYNC_ERR_BIT << 8)); writel(rf_ana29, readl(rf_ana29) & ~(0x01 << 1)); writel(rf_ana2, 0x615f); rf_rccalib(); #if CFG_RSSI_ENABLE //auto_agc auto_agc_init(); #else ////ana0<7>默认0改成1，进入手动agc模式。用ana0<6:0>配置增益 value = readl(rf_ana0); writel(rf_ana0, value | (0x1 << 7)); // value = readl(rf_ana0) & (~0x7f) ; writel(rf_ana0, value | (0x7A)); value = readl(rf_ana0) & (~0x7f); writel(rf_ana0, value | (0x77)); #endif #ifdef USED_DCDC writel(rf_ana21, TRANS_POWER_9_2DBM); #error #else writel(rf_ana21, TRANS_POWER_NEGTIVE_8_9_DBM); #endif // USED_DCDC // 配置 VCO 电流ana18<2:0> --000, ana18<5:3> --001 value = readl(rf_ana18) & ~(0x7); writel(rf_ana18, value); value = readl(rf_ana18) & ~(0x7 << 3); writel(rf_ana18, (value | (0x1 << 3))); value = readl(rf_ana2) & ~(0xf << 5); writel(rf_ana2, value | (0x8 << 5)); value = readl(rf_ana24); value=0x952c; writel(rf_ana24, value); #ifdef VCO_POWER // ana4<15:12>默认1001（量产版默认值1000）改成0000 value = readl(rf_ana4) & ~(0xf << 12); writel(rf_ana4, value); // ana18<5:3>默认000改成001； value = readl(rf_ana18) | (0x001 << 3); writel(rf_ana18, value); // ana18<2:0>默认101改成000； value = readl(rf_ana18) & ~(0x7 << 0); writel(rf_ana18, value); // ana28<4:2>默认100改成000. value = readl(rf_ana28) & ~(0x7 << 2); writel(rf_ana28, value); #endif // VCO_POWER // rf_test_pin_init(); } /**************************************************************************************** * RADIO FUNCTION INTERFACE ***************************************************************************************/ void rf_init(struct rwip_rf_api *api) { // ******************************************************** // * Initialize the RF driver API structure * // ******************************************************** api->reg_rd = rf_reg_rd; api->reg_wr = rf_reg_wr; api->txpwr_dbm_get = rf_txpwr_dbm_get; api->txpwr_min = RF_POWER_MIN; api->txpwr_max = RF_POWER_MAX; api->sleep = rf_sleep; api->reset = rf_reset; api->rssi_convert = rf_rssi_convert; api->txpwr_cs_get = rf_txpwr_cs_get; #if (BLE_EMB_PRESENT) api->force_agc_enable = rf_force_agc_enable; #endif //(BLE_EMB_PRESENT) #if (BT_EMB_PRESENT) api->txpwr_dec = rf_txpwr_dec; api->txpwr_inc = rf_txpwr_inc; api->txpwr_max_set = rf_txpwr_max_set; #endif //(BT_EMB_PRESENT) api->rssi_interf_thr = RF_RSSI_70dB_THRHLD; api->rssi_high_thr = RF_RSSI_40dB_THRHLD; api->rssi_low_thr = RF_RSSI_60dB_THRHLD; #if (HCI_TEST_NO_IP) return; #endif // ******************************************************** // * Initialize Exchange Memory * // ******************************************************** rf_em_init(); // ******************************************************** // * Initialize BLE/BT Core Registers * // ******************************************************** /* BLE RADIOCNTL0 */ ip_radiocntl0_pack(/*uint16_t spiptr*/ 0, /*uint8_t spicfg*/ 0, /*uint8_t spifreq*/ 0, /*uint8_t spigo*/ 0); /* BLE RADIOCNTL1 */ ip_radiocntl1_pack(/*uint8_t forceagcen*/ 0, /*uint8_t forceiq*/ 0, /*uint8_t rxdnsl*/ 0, /*uint8_t txdnsl*/ 0, /*uint16_t forceagclength*/ 0, /*uint8_t syncpulsemode*/ 0, /*uint8_t syncpulsesrc*/ 0, /*uint8_t dpcorren*/ 0, /*uint8_t jefselect*/ 1, /*uint8_t xrfsel*/ 2, /*uint8_t subversion*/ 0); #if (BLE_EMB_PRESENT) uint8_t dely1, dely2, dely3, dely4; ble_radiocntl2_phymsk_setf( 0x3); // mark that 2mbps and Coded phy are supported for TLM /* BLE RADIOPWRUPDN0 */ ble_radiopwrupdn0_pack(/*uint8_t syncposition0*/ 0, /*uint8_t rxpwrup0*/ EXTRC_RXPWRUP, /*uint8_t txpwrdn0*/ 07, /*uint8_t txpwrup0*/ EXTRC_TXPWRUP); ble_radiopwrupdn0_unpack(&dely1, &dely2, &dely3, &dely4); /* BLE RADIOPWRUPDN1 */ ble_radiopwrupdn1_pack(/*uint8_t syncposition1*/ 0, /*uint8_t rxpwrup1*/ EXTRC_RXPWRUP, /*uint8_t txpwrdn1*/ 07, /*uint8_t txpwrup1*/ EXTRC_TXPWRUP); ble_radiopwrupdn1_unpack(&dely1, &dely2, &dely3, &dely4); /* BLE RADIOPWRUPDN2 */ ble_radiopwrupdn2_pack(/*uint8_t syncposition2*/ 0, /*uint8_t rxpwrup2*/ EXTRC_RXPWRUP, /*uint8_t txpwrdn2*/ 07, /*uint8_t txpwrup2*/ EXTRC_TXPWRUP); ble_radiopwrupdn2_unpack(&dely1, &dely2, &dely3, &dely4); /* BLE RADIOPWRUPDN3 */ ble_radiopwrupdn3_pack(/*uint8_t txpwrdn3*/ 07, /*uint8_t txpwrup3*/ EXTRC_TXPWRUP); ble_radiopwrupdn3_unpack(&dely1, &dely2); /* BLE RADIOTXRXTIM0 */ ble_radiotxrxtim0_pack(/*uint8_t rfrxtmda0*/ EXTRC_RFRXTMDA0, /*uint8_t rxpathdly0*/ EXTRC_RXPATHDLY0, /*uint8_t txpathdly0*/ 4); ble_radiotxrxtim0_unpack(&dely1, &dely2, &dely3); /* BLE RADIOTXRXTIM1 */ ble_radiotxrxtim1_pack(/*uint8_t rfrxtmda1*/ EXTRC_RFRXTMDA1, /*uint8_t rxpathdly1*/ EXTRC_RXPATHDLY1, /*uint8_t txpathdly1*/ 3); ble_radiotxrxtim1_unpack(&dely1, &dely2, &dely3); /* BLE RADIOTXRXTIM2 */ ble_radiotxrxtim2_pack(/*uint8_t rxflushpathdly2*/ EXTRC_RXFLUSHPATHDLY2, /*uint8_t rfrxtmda2*/ EXTRC_RFRXTMDA2, /*uint8_t rxpathdly2*/ EXTRC_RXPATHDLY2, /*uint8_t txpathdly2*/ 4); ble_radiotxrxtim2_unpack(&dely1, &dely2, &dely3, &dely4); /* BLE RADIOTXRXTIM3 */ ble_radiotxrxtim3_pack(/*uint8_t rxflushpathdly3*/ EXTRC_RXFLUSHPATHDLY3, /*uint8_t rfrxtmda3*/ EXTRC_RFRXTMDA3, /*uint8_t txpathdly3*/ 4); ble_radiotxrxtim3_unpack(&dely1, &dely2, &dely3); #endif //(BLE_EMB_PRESENT) #if (BT_EMB_PRESENT) /* EDRCNTL */ bt_rwbtcntl_nwinsize_setf(NORMAL_WIN_SIZE / 2); bt_edrcntl_rxgrd_timeout_setf(0x12); bt_edrcntl_rx_swap_setf(1); bt_edrcntl_tx_swap_setf(1); /* BT RADIOPWRUPDN */ bt_radiopwrupdn_rxpwrupct_setf(EXTRC_RXPWRUP); bt_radiopwrupdn_txpwrdnct_setf(7); bt_radiopwrupdn_txpwrupct_setf(EXTRC_TXPWRUP); /* IP RADIOCNTL */ ip_radiocntl0_spifreq_setf(0); ip_radiocntl0_spigo_setf(0); ip_radiocntl0_spiptr_setf(0); ip_radiocntl1_forceagc_length_setf(0); ip_radiocntl1_sync_pulse_mode_setf(1); // SYNC_PULSE_SRC ip_radiocntl1_dpcorr_en_setf(0); ip_radiocntl1_xrfsel_setf(2); // xrfsel is 2 in our platform ip_radiocntl1_forceagc_en_setf(0); /* BT RADIOTXRXTIM */ bt_radiotxrxtim_rxpathdly_setf(24); // 21->24 2022/4/13 bt_radiotxrxtim_txpathdly_setf(1); bt_radiotxrxtim_sync_position_setf(0); /* BT RADIOCNTL 2 */ bt_radiocntl2_freqtable_ptr_setf((EM_FT_OFFSET >> 2)); bt_radiocntl2_syncerr_setf(0x7); /* BT RADIOCNTL3 */ bt_radiocntl3_rxrate0cfg_setf(1); bt_radiocntl3_txrate0cfg_setf(1); bt_radiocntl3_pack(/*uint8_t rxrate2cfg*/ 3, /*uint8_t rxrate1cfg*/ 2, /*uint8_t rxrate0cfg*/ 1, /*uint8_t getrssidelay*/ 0, /*uint8_t rxserparif*/ 0, /*uint8_t rxsyncrouting*/ 0, /*uint8_t rxvalidbeh*/ 0, /*uint8_t txrate2cfg*/ 3, /*uint8_t txrate1cfg*/ 2, /*uint8_t txrate0cfg*/ 1, /*uint8_t txserparif*/ 0, /*uint8_t txvalidbeh*/ 0); #endif //(BT_EMB_PRESENT) } ///@} RF_EXTRC