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/*!
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* \file xc_hal_ll_usb_np.h
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*
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* \brief USB Low Layer HAL module driver.(use non-periodic fifo)
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author MCD Application Team
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*
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* \author ( XinChip ) Alex-J
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*/
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#ifndef __XC_HAL_LL_USB_NP_H
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#define __XC_HAL_LL_USB_NP_H
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "xc_usb_bitfields.h"
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#include "xc6xxx.h"
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/*------------------------------------------------------------------------------------
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Typedef
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------------------------------------------------------------------------------------*/
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#if defined (USB_OTG_FS)
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/**
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* @brief USB Mode definition
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*/
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typedef enum
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{
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USB_DEVICE_MODE = 0,
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USB_HOST_MODE = 1,
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USB_DRD_MODE = 2
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} USB_OTG_ModeTypeDef;
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/**
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* @brief URB States definition
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*/
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typedef enum
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{
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URB_IDLE = 0,
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URB_DONE,
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URB_NOTREADY,
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URB_NYET,
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URB_ERROR,
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URB_STALL
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} USB_OTG_URBStateTypeDef;
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/**
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* @brief Host channel States definition
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*/
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//typedef enum
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//{
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// HC_IDLE = 0,
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// HC_XFRC,
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// HC_HALTED,
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// HC_NAK,
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// HC_NYET,
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// HC_STALL,
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// HC_XACTERR,
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// HC_BBLERR,
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// HC_DATATGLERR
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//} USB_OTG_HCStateTypeDef;
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/**
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* @brief USB Instance Initialization Structure definition
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*/
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typedef struct
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{
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uint32_t dev_endpoints; /*!< Device Endpoints number.
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This parameter depends on the used USB core.
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This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
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uint32_t Host_channels; /*!< Host Channels number.
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This parameter Depends on the used USB core.
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This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
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uint32_t speed; /*!< USB Core speed.
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This parameter can be any value of @ref PCD_Speed/HCD_Speed
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(HCD_SPEED_xxx, HCD_SPEED_xxx) */
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uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
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uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
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uint32_t phy_itface; /*!< Select the used PHY interface.
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This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
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uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
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uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
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uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
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uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
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uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
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uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
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uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
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} USB_OTG_CfgTypeDef;
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typedef struct
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{
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uint8_t num; /*!< Endpoint number
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This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
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uint8_t is_in; /*!< Endpoint direction
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint8_t is_stall; /*!< Endpoint stall condition
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint8_t is_iso_incomplete; /*!< Endpoint isoc condition
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint8_t type; /*!< Endpoint type
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This parameter can be any value of @ref USB_LL_EP_Type */
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uint8_t data_pid_start; /*!< Initial data PID
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint8_t even_odd_frame; /*!< IFrame parity
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint16_t tx_fifo_num; /*!< Transmission FIFO number
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This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
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uint32_t maxpacket; /*!< Endpoint Max packet size
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This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
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uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
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uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
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uint32_t xfer_len; /*!< Current transfer length */
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uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
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} USB_OTG_EPTypeDef;
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typedef struct
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{
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uint8_t dev_addr; /*!< USB device address.
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This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
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uint8_t ch_num; /*!< Host channel number.
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This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
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uint8_t ep_num; /*!< Endpoint number.
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This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
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uint8_t ep_is_in; /*!< Endpoint direction
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint8_t speed; /*!< USB Host Channel speed.
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This parameter can be any value of @ref HCD_Device_Speed:
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(HCD_DEVICE_SPEED_xxx) */
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uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
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uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
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uint8_t ep_type; /*!< Endpoint Type.
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This parameter can be any value of @ref USB_LL_EP_Type */
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uint16_t max_packet; /*!< Endpoint Max packet size.
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This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
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uint8_t data_pid; /*!< Initial data PID.
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
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uint32_t XferSize; /*!< OTG Channel transfer size. */
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uint32_t xfer_len; /*!< Current transfer length. */
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uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
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uint8_t toggle_in; /*!< IN transfer current toggle flag.
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint8_t toggle_out; /*!< OUT transfer current toggle flag
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This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
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uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
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uint32_t ErrCnt; /*!< Host channel error count. */
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USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
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This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
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// USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
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// This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
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} USB_OTG_HCTypeDef;
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/* =========================================================================================================================== */
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/* ================ USB ================ */
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/* =========================================================================================================================== */
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/**
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* @brief USB_OTG_Core_Registers
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*/
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typedef struct
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{
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__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
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__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
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__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
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__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
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__IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
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__IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
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__IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
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__IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
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__IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
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__IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
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__IO uint32_t GNPTXFSIZ; /*!< Non Periodic Tx FIFO Size Register 028h */
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__IO uint32_t GNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
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uint32_t Reserved30[57]; /*!< Reserved 0x30-0x110 */
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} USB_OTG_GlobalTypeDef;
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/**
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* @brief USB_OTG_device_Registers
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*/
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typedef struct
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{
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__IO uint32_t DCFG; /*!< dev Configuration Register 800h */
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__IO uint32_t DCTL; /*!< dev Control Register 804h */
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__IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
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uint32_t Reserved0C; /*!< Reserved 80Ch */
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__IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
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__IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
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__IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
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__IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
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__I uint32_t DTKNQR1; /*!< dev IN Token Seq Reg 1 820h */
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__I uint32_t DTKNQR2; /*!< dev IN Token Seq Reg 2 824h */
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__IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
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__IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
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__I uint32_t DTKNQR3; /*!< dev IN Token Seq Reg 3 830h */
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__I uint32_t DTKNQR4; /*!< dev IN Token Seq Reg 4 834h */
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} USB_OTG_DeviceTypeDef;
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/**
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* @brief USB_OTG_IN_Endpoint-Specific_Register
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*/
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typedef struct
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{
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__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
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uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
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__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
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uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
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__IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
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uint32_t Reserved14; /*!< Reserved 900h + (ep_num * 20h) + 14h */
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__IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
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uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
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} USB_OTG_INEndpointTypeDef;
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/**
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* @brief USB_OTG_OUT_Endpoint-Specific_Registers
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*/
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/**
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* @brief USB_OTG_OUT_Endpoint-Specific_Registers
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*/
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typedef struct
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{
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__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
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uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
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__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
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uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
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__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
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uint32_t Reserved14[5]; /*!< Reserved B00h + (ep_num * 20h) + 14h - B00h + (ep_num * 20h) + 1Ch */
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} USB_OTG_OUTEndpointTypeDef;
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/*------------------------------------------------------------------------------------
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Macros
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-------------------------------------------------------------------------------------*/
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#define XC_USB_FS_PERIPH_BASE 0x50010000UL
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#define XC_USB_OTG_FS ((USB_OTG_GlobalTypeDef *) XC_USB_FS_PERIPH_BASE)
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/** @defgroup USB_OTG_CORE VERSION ID
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* @{
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*/
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#define USB_OTG_CORE_ID_300A 0x4F54300AU
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#define USB_OTG_CORE_ID_310A 0x4F54310AU
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/**
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* @}
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*/
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/** @defgroup USB_Core_Mode_ USB Core Mode
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* @{
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*/
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#define USB_OTG_MODE_DEVICE 0U
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#define USB_OTG_MODE_HOST 1U
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#define USB_OTG_MODE_DRD 2U
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/**
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* @}
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*/
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/** @defgroup USB_LL Device Speed
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* @{
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*/
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#define USBD_HS_SPEED 0U
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#define USBD_HSINFS_SPEED 1U
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#define USBH_HS_SPEED 0U
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#define USBD_FS_SPEED 2U
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#define USBH_FSLS_SPEED 1U
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/**
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* @}
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*/
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/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
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* @{
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*/
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#define USB_OTG_SPEED_HIGH 0U
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#define USB_OTG_SPEED_HIGH_IN_FULL 1U
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#define USB_OTG_SPEED_FULL 3U
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/**
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* @}
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*/
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/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
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* @{
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||||
*/
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#define USB_OTG_ULPI_PHY 1U
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#define USB_OTG_EMBEDDED_PHY 2U
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/**
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* @}
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*/
|
||||
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/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
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* @{
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||||
*/
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||||
#ifndef USBD_HS_TRDT_VALUE
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#define USBD_HS_TRDT_VALUE 9U
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#endif /* USBD_HS_TRDT_VALUE */
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#ifndef USBD_FS_TRDT_VALUE
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||||
#define USBD_FS_TRDT_VALUE 5U
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#define USBD_DEFAULT_TRDT_VALUE 9U
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#endif /* USBD_HS_TRDT_VALUE */
|
||||
/**
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||||
* @}
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||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
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* @{
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||||
*/
|
||||
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
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||||
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
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||||
#define USB_OTG_MAX_EP0_SIZE 64U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
|
||||
* @{
|
||||
*/
|
||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
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||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
|
||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
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||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
|
||||
* @{
|
||||
*/
|
||||
#define DCFG_FRAME_INTERVAL_80 0U
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||||
#define DCFG_FRAME_INTERVAL_85 1U
|
||||
#define DCFG_FRAME_INTERVAL_90 2U
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||||
#define DCFG_FRAME_INTERVAL_95 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define EP_MPS_64 0U
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||||
#define EP_MPS_32 1U
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||||
#define EP_MPS_16 2U
|
||||
#define EP_MPS_8 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
|
||||
* @{
|
||||
*/
|
||||
#define EP_SPEED_LOW 0U
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||||
#define EP_SPEED_FULL 1U
|
||||
#define EP_SPEED_HIGH 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
|
||||
* @{
|
||||
*/
|
||||
#define EP_TYPE_CTRL 0U
|
||||
#define EP_TYPE_ISOC 1U
|
||||
#define EP_TYPE_BULK 2U
|
||||
#define EP_TYPE_INTR 3U
|
||||
#define EP_TYPE_MSK 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
|
||||
* @{
|
||||
*/
|
||||
#define STS_GOUT_NAK 1U
|
||||
#define STS_DATA_UPDT 2U
|
||||
#define STS_XFER_COMP 3U
|
||||
#define STS_SETUP_COMP 4U
|
||||
#define STS_SETUP_UPDT 6U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
|
||||
* @{
|
||||
*/
|
||||
#define HCFG_30_60_MHZ 0U
|
||||
#define HCFG_48_MHZ 1U
|
||||
#define HCFG_6_MHZ 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
|
||||
* @{
|
||||
*/
|
||||
#define HPRT0_PRTSPD_HIGH_SPEED 0U
|
||||
#define HPRT0_PRTSPD_FULL_SPEED 1U
|
||||
#define HPRT0_PRTSPD_LOW_SPEED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define HCCHAR_CTRL 0U
|
||||
#define HCCHAR_ISOC 1U
|
||||
#define HCCHAR_BULK 2U
|
||||
#define HCCHAR_INTR 3U
|
||||
|
||||
#define HC_PID_DATA0 0U
|
||||
#define HC_PID_DATA2 1U
|
||||
#define HC_PID_DATA1 2U
|
||||
#define HC_PID_SETUP 3U
|
||||
|
||||
#define GRXSTS_PKTSTS_IN 2U
|
||||
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
|
||||
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
|
||||
#define GRXSTS_PKTSTS_CH_HALTED 7U
|
||||
|
||||
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
|
||||
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
|
||||
|
||||
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
|
||||
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
|
||||
+ USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||
|
||||
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
|
||||
+ USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
|
||||
|
||||
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
|
||||
|
||||
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
|
||||
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
|
||||
+ USB_OTG_HOST_CHANNEL_BASE\
|
||||
+ ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
|
||||
|
||||
#define EP_ADDR_MSK 0xFU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
|
||||
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
|
||||
|
||||
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
|
||||
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
------------------------------------------------------------------------------------*/
|
||||
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
|
||||
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
|
||||
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
||||
uint8_t ch_ep_num, uint16_t len, uint8_t dma);
|
||||
|
||||
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
||||
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
|
||||
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
|
||||
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
|
||||
|
||||
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
|
||||
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address, uint8_t speed,
|
||||
uint8_t ep_type, uint16_t mps);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
|
||||
USB_OTG_HCTypeDef *hc, uint8_t dma);
|
||||
|
||||
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
|
||||
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
|
||||
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#endif /* __XC_HAL_LL_USB_NP_H */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,686 @@
|
||||
/*!
|
||||
* \file xc_hal_pcd_np.h
|
||||
*
|
||||
* \brief PCD HAL module driver.(use non-periodic fifo)
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author MCD Application Team
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*/
|
||||
|
||||
#ifndef __XC_HAL_PCD_NP_H
|
||||
#define __XC_HAL_PCD_NP_H
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "xc_hal_ll_usb_np.h"
|
||||
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
/*------------------------------------------------------------------------------------
|
||||
Typedef
|
||||
------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief PCD State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_STATE_RESET = 0x00,
|
||||
HAL_PCD_STATE_READY = 0x01,
|
||||
HAL_PCD_STATE_ERROR = 0x02,
|
||||
HAL_PCD_STATE_BUSY = 0x03,
|
||||
HAL_PCD_STATE_TIMEOUT = 0x04
|
||||
} PCD_StateTypeDef;
|
||||
|
||||
/* Device LPM suspend state */
|
||||
typedef enum
|
||||
{
|
||||
LPM_L0 = 0x00, /* on */
|
||||
LPM_L1 = 0x01, /* LPM L1 sleep */
|
||||
LPM_L2 = 0x02, /* suspend */
|
||||
LPM_L3 = 0x03, /* off */
|
||||
} PCD_LPM_StateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_LPM_L0_ACTIVE = 0x00, /* on */
|
||||
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
|
||||
} PCD_LPM_MsgTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_BCD_ERROR = 0xFF,
|
||||
PCD_BCD_CONTACT_DETECTION = 0xFE,
|
||||
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
|
||||
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
|
||||
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
|
||||
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
|
||||
|
||||
} PCD_BCD_MsgTypeDef;
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
|
||||
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
|
||||
typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
/**
|
||||
* @brief PCD Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __PCD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
__IO uint8_t USB_Address; /*!< USB Address */
|
||||
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< PCD Error code */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
uint32_t BESL;
|
||||
uint32_t FrameNumber; /*!< Store Current Frame number */
|
||||
|
||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
|
||||
void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
|
||||
void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
|
||||
void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
|
||||
void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
|
||||
void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
|
||||
void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
|
||||
|
||||
void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
|
||||
void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
|
||||
void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
|
||||
void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
|
||||
void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
|
||||
void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
|
||||
|
||||
void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
typedef struct {
|
||||
uint8_t IN_Lock;
|
||||
uint8_t OUT_Lock;
|
||||
} PCD_IN_OUT_Status;
|
||||
|
||||
extern PCD_IN_OUT_Status PCD_Sta;
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Speed PCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SPEED_HIGH USBD_HS_SPEED
|
||||
#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
|
||||
#define PCD_SPEED_FULL USBD_FS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define PCD_PHY_ULPI 1U
|
||||
#define PCD_PHY_EMBEDDED 2U
|
||||
#define PCD_PHY_UTMI 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
|
||||
* @brief PCD Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
|
||||
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
|
||||
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
|
||||
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
|
||||
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
|
||||
((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
|
||||
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
#ifndef USB_OTG_DOEPINT_OTEPSPR
|
||||
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
|
||||
#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
|
||||
|
||||
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
|
||||
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
|
||||
#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
|
||||
|
||||
#ifndef USB_OTG_DOEPINT_NAK
|
||||
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
|
||||
#endif /* defined USB_OTG_DOEPINT_NAK */
|
||||
|
||||
#ifndef USB_OTG_DOEPMSK_NAKM
|
||||
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
|
||||
#endif /* defined USB_OTG_DOEPMSK_NAKM */
|
||||
|
||||
#ifndef USB_OTG_DOEPINT_STPKTRX
|
||||
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
|
||||
#endif /* defined USB_OTG_DOEPINT_STPKTRX */
|
||||
|
||||
#ifndef USB_OTG_DOEPMSK_NYETM
|
||||
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
|
||||
#endif /* defined USB_OTG_DOEPMSK_NYETM */
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
------------------------------------------------------------------------------------*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
|
||||
* @brief HAL USB OTG PCD Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
|
||||
HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
|
||||
HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
|
||||
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
|
||||
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
|
||||
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
|
||||
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
|
||||
|
||||
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
|
||||
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
|
||||
|
||||
} HAL_PCD_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
|
||||
* @brief HAL USB OTG PCD Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
|
||||
typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
|
||||
typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
|
||||
typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
|
||||
typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
|
||||
typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
|
||||
typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
pPCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataInStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_BcdCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_LpmCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint16_t ep_mps, uint8_t ep_type);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if 0
|
||||
#if defined(USB_OTG_FS)
|
||||
/*------------------------------------------------------------------------------------
|
||||
Typedef
|
||||
------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief PCD State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_STATE_RESET = 0x00,
|
||||
HAL_PCD_STATE_READY = 0x01,
|
||||
HAL_PCD_STATE_ERROR = 0x02,
|
||||
HAL_PCD_STATE_BUSY = 0x03,
|
||||
HAL_PCD_STATE_TIMEOUT = 0x04
|
||||
} PCD_StateTypeDef;
|
||||
|
||||
/* Device LPM suspend state */
|
||||
typedef enum
|
||||
{
|
||||
LPM_L0 = 0x00, /* on */
|
||||
LPM_L1 = 0x01, /* LPM L1 sleep */
|
||||
LPM_L2 = 0x02, /* suspend */
|
||||
LPM_L3 = 0x03, /* off */
|
||||
} PCD_LPM_StateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_LPM_L0_ACTIVE = 0x00, /* on */
|
||||
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
|
||||
} PCD_LPM_MsgTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_BCD_ERROR = 0xFF,
|
||||
PCD_BCD_CONTACT_DETECTION = 0xFE,
|
||||
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
|
||||
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
|
||||
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
|
||||
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
|
||||
|
||||
} PCD_BCD_MsgTypeDef;
|
||||
|
||||
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
|
||||
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
|
||||
typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
|
||||
|
||||
/**
|
||||
* @brief PCD Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
__IO uint8_t USB_Address; /*!< USB Address */
|
||||
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< PCD Error code */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
uint32_t BESL;
|
||||
uint32_t FrameNumber; /*!< Store Current Frame number */
|
||||
|
||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Speed PCD Speed
|
||||
* @{
|
||||
*/
|
||||
//#define PCD_SPEED_HIGH USBD_HS_SPEED
|
||||
//#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
|
||||
#define PCD_SPEED_FULL USBD_FS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define PCD_PHY_ULPI 1U
|
||||
#define PCD_PHY_EMBEDDED 2U
|
||||
#define PCD_PHY_UTMI 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
|
||||
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
|
||||
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
|
||||
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
|
||||
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
|
||||
((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
|
||||
|
||||
//#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
//#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
//#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
//#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
|
||||
//#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
// do { \
|
||||
// EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
|
||||
// EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
|
||||
// } while(0U)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||
do { \
|
||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||
} while(0U)
|
||||
|
||||
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||
//#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifndef USB_OTG_DOEPINT_OTEPSPR
|
||||
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
|
||||
#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
|
||||
|
||||
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
|
||||
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
|
||||
#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
|
||||
|
||||
#ifndef USB_OTG_DOEPINT_NAK
|
||||
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
|
||||
#endif /* defined USB_OTG_DOEPINT_NAK */
|
||||
|
||||
#ifndef USB_OTG_DOEPMSK_NAKM
|
||||
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
|
||||
#endif /* defined USB_OTG_DOEPMSK_NAKM */
|
||||
|
||||
#ifndef USB_OTG_DOEPINT_STPKTRX
|
||||
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
|
||||
#endif /* defined USB_OTG_DOEPINT_STPKTRX */
|
||||
|
||||
#ifndef USB_OTG_DOEPMSK_NYETM
|
||||
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
|
||||
#endif /* defined USB_OTG_DOEPMSK_NYETM */
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
------------------------------------------------------------------------------------*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint16_t ep_mps, uint8_t ep_type);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (USB_OTG_FS) */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __XC_HAL_PCD_NP_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,266 @@
|
||||
/*!
|
||||
* \file xc_hal_usb.c
|
||||
*
|
||||
* \brief Target xinchip hal usb implementation
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "xc_hal_usb.h"
|
||||
#include "xc6xxx.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
#define USB_RESET_ON( ) cpr_rf_reg1__usb_rstn_reg__setf(0)//CLEAR_BIT(XC_CPR->RF_REG1, (1 << 20))
|
||||
#define USB_RESET_OFF( ) cpr_rf_reg1__usb_rstn_reg__setf(1)//SET_BIT(XC_CPR->RF_REG1, (1 << 20))
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief usb phy dm operation
|
||||
* @param uint32_t - bit
|
||||
* @retval None
|
||||
*/
|
||||
void USB_Phy_DM_Oprt(uint32_t bit)
|
||||
{
|
||||
cpr_rf_reg5__usb_rwreg__setf(bit << 3);
|
||||
// if(bit == PULL_UP)
|
||||
// SET_BIT(XC_CPR->RF_REG5, (bit << 3));
|
||||
// else if(bit == PULL_DOWN)
|
||||
// CLEAR_BIT(XC_CPR->RF_REG5, (bit << 3));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb phy dp operation
|
||||
* @param uint32_t - bit
|
||||
* @retval None
|
||||
*/
|
||||
void USB_Phy_DP_Oprt(uint32_t bit)
|
||||
{
|
||||
cpr_rf_reg5__usb_rwreg__setf(bit << 2);
|
||||
// if(bit == PULL_UP)
|
||||
// SET_BIT(XC_CPR->RF_REG5, (bit << 2));
|
||||
// else if(bit == PULL_DOWN)
|
||||
// CLEAR_BIT(XC_CPR->RF_REG5, (bit << 2));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb phy enable
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void USB_Phy_Enable( void )
|
||||
{
|
||||
cpr_rf_reg5__usb_rwreg__setf(0 << 4);
|
||||
// CLEAR_BIT(XC_CPR->RF_REG5, (1 << 4));
|
||||
// SET_BIT(XC_CPR->RF_REG5, (1 << 4));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb phy disable
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void USB_Phy_Disable( void )
|
||||
{
|
||||
cpr_rf_reg5__usb_rwreg__setf(1 << 4);
|
||||
// SET_BIT(XC_CPR->RF_REG5, (1 << 4));
|
||||
}
|
||||
|
||||
#define readl(addr) (*(volatile unsigned int *) (addr))
|
||||
#define writel(addr, value) (*(volatile unsigned int *) (addr) = (value))
|
||||
|
||||
/**
|
||||
* @brief 32M OSC multiper bbpll to 96M
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void OSC32M_Multi_BBPLL_96M( void )
|
||||
{
|
||||
#if (XC6XX_5C != 1)
|
||||
if(xc_clock_hfclk_in_get() == CLOCK_HFCLK_IN_32M)
|
||||
{
|
||||
xc_clock_bbpll_common_cfg( );
|
||||
rf_ana27__bbpll_16m_sel__setf(DISABLE);
|
||||
rf_ana27__bbpll_core_96m_en__setf(ENABLE);
|
||||
rf_ana26__bbpll_loopdiv__setf(0x06);
|
||||
rf_ana26__clk_bbpll_en__setf(ENABLE);
|
||||
rf_ana26__clk_bbpll_rstn__setf(ENABLE);
|
||||
rf_ana26__bbpll_en__setf(ENABLE);
|
||||
rf_ana26__bbpll_core_64m_en__setf(ENABLE);
|
||||
|
||||
// /* BT_CLK 时钟控制寄存器 */
|
||||
// XC_CPR->BT_CLK_CTL = (CPR_BT_CLK_CTL_BT_CLK_EN_ENABLE | (CPR_BT_CLK_CTL_BT_CLK_EN_Msk << 16));
|
||||
// /* BT_MODEM_CLK 时钟控制寄存器 */
|
||||
//// XC_CPR->BT_MODEM_CTL = (CPR_BT_MODEM_CLK_CTL_BT_MODEM_CLK_EN_ENABLE |
|
||||
//// (CPR_BT_MODEM_CLK_CTL_BT_MODEM_CLK_EN_Msk << 16));
|
||||
// /* 配置 BT_PCLK_EN 使能 */
|
||||
// XC_CPR->CTLAPBCLKEN_GRCTL |= (CPR_CTLAPBCLKEN_GRCTL_BT_PCLK_EN_ENABLE |
|
||||
// (CPR_CTLAPBCLKEN_GRCTL_BT_PCLK_EN_Msk << CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET));
|
||||
//
|
||||
// SET_BIT(XC_BT_RF->BT.rx_pm_reg_l, (1 << 14));
|
||||
// XC_CPR_AO->AON_CORERFLDO_EN = 0x1;
|
||||
|
||||
|
||||
// SET_BIT(XC_BT_RF->ana26_reg_l, (0xf << 12));
|
||||
// SET_BIT(XC_BT_RF->ana27_reg_l, 0x02); // ana27 div 2
|
||||
// SET_BIT(XC_BT_RF->ana26_reg_l, 0x06); // ana26 6*32 / 2 = 192M / 2 = 96M
|
||||
}
|
||||
#else
|
||||
uint32_t last_idx = xc_clock_hfclk_in_get()/1000000;
|
||||
// CLEAR_BIT(XC_CPR->RF_REG4, (uint32_t)0x1f);
|
||||
// SET_BIT(XC_CPR->RF_REG4, (uint32_t)0x11);
|
||||
|
||||
// CLEAR_BIT(XC_CPR->RF_REG3, (uint32_t)(0x07 | (0x1f<<8) | (0x3f<<14)));
|
||||
// SET_BIT(XC_CPR->RF_REG3, (uint32_t)((0x1 << 1) | (0x07<<8) | (0x08<<14)));
|
||||
|
||||
uint32_t val = XC_CPR->RF_REG4;
|
||||
XC_CPR->RF_REG4 = (val & 0xFFFFFFE0) | 0x11; // div2
|
||||
|
||||
val = XC_CPR->RF_REG3;
|
||||
//[00-OSC32M],[01-bbpll direct output],[10-bbpll div output],[11-rc16M]
|
||||
XC_CPR->RF_REG3 = (val & (~(uint32_t)(0x07 | (0x1f<<8) | (0x3f<<14)))) |
|
||||
(0x1 << 1) | (0x07<<8) | (0x08<<14);
|
||||
|
||||
m_clock_cb.hfclk_in = CLOCK_HFCLK_IN_96M;
|
||||
|
||||
uint32_t baudrate, uart_clk, div, mul, clk_ctl, adj_div;
|
||||
|
||||
uart_clk = xc_clock_hfclk_in_get();
|
||||
baudrate = XC_CPR->UART0_CLK_CTL;
|
||||
mul = (baudrate >> 16) & 0xFFFF;
|
||||
div = (baudrate & 0xFFFF);
|
||||
|
||||
adj_div = uart_clk / 1000000;
|
||||
clk_ctl = (mul << 16 ) | ( div * adj_div / last_idx);
|
||||
|
||||
XC_CPR->UART0_CLK_CTL = clk_ctl;
|
||||
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
SysTick_Config(xc_clock_hfclk_in_get() / 100);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb bbpll close
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void USB_BBPLL_Close( void )
|
||||
{
|
||||
rf_ana26__bbpll_core_64m_en__setf(DISABLE);
|
||||
rf_ana26__bbpll_en__setf(DISABLE);
|
||||
rf_ana26__clk_bbpll_rstn__setf(DISABLE);
|
||||
rf_ana26__clk_bbpll_en__setf(DISABLE);
|
||||
rf_ana26__bbpll_loopdiv__setf(0x00);
|
||||
// CLEAR_BIT(XC_BT_RF->ana26_reg_l, (0xf << 12));
|
||||
// CLEAR_BIT(XC_BT_RF->ana26_reg_l, 0x06);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb pll enable
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void USB_PLL_Enable( void )
|
||||
{
|
||||
OSC32M_Multi_BBPLL_96M( );
|
||||
|
||||
cpr_rf_reg1__usb_mclk_div__setf(1);
|
||||
cpr_rf_reg1__usb_hclk_en__setf(1);
|
||||
cpr_rf_reg1__usb_mclk_en__setf(1);
|
||||
cpr_rf_reg1__usb_utmi_clk_div__setf(1);
|
||||
cpr_rf_reg1__usb_utmi_clk_en__setf(1);
|
||||
|
||||
// WRITE_REG(XC_CPR->RF_REG1, (XC_CPR->RF_REG1 & 0xE0FFCFF0) | 0x11003001); // usb clk enable
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb pll disable
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void USB_PLL_Disable( void )
|
||||
{
|
||||
USB_BBPLL_Close( );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb phy init
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void USB_Phy_Init( void )
|
||||
{
|
||||
USB_PLL_Enable( );
|
||||
|
||||
USB_RESET_ON( );
|
||||
HAL_Delay(100);//for(int i = 0; i < 0x4550; i++);//HAL_Delay(100);
|
||||
USB_RESET_OFF( );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb phy deinit
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void USB_Phy_Deinit( void )
|
||||
{
|
||||
cpr_rf_reg1__usb_utmi_clk_en__setf(0);
|
||||
cpr_rf_reg1__usb_utmi_clk_div__setf(0);
|
||||
cpr_rf_reg1__usb_hclk_en__setf(0);
|
||||
cpr_rf_reg1__usb_mclk_en__setf(0);
|
||||
// WRITE_REG(XC_CPR->RF_REG1, (XC_CPR->RF_REG1 & 0xE0FFCFF0) | (~0x00003000)); // usb clk disable
|
||||
USB_Phy_Disable( );
|
||||
NVIC_DisableIRQ(USB_IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb phy reset
|
||||
* @param void
|
||||
* @retval None
|
||||
*/
|
||||
void USB_Phy_Reset( void )
|
||||
{
|
||||
USB_RESET_ON( );
|
||||
HAL_Delay(150); //for(int i = 0; i < 0x4550; i++);//HAL_Delay(100);
|
||||
USB_RESET_OFF( );
|
||||
HAL_Delay(10);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb current control
|
||||
* @param uint8_t - val
|
||||
* @retval None
|
||||
*/
|
||||
void USB_Current_Ctrl( uint8_t val )
|
||||
{
|
||||
cpr_rf_reg5__usbphy_usb_ibc__setf(val);
|
||||
|
||||
// CLEAR_BIT(XC_CPR->RF_REG5, (3 << 21));
|
||||
|
||||
// SET_BIT(XC_CPR->RF_REG5, (val << 21));
|
||||
}
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
/*!
|
||||
* \file xc_hal_usb.h
|
||||
*
|
||||
* \brief The header of xc_hal_usb.c
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
#ifndef __XC_HAL_USB_H_
|
||||
#define __XC_HAL_USB_H_
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
//#define SET_REG_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
//#define CLEAR_REG_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
//#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
//#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
//#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
//#define READ_REG(REG) ((REG))
|
||||
|
||||
#define PULL_UP 1U
|
||||
#define PULL_DOWN 0U
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
------------------------------------------- -----------------------------------------*/
|
||||
void USB_Phy_DM_Oprt(uint32_t bit);
|
||||
void USB_Phy_DP_Oprt(uint32_t bit);
|
||||
void USB_Phy_Enable( void );
|
||||
void USB_Phy_Disable( void );
|
||||
void USB_PLL_Enable( void );
|
||||
void USB_PLL_Disable( void );
|
||||
void USB_Phy_Init( void );
|
||||
void USB_Phy_Deinit( void );
|
||||
void USB_Phy_Reset( void );
|
||||
void USB_Current_Ctrl( uint8_t val );
|
||||
|
||||
|
||||
#endif /* __XC_HAL_USB_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user