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Stair56E UART project

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This commit is contained in:
吴琪
2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
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component/boot2/bsp/startup/Initialization.ini
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FUNC void Initialization(void)
{
SP = _RDWORD(0x10000000);
PC = _RDWORD(0x10000004);
_WDWORD(0x4000013C, 0x10000001);
}
LOAD %L INCREMENTAL
Initialization();
component/boot2/bsp/startup/core_cm0.c
+241
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#include <stdint.h>
/* define compiler specific symbols */
#if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ########################## Core Instruction Access ######################### */
#if defined(__CC_ARM) /*------------------ RealView Compiler ----------------*/
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
__ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
__ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __CLREX(void)
{
clrex
}
#endif /* __ARMCC_VERSION */
#elif (defined(__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined(__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined(__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
/* ########################### Core Function Access ########################### */
#if defined(__CC_ARM) /*------------------ RealView Compiler ----------------*/
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_IPSR(void)
{
mrs r0, ipsr
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_APSR(void)
{
mrs r0, apsr
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_xPSR(void)
{
mrs r0, xpsr
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined(__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined(__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined(__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
component/boot2/bsp/startup/core_cm0.h
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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \mainpage CMSIS Cortex-M0
This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
It consists of:
- Cortex-M Core Register Definitions
- Cortex-M functions
- Cortex-M instructions
The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
access to the Cortex-M Core
*/
/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
List of Lint messages which will be suppressed and not shown:
- not yet checked
.
Note: To re-enable a Message, insert a space before 'lint' *
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
This file defines all structures and symbols for CMSIS core:
- CMSIS version number
- Cortex-M core
- Cortex-M core Revision Number
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
#include <stdint.h> /*!< standard types definitions */
#include "core_cmInstr.h" /*!< Core Instruction Access */
#include "core_cmFunc.h" /*!< Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* IO definitions (access restrictions to peripheral registers) */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/*@} end of group CMSIS_core_definitions */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** \defgroup CMSIS_core_register CMSIS Core Register
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE CMSIS Core
Type definitions for the Cortex-M Core Registers
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC CMSIS NVIC
Type definitions for the Cortex-M NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IPR[8]; /*!< Offset: 0x3EC (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB CMSIS SCB
Type definitions for the Cortex-M System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED2[2];
__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick CMSIS SysTick
Type definitions for the Cortex-M System Timer Registers
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug CMSIS Core Debug
Type definitions for the Cortex-M Core Debug Registers
@{
*/
/** \brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_DWTENA_Pos 24 /*!< CoreDebug DEMCR: DWTENA Position */
#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
This function enables a device specific interupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to enable
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
This function disables a device specific interupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to disable
*/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
This function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Number of the interrupt for get pending
\return 0 Interrupt status is not pending
\return 1 Interrupt status is pending
*/
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
This function sets the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for set pending
*/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
This function clears the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for clear pending
*/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
This function sets the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
Note: The priority cannot be set for every core interrupt.
\param [in] IRQn Number of the interrupt for set priority
\param [in] priority Priority to set
*/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
This function reads the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
The returned priority value is automatically aligned to the implemented
priority bits of the microcontroller.
\param [in] IRQn Number of the interrupt for get priority
\return Interrupt Priority
*/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
This function initiate a system reset request to reset the MCU.
*/
static __INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
This function initialises the system tick timer and its interrupt and start the system tick timer.
Counter is in free running mode to generate periodical interrupts.
\param [in] ticks Number of ticks between two interrupts
\return 0 Function succeeded
\return 1 Function failed
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif
/*lint -restore */
component/boot2/bsp/startup/core_cmFunc.h
+844
View File
@@ -0,0 +1,844 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H__
#define __CORE_CMFUNC_H__
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_CONTROL(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_IPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_APSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_xPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PSP(uint32_t topOfProcStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_MSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_MSP(uint32_t topOfMainStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PRIMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PRIMASK(uint32_t priMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_BASEPRI(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_BASEPRI(uint32_t basePri);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_FAULTMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_FAULTMASK(uint32_t faultMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & 1);
}
#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#pragma diag_suppress=Pe940
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_irq __enable_interrupt
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_irq __disable_interrupt
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static uint32_t __get_IPSR(void)
{
__ASM("mrs r0, ipsr");
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static uint32_t __get_APSR(void)
{
__ASM("mrs r0, apsr");
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static uint32_t __get_xPSR(void)
{
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
}
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __enable_fault_irq(void)
{
__ASM ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __disable_fault_irq(void)
{
__ASM ("cpsid f");
}
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
__ASM("vmrs r0, fpscr");
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM("vmsr fpscr, r0");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H__ */
component/boot2/bsp/startup/core_cmInstr.h
+776
View File
@@ -0,0 +1,776 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H__
#define __CORE_CMINSTR_H__
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern uint32_t __REV16(uint32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern int32_t __REVSH(int32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#if (__ARMCC_VERSION < 400000)
extern void __CLREX(void);
#else /* (__ARMCC_VERSION >= 400000) */
#define __CLREX __clrex
#endif /* __ARMCC_VERSION */
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#include <intrinsics.h> /* IAR Intrinsics */
#pragma diag_suppress=Pe940
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __no_operation
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
static __INLINE void __WFI(void)
{
__ASM ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE(void)
{
__ASM ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
static __INLINE void __SEV(void)
{
__ASM ("sev");
}
/* intrinsic void __ISB(void) (see intrinsics.h) */
/* intrinsic void __DSB(void) (see intrinsics.h) */
/* intrinsic void __DMB(void) (see intrinsics.h) */
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
/* intrinsic __SSAT (see intrinsics.h) */
/* intrinsic __USAT (see intrinsics.h) */
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __REV16(uint32_t value)
{
__ASM("rev16 r0, r0");
}
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
static uint8_t __LDREXB(volatile uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
static uint16_t __LDREXH(volatile uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
static uint32_t __LDREXW(volatile uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
static __INLINE void __CLREX(void)
{
__ASM ("clrex");
}
/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
#endif /* (__CORTEX_M >= 0x03) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H__ */
component/boot2/bsp/startup/cpu.scat
+37
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@@ -0,0 +1,37 @@
;LOAD 0x10000000
;{
; EXE 0x10000000
; {
; startup_xinc.o (RESET, +FIRST)
; * (+RO)
;
; }
; RW +0x1000
; {
; * (+RW,+ZI)
; }
;}
LOAD_ROM 0x11001000 ;NOCOMPRESS ;ALIGN 32
{
USER_ROM 0x11001000 NOCOMPRESS
{
startup_xinc.o (RESET, +FIRST)
*(+RO)
}
USER_RAM 0x10000100 NOCOMPRESS
{
*(ram_code)
*(+RW,+ZI)
}
}
component/boot2/bsp/startup/startup_xinc.s
+236
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@@ -0,0 +1,236 @@
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler
DCD DMAS_Handler
DCD CPR_Handler
DCD GPIO_Handler
DCD RTC_Handler
DCD TIMER0_Handler
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD KBS_Handler
DCD QDEC_Handler
DCD GADC_Handler
DCD SIM_Handler
DCD AES_Handler
DCD USB_Handler
DCD RESV0_Handler
DCD SUB1G_Handler
DCD RESV1_Handler
DCD BOR_Handler
DCD RESV2_Handler
DCD RESV3_Handler
DCD AOTIMER0_Handler
DCD AOTIMER1_Handler
DCD CMP_Handler
DCD FMC_Handler
DCD CAN_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
EXPORT KBS_Handler [WEAK]
EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT SIM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT RESV0_Handler [WEAK]
EXPORT SUB1G_Handler [WEAK]
EXPORT RESV1_Handler [WEAK]
EXPORT BOR_Handler [WEAK]
EXPORT RESV2_Handler [WEAK]
EXPORT RESV3_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
PendSV_Handler
SysTick_Handler
BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
KBS_Handler
QDEC_Handler
GADC_Handler
SIM_Handler
AES_Handler
USB_Handler
RESV0_Handler
SUB1G_Handler
RESV1_Handler
BOR_Handler
RESV2_Handler
RESV3_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
component/boot2/bsp/startup/system_xinc.c
+22
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@@ -0,0 +1,22 @@
#include "xinc_m0.h"
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
*
*/
extern void retarget_init(void);
void SystemInit(void)
{
/*bit2:1 select clock source([00-OSC32M],[01-bbpll direct output],[10-bbpll div output],[11-rc16M])*/
*((volatile unsigned *)(0x40000000 + 0x130)) &= (~0x06); //*((volatile unsigned *)(0x40000000+ 0x130)) |=0x06;
/*release BootDone --release pin bootctl1(gpio35)*/
*((volatile unsigned *)(0x40000000 + 0x1B0)) |= 0x10000000;
retarget_init();
}
component/boot2/bsp/startup/xinc_m0.h
+124
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@@ -0,0 +1,124 @@
#ifndef __XINC_M0_H__
#define __XINC_M0_H__
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
Configuration of the Cortex-M# Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/****** Device Specific Interrupt Numbers ********************************************************/
/* ToDo: add here your device specific external interrupt numbers
according the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
BLUETOOTH_IRQn = 0, /*!< Device Interrupt */
DMAS_IRQn = 1,
CPR_IRQn = 2,
GPIO_IRQn = 3,
RTC_IRQn = 4,
TIMER0_IRQn = 5,
TIMER1_IRQn = 6,
TIMER2_IRQn = 7,
TIMER3_IRQn = 8,
WDT_IRQn = 9,
I2C_IRQn = 10,
UART0_IRQn = 11,
UART1_IRQn = 12,
SPI0_IRQn = 13,
SPI1_IRQn = 14,
KBS_IRQn = 15,
QDEC_IRQn = 16,
GADC_IRQn = 17,
SIM_IRQn = 18,
AES_IRQn = 19,
USB_IRQn = 20,
RESV0_IRQn = 21,
SUB1G_IRQn = 22,
RESV1_IRQn = 23,
BOR = 24,
RESV2_IRQn = 25,
RESV3_IRQn = 26,
AOTIMER0_IRQn = 27,
AOTIMER1_IRQn = 28,
CMP_IRQn = 29,
FMC_IRQn = 30,
CAN_IRQn = 31,
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
/* ToDo: set the defines according your Device */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#define __FPU_PRESENT 1 /*!< FPU present or not */
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
/*@}*/ /* end of group <Device>_CMSIS */
#include "core_cm0.h"
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup <Device>_Peripherals <Device> Peripherals
<Device> Device Specific Peripheral registers structures
@{
*/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
#include "xinc_reg.h"
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#ifdef __cplusplus
}
#endif
#endif // __<Device>_H__
component/boot2/bsp/startup/xinc_map.h
+765
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@@ -0,0 +1,765 @@
#ifndef __XINC_H
#define __XINC_H
/*******************************************************************************
Modules` base address on XINC
********************************************************************************/
#define ROM_BASE 0x00000000
#define M0_RAM_BASE 0x10000000
#define SHRAM0_BASE 0x20000000
#define SHRAM1_BASE 0x20020000
#define DMAS_BASE 0x50001000
#define CPR_BASE 0x40000000
#define GPIO_BASE 0x40001000
#define RTC_BASE 0x40002000
#define TIMER_BASE 0x40003000
#define WDT_BASE 0x40004000
#define I2C_BASE 0x40006000
#define UART0_BASE 0x40010000
#define UART1_BASE 0x40011000
#define SIM_BASE 0x40012000
#define SPI0_BASE 0x40013000 //0x40013000
#define SPI1_BASE 0x40014000
#define SPI2_BASE 0x40014800
#define KBS_BASE 0x40015000
#define QDEC_BASE 0x40016000
#define PWM_BASE 0x40017000
#define GPADC_BASE 0x40018000
#define CPR_AO_BASE 0x40002400
#define AES_BASE 0x20020000
#define GPIO_PORT_DR0 ((volatile unsigned *)(GPIO_BASE + 0x00))
#define GPIO_PORT_DR1 ((volatile unsigned *)(GPIO_BASE + 0x04))
#define GPIO_PORT_DR2 ((volatile unsigned *)(GPIO_BASE + 0x08))
#define GPIO_PORT_DDR0 ((volatile unsigned *)(GPIO_BASE + 0x20))
#define GPIO_PORT_DDR1 ((volatile unsigned *)(GPIO_BASE + 0x24))
#define GPIO_PORT_DDR2 ((volatile unsigned *)(GPIO_BASE + 0x28))
#define GPIO_EXT_PORT0 ((volatile unsigned *)(GPIO_BASE + 0x40))
#define GPIO_EXT_PORT1 ((volatile unsigned *)(GPIO_BASE + 0x44))
#define GPIO_INTR_CTRL0 ((volatile unsigned *)(GPIO_BASE + 0x100))
#define GPIO_INTR_CTRL1 ((volatile unsigned *)(GPIO_BASE + 0x104))
#define GPIO_INTR_CTRL2 ((volatile unsigned *)(GPIO_BASE + 0x108))
#define GPIO_INTR_CTRL3 ((volatile unsigned *)(GPIO_BASE + 0x10c))
#define GPIO_INTR_CTRL4 ((volatile unsigned *)(GPIO_BASE + 0x110))
#define GPIO_INTR_CTRL5 ((volatile unsigned *)(GPIO_BASE + 0x114))
#define GPIO_INTR_CTRL6 ((volatile unsigned *)(GPIO_BASE + 0x118))
#define GPIO_INTR_CTRL7 ((volatile unsigned *)(GPIO_BASE + 0x11c))
#define GPIO_INTR_CTRL8 ((volatile unsigned *)(GPIO_BASE + 0x120))
#define GPIO_INTR_CTRL9 ((volatile unsigned *)(GPIO_BASE + 0x124))
#define GPIO_DEBOUNCE0 ((volatile unsigned *)(GPIO_BASE + 0x180))
#define GPIO_DEBOUNCE1 ((volatile unsigned *)(GPIO_BASE + 0x184))
#define GPIO_DEBOUNCE2 ((volatile unsigned *)(GPIO_BASE + 0x188))
#define GPIO_INTR_RAW0 ((volatile unsigned *)(GPIO_BASE + 0x1a0))
#define GPIO_INTR_RAW1 ((volatile unsigned *)(GPIO_BASE + 0x1a4))
#define GPIO_INTR_CLR0 ((volatile unsigned *)(GPIO_BASE + 0x1b0))
#define GPIO_INTR_CLR1 ((volatile unsigned *)(GPIO_BASE + 0x1b4))
#define GPIO_INTR_MASK_C00 ((volatile unsigned *)(GPIO_BASE + 0x200))
#define GPIO_INTR_MASK_C01 ((volatile unsigned *)(GPIO_BASE + 0x204))
#define GPIO_INTR_MASK_C02 ((volatile unsigned *)(GPIO_BASE + 0x208))
#define GPIO_INTR_STATUS_C00 ((volatile unsigned *)(GPIO_BASE + 0x220))
#define GPIO_INTR_STATUS_C01 ((volatile unsigned *)(GPIO_BASE + 0x224))
#define GPIO_INTR_MASK_C10 ((volatile unsigned *)(GPIO_BASE + 0x240))
#define GPIO_INTR_MASK_C11 ((volatile unsigned *)(GPIO_BASE + 0x244))
#define GPIO_INTR_MASK_C12 ((volatile unsigned *)(GPIO_BASE + 0x248))
#define GPIO_INTR_STATUS_C10 ((volatile unsigned *)(GPIO_BASE + 0x260))
#define GPIO_INTR_STATUS_C11 ((volatile unsigned *)(GPIO_BASE + 0x264))
#define RTC_CCVR ((volatile unsigned *)(RTC_BASE + 0x00))
#define RTC_CLR ((volatile unsigned *)(RTC_BASE + 0x04))
#define RTC_CMR_ONE ((volatile unsigned *)(RTC_BASE + 0x08))
#define RTC_CMR_TWO ((volatile unsigned *)(RTC_BASE + 0x0C))
#define RTC_CMR_THREE ((volatile unsigned *)(RTC_BASE + 0x10))
#define RTC_ICR ((volatile unsigned *)(RTC_BASE + 0x14))
#define RTC_ISR ((volatile unsigned *)(RTC_BASE + 0x18))
#define RTC_EOI ((volatile unsigned *)(RTC_BASE + 0x18))
#define RTC_WVR ((volatile unsigned *)(RTC_BASE + 0x1C))
#define RTC_WLR ((volatile unsigned *)(RTC_BASE + 0x20))
#define RTC_RAW_LIMIT ((volatile unsigned *)(RTC_BASE + 0x24))
#define RTC_SECOND_LIMIT ((volatile unsigned *)(RTC_BASE + 0x28))
#define RTC_MINUTE_LIMIT ((volatile unsigned *)(RTC_BASE + 0x2C))
#define RTC_HOUR_LIMIT ((volatile unsigned *)(RTC_BASE + 0x30))
#define RTC_ISR_RAW ((volatile unsigned *)(RTC_BASE + 0x34))
#define RTC_RVR ((volatile unsigned *)(RTC_BASE + 0x38))
#define AO_TIMER_CTL ((volatile unsigned *)(RTC_BASE + 0x0040))
#define AO_GPIO_MODE ((volatile unsigned *)(RTC_BASE + 0x0044))
#define AO_GPIO_CTL ((volatile unsigned *)(RTC_BASE + 0x0048))
#define AO_ALL_INTR ((volatile unsigned *)(RTC_BASE + 0x004C))
#define FREQ_TIMER_VAL ((volatile unsigned *)(RTC_BASE + 0x0050))
#define TIMER0_TLC ((volatile unsigned *)(TIMER_BASE + 0x00))
#define TIMER0_TCV ((volatile unsigned *)(TIMER_BASE + 0x04))
#define TIMER0_TCR ((volatile unsigned *)(TIMER_BASE + 0x08))
#define TIMER0_TIC ((volatile unsigned *)(TIMER_BASE + 0x0c))
#define TIMER0_TIS ((volatile unsigned *)(TIMER_BASE + 0x10))
#define TIMER1_TLC ((volatile unsigned *)(TIMER_BASE + 0x14))
#define TIMER1_TCV ((volatile unsigned *)(TIMER_BASE + 0x18))
#define TIMER1_TCR ((volatile unsigned *)(TIMER_BASE + 0x1C))
#define TIMER1_TIC ((volatile unsigned *)(TIMER_BASE + 0x20))
#define TIMER1_TIS ((volatile unsigned *)(TIMER_BASE + 0x24))
#define TIMER2_TLC ((volatile unsigned *)(TIMER_BASE + 0x28))
#define TIMER2_TCV ((volatile unsigned *)(TIMER_BASE + 0x2C))
#define TIMER2_TCR ((volatile unsigned *)(TIMER_BASE + 0x30))
#define TIMER2_TIC ((volatile unsigned *)(TIMER_BASE + 0x34))
#define TIMER2_TIS ((volatile unsigned *)(TIMER_BASE + 0x38))
#define TIMER3_TLC ((volatile unsigned *)(TIMER_BASE + 0x3C))
#define TIMER3_TCV ((volatile unsigned *)(TIMER_BASE + 0x40))
#define TIMER3_TCR ((volatile unsigned *)(TIMER_BASE + 0x44))
#define TIMER3_TIC ((volatile unsigned *)(TIMER_BASE + 0x48))
#define TIMER3_TIS ((volatile unsigned *)(TIMER_BASE + 0x4C))
#define TIMER_TIS ((volatile unsigned *)(TIMER_BASE + 0xA0))
#define TIMER_TIC ((volatile unsigned *)(TIMER_BASE + 0xA4))
#define TIMER_RTIS ((volatile unsigned *)(TIMER_BASE + 0xA8))
#define WDT_CR ((volatile unsigned *)(WDT_BASE + 0x00))
#define WDT_TORR ((volatile unsigned *)(WDT_BASE + 0x04))
#define WDT_CCVR ((volatile unsigned *)(WDT_BASE + 0x08))
#define WDT_CRR ((volatile unsigned *)(WDT_BASE + 0x0C))
#define WDT_STAT ((volatile unsigned *)(WDT_BASE + 0x10))
#define WDT_ICR ((volatile unsigned *)(WDT_BASE + 0x14))
#define NVIC_ISER0 ((volatile unsigned *)0xE000E100)
#define NVIC_ISER1 ((volatile unsigned *)0xE000E104)
#define NVIC_ISER2 ((volatile unsigned *)0xE000E108)
#define NVIC_ISER3 ((volatile unsigned *)0xE000E10C)
#define NVIC_ISER4 ((volatile unsigned *)0xE000E110)
#define NVIC_ISER5 ((volatile unsigned *)0xE000E114)
#define NVIC_ISER6 ((volatile unsigned *)0xE000E118)
#define NVIC_ISER7 ((volatile unsigned *)0xE000E11C)
#define I2C_CON ((volatile unsigned *)(I2C_BASE + 0x00))
#define I2C_TAR ((volatile unsigned *)(I2C_BASE + 0x04))
#define I2C_DATA_CMD ((volatile unsigned *)(I2C_BASE + 0x10))
#define I2C_SS_SCL_HCNT ((volatile unsigned *)(I2C_BASE + 0x14))
#define I2C_SS_SCL_LCNT ((volatile unsigned *)(I2C_BASE + 0x18))
#define I2C_FS_SCL_HCNT ((volatile unsigned *)(I2C_BASE + 0x1c))
#define I2C_FS_SCL_LCNT ((volatile unsigned *)(I2C_BASE + 0x20))
#define I2C_INTR_STAT ((volatile unsigned *)(I2C_BASE + 0x2c))
#define I2C_INTR_EN ((volatile unsigned *)(I2C_BASE + 0x30))
#define I2C_RAW_INTR_STAT ((volatile unsigned *)(I2C_BASE + 0x34))
#define I2C_RX_TL ((volatile unsigned *)(I2C_BASE + 0x38))
#define I2C_TX_TL ((volatile unsigned *)(I2C_BASE + 0x3c))
#define I2C_CLR_INTR ((volatile unsigned *)(I2C_BASE + 0x40))
#define I2C_CLR_RX_UNDER ((volatile unsigned *)(I2C_BASE + 0x44))
#define I2C_CLR_RX_OVER ((volatile unsigned *)(I2C_BASE + 0x48))
#define I2C_CLR_TX_OVER ((volatile unsigned *)(I2C_BASE + 0x4c))
#define I2C_CLR_TX_ABRT ((volatile unsigned *)(I2C_BASE + 0x54))
#define I2C_CLR_ACTIVITY ((volatile unsigned *)(I2C_BASE + 0x5c))
#define I2C_CLR_STOP_DET ((volatile unsigned *)(I2C_BASE + 0x60))
#define I2C_CLR_START_DET ((volatile unsigned *)(I2C_BASE + 0x64))
#define I2C_CLR_GEN_CALL ((volatile unsigned *)(I2C_BASE + 0x68))
#define I2C_ENABLE ((volatile unsigned *)(I2C_BASE + 0x6c))
#define I2C_STATUS ((volatile unsigned *)(I2C_BASE + 0x70))
#define I2C_TXFLR ((volatile unsigned *)(I2C_BASE + 0x74))
#define I2C_RXFLR ((volatile unsigned *)(I2C_BASE + 0x78))
#define I2C_SDA_HOLD ((volatile unsigned *)(I2C_BASE + 0x7c))
#define I2C_TX_ABRT_SOURCE ((volatile unsigned *)(I2C_BASE + 0x80))
#define IC_SLV_DATA_NACK_ONLY ((volatile unsigned *)(I2C_BASE + 0x84))
#define I2C_SAR ((volatile unsigned *)(I2C_BASE + 0x08))
#define IC_ACK_GENERAL_CALL ((volatile unsigned *)(I2C_BASE + 0x98))
#define IC_CLR_RD_REQ ((volatile unsigned *)(I2C_BASE + 0x50))
#define UART0_RBR ((volatile unsigned *)(UART0_BASE + 0x00))
#define UART0_THR ((volatile unsigned *)(UART0_BASE + 0x00))
#define UART0_DLL ((volatile unsigned *)(UART0_BASE + 0x00))
#define UART0_IER ((volatile unsigned *)(UART0_BASE + 0x04))
#define UART0_DLH ((volatile unsigned *)(UART0_BASE + 0x04))
#define UART0_IIR ((volatile unsigned *)(UART0_BASE + 0x08))
#define UART0_FCR ((volatile unsigned *)(UART0_BASE + 0x08))
#define UART0_TCR ((volatile unsigned *)(UART0_BASE + 0x0c))
#define UART0_MCR ((volatile unsigned *)(UART0_BASE + 0x10))
#define UART0_TSR ((volatile unsigned *)(UART0_BASE + 0x14))
#define UART0_MSR ((volatile unsigned *)(UART0_BASE + 0x18))
#define UART0_USR ((volatile unsigned *)(UART0_BASE + 0x7c))
#define UART1_RBR ((volatile unsigned *)(UART1_BASE + 0x00))
#define UART1_THR ((volatile unsigned *)(UART1_BASE + 0x00))
#define UART1_DLL ((volatile unsigned *)(UART1_BASE + 0x00))
#define UART1_IER ((volatile unsigned *)(UART1_BASE + 0x04))
#define UART1_DLH ((volatile unsigned *)(UART1_BASE + 0x04))
#define UART1_IIR ((volatile unsigned *)(UART1_BASE + 0x08))
#define UART1_FCR ((volatile unsigned *)(UART1_BASE + 0x08))
#define UART1_TCR ((volatile unsigned *)(UART1_BASE + 0x0c))
#define UART1_MCR ((volatile unsigned *)(UART1_BASE + 0x10))
#define UART1_TSR ((volatile unsigned *)(UART1_BASE + 0x14))
#define UART1_MSR ((volatile unsigned *)(UART1_BASE + 0x18))
#define UART1_USR ((volatile unsigned *)(UART1_BASE + 0x7c))
#define DMAS_EN ((volatile unsigned *)(DMAS_BASE + 0x00))
#define DMAS_CLR ((volatile unsigned *)(DMAS_BASE + 0x04))
#define DMAS_STA ((volatile unsigned *)(DMAS_BASE + 0x08))
#define DMAS_INT_RAW ((volatile unsigned *)(DMAS_BASE + 0x0C))
#define DMAS_INT_EN0 ((volatile unsigned *)(DMAS_BASE + 0x10))
#define DMAS_INT_EN1 ((volatile unsigned *)(DMAS_BASE + 0x14))
#define DMAS_INT0 ((volatile unsigned *)(DMAS_BASE + 0x1C))
#define DMAS_INT1 ((volatile unsigned *)(DMAS_BASE + 0x20))
#define DMAS_INT_CLR ((volatile unsigned *)(DMAS_BASE + 0x28))
#define DMAS_INTV_UNIT ((volatile unsigned *)(DMAS_BASE + 0x2C))
#define DMAS_CH0_SAR ((volatile unsigned *)(DMAS_BASE + 0x40))
#define DMAS_CH0_DAR ((volatile unsigned *)(DMAS_BASE + 0x44))
#define DMAS_CH0_CTL0 ((volatile unsigned *)(DMAS_BASE + 0x48))
#define DMAS_CH0_CTL1 ((volatile unsigned *)(DMAS_BASE + 0x4C))
#define DMAS_CH0_CA ((volatile unsigned *)(DMAS_BASE + 0x50))
#define DMAS_CH1_SAR ((volatile unsigned *)(DMAS_BASE + 0x60))
#define DMAS_CH1_DAR ((volatile unsigned *)(DMAS_BASE + 0x64))
#define DMAS_CH1_CTL0 ((volatile unsigned *)(DMAS_BASE + 0x68))
#define DMAS_CH1_CTL1 ((volatile unsigned *)(DMAS_BASE + 0x6C))
#define DMAS_CH1_CA ((volatile unsigned *)(DMAS_BASE + 0x70))
#define DMAS_CH2_SAR ((volatile unsigned *)(DMAS_BASE + 0x80))
#define DMAS_CH2_DAR ((volatile unsigned *)(DMAS_BASE + 0x84))
#define DMAS_CH2_CTL0 ((volatile unsigned *)(DMAS_BASE + 0x88))
#define DMAS_CH2_CTL1 ((volatile unsigned *)(DMAS_BASE + 0x8C))
#define DMAS_CH2_CA ((volatile unsigned *)(DMAS_BASE + 0x90))
#define DMAS_CH3_SAR ((volatile unsigned *)(DMAS_BASE + 0xA0))
#define DMAS_CH3_DAR ((volatile unsigned *)(DMAS_BASE + 0xA4))
#define DMAS_CH3_CTL0 ((volatile unsigned *)(DMAS_BASE + 0xA8))
#define DMAS_CH3_CTL1 ((volatile unsigned *)(DMAS_BASE + 0xAC))
#define DMAS_CH3_CA ((volatile unsigned *)(DMAS_BASE + 0xB0))
#define DMAS_CH8_SAR ((volatile unsigned *)(DMAS_BASE + 0x140))
#define DMAS_CH8_DAR ((volatile unsigned *)(DMAS_BASE + 0x144))
#define DMAS_CH8_CTL0 ((volatile unsigned *)(DMAS_BASE + 0x148))
#define DMAS_CH8_CTL1 ((volatile unsigned *)(DMAS_BASE + 0x14C))
#define DMAS_CH8_CA ((volatile unsigned *)(DMAS_BASE + 0x150))
#define DMAS_CH9_SAR ((volatile unsigned *)(DMAS_BASE + 0x160))
#define DMAS_CH9_DAR ((volatile unsigned *)(DMAS_BASE + 0x164))
#define DMAS_CH9_CTL0 ((volatile unsigned *)(DMAS_BASE + 0x168))
#define DMAS_CH9_CTL1 ((volatile unsigned *)(DMAS_BASE + 0x16C))
#define DMAS_CH9_CA ((volatile unsigned *)(DMAS_BASE + 0x170))
#define DMAS_CH10_SAR ((volatile unsigned *)(DMAS_BASE + 0x180))
#define DMAS_CH10_DAR ((volatile unsigned *)(DMAS_BASE + 0x184))
#define DMAS_CH10_CTL0 ((volatile unsigned *)(DMAS_BASE + 0x188))
#define DMAS_CH10_CTL1 ((volatile unsigned *)(DMAS_BASE + 0x18C))
#define DMAS_CH10_CA ((volatile unsigned *)(DMAS_BASE + 0x190))
#define DMAS_CH11_SAR ((volatile unsigned *)(DMAS_BASE + 0x1A0))
#define DMAS_CH11_DAR ((volatile unsigned *)(DMAS_BASE + 0x1A4))
#define DMAS_CH11_CTL0 ((volatile unsigned *)(DMAS_BASE + 0x1A8))
#define DMAS_CH11_CTL1 ((volatile unsigned *)(DMAS_BASE + 0x1AC))
#define DMAS_CH11_CA ((volatile unsigned *)(DMAS_BASE + 0x1B0))
#define DMAS_CH0_WD ((volatile unsigned *)(DMAS_BASE + 0x240))
#define DMAS_CH1_WD ((volatile unsigned *)(DMAS_BASE + 0x244))
#define DMAS_CH2_WD ((volatile unsigned *)(DMAS_BASE + 0x248))
#define DMAS_CH3_WD ((volatile unsigned *)(DMAS_BASE + 0x24C))
#define DMAS_LP_CTL ((volatile unsigned *)(DMAS_BASE + 0x3FC))
#define CPR_SLP_SRC_MASK ((volatile unsigned *)(CPR_BASE + 0x000))
//#define CPR_SLP_CTL ((volatile unsigned *)(CPR_BASE + 0x004))
//#define CPR_SLPCTL_INT_MASK ((volatile unsigned *)(CPR_BASE + 0x008))
//#define CPR_SLP_PD_MASK ((volatile unsigned *)(CPR_BASE + 0x00c))
#define CPR_SLP_CNT_LIMIT ((volatile unsigned *)(CPR_BASE + 0x010))
#define CPR_SLP_ST ((volatile unsigned *)(CPR_BASE + 0x014))
#define CPR_SLP_FSM_STATE ((volatile unsigned *)(CPR_BASE + 0x018))
//#define CPR_SYSST_TIME ((volatile unsigned *)(CPR_BASE + 0x01c))
#define CPR_M0_FCLK_GRCTL ((volatile unsigned *)(CPR_BASE + 0x020))
#define CPR_CTL_PCLK_GRCTL ((volatile unsigned *)(CPR_BASE + 0x024))
#define CPR_SIM_CLK_GRCTL ((volatile unsigned *)(CPR_BASE + 0x028))
#define CPR_SIM_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x02c))
#define CPR_UART0_CLK_GRCTL ((volatile unsigned *)(CPR_BASE + 0x030))
#define CPR_UART0_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x034))
#define CPR_UART1_CLK_GRCTL ((volatile unsigned *)(CPR_BASE + 0x038))
#define CPR_UART1_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x03c))
#define CPR_BT_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x040))
#define CPR_BTRF_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x044))
#define CPR_BT_MODEM_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x048))
#define CPR_QDEC_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x04c))
#define CPR_SPI0_MCLK_CTL ((volatile unsigned *)(CPR_BASE + 0x050))
#define CPR_SPI1_MCLK_CTL ((volatile unsigned *)(CPR_BASE + 0x054))
#define CPR_TIMER0_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x058))
#define CPR_TIMER1_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x05c))
#define CPR_TIMER2_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x060))
#define CPR_TIMER3_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x064))
#define CPR_PWM_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x068))
#define CPR_AHBCLKEN_GRCTL ((volatile unsigned *)(CPR_BASE + 0x06c))
#define CPR_CTLAPBCLKEN_GRCTL ((volatile unsigned *)(CPR_BASE + 0x070))
#define CPR_OTHERCLKEN_GRCTL ((volatile unsigned *)(CPR_BASE + 0x074))
#define CPR_I2C_CLK_CTL ((volatile unsigned *)(CPR_BASE + 0x078))
#define CPR_INT ((volatile unsigned *)(CPR_BASE + 0x0a0))
#define CPR_INT_EN ((volatile unsigned *)(CPR_BASE + 0x0a4))
#define CPR_INT_RAW ((volatile unsigned *)(CPR_BASE + 0x0a8))
#if 0
#define CPR_PD_FLAG ((volatile unsigned *)(CPR_BASE + 0x0ac))
#define CPR_ROM_PD_CTL ((volatile unsigned *)(CPR_BASE + 0x0b0))
#define CPR_ROM_PD_CNT1 ((volatile unsigned *)(CPR_BASE + 0x0b4))
#define CPR_ROM_PD_CNT2 ((volatile unsigned *)(CPR_BASE + 0x0b8))
#define CPR_ROM_PD_CNT3 ((volatile unsigned *)(CPR_BASE + 0x0bc))
#define CPR_BTRF_PD_CTL ((volatile unsigned *)(CPR_BASE + 0x0c0))
#define CPR_BTRF_PD_CNT1 ((volatile unsigned *)(CPR_BASE + 0x0c4))
#define CPR_BTRF_PD_CNT2 ((volatile unsigned *)(CPR_BASE + 0x0c8))
#define CPR_BTRF_PD_CNT3 ((volatile unsigned *)(CPR_BASE + 0x0cc))
#define CPR_M0RAM_PD_CTL ((volatile unsigned *)(CPR_BASE + 0x0d0))
#define CPR_M0RAM_PD_CNT1 ((volatile unsigned *)(CPR_BASE + 0x0d4))
#define CPR_M0RAM_PD_CNT2 ((volatile unsigned *)(CPR_BASE + 0x0d8))
#define CPR_M0RAM_PD_CNT3 ((volatile unsigned *)(CPR_BASE + 0x0dc))
#define CPR_SHRAM0_PD_CTL ((volatile unsigned *)(CPR_BASE + 0x0e0))
#define CPR_SHRAM0_PD_CNT1 ((volatile unsigned *)(CPR_BASE + 0x0e4))
#define CPR_SHRAM0_PD_CNT2 ((volatile unsigned *)(CPR_BASE + 0x0e8))
#define CPR_SHRAM0_PD_CNT3 ((volatile unsigned *)(CPR_BASE + 0x0ec))
#define CPR_SHRAM1_PD_CTL ((volatile unsigned *)(CPR_BASE + 0x0f0))
#define CPR_SHRAM1_PD_CNT1 ((volatile unsigned *)(CPR_BASE + 0x0f4))
#define CPR_SHRAM1_PD_CNT2 ((volatile unsigned *)(CPR_BASE + 0x0f8))
#define CPR_SHRAM1_PD_CNT3 ((volatile unsigned *)(CPR_BASE + 0x0fc))
#else
#define CPR_GPIO_FUN_SEL0 ((volatile unsigned *)(CPR_BASE + 0x0c0))
#define CPR_GPIO_FUN_SEL1 ((volatile unsigned *)(CPR_BASE + 0x0c4))
#define CPR_GPIO_FUN_SEL2 ((volatile unsigned *)(CPR_BASE + 0x0c8))
#define CPR_GPIO_FUN_SEL3 ((volatile unsigned *)(CPR_BASE + 0x0cc))
#define CPR_GPIO_FUN_SEL4 ((volatile unsigned *)(CPR_BASE + 0x0d0))
#define CPR_GPIO_FUN_SEL5 ((volatile unsigned *)(CPR_BASE + 0x0d4))
#define CPR_GPIO_FUN_SEL6 ((volatile unsigned *)(CPR_BASE + 0x0d8))
#define CPR_GPIO_FUN_SEL7 ((volatile unsigned *)(CPR_BASE + 0x0dc))
#endif
#define CPR_RSTCTL_CTLAPB_SW ((volatile unsigned *)(CPR_BASE + 0x100))
#define CPR_RSTCTL_SUBRST_SW ((volatile unsigned *)(CPR_BASE + 0x104))
#define CPR_RSTCTL_M0RST_SW ((volatile unsigned *)(CPR_BASE + 0x108))
#define CPR_RSTCTL_M0RST_MASK ((volatile unsigned *)(CPR_BASE + 0x10c))
#define CPR_RSTCTL_LOCKUP_STATE ((volatile unsigned *)(CPR_BASE + 0x110))
#define CPR_RSTCTL_WDTRST_MASK ((volatile unsigned *)(CPR_BASE + 0x114))
#define CPR_LP_CTL ((volatile unsigned *)(CPR_BASE + 0x118))
#define CPR_RAM_RET1N ((volatile unsigned *)(CPR_BASE + 0x11c))
#define CPR_CTL_M0_RAM_ICM_PRI ((volatile unsigned *)(CPR_BASE + 0x120))
#define CPR_CTL_CTLAPB_ICM_PRI ((volatile unsigned *)(CPR_BASE + 0x124))
#define CPR_CTL_MUXCTL1 ((volatile unsigned *)(CPR_BASE + 0x128))
#define CPR_CTL_MUXCTL2 ((volatile unsigned *)(CPR_BASE + 0x12c))
#define CPR_CTL_MUXCTL3 ((volatile unsigned *)(CPR_BASE + 0x19c))
#define CPR_CTL_PECTL1 ((volatile unsigned *)(CPR_BASE + 0x130))
#define CPR_CTL_PECTL2 ((volatile unsigned *)(CPR_BASE + 0x134))
#define CPR_CTL_RAM_EMA ((volatile unsigned *)(CPR_BASE + 0x138))
#define CPR_REMAP_CTRL ((volatile unsigned *)(CPR_BASE + 0x13c))
#define CPR_CTL_BOOTCTL ((volatile unsigned *)(CPR_BASE + 0x140))
#define CPR_CTL_M0_STCALIB ((volatile unsigned *)(CPR_BASE + 0x144))
#define CPR_CTL_M0_IRQLATENCY ((volatile unsigned *)(CPR_BASE + 0x148))
//#define CPR_CTL_CLK32K ((volatile unsigned *)(CPR_BASE + 0x14c))
//#define CPR_AO_SYNC ((volatile unsigned *)(CPR_BASE + 0x150))
//#define CPR_AO_REG0 ((volatile unsigned *)(CPR_BASE + 0x154))
//#define CPR_AO_REG1 ((volatile unsigned *)(CPR_BASE + 0x158))
//#define CPR_AO_CTRL ((volatile unsigned *)(CPR_BASE + 0x15c))
#define CPR_SSI_CTRL ((volatile unsigned *)(CPR_BASE + 0x160))
#define CPR_PMU_LDO ((volatile unsigned *)(CPR_BASE + 0x164))
#define CPR_PMU_BOOST ((volatile unsigned *)(CPR_BASE + 0x168))
#define CPR_PMU_BUCK ((volatile unsigned *)(CPR_BASE + 0x16c))
#define CPR_TEST_CTRL0 ((volatile unsigned *)(CPR_BASE + 0x170))
#define CPR_TEST_CTRL1 ((volatile unsigned *)(CPR_BASE + 0x174))
#define CPR_TEST_CTRL2 ((volatile unsigned *)(CPR_BASE + 0x178))
#define CPR_TEST_CTRL3 ((volatile unsigned *)(CPR_BASE + 0x17c))
#define CPR_TEST_CTRL4 ((volatile unsigned *)(CPR_BASE + 0x180))
#define CPR_TEST_CTRL5 ((volatile unsigned *)(CPR_BASE + 0x184))
#define CPR_TEST_CTRL6 ((volatile unsigned *)(CPR_BASE + 0x188))
#define CPR_TEST_CTRL7 ((volatile unsigned *)(CPR_BASE + 0x19c))
#define CPR_TEST_CTRL8 ((volatile unsigned *)(CPR_BASE + 0x190))
#define CPR_TEST_CTRL9 ((volatile unsigned *)(CPR_BASE + 0x194))
//#define CPR_SIM_CARD ((volatile unsigned *)(CPR_BASE + 0x198))
//- CPR_AO
#define CPR_SLP_CTL ((volatile unsigned *)(CPR_AO_BASE + 0x4))
#define CPR_SLPCTL_INT_MASK ((volatile unsigned *)(CPR_AO_BASE + 0x8))
#define CPR_SLP_PD_MASK ((volatile unsigned *)(CPR_AO_BASE + 0xC))
#define CPR_MCLK_DIV_CLK_CTL ((volatile unsigned *)(CPR_AO_BASE + 0x10))
#define CPR_RFPMU_SPI_CTL ((volatile unsigned *)(CPR_AO_BASE + 0x14))
#define CPR_SYS_TIME ((volatile unsigned *)(CPR_AO_BASE + 0x1C))
#define CPR_AOCLKEN_GRCTL ((volatile unsigned *)(CPR_AO_BASE + 0x7C))
#define CPR_CTL_CLK32K ((volatile unsigned *)(CPR_AO_BASE + 0x14C))
#define CPR_AO_REG0 ((volatile unsigned *)(CPR_AO_BASE + 0x154))
#define CPR_AO_REG1 ((volatile unsigned *)(CPR_AO_BASE + 0x158))
#define CPR_AO_CTRL ((volatile unsigned *)(CPR_AO_BASE + 0x15C))
#define BT_BASE 0x40020000
#define BT_LC_BASE BT_BASE+0x6000
#define BT_DSP_BASE BT_BASE+0x8000
#define BT_PTA_BASE BT_BASE+0x9000
#define BT_PHY_BASE BT_BASE+0xC000
#define LE_BASE BT_BASE+0xa000
//lc reg
#define BT_BD_ADDR_LOW ((volatile unsigned *)(BT_LC_BASE+0x0))
#define BT_BD_ADDR_HIGH ((volatile unsigned *)(BT_LC_BASE+0x4))
#define BT_SYNCWORD_LOW ((volatile unsigned *)(BT_LC_BASE+0x8))
#define BT_SYNCWORD_HIGH ((volatile unsigned *)(BT_LC_BASE+0xC))
#define BT_INTRASLOT_OFFSET ((volatile unsigned *)(BT_LC_BASE+0x10))
#define BT_CLK_UPDATE_INTRASLOT_VALUE ((volatile unsigned *)(BT_LC_BASE+0x14))
#define BT_CLK_OFFSET ((volatile unsigned *)(BT_LC_BASE+0x18))
#define BT_NATIVE_CLK ((volatile unsigned *)(BT_LC_BASE+0x1C))
#define BT_COMMON_CTRL0 ((volatile unsigned *)(BT_LC_BASE+0x20))
#define BT_COMMON_CTRL1 ((volatile unsigned *)(BT_LC_BASE+0x24))
#define BT_INTR_CTRL ((volatile unsigned *)(BT_LC_BASE+0x28))
#define BT_COMMON_STAT ((volatile unsigned *)(BT_LC_BASE+0x2C))
#define BT_TX_CTRL ((volatile unsigned *)(BT_LC_BASE+0x30))
#define BT_TX_CTRL_EDR ((volatile unsigned *)(BT_LC_BASE+0x710))
#define BT_ESCO_CTRL ((volatile unsigned *)(BT_LC_BASE+0x34))
#define BT_ESCO_CTRL_EDR ((volatile unsigned *)(BT_LC_BASE+0x720))
#define BT_NATIVE_CNT ((volatile unsigned *)(BT_LC_BASE+0x38))
#define BT_CODEC_TYPE ((volatile unsigned *)(BT_LC_BASE+0x3C))
#define BT_TX_STAT ((volatile unsigned *)(BT_LC_BASE+0x40))
#define BT_RX_CTRL ((volatile unsigned *)(BT_LC_BASE+0x48))
#define BT_RX_STAT0_EDR ((volatile unsigned *)(BT_LC_BASE+0x730))
#define BT_RX_STAT0 ((volatile unsigned *)(BT_LC_BASE+0x50))
#define BT_RX_STAT1 ((volatile unsigned *)(BT_LC_BASE+0x54))
#define BT_RX_STAT2 ((volatile unsigned *)(BT_LC_BASE+0x58))
#define BT_RX_STAT3 ((volatile unsigned *)(BT_LC_BASE+0x5C))
#define BT_SER_CFG ((volatile unsigned *)(BT_LC_BASE+0x64))
#define BT_SER_READ_DATA ((volatile unsigned *)(BT_LC_BASE+0x6c))
#define BT_RX_VOL_CTRL ((volatile unsigned *)(BT_LC_BASE+0x9C))
#define BT_AUX_TIMER ((volatile unsigned *)(BT_LC_BASE+0xA0))
#define BT_PATH_DELAY ((volatile unsigned *)(BT_LC_BASE+0xB0))
#define BT_ENCRYP_KEY_LENGTH ((volatile unsigned *)(BT_LC_BASE+0xB8))
#define BT_ENCRYP_KEY0 ((volatile unsigned *)(BT_LC_BASE+0xC0))
#define BT_ENCRYP_KEY1 ((volatile unsigned *)(BT_LC_BASE+0xC4))
#define BT_ENCRYP_KEY2 ((volatile unsigned *)(BT_LC_BASE+0xC8))
#define BT_ENCRYP_KEY3 ((volatile unsigned *)(BT_LC_BASE+0xCC))
#define BT_HSE0 ((volatile unsigned *)(BT_LC_BASE+0xD0))
#define BT_HSE1 ((volatile unsigned *)(BT_LC_BASE+0xD4))
#define BT_HSE2 ((volatile unsigned *)(BT_LC_BASE+0xD8))
#define BT_HSE3 ((volatile unsigned *)(BT_LC_BASE+0xDC))
#define BT_CLK_CTRL ((volatile unsigned *)(BT_LC_BASE+0xF0))
#define BT_MEM_CFG ((volatile unsigned *)(BT_LC_BASE+0xF4))
#define BT_REV_CODE ((volatile unsigned *)(BT_LC_BASE+0xF8))
#define BT_RESET_CTRL ((volatile unsigned *)(BT_LC_BASE+0xFC))
#define BT_WR_RX_HPF_FILTER ((volatile unsigned *)(BT_LC_BASE+0x110))
#define BT_WR_RX_PF1_FILTER_A ((volatile unsigned *)(BT_LC_BASE+0x114))
#define BT_WR_RX_PF1_FILTER_B ((volatile unsigned *)(BT_LC_BASE+0x118))
#define BT_WR_RX_PF2_FILTER ((volatile unsigned *)(BT_LC_BASE+0x11C))
#define BT_WR_RX_PF3_FILTER ((volatile unsigned *)(BT_LC_BASE+0x120))
#define BT_WR_RX_CVSD_FILTER_A ((volatile unsigned *)(BT_LC_BASE+0x124))
#define BT_WR_RX_CVSD_FILTER_B ((volatile unsigned *)(BT_LC_BASE+0x128))
#define BT_WR_TX_HPF_FILTER ((volatile unsigned *)(BT_LC_BASE+0x130))
#define BT_WR_TX_PF1_FILTER_A ((volatile unsigned *)(BT_LC_BASE+0x134))
#define BT_WR_TX_PF1_FILTER_B ((volatile unsigned *)(BT_LC_BASE+0x138))
#define BT_WR_TX_PF2_FILTER ((volatile unsigned *)(BT_LC_BASE+0x13C))
#define BT_WR_TX_PF3_FILTER ((volatile unsigned *)(BT_LC_BASE+0x140))
#define BT_WR_TX_CVSD_FILTER_A ((volatile unsigned *)(BT_LC_BASE+0x144))
#define BT_WR_TX_CVSD_FILTER_B ((volatile unsigned *)(BT_LC_BASE+0x148))
#define BT_TX_HPF_FILTER ((volatile unsigned *)(BT_LC_BASE+0x150))
#define BT_TX_PF1_FILTER_A ((volatile unsigned *)(BT_LC_BASE+0x154))
#define BT_TX_PF1_FILTER_B ((volatile unsigned *)(BT_LC_BASE+0x158))
#define BT_TX_PF2_FILTER ((volatile unsigned *)(BT_LC_BASE+0x15C))
#define BT_TX_PF3_FILTER ((volatile unsigned *)(BT_LC_BASE+0x160))
#define BT_TX_CVSD_FILTER_A ((volatile unsigned *)(BT_LC_BASE+0x164))
#define BT_TX_CVSD_FILTER_B ((volatile unsigned *)(BT_LC_BASE+0x168))
#define BT_RX_HPF_FILTER ((volatile unsigned *)(BT_LC_BASE+0x170))
#define BT_RX_PF1_FILTER_A ((volatile unsigned *)(BT_LC_BASE+0x174))
#define BT_RX_PF1_FILTER_B ((volatile unsigned *)(BT_LC_BASE+0x178))
#define BT_RX_PF2_FILTER ((volatile unsigned *)(BT_LC_BASE+0x17C))
#define BT_RX_PF3_FILTER ((volatile unsigned *)(BT_LC_BASE+0x180))
#define BT_RX_CVSD_FILTER_A ((volatile unsigned *)(BT_LC_BASE+0x184))
#define BT_RX_CVSD_FILTER_B ((volatile unsigned *)(BT_LC_BASE+0x188))
#define BT_SCO_FIFO_CTRL ((volatile unsigned *)(BT_LC_BASE+0x1A0))
#define BT_SCO_FIFO_TX_DATA ((volatile unsigned *)(BT_LC_BASE+0x1A4))
#define BT_SCO_FIFO_RX_DATA ((volatile unsigned *)(BT_LC_BASE+0x1A4))
#define BT_TX_ACL ((volatile unsigned *)(BT_LC_BASE+0x200))
#define BT_RX_ACL ((volatile unsigned *)(BT_LC_BASE+0x400))
#define BT_TX_ACL_EDR ((volatile unsigned *)(BT_LC_BASE+0x740))
#define BT_RX_ACL_EDR ((volatile unsigned *)(BT_LC_BASE+0xB80))
#define BT_SER_DATA16_0 ((volatile unsigned *)(BT_LC_BASE+0x600))
#define BT_SER_DATA16_1 ((volatile unsigned *)(BT_LC_BASE+0x604))
#define BT_SER_DATA16_2 ((volatile unsigned *)(BT_LC_BASE+0x608))
#define BT_SER_DATA16_3 ((volatile unsigned *)(BT_LC_BASE+0x60C))
#define BT_SER_DATA16_4 ((volatile unsigned *)(BT_LC_BASE+0x610))
#define BT_SER_DATA16_5 ((volatile unsigned *)(BT_LC_BASE+0x614))
#define BT_SER_DATA16_6 ((volatile unsigned *)(BT_LC_BASE+0x618))
#define BT_SER_DATA16_7 ((volatile unsigned *)(BT_LC_BASE+0x61C))
#define BT_SER_DATA16_8 ((volatile unsigned *)(BT_LC_BASE+0x620))
#define BT_SER_DATA16_9 ((volatile unsigned *)(BT_LC_BASE+0x624))
#define BT_SER_DATA16_10 ((volatile unsigned *)(BT_LC_BASE+0x628))
#define BT_SER_DATA16_11 ((volatile unsigned *)(BT_LC_BASE+0x62C))
#define BT_SER_DATA16_12 ((volatile unsigned *)(BT_LC_BASE+0x630))
#define BT_SER_DATA16_13 ((volatile unsigned *)(BT_LC_BASE+0x634))
#define BT_SER_DATA16_14 ((volatile unsigned *)(BT_LC_BASE+0x638))
#define BT_SER_DATA16_15 ((volatile unsigned *)(BT_LC_BASE+0x63C))
#define BT_EDR_CTRL ((volatile unsigned *)(BT_LC_BASE+0x700))
#define BT_SPI_CFG ((volatile unsigned *)(BT_LC_BASE+0x60))
#define BT_SER_CTRL ((volatile unsigned *)(BT_LC_BASE+0x64))
#define BT_SPI_RD_DATA ((volatile unsigned *)(BT_LC_BASE+0x6C))
#define BT_SPI_DATA0 ((volatile unsigned *)(BT_LC_BASE+0x70))
#define BT_SPI_DATA1 ((volatile unsigned *)(BT_LC_BASE+0x74))
#define BT_SPI_DATA2 ((volatile unsigned *)(BT_LC_BASE+0x78))
#define BT_SPI_DATA3 ((volatile unsigned *)(BT_LC_BASE+0x7C))
//dsp reg
#define BT_DSP_RX_CTRL ((volatile unsigned *)(BT_DSP_BASE+0x8))
#define BT_DSP_INTR_CTRL0 ((volatile unsigned *)(BT_DSP_BASE+0x20))
#define BT_DSP_INTR_CTRL1 ((volatile unsigned *)(BT_DSP_BASE+0x24))
#define BT_PHY_CFG ((volatile unsigned *)(BT_DSP_BASE+0x28))
#define BT_DSP_STAT ((volatile unsigned *)(BT_DSP_BASE+0x2C))
#define BT_GIO_HIGH_CTRL_01 ((volatile unsigned *)(BT_DSP_BASE+0x30))
#define BT_GIO_HIGH_CTRL_23 ((volatile unsigned *)(BT_DSP_BASE+0x34))
#define BT_GIO_HIGH_CTRL_45 ((volatile unsigned *)(BT_DSP_BASE+0x38))
#define BT_GIO_HIGH_CTRL_67 ((volatile unsigned *)(BT_DSP_BASE+0x3C))
#define BT_GIO_HIGH_CTRL_89 ((volatile unsigned *)(BT_DSP_BASE+0x40))
#define BT_GIO_HIGH_CTRL_1011 ((volatile unsigned *)(BT_DSP_BASE+0x44))
#define BT_GIO_LOW_CTRL_01 ((volatile unsigned *)(BT_DSP_BASE+0x48))
#define BT_GIO_LOW_CTRL_23 ((volatile unsigned *)(BT_DSP_BASE+0x4C))
#define BT_GIO_LOW_CTRL_45 ((volatile unsigned *)(BT_DSP_BASE+0x50))
#define BT_GIO_LOW_CTRL_67 ((volatile unsigned *)(BT_DSP_BASE+0x54))
#define BT_GIO_LOW_CTRL_89 ((volatile unsigned *)(BT_DSP_BASE+0x58))
#define BT_GIO_LOW_CTRL_1011 ((volatile unsigned *)(BT_DSP_BASE+0x5C))
#define BT_GIO_COMB_0123 ((volatile unsigned *)(BT_DSP_BASE+0x60))
#define BT_GIO_COMB_4567 ((volatile unsigned *)(BT_DSP_BASE+0x64))
#define BT_GIO_COMB_891011 ((volatile unsigned *)(BT_DSP_BASE+0x68))
#define BT_GIO_WIN_EXT_HIGH_011 ((volatile unsigned *)(BT_DSP_BASE+0x80))
#define BT_GIO_WIN_EXT_LOW_011 ((volatile unsigned *)(BT_DSP_BASE+0x84))
//PTA
#define BT_GIO_HIGH_CTRL_1213 ((volatile unsigned *)(BT_PTA_BASE+0xB0))
#define BT_GIO_HIGH_CTRL_1415 ((volatile unsigned *)(BT_PTA_BASE+0xB4))
#define BT_GIO_HIGH_CTRL_1617 ((volatile unsigned *)(BT_PTA_BASE+0xB8))
#define BT_GIO_HIGH_CTRL_1819 ((volatile unsigned *)(BT_PTA_BASE+0xBC))
#define BT_GIO_HIGH_CTRL_2021 ((volatile unsigned *)(BT_PTA_BASE+0xC0))
#define BT_GIO_HIGH_CTRL_2223 ((volatile unsigned *)(BT_PTA_BASE+0xC4))
#define BT_GIO_LOW_CTRL_1213 ((volatile unsigned *)(BT_PTA_BASE+0xC8))
#define BT_GIO_LOW_CTRL_1415 ((volatile unsigned *)(BT_PTA_BASE+0xCC))
#define BT_GIO_LOW_CTRL_1617 ((volatile unsigned *)(BT_PTA_BASE+0xD0))
#define BT_GIO_LOW_CTRL_1819 ((volatile unsigned *)(BT_PTA_BASE+0xD4))
#define BT_GIO_LOW_CTRL_2021 ((volatile unsigned *)(BT_PTA_BASE+0xD8))
#define BT_GIO_LOW_CTRL_2223 ((volatile unsigned *)(BT_PTA_BASE+0xDC))
#define BT_GIO_COMB_12131415 ((volatile unsigned *)(BT_PTA_BASE+0xE0))
#define BT_GIO_COMB_16171819 ((volatile unsigned *)(BT_PTA_BASE+0xE4))
#define BT_GIO_COMB_20212223 ((volatile unsigned *)(BT_PTA_BASE+0xE8))
#define BT_GIO_WIN_EXT_HIGH_1223 ((volatile unsigned *)(BT_PTA_BASE+0xF0))
#define BT_GIO_WIN_EXT_LOW_1223 ((volatile unsigned *)(BT_PTA_BASE+0xF4))
//phy reg
#define BTPHY_CTL0 ((volatile unsigned *)(BT_PHY_BASE+0x240))
#define BTPHY_CTL1 ((volatile unsigned *)(BT_PHY_BASE+0x244))
#define BTPHY_SYNCWORD ((volatile unsigned *)(BT_PHY_BASE+0x248))
#define BTPHY_MODEM_PARAM0 ((volatile unsigned *)(BT_PHY_BASE+0x250))
#define BTPHY_MODEM_PARAM1 ((volatile unsigned *)(BT_PHY_BASE+0x258))
#define BTPHY_MODEM_PARAM2 ((volatile unsigned *)(BT_PHY_BASE+0x25c))
#define BTPHY_MODEM_PARAM3 ((volatile unsigned *)(BT_PHY_BASE+0x260))
#define BTPHY_AGC_CTL0 ((volatile unsigned *)(BT_PHY_BASE+0x264))
#define BTPHY_AGC_CTL1 ((volatile unsigned *)(BT_PHY_BASE+0x268))
#define BTPHY_AGC_CTL2 ((volatile unsigned *)(BT_PHY_BASE+0x26c))
#define BTPHY_DC_NOTCH_CTL ((volatile unsigned *)(BT_PHY_BASE+0x270))
#define BTPHY_DATAPATH_CTL ((volatile unsigned *)(BT_PHY_BASE+0x274))
#define BTPHY_TXRX_CTL ((volatile unsigned *)(BT_PHY_BASE+0x278))
#define BTPHY_TXDELAY_CTL0 ((volatile unsigned *)(BT_PHY_BASE+0x27c))
#define BTPHY_TXDELAY_CTL1 ((volatile unsigned *)(BT_PHY_BASE+0x280))
#define BTPHY_TXDELAY_CTL2 ((volatile unsigned *)(BT_PHY_BASE+0x284))
#define BTPHY_RXDELAY_CTL0 ((volatile unsigned *)(BT_PHY_BASE+0x288))
#define BTPHY_RXDELAY_CTL1 ((volatile unsigned *)(BT_PHY_BASE+0x28c))
#define BTPHY_RXDELAY_CTL2 ((volatile unsigned *)(BT_PHY_BASE+0x290))
#define BTPHY_SOFTGAIN_CTL ((volatile unsigned *)(BT_PHY_BASE+0x294))
#define BTPHY_AGCCFG_CTL0 ((volatile unsigned *)(BT_PHY_BASE+0x298))
#define BTPHY_AGCCFG_CTL1 ((volatile unsigned *)(BT_PHY_BASE+0x29c))
#define BTPHY_AGCCFG_CTL2 ((volatile unsigned *)(BT_PHY_BASE+0x2a0))
#define BTPHY_AGCCFG_CTL3 ((volatile unsigned *)(BT_PHY_BASE+0x2a4))
#define BTPHY_AGCCFG_CTL4 ((volatile unsigned *)(BT_PHY_BASE+0x2a8))
#define BTPHY_AGCCFG_CTL5 ((volatile unsigned *)(BT_PHY_BASE+0x2ac))
#define BTPHY_AGCCFG_CTL6 ((volatile unsigned *)(BT_PHY_BASE+0x2b0))
#define BTPHY_AGCCFG_CTL7 ((volatile unsigned *)(BT_PHY_BASE+0x2b4))
#define BTPHY_AGCCFG_CTL8 ((volatile unsigned *)(BT_PHY_BASE+0x2b8))
#define BTPHY_AGCCFG_CTL9 ((volatile unsigned *)(BT_PHY_BASE+0x2bc))
#define BTPHY_AGCCFG_CTL10 ((volatile unsigned *)(BT_PHY_BASE+0x2c0))
#define BTPHY_AGCCFG_CTL11 ((volatile unsigned *)(BT_PHY_BASE+0x2c4))
#define BTPHY_AGCCFG_CTL12 ((volatile unsigned *)(BT_PHY_BASE+0x2c8))
#define BTPHY_AGCCFG_CTL13 ((volatile unsigned *)(BT_PHY_BASE+0x2cc))
#define BTPHY_AGCCFG_CTL14 ((volatile unsigned *)(BT_PHY_BASE+0x2d0))
#define BTPHY_AGCCFG_CTL15 ((volatile unsigned *)(BT_PHY_BASE+0x2d4))
#define BTPHY_AGCCMP_CTL0 ((volatile unsigned *)(BT_PHY_BASE+0x2d8))
#define BTPHY_AGCCMP_CTL1 ((volatile unsigned *)(BT_PHY_BASE+0x2dc))
#define BTPHY_AGCCMP_CTL2 ((volatile unsigned *)(BT_PHY_BASE+0x2e0))
#define BTPHY_AGCCMP_CTL3 ((volatile unsigned *)(BT_PHY_BASE+0x2e4))
#define BTPHY_AGCCMP_CTL4 ((volatile unsigned *)(BT_PHY_BASE+0x2e8))
#define BTPHY_AGCCMP_CTL5 ((volatile unsigned *)(BT_PHY_BASE+0x2ec))
#define BTPHY_AGCCMP_CTL6 ((volatile unsigned *)(BT_PHY_BASE+0x2f0))
#define BTPHY_AGCCMP_CTL7 ((volatile unsigned *)(BT_PHY_BASE+0x2f4))
#define BTPHY_RSSI_STAT ((volatile unsigned *)(BT_PHY_BASE+0x300))
#define BTPHY_INITAGC_STAT ((volatile unsigned *)(BT_PHY_BASE+0x304))
#define BTPHY_FINEAGC_STAT ((volatile unsigned *)(BT_PHY_BASE+0x308))
#define BTPHY_RXPWR_STAT ((volatile unsigned *)(BT_PHY_BASE+0x30c))
#define BTPHY_CFO_STAT ((volatile unsigned *)(BT_PHY_BASE+0x310))
#define BTPHY_TIMINGERR_STAT ((volatile unsigned *)(BT_PHY_BASE+0x314))
#define BTPHY_XCORR_STAT ((volatile unsigned *)(BT_PHY_BASE+0x318))
#define BTPHY_DC_STAT ((volatile unsigned *)(BT_PHY_BASE+0x310))
//le reg
#define LE_COMM_CTRL ((volatile unsigned *)(LE_BASE+0x0))
#define LE_PD_ADDR_LOW ((volatile unsigned *)(LE_BASE+0x4))
#define LE_PD_ADDR_HIGH ((volatile unsigned *)(LE_BASE+0x8))
#define LE_RD_ADDR_LOW ((volatile unsigned *)(LE_BASE+0xC))
#define LE_RD_ADDR_HIGH ((volatile unsigned *)(LE_BASE+0x10))
#define LE_ACC_ADDR ((volatile unsigned *)(LE_BASE+0x14))
#define LE_READ_ONLY_REG ((volatile unsigned *)(LE_BASE+0x18))
#define LE_CRC_INIT ((volatile unsigned *)(LE_BASE+0x1C))
#define LE_AES_KEY0 ((volatile unsigned *)(LE_BASE+0x20))
#define LE_AES_KEY1 ((volatile unsigned *)(LE_BASE+0x24))
#define LE_AES_KEY2 ((volatile unsigned *)(LE_BASE+0x28))
#define LE_AES_KEY3 ((volatile unsigned *)(LE_BASE+0x2C))
#define LE_AES_IV_LOW ((volatile unsigned *)(LE_BASE+0x30))
#define LE_AES_IV_HIGH ((volatile unsigned *)(LE_BASE+0x34))
#define LE_AES_PKT0 ((volatile unsigned *)(LE_BASE+0x38))
#define LE_AES_PKT1 ((volatile unsigned *)(LE_BASE+0x3C))
#define LE_TX_HEADER ((volatile unsigned *)(LE_BASE+0x40))
#define LE_RX_HEADER ((volatile unsigned *)(LE_BASE+0x44))
#define LE_AUX_LE_TIMER1 ((volatile unsigned *)(LE_BASE+0x48))
#define LE_AUX_LE_TIMER2 ((volatile unsigned *)(LE_BASE+0x4C))
#define LE_COMM_STATUS ((volatile unsigned *)(LE_BASE+0x50))
#define LE_AES_MIC ((volatile unsigned *)(LE_BASE+0x200))
#define LE_AES_DATA0 ((volatile unsigned *)(LE_BASE+0x204))
#define LE_AES_DATA1 ((volatile unsigned *)(LE_BASE+0x208))
#define LE_AES_DATA2 ((volatile unsigned *)(LE_BASE+0x20C))
#define LE_AES_DATA3 ((volatile unsigned *)(LE_BASE+0x210))
#define LE_AES_DATA4 ((volatile unsigned *)(LE_BASE+0x214))
#define LE_AES_DATA5 ((volatile unsigned *)(LE_BASE+0x218))
#define LE_AES_DATA6 ((volatile unsigned *)(LE_BASE+0x21C))
#define LE_DELAY_CTRL ((volatile unsigned *)(LE_BASE+0xA0))
#define LE_FILTER_CTRL ((volatile unsigned *)(LE_BASE+0x58))
#define LE_WHITE_LIST_LOW0 ((volatile unsigned *)(LE_BASE+0x60))
#define LE_WHITE_LIST_HIGH0 ((volatile unsigned *)(LE_BASE+0x64))
#define LE_WHITE_LIST_LOW1 ((volatile unsigned *)(LE_BASE+0x68))
#define LE_WHITE_LIST_HIGH1 ((volatile unsigned *)(LE_BASE+0x6C))
#define LE_WHITE_LIST_LOW2 ((volatile unsigned *)(LE_BASE+0x70))
#define LE_WHITE_LIST_HIGH2 ((volatile unsigned *)(LE_BASE+0x74))
#define LE_WHITE_LIST_LOW3 ((volatile unsigned *)(LE_BASE+0x78))
#define LE_WHITE_LIST_HIGH3 ((volatile unsigned *)(LE_BASE+0x7C))
#define LE_WHITE_LIST_LOW4 ((volatile unsigned *)(LE_BASE+0x80))
#define LE_WHITE_LIST_HIGH4 ((volatile unsigned *)(LE_BASE+0x84))
#define LE_WHITE_LIST_LOW5 ((volatile unsigned *)(LE_BASE+0x88))
#define LE_WHITE_LIST_HIGH5 ((volatile unsigned *)(LE_BASE+0x8C))
#define LE_DIRECT_ADDR_LOW ((volatile unsigned *)(LE_BASE+0x90))
#define LE_DIRECT_ADDR_HIGH ((volatile unsigned *)(LE_BASE+0x94))
#define LE_LOCAL_ADDR_LOW ((volatile unsigned *)(LE_BASE+0x98))
#define LE_LOCAL_ADDR_HIGH ((volatile unsigned *)(LE_BASE+0x9C))
#define SSI0_CTRL0 ((volatile unsigned *)(SPI0_BASE + 0x00))
#define SSI0_EN ((volatile unsigned *)(SPI0_BASE + 0x08))
#define SSI0_SE ((volatile unsigned *)(SPI0_BASE + 0x10))
#define SSI0_BAUD ((volatile unsigned *)(SPI0_BASE + 0x14))
#define SSI0_TXFTL ((volatile unsigned *)(SPI0_BASE + 0x18))
#define SSI0_RXFTL ((volatile unsigned *)(SPI0_BASE + 0x1c))
#define SSI0_TXFL ((volatile unsigned *)(SPI0_BASE + 0x20))
#define SSI0_RXFL ((volatile unsigned *)(SPI0_BASE + 0x24))
#define SSI0_STS ((volatile unsigned *)(SPI0_BASE + 0x28))
#define SSI0_IE ((volatile unsigned *)(SPI0_BASE + 0x2c))
#define SSI0_IS ((volatile unsigned *)(SPI0_BASE + 0x30))
#define SSI0_RIS ((volatile unsigned *)(SPI0_BASE + 0x34))
#define SSI0_TXOIC ((volatile unsigned *)(SPI0_BASE + 0x38))
#define SSI0_RXOIC ((volatile unsigned *)(SPI0_BASE + 0x3c))
#define SSI0_RXUIC ((volatile unsigned *)(SPI0_BASE + 0x40))
#define SSI0_IC ((volatile unsigned *)(SPI0_BASE + 0x48))
#define SSI0_DMAS ((volatile unsigned *)(SPI0_BASE + 0x4c))
#define SSI0_DMATDL ((volatile unsigned *)(SPI0_BASE + 0x50))
#define SSI0_DMARDL ((volatile unsigned *)(SPI0_BASE + 0x54))
#define SSI0_DATA ((volatile unsigned *)(SPI0_BASE + 0x60))
#define SSI0_CTRLR0 ((volatile unsigned *)(SPI0_BASE + 0xF4))
#define SSI1_CTRL0 ((volatile unsigned *)(SPI1_BASE + 0x00))
#define SSI1_EN ((volatile unsigned *)(SPI1_BASE + 0x08))
#define SSI1_SE ((volatile unsigned *)(SPI1_BASE + 0x10))
#define SSI1_BAUD ((volatile unsigned *)(SPI1_BASE + 0x14))
#define SSI1_TXFTL ((volatile unsigned *)(SPI1_BASE + 0x18))
#define SSI1_RXFTL ((volatile unsigned *)(SPI1_BASE + 0x1c))
#define SSI1_TXFL ((volatile unsigned *)(SPI1_BASE + 0x20))
#define SSI1_RXFL ((volatile unsigned *)(SPI1_BASE + 0x24))
#define SSI1_STS ((volatile unsigned *)(SPI1_BASE + 0x28))
#define SSI1_IE ((volatile unsigned *)(SPI1_BASE + 0x2c))
#define SSI1_IS ((volatile unsigned *)(SPI1_BASE + 0x30))
#define SSI1_RIS ((volatile unsigned *)(SPI1_BASE + 0x34))
#define SSI1_TXOIC ((volatile unsigned *)(SPI1_BASE + 0x38))
#define SSI1_RXOIC ((volatile unsigned *)(SPI1_BASE + 0x3c))
#define SSI1_RXUIC ((volatile unsigned *)(SPI1_BASE + 0x40))
#define SSI1_IC ((volatile unsigned *)(SPI1_BASE + 0x48))
#define SSI1_DMAS ((volatile unsigned *)(SPI1_BASE + 0x4c))
#define SSI1_DMATDL ((volatile unsigned *)(SPI1_BASE + 0x50))
#define SSI1_DMARDL ((volatile unsigned *)(SPI1_BASE + 0x54))
#define SSI1_DATA ((volatile unsigned *)(SPI1_BASE + 0x60))
#define SIM_PORT ((volatile unsigned *)(SIM_BASE + 0x0000))
#define SIM_CNTL ((volatile unsigned *)(SIM_BASE + 0x0004))
#define SIM_ENABLE ((volatile unsigned *)(SIM_BASE + 0x000c))
#define SIM_INT_STAT ((volatile unsigned *)(SIM_BASE + 0x0010))
#define SIM_INT_RAW_STAT ((volatile unsigned *)(SIM_BASE + 0x0014))
#define SIM_INT_ENABLE ((volatile unsigned *)(SIM_BASE + 0x0018))
#define SIM_XMT_BUF ((volatile unsigned *)(SIM_BASE + 0x001c))
#define SIM_RCV_BUF ((volatile unsigned *)(SIM_BASE + 0x0020))
#define SIM_XMT_TH ((volatile unsigned *)(SIM_BASE + 0x0024))
#define SIM_GUARD ((volatile unsigned *)(SIM_BASE + 0x0028))
#define SIM_SRES ((volatile unsigned *)(SIM_BASE + 0x002c))
#define SIM_CH_WAIT ((volatile unsigned *)(SIM_BASE + 0x0030))
#define SIM_GPCNT ((volatile unsigned *)(SIM_BASE + 0x0034))
#define SIM_DIVISOR ((volatile unsigned *)(SIM_BASE + 0x0038))
#define KBS_CTL ((volatile unsigned *)(KBS_BASE + 0x0000))
#define KBS_MASK ((volatile unsigned *)(KBS_BASE + 0x0004))
#define KBS_DETECT_INTVAL ((volatile unsigned *)(KBS_BASE + 0x0008))
#define KBS_DBC_INTVAL ((volatile unsigned *)(KBS_BASE + 0x000C))
#define KBS_LPRS_INTVAL ((volatile unsigned *)(KBS_BASE + 0x0010))
#define KBS_MTXKEY_MANUAL_ROWOUT ((volatile unsigned *)(KBS_BASE + 0x0014))
#define KBS_MTXKEY_MANUAL_COLIN ((volatile unsigned *)(KBS_BASE + 0x0018))
#define KBS_MTXKEY_FIFO ((volatile unsigned *)(KBS_BASE + 0x001C))
#define KBS_MTXKEY_ASREG0 ((volatile unsigned *)(KBS_BASE + 0x0020))
#define KBS_MTXKEY_ASREG1 ((volatile unsigned *)(KBS_BASE + 0x0024))
#define KBS_MTXKEY_INT ((volatile unsigned *)(KBS_BASE + 0x0028))
#define KBS_MTXKEY_INT_RAW ((volatile unsigned *)(KBS_BASE + 0x002C))
#define KBS_MTXKEY_INT_EN ((volatile unsigned *)(KBS_BASE + 0x0030))
#define QDEC_CTL ((volatile unsigned *)(QDEC_BASE + 0x0000))
#define QDEC_INT ((volatile unsigned *)(QDEC_BASE + 0x0004))
#define QDEC_INT_RAW ((volatile unsigned *)(QDEC_BASE + 0x0008))
#define QDEC_INT_EN ((volatile unsigned *)(QDEC_BASE + 0x000c))
#define QDEC_XCNT ((volatile unsigned *)(QDEC_BASE + 0x0010))
#define QDEC_YCNT ((volatile unsigned *)(QDEC_BASE + 0x0014))
#define QDEC_ZCNT ((volatile unsigned *)(QDEC_BASE + 0x0018))
#define QDEC_SAMPLE ((volatile unsigned *)(QDEC_BASE + 0x001c))
#define QDEC_FIFO_CFG ((volatile unsigned *)(QDEC_BASE + 0x0020))
#define QDEC_FIFO_NUM ((volatile unsigned *)(QDEC_BASE + 0x0024))
#define PWM0_EN ((volatile unsigned *)(PWM_BASE + 0x0000))
#define PWM0_UP ((volatile unsigned *)(PWM_BASE + 0x0004))
#define PWM0_RST ((volatile unsigned *)(PWM_BASE + 0x0008))
#define PWM0_P ((volatile unsigned *)(PWM_BASE + 0x000c))
#define PWM0_OCPY ((volatile unsigned *)(PWM_BASE + 0x0010))
#define PWM1_EN ((volatile unsigned *)(PWM_BASE + 0x0040))
#define PWM1_UP ((volatile unsigned *)(PWM_BASE + 0x0044))
#define PWM1_RST ((volatile unsigned *)(PWM_BASE + 0x0048))
#define PWM1_P ((volatile unsigned *)(PWM_BASE + 0x004c))
#define PWM1_OCPY ((volatile unsigned *)(PWM_BASE + 0x0050))
#define GPADC_MAIN_CTL ((volatile unsigned *)(GPADC_BASE + 0x0000))
#define GPADC_CHAN_CTL ((volatile unsigned *)(GPADC_BASE + 0x0004))
#define GPADC_FIFO_CTL ((volatile unsigned *)(GPADC_BASE + 0x0008))
#define GPADC_TIMER0 ((volatile unsigned *)(GPADC_BASE + 0x000c))
#define GPADC_TIMER1 ((volatile unsigned *)(GPADC_BASE + 0x0010))
#define GPADC_INT ((volatile unsigned *)(GPADC_BASE + 0x0014))
#define GPADC_INT_RAW ((volatile unsigned *)(GPADC_BASE + 0x0018))
#define GPADC_INT_EN ((volatile unsigned *)(GPADC_BASE + 0x001c))
#define GPADC_FIFO ((volatile unsigned *)(GPADC_BASE + 0x0020))
#define GPADC_RF_CTL ((volatile unsigned *)(GPADC_BASE + 0x0024))
#define AES_START ((volatile unsigned *)(AES_BASE + 0x0000))
#define AES_CTL ((volatile unsigned *)(AES_BASE + 0x0004))
#define AES_INTR ((volatile unsigned *)(AES_BASE + 0x0008))
#define AES_INTE ((volatile unsigned *)(AES_BASE + 0x000c))
#define AES_INTS ((volatile unsigned *)(AES_BASE + 0x0010))
#define AES_KEY_LEN ((volatile unsigned *)(AES_BASE + 0x0014))
#define AES_KEY_UPDATE ((volatile unsigned *)(AES_BASE + 0x0018))
#define AES_BLK_NUM ((volatile unsigned *)(AES_BASE + 0x001c))
#define AES_IN0 ((volatile unsigned *)(AES_BASE + 0x0040))
#define AES_IN1 ((volatile unsigned *)(AES_BASE + 0x0044))
#define AES_IN2 ((volatile unsigned *)(AES_BASE + 0x0048))
#define AES_IN3 ((volatile unsigned *)(AES_BASE + 0x004c))
#define AES_OUT0 ((volatile unsigned *)(AES_BASE + 0x0050))
#define AES_OUT1 ((volatile unsigned *)(AES_BASE + 0x0054))
#define AES_OUT2 ((volatile unsigned *)(AES_BASE + 0x0058))
#define AES_OUT3 ((volatile unsigned *)(AES_BASE + 0x005c))
#define AES_KEY0 ((volatile unsigned *)(AES_BASE + 0x0060))
#define AES_KEY1 ((volatile unsigned *)(AES_BASE + 0x0064))
#define AES_KEY2 ((volatile unsigned *)(AES_BASE + 0x0068))
#define AES_KEY3 ((volatile unsigned *)(AES_BASE + 0x006c))
#define AES_KEY4 ((volatile unsigned *)(AES_BASE + 0x0070))
#define AES_KEY5 ((volatile unsigned *)(AES_BASE + 0x0074))
#define AES_KEY6 ((volatile unsigned *)(AES_BASE + 0x0078))
#define AES_KEY7 ((volatile unsigned *)(AES_BASE + 0x007c))
#endif
component/boot2/bsp/startup/xinc_reg.h
+119
View File
@@ -0,0 +1,119 @@
#ifndef __XINC_HW_H
#define __XINC_HW_H
#include "xinc_map.h"
#define __RAM_CODE __attribute__((section("ram_code")))
typedef short int16_t;
typedef int int32_t;
typedef long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
//- DMAS
#define DMAS_CHx_SAR(a) ((volatile unsigned *)(DMAS_BASE + 0x40 + (a * 0x20)))
#define DMAS_CHx_DAR(a) ((volatile unsigned *)(DMAS_BASE + 0x44 + (a * 0x20)))
#define DMAS_CHx_CTL0(a) ((volatile unsigned *)(DMAS_BASE + 0x48 + (a * 0x20)))
#define DMAS_CHx_CTL1(a) ((volatile unsigned *)(DMAS_BASE + 0x4C + (a * 0x20)))
#define DMAS_CHx_CA(a) ((volatile unsigned *)(DMAS_BASE + 0x50 + (a * 0x20)))
//- TIMER
#define CPR_TIMER_CLK_CTL(a) ((volatile unsigned *)(CPR_BASE + 0x58 + (a * 0x04)))
#define TIMERx_TLC(a) ((volatile unsigned *)(TIMER_BASE + 0x00 + (a * 0x14)))
#define TIMERx_TCV(a) ((volatile unsigned *)(TIMER_BASE + 0x04 + (a * 0x14)))
#define TIMERx_TCR(a) ((volatile unsigned *)(TIMER_BASE + 0x08 + (a * 0x14)))
#define TIMERx_TIC(a) ((volatile unsigned *)(TIMER_BASE + 0x0C + (a * 0x14)))
#define TIMERx_TIS(a) ((volatile unsigned *)(TIMER_BASE + 0x10 + (a * 0x14)))
//- UART
#define CPR_UARTx_CLK_GRCTL(a) ((volatile unsigned *)(CPR_BASE + 0x30 + (a * 0x08)))
#define CPR_UARTx_CLK_CTL(a) ((volatile unsigned *)(CPR_BASE + 0x34 + (a * 0x08)))
#define UARTx_RBR(a) ((volatile unsigned *)(UART0_BASE + 0x00 + (a * 0x1000)))
#define UARTx_THR(a) ((volatile unsigned *)(UART0_BASE + 0x00 + (a * 0x1000)))
#define UARTx_DLL(a) ((volatile unsigned *)(UART0_BASE + 0x00 + (a * 0x1000)))
#define UARTx_IER(a) ((volatile unsigned *)(UART0_BASE + 0x04 + (a * 0x1000)))
#define UARTx_DLH(a) ((volatile unsigned *)(UART0_BASE + 0x04 + (a * 0x1000)))
#define UARTx_IIR(a) ((volatile unsigned *)(UART0_BASE + 0x08 + (a * 0x1000)))
#define UARTx_FCR(a) ((volatile unsigned *)(UART0_BASE + 0x08 + (a * 0x1000)))
#define UARTx_TCR(a) ((volatile unsigned *)(UART0_BASE + 0x0c + (a * 0x1000)))
#define UARTx_MCR(a) ((volatile unsigned *)(UART0_BASE + 0x10 + (a * 0x1000)))
#define UARTx_TSR(a) ((volatile unsigned *)(UART0_BASE + 0x14 + (a * 0x1000)))
#define UARTx_MSR(a) ((volatile unsigned *)(UART0_BASE + 0x18 + (a * 0x1000)))
#define UARTx_USR(a) ((volatile unsigned *)(UART0_BASE + 0x7c + (a * 0x1000)))
//- SPI
#define CPR_SPIx_MCLK_CTL(a) ((volatile unsigned *)(CPR_BASE + 0x050 + (a*0x04)))
#define SSIx_CTRL0(a) ((volatile unsigned *)(SPI0_BASE + 0x00 + (a * 0x1000)))
#define SSIx_EN(a) ((volatile unsigned *)(SPI0_BASE + 0x08 + (a * 0x1000)))
#define SSIx_SE(a) ((volatile unsigned *)(SPI0_BASE + 0x10 + (a * 0x1000)))
#define SSIx_BAUD(a) ((volatile unsigned *)(SPI0_BASE + 0x14 + (a * 0x1000)))
#define SSIx_TXFTL(a) ((volatile unsigned *)(SPI0_BASE + 0x18 + (a * 0x1000)))
#define SSIx_RXFTL(a) ((volatile unsigned *)(SPI0_BASE + 0x1c + (a * 0x1000)))
#define SSIx_TXFL(a) ((volatile unsigned *)(SPI0_BASE + 0x20 + (a * 0x1000)))
#define SSIx_RXFL(a) ((volatile unsigned *)(SPI0_BASE + 0x24 + (a * 0x1000)))
#define SSIx_STS(a) ((volatile unsigned *)(SPI0_BASE + 0x28 + (a * 0x1000)))
#define SSIx_IE(a) ((volatile unsigned *)(SPI0_BASE + 0x2c + (a * 0x1000)))
#define SSIx_IS(a) ((volatile unsigned *)(SPI0_BASE + 0x30 + (a * 0x1000)))
#define SSIx_RIS(a) ((volatile unsigned *)(SPI0_BASE + 0x34 + (a * 0x1000)))
#define SSIx_TXOIC(a) ((volatile unsigned *)(SPI0_BASE + 0x38 + (a * 0x1000)))
#define SSIx_RXOIC(a) ((volatile unsigned *)(SPI0_BASE + 0x3c + (a * 0x1000)))
#define SSIx_RXUIC(a) ((volatile unsigned *)(SPI0_BASE + 0x40 + (a * 0x1000)))
#define SSIx_IC(a) ((volatile unsigned *)(SPI0_BASE + 0x48 + (a * 0x1000)))
#define SSIx_DMAS(a) ((volatile unsigned *)(SPI0_BASE + 0x4c + (a * 0x1000)))
#define SSIx_DMATDL(a) ((volatile unsigned *)(SPI0_BASE + 0x50 + (a * 0x1000)))
#define SSIx_DMARDL(a) ((volatile unsigned *)(SPI0_BASE + 0x54 + (a * 0x1000)))
#define SSIx_DATA(a) ((volatile unsigned *)(SPI0_BASE + 0x60 + (a * 0x1000)))
#define SSI2_CTRL0 ((volatile unsigned *)(SPI2_BASE + 0x00))
#define SSI2_EN ((volatile unsigned *)(SPI2_BASE + 0x08))
#define SSI2_SE ((volatile unsigned *)(SPI2_BASE + 0x10))
#define SSI2_BAUD ((volatile unsigned *)(SPI2_BASE + 0x14))
#define SSI2_TXFTL ((volatile unsigned *)(SPI2_BASE + 0x18))
#define SSI2_RXFTL ((volatile unsigned *)(SPI2_BASE + 0x1c))
#define SSI2_TXFL ((volatile unsigned *)(SPI2_BASE + 0x20))
#define SSI2_RXFL ((volatile unsigned *)(SPI2_BASE + 0x24))
#define SSI2_STS ((volatile unsigned *)(SPI2_BASE + 0x28))
#define SSI2_IE ((volatile unsigned *)(SPI2_BASE + 0x2c))
#define SSI2_IS ((volatile unsigned *)(SPI2_BASE + 0x30))
#define SSI2_RIS ((volatile unsigned *)(SPI2_BASE + 0x34))
#define SSI2_TXOIC ((volatile unsigned *)(SPI2_BASE + 0x38))
#define SSI2_RXOIC ((volatile unsigned *)(SPI2_BASE + 0x3c))
#define SSI2_RXUIC ((volatile unsigned *)(SPI2_BASE + 0x40))
#define SSI2_IC ((volatile unsigned *)(SPI2_BASE + 0x48))
#define SSI2_DMAS ((volatile unsigned *)(SPI2_BASE + 0x4c))
#define SSI2_DMATDL ((volatile unsigned *)(SPI2_BASE + 0x50))
#define SSI2_DMARDL ((volatile unsigned *)(SPI2_BASE + 0x54))
#define SSI2_DATA ((volatile unsigned *)(SPI2_BASE + 0x60))
//- RTC
#define RTC_CMR_X(a) ((volatile unsigned *)(RTC_BASE + 0x08 + (a * 0x4)))
////48PIN- PWM
//#define PWMx_EN(a) ((volatile unsigned *)(PWM_BASE + 0x0000 + (a*0x40)))
//#define PWMx_UP(a) ((volatile unsigned *)(PWM_BASE + 0x0004 + (a*0x40)))
//#define PWMx_RST(a) ((volatile unsigned *)(PWM_BASE + 0x0008 + (a*0x40)))
//#define PWMx_P(a) ((volatile unsigned *)(PWM_BASE + 0x000c + (a*0x40)))
//#define PWMx_OCPY(a) ((volatile unsigned *)(PWM_BASE + 0x0010 + (a*0x40)))
//32/16PIN- PWM
#define PWMx_EN(a) ((volatile unsigned *)((PWM_BASE +((a/2)*0x400)) + 0x0000 + ((a%2)*0x40)))
#define PWMx_UP(a) ((volatile unsigned *)((PWM_BASE +((a/2)*0x400)) + 0x0004 + ((a%2)*0x40)))
#define PWMx_RST(a) ((volatile unsigned *)((PWM_BASE +((a/2)*0x400)) + 0x0008 + ((a%2)*0x40)))
#define PWMx_P(a) ((volatile unsigned *)((PWM_BASE +((a/2)*0x400)) + 0x000c + ((a%2)*0x40)))
#define PWMx_OCPY(a) ((volatile unsigned *)((PWM_BASE +((a/2)*0x400)) + 0x0010 + ((a%2)*0x40)))
//pwm0 pwm1 effective
#define PWMCOMPEN(a) ((volatile unsigned *)((PWM_BASE +((a/2)*0x400)) + 0x0014 + ((a%2)*0x40)))
#define PWMCOMPTIME(a) ((volatile unsigned *)((PWM_BASE +((a/2)*0x400)) + 0x0018 + ((a%2)*0x40)))
#define PWM_BREAK_CTL ((volatile unsigned *)((PWM_BASE +0x20)))
#define __write_hw_reg32(reg,val) ((*reg) = (val))
#define __read_hw_reg32(reg, val) ((val) = (*reg))
#define setbit(x,y) ((x) |= (1<<(y)))
#define clrbit(x,y) ((x) &= ~(1<<(y)))
#endif