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Stair56E UART project

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吴琪
2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
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component/boot2/mdk/.vscode/c_cpp_properties.json
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{
"configurations": [
{
"name": "m0_ota_boot2",
"includePath": [
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\bsp",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\ble",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\app",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\bsp\\startup",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\mdk",
"C:\\Keil_v5\\ARM\\ARMCC\\include",
"C:\\Keil_v5\\ARM\\ARMCC\\include\\rw"
],
"defines": [
"BLE_OTA",
"__CC_ARM",
"__arm__",
"__align(x)=",
"__ALIGNOF__(x)=",
"__alignof__(x)=",
"__asm(x)=",
"__forceinline=",
"__restrict=",
"__global_reg(n)=",
"__inline=",
"__int64=long long",
"__INTADDR__(expr)=0",
"__irq=",
"__packed=",
"__pure=",
"__smc(n)=",
"__svc(n)=",
"__svc_indirect(n)=",
"__svc_indirect_r7(n)=",
"__value_in_regs=",
"__weak=",
"__writeonly=",
"__declspec(x)=",
"__attribute__(x)=",
"__nonnull__(x)=",
"__register=",
"__breakpoint(x)=",
"__cdp(x,y,z)=",
"__clrex()=",
"__clz(x)=0U",
"__current_pc()=0U",
"__current_sp()=0U",
"__disable_fiq()=",
"__disable_irq()=",
"__dmb(x)=",
"__dsb(x)=",
"__enable_fiq()=",
"__enable_irq()=",
"__fabs(x)=0.0",
"__fabsf(x)=0.0f",
"__force_loads()=",
"__force_stores()=",
"__isb(x)=",
"__ldrex(x)=0U",
"__ldrexd(x)=0U",
"__ldrt(x)=0U",
"__memory_changed()=",
"__nop()=",
"__pld(...)=",
"__pli(...)=",
"__qadd(x,y)=0",
"__qdbl(x)=0",
"__qsub(x,y)=0",
"__rbit(x)=0U",
"__rev(x)=0U",
"__return_address()=0U",
"__ror(x,y)=0U",
"__schedule_barrier()=",
"__semihost(x,y)=0",
"__sev()=",
"__sqrt(x)=0.0",
"__sqrtf(x)=0.0f",
"__ssat(x,y)=0",
"__strex(x,y)=0U",
"__strexd(x,y)=0",
"__strt(x,y)=",
"__swp(x,y)=0U",
"__usat(x,y)=0U",
"__wfe()=",
"__wfi()=",
"__yield()=",
"__vfp_status(x,y)=0"
],
"intelliSenseMode": "${default}"
},
{
"name": "m4_ota_boot2",
"includePath": [
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\bsp",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\ble",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\app",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\bsp\\startup",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\mdk",
"C:\\Keil_v5\\ARM\\ARMCC\\include",
"C:\\Keil_v5\\ARM\\ARMCC\\include\\rw"
],
"defines": [
"QUAD_ENABLE",
"BLE_OTA",
"__CC_ARM",
"__arm__",
"__align(x)=",
"__ALIGNOF__(x)=",
"__alignof__(x)=",
"__asm(x)=",
"__forceinline=",
"__restrict=",
"__global_reg(n)=",
"__inline=",
"__int64=long long",
"__INTADDR__(expr)=0",
"__irq=",
"__packed=",
"__pure=",
"__smc(n)=",
"__svc(n)=",
"__svc_indirect(n)=",
"__svc_indirect_r7(n)=",
"__value_in_regs=",
"__weak=",
"__writeonly=",
"__declspec(x)=",
"__attribute__(x)=",
"__nonnull__(x)=",
"__register=",
"__breakpoint(x)=",
"__cdp(x,y,z)=",
"__clrex()=",
"__clz(x)=0U",
"__current_pc()=0U",
"__current_sp()=0U",
"__disable_fiq()=",
"__disable_irq()=",
"__dmb(x)=",
"__dsb(x)=",
"__enable_fiq()=",
"__enable_irq()=",
"__fabs(x)=0.0",
"__fabsf(x)=0.0f",
"__force_loads()=",
"__force_stores()=",
"__isb(x)=",
"__ldrex(x)=0U",
"__ldrexd(x)=0U",
"__ldrt(x)=0U",
"__memory_changed()=",
"__nop()=",
"__pld(...)=",
"__pli(...)=",
"__qadd(x,y)=0",
"__qdbl(x)=0",
"__qsub(x,y)=0",
"__rbit(x)=0U",
"__rev(x)=0U",
"__return_address()=0U",
"__ror(x,y)=0U",
"__schedule_barrier()=",
"__semihost(x,y)=0",
"__sev()=",
"__sqrt(x)=0.0",
"__sqrtf(x)=0.0f",
"__ssat(x,y)=0",
"__strex(x,y)=0U",
"__strexd(x,y)=0",
"__strt(x,y)=",
"__swp(x,y)=0U",
"__usat(x,y)=0U",
"__wfe()=",
"__wfi()=",
"__yield()=",
"__vfp_status(x,y)=0"
],
"intelliSenseMode": "${default}"
},
{
"name": "xip_dual&quad",
"includePath": [
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\bsp",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\ble",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\app",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\bsp\\startup",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\mdk",
"C:\\Keil_v5\\ARM\\ARMCC\\include",
"C:\\Keil_v5\\ARM\\ARMCC\\include\\rw"
],
"defines": [
"WITHOUT_OTA",
"XIP_JUMP",
"__CC_ARM",
"__arm__",
"__align(x)=",
"__ALIGNOF__(x)=",
"__alignof__(x)=",
"__asm(x)=",
"__forceinline=",
"__restrict=",
"__global_reg(n)=",
"__inline=",
"__int64=long long",
"__INTADDR__(expr)=0",
"__irq=",
"__packed=",
"__pure=",
"__smc(n)=",
"__svc(n)=",
"__svc_indirect(n)=",
"__svc_indirect_r7(n)=",
"__value_in_regs=",
"__weak=",
"__writeonly=",
"__declspec(x)=",
"__attribute__(x)=",
"__nonnull__(x)=",
"__register=",
"__breakpoint(x)=",
"__cdp(x,y,z)=",
"__clrex()=",
"__clz(x)=0U",
"__current_pc()=0U",
"__current_sp()=0U",
"__disable_fiq()=",
"__disable_irq()=",
"__dmb(x)=",
"__dsb(x)=",
"__enable_fiq()=",
"__enable_irq()=",
"__fabs(x)=0.0",
"__fabsf(x)=0.0f",
"__force_loads()=",
"__force_stores()=",
"__isb(x)=",
"__ldrex(x)=0U",
"__ldrexd(x)=0U",
"__ldrt(x)=0U",
"__memory_changed()=",
"__nop()=",
"__pld(...)=",
"__pli(...)=",
"__qadd(x,y)=0",
"__qdbl(x)=0",
"__qsub(x,y)=0",
"__rbit(x)=0U",
"__rev(x)=0U",
"__return_address()=0U",
"__ror(x,y)=0U",
"__schedule_barrier()=",
"__semihost(x,y)=0",
"__sev()=",
"__sqrt(x)=0.0",
"__sqrtf(x)=0.0f",
"__ssat(x,y)=0",
"__strex(x,y)=0U",
"__strexd(x,y)=0",
"__strt(x,y)=",
"__swp(x,y)=0U",
"__usat(x,y)=0U",
"__wfe()=",
"__wfi()=",
"__yield()=",
"__vfp_status(x,y)=0"
],
"intelliSenseMode": "${default}"
},
{
"name": "m0_24g_ota_boot",
"includePath": [
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\bsp",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\ble",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\app",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\bsp\\startup",
"d:\\production\\新建文件夹\\新建文件夹 (6)\\boot2\\mdk",
"C:\\Keil_v5\\ARM\\ARMCC\\include",
"C:\\Keil_v5\\ARM\\ARMCC\\include\\rw"
],
"defines": [
"OTA_24G",
"__CC_ARM",
"__arm__",
"__align(x)=",
"__ALIGNOF__(x)=",
"__alignof__(x)=",
"__asm(x)=",
"__forceinline=",
"__restrict=",
"__global_reg(n)=",
"__inline=",
"__int64=long long",
"__INTADDR__(expr)=0",
"__irq=",
"__packed=",
"__pure=",
"__smc(n)=",
"__svc(n)=",
"__svc_indirect(n)=",
"__svc_indirect_r7(n)=",
"__value_in_regs=",
"__weak=",
"__writeonly=",
"__declspec(x)=",
"__attribute__(x)=",
"__nonnull__(x)=",
"__register=",
"__breakpoint(x)=",
"__cdp(x,y,z)=",
"__clrex()=",
"__clz(x)=0U",
"__current_pc()=0U",
"__current_sp()=0U",
"__disable_fiq()=",
"__disable_irq()=",
"__dmb(x)=",
"__dsb(x)=",
"__enable_fiq()=",
"__enable_irq()=",
"__fabs(x)=0.0",
"__fabsf(x)=0.0f",
"__force_loads()=",
"__force_stores()=",
"__isb(x)=",
"__ldrex(x)=0U",
"__ldrexd(x)=0U",
"__ldrt(x)=0U",
"__memory_changed()=",
"__nop()=",
"__pld(...)=",
"__pli(...)=",
"__qadd(x,y)=0",
"__qdbl(x)=0",
"__qsub(x,y)=0",
"__rbit(x)=0U",
"__rev(x)=0U",
"__return_address()=0U",
"__ror(x,y)=0U",
"__schedule_barrier()=",
"__semihost(x,y)=0",
"__sev()=",
"__sqrt(x)=0.0",
"__sqrtf(x)=0.0f",
"__ssat(x,y)=0",
"__strex(x,y)=0U",
"__strexd(x,y)=0",
"__strt(x,y)=",
"__swp(x,y)=0U",
"__usat(x,y)=0U",
"__wfe()=",
"__wfi()=",
"__yield()=",
"__vfp_status(x,y)=0"
],
"intelliSenseMode": "${default}"
}
],
"version": 4
}
component/boot2/mdk/.vscode/keil-assistant.log
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[info] Log at : 2023/5/16|14:59:06|GMT+0800
[info] Log at : 2023/5/16|14:59:11|GMT+0800
[info] Log at : 2023/5/16|15:02:06|GMT+0800
[info] Log at : 2023/5/23|15:37:08|GMT+0800
[info] Log at : 2023/5/24|10:16:48|GMT+0800
component/boot2/mdk/.vscode/settings.json
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{
"files.associations": {
"limits": "c",
"memory": "c",
"includes.h": "c",
"bsp_spi_master.h": "c"
}
}
component/boot2/mdk/.vscode/uv4.log
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*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'm0_ota_boot2'
After Build - User command #1: fromelf --bin --output=s.bin .\Objects\Xinc_ble_sdk.axf
After Build - User command #2: Xincboot_tool s.bin boot2
Xinc v3.1 build Mar 19 2019 23:08:55
USAGE: [Xincboot_tool] <input FILE> <output FILE>
Input: s.bin boot2
Input file "s.bin" raw size = 0x13a0 byte
-):
".\Objects\Xinc_ble_sdk.axf" - 0 Error(s), 0 Warning(s).
Build Time Elapsed: 00:00:01
component/boot2/mdk/.vscode/uv4.log.lock
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2023/5/16 15:56:26
component/boot2/mdk/BootSecond.c
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/*
* INCLUDE FILES
****************************************************************************************
*/
#include "Includes.h"
//#include "xinc_reg.h"
// #include "spi_flash.h"
#include "xc_drv_spi.h"
#define FLASH_PAGE_WORDS 64
#define FLASH_PAGE_SIZE 256
#define FLASH_BLOCK_SIZE 65536
#define FLASH_SECTOR_SIZE 4096
#define PAGES_SIZE 1024
volatile uint32_t param_backup_addr = ((8*1024)-256);
sboot_message *pms;
uint8_t burn_ser=0;
//sboot_message parambuffa1;
//sboot_message parambuffa2;
static uint8_t ALIGN(4) parambuffa[FLASH_PAGE_SIZE];
static uint8_t ALIGN(4) parambuffb[FLASH_PAGE_SIZE];
static uint8_t ALIGN(4) rwbuff[FLASH_PAGE_SIZE];
uint8_t spi_idx = SPI0_IDX;
typedef void (*iapfun)(void); // 定义一个函数类型的参数.
static iapfun jump2app;
//__RAM_CODE __asm void MSR_MSP(uint32_t addr) // 设置栈顶地址 addr:栈顶地址
//{
// MSR MSP, r0 // set Main Stack value
// BX r14
//}
void flash_init()
{
SPI_InitCfg_t spi_cfg = {0};
spi_cfg.Mode = SPI_MODE_MASTER;
spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
spi_cfg.BaudRatePrescaler = SSI_BAUD_DIV_2;
spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
spi_cfg.CLKPhase = SSI_CTRL0_SCPHA_LEAD;
spi_cfg.FirstBit = SPI_FirstBit_MSB;
xc_spi_init(spi_idx, &spi_cfg);
xc_spi_flash_wake_up(spi_idx);
}
static void param_overwrite(uint8_t to, uint8_t *buff,uint8_t flag)
{
uint8_t data[256];
if(flag)
{
for(int i=0; i<256; i+=2){
data[i] = buff[i+1];
data[i+1] = buff[i];
}
}
else
{
for(int i=0; i<256; i++){
data[i] = buff[i];
}
}
uint32_t addr = (to == TO_B) ? param_backup_addr : PARAM_ADDR;
// SPI_WRITE_ENABLE();
FLASH_PAGE_ERASE(spi_idx, addr); // spi_flash_page_erase(addr);
FLASH_WAIT_READY;
/*write a page*/
// SPI_WRITE_ENABLE();
FLASH_WRITE_PAGE(spi_idx, addr, data);
FLASH_WAIT_READY;
}
/**
* Copyright (c) 2022 - 2025, XinChip
* All rights reserved.
* Author : D
*/
__RAM_CODE void bootapp(param_unit *bparam)
{
uart_printf("boot app=%x\n", bparam->aloadaddr);
if (bparam->aloadaddr < FLASH_VIR_AADDR)
{
// 4096 0 16 pagecnt=16
uint32_t words;
uint32_t remain = bparam->alen % FLASH_PAGE_SIZE;
uint32_t pagecnt = bparam->alen / FLASH_PAGE_SIZE;
pagecnt = (remain == 0) ? pagecnt : (pagecnt + 1);
for (uint32_t pageser = 0, buffser = 0, pdesser = 0; pageser < pagecnt; pageser++)
{
FLASH_READ_PAGE(spi_idx, bparam->aaddr + pageser * FLASH_PAGE_SIZE, rwbuff);
// i= (pageser==0) ? (CODES_OFFSET/4):0;
words = ((pagecnt - 1) == pageser) ? (((remain % 4) == 0) ? (remain / 4) : ((remain / 4) + 1)) : FLASH_PAGE_WORDS;
for (buffser = 0; buffser < words; buffser++, pdesser++)
{
*(((uint32_t *)bparam->aloadaddr) + pdesser) = *(((uint32_t *)rwbuff) + buffser);
}
}
}
else
{
#ifdef QUAD_ENABLE
init_xip(QUAD_MODE);
#else
init_xip(DUAL_MODE);
#endif
}
//bparam->aloadaddr = 0x11013000;// 编译 simple_peripheral_ota 工程时， 需要注释掉该行！
jump2app = (iapfun) * (uint32_t *)(bparam->aloadaddr + 4); // 用户代码区第二个字为程序开始地址(复位地址)
MSR_MSP(*(uint32_t *)(bparam->aloadaddr)); // 设置栈顶地址 addr:栈顶地址 （用户代码区第一个字为程序的栈顶地址）
jump2app();
while (1)
;
}
/**
* Copyright (c) 2022 - 2025, XinChip
* All rights reserved.
* Author : D
*/
static void boot_backup(param_unit *bParam)
{
/*reserved*/
}
/**
* Copyright (c) 2022 - 2025, XinChip
* All rights reserved.
* Author : D
*/
static uint8_t eraseapp(param_unit *eparam)
{
uint32_t addrB = eparam->baddr;
#if SINGELE_OTA==0
uint32_t addr = eparam->aaddr;
#endif
uint32_t era_sectorcnt = (eparam->blen) / FLASH_SECTOR_SIZE;
era_sectorcnt = (((eparam->blen) % FLASH_SECTOR_SIZE) == 0) ? era_sectorcnt : (era_sectorcnt + 1);
uint32_t crc = CRC32_INITIAL;
uint32_t remain = 0;
uint32_t pagecnt = (eparam->blen) / FLASH_PAGE_SIZE;
pagecnt = (((eparam->blen) % FLASH_PAGE_SIZE) == 0) ? pagecnt : (pagecnt + 1);
remain = ((eparam->blen) % FLASH_PAGE_SIZE);
if (remain == 0)
remain = FLASH_PAGE_SIZE;
for (uint32_t i = 0; i < pagecnt; i++)
{
FLASH_READ_PAGE(spi_idx, addrB + i * FLASH_PAGE_SIZE, rwbuff);
// for(int i=0;i<256;i++)
// {
// uart_printf("%x ",rwbuff[i]);
// }
crc = ((pagecnt - 1) == i) ? (get_crc32(crc, rwbuff, FLASH_PAGE_SIZE)) : (get_crc32(crc, rwbuff, FLASH_PAGE_SIZE));
// uart_printf("\ncrc:%x\n",crc);
}
// uart_printf("crc:%x eparam->bcheck:%x\n",crc,eparam->bcheck);
if (crc != (eparam->bcheck))
{
static uint8_t ErrCrcCNT = 0;
ErrCrcCNT++;
return 0;
}
for (uint32_t i = 0; i < era_sectorcnt; i++)
{
// SPI_WRITE_ENABLE();
#if SINGELE_OTA==0
FLASH_SECTOR_ERASE(spi_idx, addr + i * FLASH_SECTOR_SIZE); // spi_flash_page_erase(addr);
FLASH_WAIT_READY;
#endif
}
eparam->status = OVERWRITEASTAT;
return 1;
}
/**
* Copyright (c) 2022 - 2025, XinChip
* All rights reserved.
* Author : D
*/
static void erase_backup(param_unit *eparam)
{
#if SINGELE_OTA==0
uint32_t addr = eparam->baddr;
#endif
uint16_t era_sectorcnt = (eparam->blen) / FLASH_SECTOR_SIZE;
era_sectorcnt = (((eparam->blen) % FLASH_SECTOR_SIZE) == 0) ? era_sectorcnt : (era_sectorcnt + 1);
for (uint32_t i = 0; i < era_sectorcnt; i++)
{
// SPI_WRITE_ENABLE();
#if SINGELE_OTA==0
FLASH_SECTOR_ERASE(spi_idx, addr + i * FLASH_SECTOR_SIZE); // spi_flash_page_erase(addr);
FLASH_WAIT_READY;
#endif
}
eparam->status = ACTIVEASTAT;
pms->paramcrc32 = get_crc32(CRC32_INITIAL, (uint8_t *)pms, PARAM_LENGTH);
param_overwrite(TO_A, (uint8_t *)pms,0);
param_overwrite(TO_B, (uint8_t *)pms,0);
}
/**
* Copyright (c) 2022 - 2025, XinChip
* All rights reserved.
* Author : D
*/
// void reverse_bytes(uint8_t *data, size_t length) {
// if (length % 2 != 0) {
// // printf("Error: Length of data must be even.\n");
// return;
// }
// for (size_t i = 0; i < length; i += 2) {
// // 交换每两个字节
// uint8_t temp = data[i];
// data[i] = data[i + 1];
// data[i + 1] = temp;
// }
//}
static void overwriteapp(param_unit *oparam)
{
#if SINGELE_OTA==0
uint32_t addrA = oparam->aaddr;
uint32_t addrB = oparam->baddr;
uint32_t remain = 0;
uint32_t pagecnt = (oparam->blen) / FLASH_PAGE_SIZE;
pagecnt = (((oparam->blen) % FLASH_PAGE_SIZE) == 0) ? pagecnt : (pagecnt + 1);
remain = ((oparam->blen) % FLASH_PAGE_SIZE);
if (remain == 0)
remain = FLASH_PAGE_SIZE;
for (uint32_t i = 0; i < pagecnt; i++)
{
FLASH_READ_PAGE(spi_idx, addrB + i * FLASH_PAGE_SIZE, rwbuff);
FLASH_WAIT_READY;
// reverse_bytes(rwbuff,256);
FLASH_WRITE_PAGE(spi_idx, addrA + i * FLASH_PAGE_SIZE, rwbuff);
FLASH_WAIT_READY;
}
#endif
oparam->alen = oparam->blen;
oparam->acheck = oparam->bcheck;
oparam->status = ERASEBSTAT;
pms->paramcrc32 = get_crc32(CRC32_INITIAL, (uint8_t *)pms, PARAM_LENGTH);
param_overwrite(TO_A, (uint8_t *)pms,0);
}
/**
* Copyright (c) 2022 - 2025, XinChip
* All rights reserved.
* Author : D
*/
void overwrite_backup(param_unit *oparam)
{
/*reserved*/
}
/**
* Copyright (c) 2022 - 2025, XinChip
* All rights reserved.
* Author : D
*/
void param_analy(param_unit *sparam)
{
uart_printf("param_analy\n");
if(sparam->status==ERASEASTAT)
{
uart_printf("eraseapp\n");
if(!eraseapp(sparam))
{
uart_printf("crc err\n");
param_overwrite(TO_B, parambuffa,1);
bootapp((param_unit *)parambuffa);
}
uart_printf("overwriteapp\n");
overwriteapp(sparam);
erase_backup(sparam);
bootapp(sparam);
}
else if(sparam->status==ACTIVEBSTAT)
{
boot_backup(sparam);
}
else
{
uart_printf("status error:%d",sparam->status);
}
}
void param_backup_addr_set()
{
// uint8_t flash_sizeid = (uint8_t)spi_flash_read_identific();
uint8_t flash_sizeid = FLASH_SIZE_2M;
switch (flash_sizeid)
{
case FLASH_SIZE_4M: // 4M size
param_backup_addr = FLASH_4M_BACKUPADDR; // 4096 * 128 - 3 * 4096;
break;
case FLASH_SIZE_2M: // 2M
param_backup_addr = FLASH_2M_BACKUPADDR; // 4096 * 64 - 3 * 4096;
break;
case FLASH_SIZE_1M: // 1M
param_backup_addr = FLASH_1M_BACKUPADDR; // 4096 * 32 - 3 * 4096;
break;
default: // 4M
param_backup_addr = FLASH_4M_BACKUPADDR; // 4096 * 128 - 3 * 4096;
break;
}
}
int boot_get_status()
{
uint32_t crc32a, crc32b;
sboot_message *ptr_area = (sboot_message *)(&parambuffa[0]);
sboot_message *ptr_brea = (sboot_message *)(&parambuffb[0]);
FLASH_READ_PAGE(spi_idx, PARAM_ADDR, parambuffa);
FLASH_READ_PAGE(spi_idx, param_backup_addr, parambuffb);
crc32a = get_crc32(CRC32_INITIAL, parambuffa, PARAM_LENGTH);
crc32b = get_crc32(CRC32_INITIAL, parambuffb, PARAM_LENGTH);
if(ptr_area->paramcrc32==crc32a)
{
if(crc32a!=crc32b)
{
param_overwrite(TO_B, parambuffa,1);
}
pms = ptr_area;
for(int param_no=0;param_no<PARAM_CNT;param_no++)
{
if(ptr_area->paramunit[param_no].status==ERASEASTAT)//OTA begin,select whitch app need updata
{
burn_ser=param_no;
return STATUS_APPUPDATA;
}
else if(ptr_area->paramunit[param_no].status==ACTIVEASTAT)//OTA begin
{
burn_ser=param_no;
return STATUS_APPBOOT;
}
}
}
else
{
param_overwrite(TO_A, parambuffb,1);
pms = ptr_brea;
if(ptr_brea->paramcrc32==crc32b)
{
return STATUS_APPBOOT;
}
else
{
return STATUS_APPERROR;
}
}
return STATUS_APPERROR;
}
void boot_run_sec()
{
uint8_t status = boot_get_status();
switch (status)
{
case STATUS_APPBOOT:
bootapp(&(pms->paramunit[burn_ser]));
break;
case STATUS_APPUPDATA:
while (1)
{
param_analy(&(pms->paramunit[burn_ser]));
}
case STATUS_APPERROR:
uart_printf(" error_status\r\n");
boot_run_sec();
break;
}
}
component/boot2/mdk/BootSecond.h
+127
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@@ -0,0 +1,127 @@
#ifndef _BOOTSECOND_H_
#define _BOOTSECOND_H_
#define __RAM_DMA __attribute__((section("ram_code")))
typedef enum
{
INVALIDSTAT = 0,
ACTIVEASTAT = 1,
ERASEASTAT = 2,
OVERWRITEASTAT = 3,
ACTIVEBSTAT = 4,
ERASEBSTAT = 5,
OVERWRITEBSTAT = 6,
} STATUS_T;
typedef enum
{
ERRNONE = 0,
ERRPARAMDAMAGE = 1,
ERROVERWRITE = 2,
ERRCHECK = 3,
} ERROR_T;
typedef enum
{
STATUS_APPBOOT,
STATUS_APPUPDATA,
STATUS_APPERROR,
} PARMSTATUS;
typedef enum
{
APPBOOTA = 0,
APPUPDATA = 2,
APPBOOTB = 3,
APPBOOTERR = 4,
} APPSTATUS;
typedef enum
{
FLASH_SIZE_1M = 0x11,
FLASH_SIZE_2M = 0x12,
FLASH_SIZE_4M = 0x13,
} FLASH_SIZEID;
typedef enum
{
FLASH_1M_BACKUPADDR = 29 * 4096,
FLASH_2M_BACKUPADDR = 61 * 4096,
FLASH_4M_BACKUPADDR = 125 * 4096,
} FLASH_SIZE;
#define DEBUG_PRINT
#define PIN_AB_DAMAGE 18
// #define PIN_DETECT
#define PIN_AB_ACTIVE 0
#define CRC32_INITIAL 0
#define CODES_OFFSET 0x20
#define PARAM_CNT 5
#define PARAM_LENGTH 240
#define TO_B 0
#define TO_A 1
#define CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET (16UL)
#define CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Pos (0x0UL) // /*!< Position of WDT_PCLK_EN field. */
#define CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Msk (0x1UL << CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Pos)
#define CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_DISABLE (0x0UL << CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Pos) /*!< 0����ʹ��ʱ�� */
#define CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_ENABLE (0x1UL << CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Pos) /*!< 1��ʹ��ʱ��*/
#define CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Pos (0x2UL) // /*!< Position of WDT_RSTN field. */
#define CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Msk (0x1UL << CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Pos)
#define CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_DISABLE (RSTN_INVALID << CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Pos) /*!< 1������λ */
#define CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_ENABLE (RSTN_VALID << CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Pos) /*!< 0����λ*/
#define CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Pos (0x0UL) // /*!< Position of WDT_SYS_RSTN_MASK field. */
#define CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Msk (0x1UL << CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Pos)
#define CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_DISABLE (0x0UL << CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Pos) /*!< 0�������� */
#define CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_ENABLE (0x1UL << CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Pos) /*!< 1������*/
#define CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Pos (0x1UL) // /*!< Position of WDT_M0_RSTN_MASK field. */
#define CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Msk (0x1UL << CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Pos)
#define CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_DISABLE (0x0UL << CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Pos) /*!< 0�������� */
#define CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_ENABLE (0x1UL << CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Pos) /*!< 1������*/
#define RSTN_VALID (0UL)
#define RSTN_INVALID (1UL)
#define PARAM_ADDR ((8*1024)-512)
#define FLASH_VIR_AADDR 0x11000000
#define ALIGN(num) __attribute__((aligned(num)))
//#define FLASH_READ_PAGE spi_flash_Read_Page
//#define FLASH_SECTOR_ERASE spi_flash_sector_erase
//#define SPI_WRITE_ENABLE spi_flash_write_enable
//#define FLASH_WRITE_PAGE xc_spi_flash_write_page
//#define FLASH_WAIT_READY while (spi_flash_wait_till_ready())
#define FLASH_READ_PAGE xc_spi_flash_read_page
#define FLASH_SECTOR_ERASE xc_spi_flash_erase_sector
#define FLASH_PAGE_ERASE xc_spi_flash_erase_page
#define SPI_WRITE_ENABLE
#define FLASH_WRITE_PAGE xc_spi_flash_write_page
#define FLASH_WAIT_READY
typedef struct
{
uint32_t status; /**/
uint32_t softver; /**/
uint32_t acheck; /*crc32*/
uint32_t aaddr; /*sector align*/
uint32_t alen; /*page align*/
uint32_t bcheck; /**/
uint32_t baddr; /**/
uint32_t blen; /**/
uint32_t aloadaddr;
uint32_t bloadaddr;
uint32_t RESERVED0[2];
} param_unit;
typedef struct
{
param_unit paramunit[PARAM_CNT];
uint32_t paramcrc32;
uint32_t RESERVED1[3];
} sboot_message;
void boot_run_sec(void);
extern volatile uint32_t param_backup_addr;
void boot_run(void);
void param_analy(param_unit *sParam);
__RAM_CODE __asm void MSR_MSP(uint32_t addr);
void flash_init(void);
void overwrite_backup(param_unit *oparam);
int uart_printf(const char *fmt,...);
#endif
component/boot2/mdk/Initialization.ini
+12
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@@ -0,0 +1,12 @@
FUNC void Initialization(void)
{
SP = _RDWORD(0x10000000);
PC = _RDWORD(0x10000004);
}
LOAD %L INCREMENTAL
Initialization();
component/boot2/mdk/Xincboot_tool.exe
BIN
View File
Binary file not shown.
component/boot2/mdk/boot2
BIN
View File
Binary file not shown.
component/boot2/mdk/boot2.uvoptx
+364
View File
@@ -0,0 +1,364 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>m0_ota_boot2</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>startup</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\hal\startup_xinc.s</PathWithFileName>
<FilenameWithoutPath>startup_xinc.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\hal\system_xinc.c</PathWithFileName>
<FilenameWithoutPath>system_xinc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>application</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\BootSecond.c</PathWithFileName>
<FilenameWithoutPath>BootSecond.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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</File>
<File>
<GroupNumber>2</GroupNumber>
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<bDave2>0</bDave2>
<PathWithFileName>..\app\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
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</File>
</Group>
<Group>
<GroupName>bsp</GroupName>
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<bDave2>0</bDave2>
<PathWithFileName>..\bsp\bsp_xip.c</PathWithFileName>
<FilenameWithoutPath>bsp_xip.c</FilenameWithoutPath>
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</File>
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<bDave2>0</bDave2>
<PathWithFileName>..\bsp\bsp_crc.c</PathWithFileName>
<FilenameWithoutPath>bsp_crc.c</FilenameWithoutPath>
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<FileNumber>7</FileNumber>
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<FilenameWithoutPath>xc_drv_gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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</ProjectOpt>
component/boot2/mdk/boot2.uvprojx
+493
View File
@@ -0,0 +1,493 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>m0_ota_boot2</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM0</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.8.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>Xinc_ble_sdk</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>xinchip_tool s.bin download.bin</UserProg1Name>
<UserProg2Name>Xincboot_tool s.bin download.bin</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>ram_program.bat</UserProg1Name>
<UserProg2Name>fromelf --text -a -c --output=@L_asm !L</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>1</RunUserProg2>
<UserProg1Name>fromelf --bin --output=s.bin !L</UserProg1Name>
<UserProg2Name>Xincboot_tool s.bin boot2</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>1</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x11001000</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>1</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>BLE_OTA XC65XX USED_DCDC=1 SINGELE_OTA=0</Define>
<Undefine></Undefine>
<IncludePath>..\ble;..\app;..\mdk;..\..\xc6xx_drivers\Drivers\Startup\xc65xx;..\..\xc6xx_drivers\Drivers\Periph_HAL_Driver;..\..\xc6xx_drivers\Drivers\Startup;..\..\xc6xx_drivers\Drivers\CMSIS\Device;..\..\xc6xx_drivers\Drivers\Periph_HAL_Driver\Bitfields;..\..\xc6xx_drivers\Drivers\Periph_HAL_Driver\Ringbuffer;..\..\xc6xx_drivers\Drivers\xc_driver;..\..\xc6xx_drivers\Drivers\CMSIS\Device\xc_m0_register;..\..\xc6xx_drivers\Drivers\CMSIS;..\bsp;..\..\xc6xx_drivers\Drivers\CMSIS\Device</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\linker\cpu_boot2.scat</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>startup</GroupName>
<Files>
<File>
<FileName>startup_xinc.s</FileName>
<FileType>2</FileType>
<FilePath>..\hal\startup_xinc.s</FilePath>
</File>
<File>
<FileName>system_xinc.c</FileName>
<FileType>1</FileType>
<FilePath>..\hal\system_xinc.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>application</GroupName>
<Files>
<File>
<FileName>BootSecond.c</FileName>
<FileType>1</FileType>
<FilePath>.\BootSecond.c</FilePath>
</File>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>..\app\main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>bsp</GroupName>
<Files>
<File>
<FileName>bsp_xip.c</FileName>
<FileType>1</FileType>
<FilePath>..\bsp\bsp_xip.c</FilePath>
</File>
<File>
<FileName>bsp_crc.c</FileName>
<FileType>1</FileType>
<FilePath>..\bsp\bsp_crc.c</FilePath>
</File>
<File>
<FileName>xc_drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\xc6xx_drivers\Drivers\xc_driver\xc_drv_gpio.c</FilePath>
</File>
<File>
<FileName>xc_drv_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\xc6xx_drivers\Drivers\xc_driver\xc_drv_spi.c</FilePath>
</File>
<File>
<FileName>xc_drv_wdt.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\xc6xx_drivers\Drivers\xc_driver\xc_drv_wdt.c</FilePath>
</File>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\xc6xx_drivers\Drivers\xc_driver\ringbuffer.c</FilePath>
</File>
<File>
<FileName>xc_drv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\xc6xx_drivers\Drivers\xc_driver\xc_drv_clock.c</FilePath>
</File>
<File>
<FileName>xc_drv_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\xc6xx_drivers\Drivers\xc_driver\xc_drv_pwr.c</FilePath>
</File>
<File>
<FileName>xc_drv_systick.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\xc6xx_drivers\Drivers\xc_driver\xc_drv_systick.c</FilePath>
</File>
<File>
<FileName>xc_drv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\xc6xx_drivers\Drivers\xc_driver\xc_drv_uart.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>
component/boot2/mdk/linker/cpu_boot2.scat
+60
View File
@@ -0,0 +1,60 @@
;RAM 128KByte
LOAD 0x10000000
{
EXE 0x10000000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
ScatterAssert((ImageLength(EXE)) < (8*1024 -512) )
RW +0x000
{
*(ram_code)
* (+RW,+ZI)
}
}
;RAM 96KByte
;LOAD 0x10000000
;{
; EXE 0x10000000
; {
; startup_xinc.o (RESET, +FIRST)
; * (+RO)
;
; }
; RW +0x00000
; {
; *(ram_code)
; * (+RW,+ZI)
; }
;}
;LOAD_ROM 0x11001000 ;NOCOMPRESS ;ALIGN 32
;{
;
; USER_ROM 0x11001000 NOCOMPRESS
; {
; startup_xinc.o (RESET, +FIRST)
; *(+RO)
; }
;
; USER_RAM 0x10000100 NOCOMPRESS
; {
; *(ram_code)
; *(+RW,+ZI)
; }
component/boot2/mdk/linker/cpu_boot2m4.scat
+59
View File
@@ -0,0 +1,59 @@
;RAM 128KByte
LOAD 0x10000000
{
EXE 0x10000000
{
startup_xinc.o (RESET, +FIRST)
* (+RO)
}
RW +0x00000
{
*(ram_code)
* (+RW,+ZI)
}
}
;RAM 96KByte
;LOAD 0x10000000
;{
; EXE 0x10000000
; {
; startup_xinc.o (RESET, +FIRST)
; * (+RO)
;
; }
; RW +0x00000
; {
; *(ram_code)
; * (+RW,+ZI)
; }
;}
;LOAD_ROM 0x11001000 ;NOCOMPRESS ;ALIGN 32
;{
;
; USER_ROM 0x11001000 NOCOMPRESS
; {
; startup_xinc.o (RESET, +FIRST)
; *(+RO)
; }
;
; USER_RAM 0x10000100 NOCOMPRESS
; {
; *(ram_code)
; *(+RW,+ZI)
; }
component/boot2/mdk/ram_program.bat
+1
View File
@@ -0,0 +1 @@
Xincboot_tool.exe s.bin download.bin 0 0 0 0 1
component/boot2/mdk/s.bin
BIN
View File
Binary file not shown.
component/boot2/mdk/test_24g.c
+310
View File
@@ -0,0 +1,310 @@
/*----------------------------------------------------------------------------------------------------
INCLUDE HEADE FILES
----------------------------------------------------------------------------------------------------*/
#include "Includes.h"
#include "bsp_spi_master.h"
#include "BootSecond.h"
#include "bsp_2_4G.h"
volatile uint8_t rf_intrrupt_flag = 0;
volatile INFO_24G info_24g = {
.DataStatus = STATUS_OK,
.CheckStatus = STATUS_BUSY,
.WriteAddr = FLASH_BIN_ADDR_OFFSET,
.cPacketNo = 1,
.cFrameNo = 1,
.RevComplete = rFALSE,
};
uint8_t __attribute__((aligned(4))) data_buffer[1200];
uint8_t __attribute__((aligned(4))) xc_buffer[32];
uint8_t __attribute__((aligned(4))) ack_pay_buf[32] = {0x01, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00};
// #define printf(...) (0)
extern void makeCRC32table(unsigned int table[]);
extern unsigned int crc32table[];
extern unsigned int get_crc32(unsigned int hash, unsigned char *data, unsigned int length);
/**
* Copyright (c) 2022 - 2025, XinChip
*
* All rights reserved.
*
* Author :
*
*/
void dump_log(void)
{
printf("CFG_TOP: 0x%08x\r\n", *CFG_TOP);
printf("EN_AA: 0x%08x\r\n", *EN_AA);
printf("EN_RXADDR: 0x%08x\r\n", *EN_RXADDR);
printf("SETUP_AW: 0x%08x\r\n", *SETUP_AW);
printf("SETUP_RETR: 0x%08x\r\n", *SETUP_RETR);
printf("RF_CH: 0x%08x\r\n", *RF_CH);
printf("SETUP_RF: 0x%08x\r\n", *SETUP_RF);
printf("STATUS: 0x%08x\r\n", *STATUS);
printf("OBSERVE_TX: 0x%08x\r\n", *OBSERVE_TX);
printf("RSSI: 0x%08x\r\n", *RSSI);
printf("RX_ADDR_P0: 0x%02x%08x\r\n", 0xFF & (*RX_ADDR_P0_H), *RX_ADDR_P0_L);
printf("RX_ADDR_P1: 0x%02x%08x\r\n", 0xFF & (*RX_ADDR_P1_H), *RX_ADDR_P1_L);
printf("RX_ADDR_P2TOP5:0x%08x\r\n", *RX_ADDR_P2TOP5);
printf("BER_RESULT: 0x%08x%08x\r\n", *BER_RESULT_H, *BER_RESULT_L);
printf("AGC_SETTING: 0x%08x\r\n", *AGC_SETTING);
printf("PGA_SETTING: 0x%02x%08x\r\n", ((*PGA_SETTING_H) & 0xFF00) >> 8, *PGA_SETTING_L);
printf("TX_ADDR: 0x%02x%08x\r\n", ((*TX_ADDR_H) & 0xFF), *TX_ADDR_L);
printf("RX_PW_PX: 0x%04x%08x\r\n", 0xFFFF & (*RX_PW_PX_H), *RX_PW_PX_L);
printf("STATUS_FIFO: 0x%08x\r\n", *STATUS_FIFO);
printf("RSSIREC: 0x%08x\r\n", *RSSIREC);
printf("TXPROC_CFG: 0x%08x\r\n", *TXPROC_CFG);
printf("RXPROC_CFG: 0x%02x%08x\r\n", 0xFF & (*RXPROC_CFG_H), *RXPROC_CFG_L);
printf("DYNPD: 0x%08x\r\n", *DYNPD);
printf("FEATURE: 0x%08x\r\n", *FEATURE);
printf("PGA_SETTING_H: 0x%08x\r\n", *PGA_SETTING_H);
printf("TX_ADDR_H: 0x%08x\r\n", *TX_ADDR_H);
}
/**
* Copyright (c) 2022 - 2025, XinChip
*
* All rights reserved.
*
* Author :
*
*/
void my_memcpy(uint8_t *des, uint8_t *src, uint16_t len)
{
for (int i = 0; i < len; i++)
des[i] = src[i];
}
void my_memset(uint8_t *s, uint8_t val, uint16_t len)
{
for (int i = 0; i < len; i++)
s[i] = val;
}
/**
* Copyright (c) 2022 - 2025, XinChip
*
* All rights reserved.
*
* Author :
*
*/
__RAM_CODE void packet_24g(void)
{
static uint8_t xCount = 0;
static uint16_t xPacketNo = 0;
uint8_t packet_len = 0;
// for (uint8_t idx=0; idx<BUFF_24G_ACK_PAY_LENGTH; idx++) ack_pay_buf[idx] = idx;//���������
// packet_len = XC_RxPacket(DIS_ACK_PAY,ack_pay_buf,BUFF_24G_ACK_PAY_LENGTH,xc_buffer);//������������
packet_len = XC_RxPacket(EN_ACK_PAY, ack_pay_buf, BUFF_24G_ACK_PAY_LENGTH, xc_buffer); // ������������
if (packet_len == BUFF_24G_LENGTH)
{
switch (xc_buffer[2])
{
case 1: // match packet
xCount++;
if (xCount >= 3)
{
xCount = 0;
static uint8_t once_flag = 0;
if (once_flag == 0)
{
once_flag = 1;
info_24g.SoftVer = xc_buffer[5] + (xc_buffer[6] << 8);
info_24g.RomVer = xc_buffer[7] + (xc_buffer[8] << 8);
info_24g.Len = xc_buffer[9] + (xc_buffer[10] << 8) +
(xc_buffer[11] << 16) + (xc_buffer[12] << 24);
info_24g.CRC32 = xc_buffer[13] + (xc_buffer[14] << 8) +
(xc_buffer[15] << 16) + (xc_buffer[16] << 24);
info_24g.PacketNum = xc_buffer[17] + (xc_buffer[18] << 8);
info_24g.AddrH = xc_buffer[24];
info_24g.AddrL = xc_buffer[20] + (xc_buffer[21] << 8) +
(xc_buffer[22] << 16) + (xc_buffer[23] << 24);
info_24g.Channel = 2400 + xc_buffer[19];
set_txaddr(info_24g.AddrL, info_24g.AddrH);
set_pipe0_rxaddr(info_24g.AddrL, info_24g.AddrH);
nop();
nop();
nop();
set_channel(info_24g.Channel);
#ifdef DEBUG1
printf("[SoftVer:0x%08X]\n[RomVer:0x%08X]\n[Len:0x%08X]\n[CRC32:0x%08X]\n",
info_24g.SoftVer, info_24g.RomVer, info_24g.Len, info_24g.CRC32);
printf("[PacketNum:0x%08X]\n", info_24g.PacketNum);
printf("[addr_H:0x%08X]\n[addr_L:0x%08X]\n[channel:%d]\n@@mathch ok@@\n",
info_24g.AddrH, info_24g.AddrL, info_24g.Channel);
#endif
}
}
break;
case 3: // bin info packet
// printf("P %02x ",xc_buffer[5]);
// info_24g.cPacketNo == (xc_buffer[5]+(xc_buffer[6]<<8))
xPacketNo = (xc_buffer[5] + (xc_buffer[6] << 8)); // packet No
info_24g.FrameNum = xc_buffer[15] + (xc_buffer[16] << 8);
info_24g.cFrameNo = 1;
// printf("info_24g.FrameNum:%X\n",info_24g.FrameNum);
break;
case 5: // bin packet
if (info_24g.cFrameNo == xc_buffer[0])
{
my_memcpy(data_buffer + PACKET_LENGTH * (info_24g.cFrameNo - 1), xc_buffer + 3, PACKET_LENGTH);
info_24g.cFrameNo++;
}
else
{
break;
}
if (xc_buffer[0] == info_24g.FrameNum)
{
if (info_24g.cPacketNo != xPacketNo)
{
info_24g.DataStatus = STATUS_FAIL;
break;
}
#ifdef DEBUG2
for (int i = 0; i < 1024; i++)
{
printf("%02x ", data_buffer[i]);
if ((i + 1) % 16 == 0)
printf("\n");
}
#endif
#if 1 // exchange byte position
for (int i = 0; i < 512; i++)
{
uint8_t t = data_buffer[2 * i];
data_buffer[2 * i] = data_buffer[2 * i + 1];
data_buffer[2 * i + 1] = t;
}
#endif
// printf("F:%02x no:%x\n",info_24g.WriteAddr,info_24g.cPacketNo);
info_24g.DataStatus = STATUS_BUSY;
// spi_flash_write_sPages(info_24g.WriteAddr, data_buffer);
my_memset(data_buffer, 0xff, PAGES_SIZE);
if (info_24g.PacketNum == info_24g.cPacketNo)
{
info_24g.RevComplete = rTRUE;
info_24g.DataStatus = STATUS_OK;
#ifdef DEBUG1
printf("Receivev Complete Write Complete !\n");
#endif
break;
}
info_24g.cPacketNo++;
info_24g.WriteAddr = ((info_24g.cPacketNo - 1) * PAGES_SIZE) + FLASH_BIN_ADDR_OFFSET; // info_24g.WriteAddr+=PAGES_SIZE;
info_24g.DataStatus = STATUS_OK;
}
// printf("F %02x ",xc_buffer[0]);
break;
case 6: // packet check result
#ifdef DEBUG1
printf("request check result...\n");
#endif
if (info_24g.RevComplete == rTRUE)
{
info_24g.RevComplete = rFALSE;
uint32_t crc = 0;
uint32_t PageCNT = (info_24g.Len) / FLASH_PAGE_SIZE;
PageCNT = (((info_24g.Len) % FLASH_PAGE_SIZE) == 0) ? PageCNT : (PageCNT + 1);
for (uint32_t i = 0; i < PageCNT; i++)
{
/*read a page*/
spi_flash_Read_Page(FLASH_BIN_ADDR_OFFSET + (i * FLASH_PAGE_SIZE), data_buffer);
for (int j = 0; j < 128; j++)
{
uint8_t t = data_buffer[2 * j];
data_buffer[2 * j] = data_buffer[2 * j + 1];
data_buffer[2 * j + 1] = t;
}
crc = ((PageCNT - 1) == i) ? (get_crc32(crc, data_buffer, ((info_24g.Len) % FLASH_PAGE_SIZE))) : (get_crc32(crc, data_buffer, FLASH_PAGE_SIZE));
}
#ifdef DEBUG1
printf("Check crc32:0x%08X\n", crc);
#endif
if (crc == info_24g.CRC32)
{
info_24g.CheckStatus = STATUS_OK;
}
else
{
info_24g.CheckStatus = STATUS_FAIL;
}
}
else
{
info_24g.CheckStatus = STATUS_BUSY;
}
break;
default:
break;
}
#ifdef DEBUG2
for (int i = 0; i < 32; i++)
{
printf("%02x ", xc_buffer[i]);
}
printf("\r\n");
#endif
}
}
/**
* Copyright (c) 2022 - 2025, XinChip
*
* All rights reserved.
*
* Author :
*
*/
__RAM_CODE void RF24G_Handler(void)
{
rf_intrrupt_flag |= (*STATUS & 0x70);
__write_hw_reg32(STATUS, ALL_IRQ_STATUS); // clear all status inter
// printf("RF24G_Handler stu=%x\n",rf_intrrupt_flag);
}
void erase_flash_chip(void)
{
spi_flash_write_enable();
// spi_flash_chip_erase();
while (spi_flash_wait_till_ready())
;
}
static uint8_t __attribute__((aligned(4))) ParamBuff1[FLASH_PAGE_SIZE];
void rx_24g_ota(void)
{
sboot_message *ptrA = (sboot_message *)(&ParamBuff1[0]);
spi_flash_Read_Page(2 * 4096, ParamBuff1);
int num_1 = 0;
init_24G(RX_MODE);
set_channel(CHANNEL_24G);
my_memset(data_buffer, 0xff, PAGES_SIZE);
#ifdef DEBUG2
dump_log();
#endif
CE_High; // ����RF����
while (1)
{
if (*STATUS & XC_RX_DR)
{
CE_Low; // ��ȡ����������ʱ��ֹRF���ա�
packet_24g();
CE_High;
}
if (num_1 == 0x45500)
{
param_analy(&(ptrA->ParamUnit[0]));
}
num_1++;
}
}
/**
* Copyright (c) 2022 - 2025, XinChip
*
* All rights reserved.
*
* Author :
*
*/