Stair56E UART project

2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
@@ -0,0 +1,127 @@
+#ifndef _BOOTSECOND_H_
+#define _BOOTSECOND_H_
+
+#define __RAM_DMA __attribute__((section("ram_code")))
+typedef enum
+{
+    INVALIDSTAT = 0,
+    ACTIVEASTAT = 1,
+    ERASEASTAT = 2,
+    OVERWRITEASTAT = 3,
+    ACTIVEBSTAT = 4,
+    ERASEBSTAT = 5,
+    OVERWRITEBSTAT = 6,
+} STATUS_T;
+
+typedef enum
+{
+    ERRNONE = 0,
+    ERRPARAMDAMAGE = 1,
+    ERROVERWRITE = 2,
+    ERRCHECK = 3,
+} ERROR_T;
+typedef enum
+{
+    STATUS_APPBOOT,
+    STATUS_APPUPDATA,
+    STATUS_APPERROR,
+} PARMSTATUS;
+typedef enum
+{
+    APPBOOTA = 0,
+    APPUPDATA = 2,
+    APPBOOTB = 3,
+    APPBOOTERR = 4,
+} APPSTATUS;
+typedef enum
+{
+    FLASH_SIZE_1M = 0x11,
+    FLASH_SIZE_2M = 0x12,
+    FLASH_SIZE_4M = 0x13,
+} FLASH_SIZEID;
+
+typedef enum
+{
+    FLASH_1M_BACKUPADDR = 29 * 4096,
+    FLASH_2M_BACKUPADDR = 61 * 4096,
+    FLASH_4M_BACKUPADDR = 125 * 4096,
+} FLASH_SIZE;
+#define DEBUG_PRINT
+#define PIN_AB_DAMAGE 18
+
+// #define PIN_DETECT
+#define PIN_AB_ACTIVE 0
+
+#define CRC32_INITIAL 0
+
+#define CODES_OFFSET 0x20
+#define PARAM_CNT 5
+#define PARAM_LENGTH 240
+#define TO_B 0
+#define TO_A 1
+
+#define CPR_CTLAPBCLKEN_GRCTL_MASK_OFFSET (16UL)
+#define CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Pos (0x0UL) // /*!< Position of WDT_PCLK_EN field. */
+#define CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Msk (0x1UL << CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Pos)
+#define CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_DISABLE (0x0UL << CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Pos) /*!< 0����ʹ��ʱ�� */
+#define CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_ENABLE (0x1UL << CPR_CTLAPBCLKEN_GRCTL_WDT_PCLK_EN_Pos)  /*!< 1��ʹ��ʱ��*/
+#define CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Pos (0x2UL)                                                  // /*!< Position of WDT_RSTN field. */
+#define CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Msk (0x1UL << CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Pos)
+#define CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_DISABLE (RSTN_INVALID << CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Pos) /*!< 1������λ */
+#define CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_ENABLE (RSTN_VALID << CPR_RSTCTL_CTLAPB_SW_WDT_RSTN_Pos)    /*!< 0����λ*/
+#define CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Pos (0x0UL)                                      // /*!< Position of WDT_SYS_RSTN_MASK field. */
+#define CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Msk (0x1UL << CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Pos)
+#define CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_DISABLE (0x0UL << CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Pos) /*!< 0�������� */
+#define CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_ENABLE (0x1UL << CPR_RSTCTL_WDTRST_MASK_WDT_SYS_RSTN_MASK_Pos)  /*!< 1������*/
+#define CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Pos (0x1UL)                                                      // /*!< Position of WDT_M0_RSTN_MASK field. */
+#define CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Msk (0x1UL << CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Pos)
+#define CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_DISABLE (0x0UL << CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Pos) /*!< 0�������� */
+#define CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_ENABLE (0x1UL << CPR_RSTCTL_WDTRST_MASK_WDT_M4_RSTN_MASK_Pos)  /*!< 1������*/
+#define RSTN_VALID (0UL)
+#define RSTN_INVALID (1UL)
+#define PARAM_ADDR ((8*1024)-512)
+#define FLASH_VIR_AADDR 0x11000000
+#define ALIGN(num) __attribute__((aligned(num)))
+
+//#define FLASH_READ_PAGE spi_flash_Read_Page
+//#define FLASH_SECTOR_ERASE spi_flash_sector_erase
+//#define SPI_WRITE_ENABLE spi_flash_write_enable
+//#define FLASH_WRITE_PAGE xc_spi_flash_write_page
+//#define FLASH_WAIT_READY while (spi_flash_wait_till_ready())
+#define FLASH_READ_PAGE    xc_spi_flash_read_page
+#define FLASH_SECTOR_ERASE xc_spi_flash_erase_sector
+#define FLASH_PAGE_ERASE xc_spi_flash_erase_page
+#define SPI_WRITE_ENABLE   
+#define FLASH_WRITE_PAGE   xc_spi_flash_write_page
+#define FLASH_WAIT_READY 
+	
+typedef struct
+{
+    uint32_t status;  /**/
+    uint32_t softver; /**/
+    uint32_t acheck;  /*crc32*/
+    uint32_t aaddr;   /*sector align*/
+    uint32_t alen;    /*page align*/
+    uint32_t bcheck;  /**/
+    uint32_t baddr;   /**/
+    uint32_t blen;    /**/
+    uint32_t aloadaddr;
+    uint32_t bloadaddr;
+    uint32_t RESERVED0[2];
+} param_unit;
+
+typedef struct
+{
+    param_unit paramunit[PARAM_CNT];
+    uint32_t paramcrc32;
+    uint32_t RESERVED1[3];
+} sboot_message;
+void boot_run_sec(void);
+extern volatile uint32_t param_backup_addr;
+void boot_run(void);
+void param_analy(param_unit *sParam);
+__RAM_CODE __asm void MSR_MSP(uint32_t addr);
+void flash_init(void);
+void overwrite_backup(param_unit *oparam);
+ int uart_printf(const char *fmt,...);
+#endif