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Stair56E UART project

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吴琪
2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
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component/rf24/Drivers/xc6xxx_rf_2_4g/xc6xxx_rf_2_4g.c
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component/rf24/Drivers/xc6xxx_rf_2_4g/xc6xxx_rf_2_4g.h
+248 -172
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@@ -1,172 +1,248 @@
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RF_2_4G_H__
#define __RF_2_4G_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_config.h"
#include "xc6xxx.h"
#include "xc_rf_24g_register.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* RF Command Code */
#define R_REG 0x00
#define W_REG 0x20
#define R_RX_PL_WID 0x60
#define R_RX_PLOAD 0x61
#define W_TX_PLOAD 0xA0
#define W_TX_PLOAD_NOACK 0xB0
#define W_ACK_PLOAD 0xA8
#define FLUSH_TX 0xE1
#define FLUSH_RX 0xE2
#define REUSE_TX_PL 0xE3
#define CMD_NOP 0xFF
#define CMD_DONE 0x100
/* FIFO status */
#define STAT_TX_REUSE (0x1 << 6)
#define STAT_TX_FULL (0x1 << 5)
#define STAT_TX_EMPTY (0x1 << 4)
#define STAT_RX_FULL (0x02)
#define STAT_RX_EMPTY (0x01)
/* STATUS Interrupt status */
#define MASK_RX_DR (0x1 << 6)
#define MASK_TX_DS (0x1 << 5)
#define MASK_MAX_RT (0x1 << 4)
#define MASK_ALL_INTER (MASK_RX_DR | MASK_TX_DS| MASK_MAX_RT)
#define CRC_1BIT 1U
#define CRC_2BIT 2U
#define DR_1M 0x02
#define DR_2M 0x0A
#define DR_250K 0x22
#define DR_125K 0x2A
#define TX_MODE 0
#define RX_MODE 1
#define CE_CTL_HIGH XC_RF_2_4G->CFG_TOP |= 0x4000
#define CE_CTL_LOW XC_RF_2_4G->CFG_TOP &= ~0x4000
#define DELAY_CNT 0U
#define RATE_1M 0x02
#define RATE_2M 0x0A
#define RATE_250K 0x22
#define RATE_125K 0x2A
#define LOGI(...) printf(__VA_ARGS__)
#ifdef RF_DEMO
#define FAIL 0U
#define SUCCESS 1U
#define ASSERT while(1)
#endif
#define RF_SEND_CMD_CNT 6U
#define RF_RECV_CMD_CNT 4U
#define BUFF_LEN XINCX_2_4G_PIPE0_LEN
/* RF Tx Status Typedef */
typedef enum
{
TX_DATA_OK = 0,
TX_DATA_INVALID = 1,
TX_RETRANS_MAX = 2
}eRF_Tx_Status;
typedef struct
{
uint8_t buff[BUFF_LEN];
uint32_t cnt;
uint32_t temp;
uint8_t data_length;
} rf_data_typedef_t;
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern uint8_t recv_len;
extern uint8_t recv_buf[BUFF_LEN];
extern bool rf24g_send_timer_flag;
extern bool rf24g_handler_flag;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void nop_cnt(uint32_t cnt);
uint8_t reverseBits(uint8_t input);
uint8_t bleWhitenStart(uint16_t Fre);
void ble_whiten(uint8_t *data, uint8_t len, uint8_t whitenCoeff);
void ble_crc(uint8_t *data, uint8_t len, uint8_t *dst);
void rf_rc_calib(void);
void reset_rf2_4g(void);
void freq_ctune(uint8_t val);
void rf24g_modem_init(void);
void rf24g_config(void);
void rf24g_init(void);
void set_rf_dynpd(uint8_t dynpd);
void set_rf_power(uint8_t tx_pwr);
void rf_set_channel(uint16_t channel);
void set_rf_txaddr(uint32_t addr_l, uint32_t addr_h);
void set_rf_pipe0_rxaddr(uint32_t addr_l, uint32_t addr_h);
void set_rf_tx_addr_width(uint8_t bytes);
void set_rf_DR(uint8_t rate);
void set_rf_feature(uint8_t long_pld, uint8_t fec, uint8_t whiten, uint8_t dpl, uint8_t ack_pay, uint8_t dyn_ack);
void set_rf_compatility_featue(uint8_t guard_cfg, uint8_t long_pld_type, uint8_t preamble_num,
uint8_t preamble_type, uint8_t crc_scope_header, uint8_t crc_scope_addr);
uint8_t set_rf_preamble(uint32_t preamble_word);
void set_rf_guard_woard(uint16_t guard_word);
void set_rf_mode(uint8_t mode);
void set_rf_crc(uint8_t enable, uint8_t crc_bit);
void set_rf_pipe_rx_payLen(uint8_t p0_len, uint8_t p1_len, uint8_t p2_len, uint8_t p3_len, uint8_t p4_len,
uint8_t p5_len);
void set_rf_retr(uint8_t cnt, uint8_t delay);
void set_rf_enaa(uint8_t pipe0_enaa, uint8_t pipe1_enaa, uint8_t pipe2_enaa, uint8_t pipe3_enaa, uint8_t pipe4_enaa,
uint8_t pipe5_enaa);
void rf_2M_config(void);
uint8_t rf_tx_packet(uint8_t *data, uint8_t len);
uint8_t rf_rx_packet(uint8_t *buff);
eRF_Tx_Status rf_tx_event(uint8_t *buff, uint8_t len);
uint8_t rf_rx_event(uint8_t *buff);
#define INFO_BUFF(buff, len) rf_buff_info(buff, len)
#ifdef __cplusplus
}
#endif
#endif /* __RF_2_4G__ */
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RF_2_4G_H__
#define __RF_2_4G_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_config.h"
#include "xc6xxx.h"
#include "xc_rf_24g_register.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* RF Command Code */
#define R_REG 0x00
#define W_REG 0x20
#define R_RX_PL_WID 0x60
#define R_RX_PLOAD 0x61
#define W_TX_PLOAD 0xA0
#define W_TX_PLOAD_NOACK 0xB0
#define W_ACK_PLOAD 0xA8
#define FLUSH_TX 0xE1
#define FLUSH_RX 0xE2
#define REUSE_TX_PL 0xE3
#define CMD_NOP 0xFF
#define CMD_DONE 0x100
/* FIFO status */
#define STAT_TX_REUSE (0x1 << 6)
#define STAT_TX_FULL (0x1 << 5)
#define STAT_TX_EMPTY (0x1 << 4)
#define STAT_RX_FULL (0x02)
#define STAT_RX_EMPTY (0x01)
/* STATUS Interrupt status */
#ifdef XC62XX
#define MASK_PBT_CRC_FAIL (0x1 << 8)
#define MASK_RX_SYNC (0x1 << 7)
#endif
#define MASK_RX_DR (0x1 << 6)
#define MASK_TX_DS (0x1 << 5)
#define MASK_MAX_RT (0x1 << 4)
#define MASK_ALL_INTER (MASK_RX_DR | MASK_TX_DS | MASK_MAX_RT)
/* RF State Machine */
#define CE_CTL_HIGH XC_RF_2_4G->CFG_TOP |= 0x4000
#define CE_CTL_LOW XC_RF_2_4G->CFG_TOP &= ~0x4000
/* Number of CRC bytes */
#define CRC_0BYTE 0U
#define CRC_1BYTE 1U
#define CRC_2BYTE 2U
/* Communication rate */
#define DR_1M 0x02
#define DR_2M 0x0A
#define DR_250K 0x22
#define DR_125K 0x2A
/* Communication mode */
#define TX_MODE 0
#define RX_MODE 1
#define TRX_MODE 2
#define DELAY_CNT 0U
#define LOGI(...) printf(__VA_ARGS__)
#ifdef RF_DEMO
#define RF_FAIL 0U
#define RF_SUCCESS 1U
#define ASSERT while (1)
#endif
#define XINCHIP_PACKET 0
#define PANCHIP_PACKET 1
#define BELKEN_PACKET 2
#define TELINK_PACKET 3
#define HUNTERSUN_PACKET 4
#ifdef XC62XX
/* The maximum payload is 256 bytes */
#define XINCX_2_4G_PIPE0_LEN 32
#else
#if (XINCX_RF_NORMAL_PACKET_MODE)
/* The maximum payload of static packets is 63 bytes */
#define XINCX_2_4G_PIPE0_LEN 32
#else
/* The maximum payload of a dynamic packet is 128 bytes */
#define XINCX_2_4G_PIPE0_LEN 32
#endif //XINCX_RF_NORMAL_PACKET_MODE
#endif //XC62XX
#define BUFF_LEN XINCX_2_4G_PIPE0_LEN
#define readl(addr) (*(volatile unsigned int *)(addr))
#define writel(addr, value) (*(volatile unsigned int *)(addr) = (value))
/* RF Tx Status Typedef */
typedef enum
{
TX_DATA_OK = 0,
TX_DATA_INVALID = 1,
TX_RETRANS_MAX = 2
} eRF_Tx_Status;
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern uint16_t recv_len;
extern uint8_t recv_buf[256];
extern bool rf24g_send_timer_flag;
extern bool rf24g_tx_irq_flag;
extern bool rf24g_rx_irq_flag;
extern eRF_Tx_Status tx_stat;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void nop_cnt(uint32_t cnt);
void rf_wr_cmd(uint8_t cmd);
void rf_rc_calib(void);
void reset_rf2_4g(void);
void freq_ctune(uint8_t val);
void rf24g_modem_init(void);
void rf24g_config(void);
void rf24g_init(void);
void set_rf_dynpd(uint8_t dynpd);
void set_rf_power(uint8_t tx_pwr);
void set_rf_afc(void);
void rf_set_channel(uint16_t channel);
void set_rf_channel(uint16_t channel);
void set_rf_txaddr(uint32_t addr_l, uint32_t addr_h);
void set_rf_pipe0_rxaddr(uint32_t addr_l, uint32_t addr_h);
void set_rf_tx_addr_width(uint8_t bytes);
void set_rf_DR(uint8_t rate);
void set_rf_feature(uint8_t long_pld, uint8_t fec, uint8_t whiten, uint8_t dpl, uint8_t ack_pay, uint8_t dyn_ack);
void set_rf_compatility_featue(uint8_t guard_cfg, uint8_t long_pld_type, uint8_t preamble_num,
uint8_t preamble_type, uint8_t crc_scope_header, uint8_t crc_scope_addr);
uint8_t set_rf_preamble(uint32_t preamble_word);
void set_rf_guard_woard(uint16_t guard_word);
void set_rf_mode(uint8_t mode);
void set_rf_crc(uint8_t crc_byte);
#ifdef XC62XX
void set_rf_pipe_rx_payLen(uint16_t p0_len, uint16_t p1_len, uint16_t p2_len, uint16_t p3_len, uint16_t p4_len,
uint16_t p5_len);
#else
void set_rf_pipe_rx_payLen(uint8_t p0_len, uint8_t p1_len, uint8_t p2_len, uint8_t p3_len, uint8_t p4_len,
uint8_t p5_len);
#endif
void set_rf_retr(uint8_t cnt, uint8_t delay);
void set_rf_enaa(uint8_t pipe0_enaa, uint8_t pipe1_enaa, uint8_t pipe2_enaa, uint8_t pipe3_enaa, uint8_t pipe4_enaa,
uint8_t pipe5_enaa);
void set_rf_en_pipe(uint8_t user_pipe);
void rf_24g_callback(void *context);
void rf_2M_config(void);
uint8_t rf_tx_packet(uint8_t *data, uint16_t len);
uint16_t rf_rx_packet(uint8_t *buff);
eRF_Tx_Status rf_tx_event(uint8_t *buff, uint16_t len);
uint16_t rf_rx_event(uint8_t *buff);
void rf_ana24_set(void);
int16_t rf_get_rssi(void);
#ifdef XC62XX
void rf_pbt_init(void);
uint8_t rf_set_pbt_hl_ord(bool ord);
uint8_t rf_set_pbt_hl_offset(uint16_t hl_offset);
uint8_t rf_set_pbt_h_len(uint8_t handler_len);
uint8_t rf_set_pbt_en(void);
uint8_t rf_set_pbt_off(void);
uint8_t rf_set_crc_bit_inv(bool crc_inv);
uint8_t rf_set_ack_type(bool ack_type);
uint8_t rf_set_pid_det(bool pin_en);
uint8_t rf_set_fifo_len(bool length_fifo);
uint16_t rf_get_pend_rxfrem_len(void);
uint8_t rf_set_pbt_auto_trx(bool auto_trx);
uint8_t rf_set_pbt_pld_len_offset(uint8_t offset);
uint8_t rf_set_pbt_crc_init(uint32_t init_val);
uint32_t rf_get_pbt_timer(void);
uint32_t rf_get_pbt_sync_timer(void);
uint8_t rf_set_pbt_tx_head(uint8_t *hadnler_buff);
uint32_t rf_get_pbt_tx_head(void);
uint32_t rf_get_pbt_rx_head(void);
uint8_t rf_set_pbt_rx2tx_timer(uint16_t timer);
uint8_t rf_set_pbt_tx2rx_timer(uint16_t timer);
uint8_t rf_set_pbt_crc_fail_on(void);
uint8_t rf_set_pbt_crc_fail_off(void);
uint8_t rf_set_sync_inter_on(void);
uint8_t rf_set_sync_inter_off(void);
uint8_t rf_set_whiten_value(uint8_t value);
uint8_t rf_set_panchip_whiten_on(void);
uint8_t rf_set_panchip_whiten_off(void);
uint8_t rf_set_whiten_opt(uint8_t whiten_opt);
uint8_t rf_set_pllon_lock_time(uint8_t pll_timer);
uint8_t rf_set_pbt_auto_trx_timer(uint16_t pbt_rx2tx_timer, uint16_t pbt_tx2rx_timer);
uint8_t rf_set_pbt_config(uint8_t pbt_auto_trx, int len_offset, uint32_t pbt_crc_init);
uint8_t rf_clk_div23_en_soften_on(void);
uint8_t rf_clk_div23_en_soften_off(void);
uint8_t rf_clk_div23_en_soft_on(void);
uint8_t rf_clk_div23_en_soft_off(void);
uint8_t rf_chan_mult_1p5_soften_on(void);
uint8_t rf_chan_mult_1p5_soften_off(void);
uint8_t rf_chan_mult_1p5_soft_on(void);
uint8_t rf_chan_mult_1p5_soft_off(void);
uint8_t rf_chan_frac_offset(uint32_t value);
#endif
void rf_set_freq_dev(uint16_t freq_dev);
uint16_t rf_get_freq_dev(void);
#define INFO_BUFF(buff, len) rf_buff_info(buff, len)
#ifdef __cplusplus
}
#endif
#endif /* __RF_2_4G__ */
component/rf24/Drivers/xc6xxx_rf_ADV/xc6xxx_rf_ADV.c
+217 -135
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@@ -1,135 +1,217 @@
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:24:01
* @LastEditors: sueRimn
* @LastEditTime: 2023-12-13 10:32:28
*/
/*!
* \file rf_2_4g.c
*
* \brief Target RF 2.4g implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx_rf_ADV.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
extern int sendchar(int c);
extern uint8_t recv_len ;
extern uint8_t recv_buf[BUFF_LEN];
extern uint8_t recv_adv_buf[ADV_LENGTH];
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
* @brief RF ADV Initialization
* @param void
*
* @retval void
*/
void rf24g_adv_init(void)
{
/* Rf modem init*/
rf24g_modem_init();
/* Set up 2.4G RF modem*/
rf24g_config();
set_rf_dynpd(XINCX_2_4G_DYNPD);
/* Set PTX address */
set_rf_txaddr(TX_ADDR_L_VAL, TX_ADDR_H_VAL);
/* Set PRX address */
set_rf_pipe0_rxaddr(RX_ADDR_L_VAL, RX_ADDR_H_VAL);
/* Set address width */
set_rf_tx_addr_width(XINCX_RF_TX_ADDR_WIDTH);
/* Set transfer rate */
set_rf_DR(XINCX_RF_TRANS_RATE);
/* Set CRC */
set_rf_crc(XINCX_RF_CRC_ENABLE, XINCX_RF_CRC_BIT);
/* Set data frame format */
set_rf_feature(XINCX_ADV_LONG_PLD, XINCX_ADV_FEC, XINCX_ADV_WHITEN,
XINCX_ADV_DPL, XINCX_ADV_ACK_PAY, XINCX_ADV_DYN_ACK);
/* Set Payload */
set_rf_pipe_rx_payLen(PIPE0_LEN, PIPE1_LEN, PIPE2_LEN, PIPE3_LEN, PIPE4_LEN,
PIPE5_LEN);
/* Set mode */
set_rf_mode(XINCX_ADV_MODE);
/* Set transmission power */
set_rf_power(XINCX_POWER);
/* RC filtering calibration */
rf_rc_calib();
}
/**
* @brief RF ADV packet whiten
* @param uint8_t * - len
* @return uint32_t - blecrc
*/
uint32_t rf_adv_packet_whiten(uint8_t *len)
{
for (int i = 0; i < recv_len; i++)
recv_adv_buf[i] = reverseBits(recv_adv_buf[i]);
ble_whiten(recv_adv_buf, recv_len, bleWhitenStart(XINCX_ADV_CHANNEL));
for (int i = 0; i < recv_len; i++)
recv_adv_buf[i] = reverseBits(recv_adv_buf[i]);
*len = (recv_adv_buf[1] > (ADV_LENGTH - 5)) ? (ADV_LENGTH - 5)
: recv_adv_buf[1];
uint32_t blecrc = (recv_adv_buf[*len + 5 - 1] << 16) +
(recv_adv_buf[*len + 5 - 2] << 8) +
recv_adv_buf[*len + 5 - 3];
recv_adv_buf[*len + 5 - 1] = recv_adv_buf[*len + 5 - 2] =
recv_adv_buf[*len + 5 - 3] = 0x55;
ble_crc(recv_adv_buf, *len + 5 - 3, recv_adv_buf + *len + 5 - 3);
return blecrc;
}
/**
* @brief RF ADV software CRC determination
* @param uint8_t * - adv_buff
* @param uint8_t * - len
* @param uint32_t - blecrc
* @return uint8_t - 0
*/
uint8_t rf_adv_crc(uint8_t *adv_buff, uint8_t *len, uint32_t blecrc)
{
if (blecrc == ((adv_buff[*len + 5 - 1] << 16) +
(adv_buff[*len + 5 - 2] << 8) + adv_buff[*len + 5 - 3]))
return 1;
else
return 0;
}
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:24:01
* @LastEditors: sueRimn
* @LastEditTime: 2023-12-13 10:32:28
*/
/*!
* \file rf_2_4g.c
*
* \brief Target RF 2.4g implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx_rf_ADV.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
extern int sendchar(int c);
extern uint8_t recv_adv_buf[ADV_LENGTH];
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
* @brief RF ADV Initialization
* @param void
*
* @retval void
*/
void rf24g_adv_init(void)
{
/* Rf modem init*/
rf24g_modem_init();
/* Set up 2.4G RF modem*/
rf24g_config();
set_rf_dynpd(XINCX_2_4G_DYNPD);
/* Set PTX address */
set_rf_txaddr(TX_ADDR_L_VAL, TX_ADDR_H_VAL);
/* Set PRX address */
set_rf_pipe0_rxaddr(RX_ADDR_L_VAL, RX_ADDR_H_VAL);
/* Set address width */
set_rf_tx_addr_width(XINCX_RF_TX_ADDR_WIDTH);
/* Set transfer rate */
set_rf_DR(XINCX_RF_TRANS_RATE);
/* Set retransmission delay and retransmission frequency */
set_rf_retr(XINCX_2_4G_RETRANS_CNT, XINCX_2_4G_RETRANS_DELAY);
/* Set CRC */
set_rf_crc(XINCX_2_4G_CRC_BYTE);
/* Set data frame format */
set_rf_feature(XINCX_ADV_LONG_PLD, XINCX_ADV_FEC, XINCX_ADV_WHITEN, XINCX_ADV_DPL, XINCX_ADV_ACK_PAY,
XINCX_ADV_DYN_ACK);
/* Set Payload */
set_rf_pipe_rx_payLen(PIPE0_LEN, PIPE1_LEN, PIPE2_LEN, PIPE3_LEN, PIPE4_LEN, PIPE5_LEN);
/* Set ack pipe*/
set_rf_en_pipe(XINCX_RF_PIPE_ENABLE);
/* Set transmission power */
set_rf_power(XINCX_POWER);
/* Set mode */
set_rf_mode(XINCX_ADV_MODE);
/* RC filtering calibration */
rf_rc_calib();
}
/**
* @brief RF ADV packet whiten
* @param uint8_t * - len
* @return uint32_t - blecrc
*/
uint32_t rf_adv_packet_whiten(uint8_t *len)
{
for (int i = 0; i < recv_len; i++)
recv_adv_buf[i] = reverseBits(recv_adv_buf[i]);
uint16_t channel = (XC_RF_2_4G->RF_CH & 0x3fff) + 1;
ble_whiten(recv_adv_buf, recv_len, bleWhitenStart(channel));
for (int i = 0; i < recv_len; i++)
recv_adv_buf[i] = reverseBits(recv_adv_buf[i]);
*len = (recv_adv_buf[1] > (ADV_LENGTH - 5)) ? (ADV_LENGTH - 5) : recv_adv_buf[1];
uint32_t blecrc =
(recv_adv_buf[*len + 5 - 1] << 16) + (recv_adv_buf[*len + 5 - 2] << 8) + recv_adv_buf[*len + 5 - 3];
recv_adv_buf[*len + 5 - 1] = recv_adv_buf[*len + 5 - 2] = recv_adv_buf[*len + 5 - 3] = 0x55;
ble_crc(recv_adv_buf, *len + 5 - 3, recv_adv_buf + *len + 5 - 3);
return blecrc;
}
/**
* @brief RF ADV software CRC determination
* @param uint8_t * - adv_buff
* @param uint8_t * - len
* @param uint32_t - blecrc
* @return uint8_t - 0
*/
uint16_t rf_adv_crc(uint8_t *adv_buff, uint8_t *len, uint32_t blecrc)
{
if (blecrc == ((adv_buff[*len + 5 - 1] << 16) + (adv_buff[*len + 5 - 2] << 8) + adv_buff[*len + 5 - 3]))
return 1;
else
return 0;
}
/**
* @brief Reverse bits
* @param uint8_t - input
* @retval uint8_t - temp
*/
uint8_t reverseBits(uint8_t input)
{
uint8_t i = 0, temp = 0;
for (; i < 8; i++) {
temp <<= 1;
temp = ((input >> i) & 0x01) ? (temp | 0x01) : (temp | 0x00);
}
return temp;
}
/**
* @brief Ble whiten channel
* @param uint16_t - fre
* @retval uint8_t - temp | 2
*/
uint8_t bleWhitenStart(uint16_t Fre)
{
uint8_t chan = (Fre == 2426) ? 38 : ((Fre == 2402) ? 37 : 39);
return reverseBits(chan) | 2;
}
/**
* @brief Ble whiten
* @param uint8_t * - data
* @param uint8_t - len
* @param uint8_t - whitenCoeff
* @retval void
*/
void ble_whiten(uint8_t *data, uint8_t len, uint8_t whitenCoeff)
{
uint8_t m;
while (len--) {
for (m = 1; m; m <<= 1) {
if (whitenCoeff & 0x80) {
whitenCoeff ^= 0x11;
(*data) ^= m;
}
whitenCoeff <<= 1;
}
// Flip variables
*data = reverseBits(*data);
data++;
}
}
/**
* @brief
* @param void
* @retval void
*/
void ble_crc(uint8_t *data, uint8_t len, uint8_t *dst)
{
// calculating the CRC based on a LFSR
uint8_t i, temp, tempData;
while (len--) {
tempData = *data++;
for (i = 0; i < 8; i++, tempData >>= 1) {
temp = dst[0] >> 7;
dst[0] <<= 1;
if (dst[1] & 0x80) {
dst[0] |= 1;
}
dst[1] <<= 1;
if (dst[2] & 0x80) {
dst[1] |= 1;
}
dst[2] <<= 1;
if (temp != (tempData & 1)) {
dst[2] ^= 0x5B;
dst[1] ^= 0x06;
}
}
}
dst[2] = reverseBits(dst[2]);
dst[1] = reverseBits(dst[1]);
dst[0] = reverseBits(dst[0]);
}
component/rf24/Drivers/xc6xxx_rf_ADV/xc6xxx_rf_ADV.h
+101 -90
View File
@@ -1,90 +1,101 @@
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:24:01
* @LastEditors: sueRimn
* @LastEditTime: 2023-12-13 13:56:02
*/
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6XXX_RF_ADV_H__
#define __XC6XXX_RF_ADV_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_adv_config.h"
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define PIPE0_LEN XINCX_ADV_PIPE0_LEN
#define PIPE1_LEN XINCX_ADV_PIPE1_LEN
#define PIPE2_LEN XINCX_ADV_PIPE2_LEN
#define PIPE3_LEN XINCX_ADV_PIPE3_LEN
#define PIPE4_LEN XINCX_ADV_PIPE4_LEN
#define PIPE5_LEN XINCX_ADV_PIPE5_LEN
#define MAC_ADDR_0 XINC_ADV_MAC_ADDR_0
#define MAC_ADDR_1 XINC_ADV_MAC_ADDR_1
#define MAC_ADDR_2 XINC_ADV_MAC_ADDR_2
#define MAC_ADDR_3 XINC_ADV_MAC_ADDR_3
#define MAC_ADDR_4 XINC_ADV_MAC_ADDR_4
#define MAC_ADDR_5 XINC_ADV_MAC_ADDR_5
#define TX_ADDR_L_VAL XINCX_ADV_ADDR_L
#define TX_ADDR_H_VAL XINCX_ADV_ADDR_H
#define RX_ADDR_L_VAL TX_ADDR_L_VAL
#define RX_ADDR_H_VAL TX_ADDR_H_VAL
#define ADV_LENGTH XINCX_ADV_PIPE0_LEN
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
typedef enum
{
CRC_ERROR = 0,
CRC_OK,
CRC_IDLE
} rf_adv_crc_stat;
void rf24g_adv_init(void);
uint32_t rf_adv_packet_whiten(uint8_t *len);
uint8_t rf_adv_crc(uint8_t *adv_buff, uint8_t *len, uint32_t blecrc);
#ifdef __cplusplus
}
#endif
#endif /* __XC6XXX_RF_ADV_H__ */
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:24:01
* @LastEditors: sueRimn
* @LastEditTime: 2023-12-13 13:56:02
*/
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6XXX_RF_ADV_H__
#define __XC6XXX_RF_ADV_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_adv_config.h"
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define PIPE0_LEN XINCX_ADV_PIPE0_LEN
#define PIPE1_LEN XINCX_ADV_PIPE1_LEN
#define PIPE2_LEN XINCX_ADV_PIPE2_LEN
#define PIPE3_LEN XINCX_ADV_PIPE3_LEN
#define PIPE4_LEN XINCX_ADV_PIPE4_LEN
#define PIPE5_LEN XINCX_ADV_PIPE5_LEN
#define MAC_ADDR_0 XINC_ADV_MAC_ADDR_0
#define MAC_ADDR_1 XINC_ADV_MAC_ADDR_1
#define MAC_ADDR_2 XINC_ADV_MAC_ADDR_2
#define MAC_ADDR_3 XINC_ADV_MAC_ADDR_3
#define MAC_ADDR_4 XINC_ADV_MAC_ADDR_4
#define MAC_ADDR_5 XINC_ADV_MAC_ADDR_5
#define TX_ADDR_L_VAL XINCX_ADV_ADDR_L
#define TX_ADDR_H_VAL XINCX_ADV_ADDR_H
#define RX_ADDR_L_VAL TX_ADDR_L_VAL
#define RX_ADDR_H_VAL TX_ADDR_H_VAL
#define ADV_LENGTH XINCX_ADV_PIPE0_LEN
#define RF_ADV_BASE 2400U
#define RF_ADV_CHANNEL_37 2
#define RF_ADV_CHANNEL_38 26
#define RF_ADV_CHANNEL_39 80
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
typedef enum
{
CRC_ERROR = 0,
CRC_OK,
CRC_IDLE
} rf_adv_crc_stat;
void rf24g_adv_init(void);
uint32_t rf_adv_packet_whiten(uint8_t *len);
uint16_t rf_adv_crc(uint8_t *adv_buff, uint8_t *len, uint32_t blecrc);
uint8_t reverseBits(uint8_t input);
uint8_t bleWhitenStart(uint16_t Fre);
void ble_whiten(uint8_t *data, uint8_t len, uint8_t whitenCoeff);
void ble_crc(uint8_t *data, uint8_t len, uint8_t *dst);
#ifdef __cplusplus
}
#endif
#endif /* __XC6XXX_RF_ADV_H__ */
component/rf24/Drivers/xc6xxx_rf_single/xc6xxx_rf_single.c
+66 -63
View File
@@ -1,63 +1,66 @@
/*!
* \file rf_2_4g.c
*
* \brief Target RF 2.4g implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx_rf_single.h"
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define RF_SINGLE 0x01
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
* @brief RF single initialization
* @param void
*
* @retval void
*/
void rf_single_init(void)
{
/* Rf modem init*/
rf24g_modem_init();
/* Set up 2.4G RF modem*/
rf24g_config();
/* Set modulation frequency offset to 0 */
XC_RF_2_4G->TXPROC_CFG = 0x00;
/* Set to enter single carrier mode */
set_rf_DR(XINCX_RF_TRANS_RATE | RF_SINGLE);
/* Set configuration register */
XC_RF_2_4G->CFG_TOP = 0x298272;
/* Set transmission power */
set_rf_power(XINCX_POWER);
}
/*!
* \file rf_2_4g.c
*
* \brief Target RF 2.4g implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx_rf_single.h"
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define RF_SINGLE 0x01
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
* @brief RF single initialization
* @param void
*
* @retval void
*/
void rf_single_init(void)
{
/* Rf modem init*/
rf24g_modem_init();
/* Set up 2.4G RF modem*/
rf24g_config();
/* Set modulation frequency offset to 0 */
XC_RF_2_4G->TXPROC_CFG = 0x00;
/* Set to enter single carrier mode */
set_rf_DR(XINCX_RF_TRANS_RATE | RF_SINGLE);
/* Set configuration register */
XC_RF_2_4G->CFG_TOP = 0x298272;
/* Set transmission power */
set_rf_power(XINCX_POWER);
}
component/rf24/Drivers/xc6xxx_rf_single/xc6xxx_rf_single.h
+55 -54
View File
@@ -1,54 +1,55 @@
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6XXX_RF_SINGLE_H__
#define __XC6XXX_RF_SINGLE_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void rf_single_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __XC6XXX_RF_SINGLE_H__ */
/*!
* \file rf_2_4g.h
*
* \brief The head file of rf_2_4g.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6XXX_RF_SINGLE_H__
#define __XC6XXX_RF_SINGLE_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
#include "rf_single_config.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void rf_single_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __XC6XXX_RF_SINGLE_H__ */
component/rf24/Drivers/xc_rf24g_register/xc_rf_24g_register.h
+205 -190
View File
@@ -1,190 +1,205 @@
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2024-03-21 10:47:04
* @LastEditors: sueRimn
* @LastEditTime: 2024-03-21 13:50:06
*/
#ifndef __XC_RF_24G_REGISTER_H__
#define __XC_RF_24G_REGISTER_H__
#include "xc60xx.h"
#include <stdint.h>
/* ===========================================================================================================================
*/
/* ================ BT RF ================ */
/* ===========================================================================================================================
*/
/* BT RF Register Typedef */
typedef struct
{
__IOM uint16_t ana0_reg_l; /* RF analog0 Reg (0x000) */
__IOM uint16_t ana0_reg_h;
__IOM uint16_t ana1_reg_l; /* RF analog1 Reg (0x004) */
__IOM uint16_t ana1_reg_h;
__IOM uint16_t ana2_reg_l; /* RF analog2 Reg (0x008) */
__IOM uint16_t ana2_reg_h;
__IOM uint16_t ana3_reg_l; /* RF analog3 Reg (0x00C) */
__IOM uint16_t ana3_reg_h;
__IOM uint16_t ana4_reg_l; /* RF analog4 Reg (0x010) */
__IOM uint16_t ana4_reg_h;
__IOM uint16_t ana5_reg_l; /* RF analog5 Reg (0x014) */
__IOM uint16_t ana5_reg_h;
__IOM uint16_t ana6_reg_l; /* RF analog6 Reg (0x018) */
__IOM uint16_t ana6_reg_h;
__IOM uint16_t ana7_reg_l; /* RF analog7 Reg (0x01C) */
__IOM uint16_t ana7_reg_h;
__IOM uint16_t ana8_reg_l; /* RF analog8 Reg (0x020) */
__IOM uint16_t ana8_reg_h;
__IOM uint16_t ana9_reg_l; /* RF analog9 Reg (0x024) */
__IOM uint16_t ana9_reg_h;
__IOM uint16_t ana10_reg_l; /* RF analog10 Reg (0x028) */
__IOM uint16_t ana10_reg_h;
__IOM uint16_t ana11_reg_l; /* RF analog11 Reg (0x02C) */
__IOM uint16_t ana11_reg_h;
__IOM uint16_t ana12_reg_l; /* RF analog12 Reg (0x030) */
__IOM uint16_t ana12_reg_h;
__IOM uint16_t ana13_reg_l; /* RF analog13 Reg (0x034) */
__IOM uint16_t ana13_reg_h;
__IOM uint16_t ana14_reg_l; /* RF analog14 Reg (0x038) */
__IOM uint16_t ana14_reg_h;
__IOM uint16_t ana15_reg_l; /* RF analog15 Reg (0x03C) */
__IOM uint16_t ana15_reg_h;
__IOM uint16_t ana16_reg_l; /* RF analog16 Reg (0x040) */
__IOM uint16_t ana16_reg_h;
__IOM uint16_t ana17_reg_l; /* RF analog17 Reg (0x044) */
__IOM uint16_t ana17_reg_h;
__IOM uint16_t ana18_reg_l; /* RF analog18 Reg (0x048) */
__IOM uint16_t ana18_reg_h;
__IOM uint16_t ana19_reg_l; /* RF analog19 Reg (0x04C) */
__IOM uint16_t ana19_reg_h;
__IOM uint16_t ana20_reg_l; /* RF analog20 Reg (0x050) */
__IOM uint16_t ana20_reg_h;
__IOM uint16_t ana21_reg_l; /* RF analog21 Reg (0x054) */
__IOM uint16_t ana21_reg_h;
__IOM uint32_t reserved1[1]; /* Reserved (0x058) - (0x05c) */
__IOM uint16_t ana23_reg_l;
__IOM uint16_t ana23_reg_h;
__IOM uint16_t ana24_reg_l; /* RF analog24 Reg (0x060) */
__IOM uint16_t ana24_reg_h;
__IOM uint16_t ana25_reg_l; /* RF analog25 Reg (0x064) */
__IOM uint16_t ana25_reg_h;
__IOM uint16_t ana26_reg_l; /* RF analog26 Reg (0x068) */
__IOM uint16_t ana26_reg_h;
__IOM uint16_t ana27_reg_l; /* RF analog27 Reg (0x06C) */
__IOM uint16_t ana27_reg_h;
__IOM uint16_t ana28_reg_l; /* RF analog28 Reg (0x070) */
__IOM uint16_t ana28_reg_h;
__IOM uint16_t ana29_reg_l; /* RF analog29 Reg (0x074) */
__IOM uint16_t ana29_reg_h;
__IOM uint16_t ana30_reg_l; /* RF analog30 Reg (0x078) */
__IOM uint16_t ana30_reg_h;
__IOM uint16_t ana31_reg_l; /* RF analog31 Reg (0x07C) */
__IOM uint16_t ana31_reg_h;
__IOM uint16_t rccal_reg_l; /* RF rccal Reg (0x080) */
__IOM uint16_t rccal_reg_h;
__IOM uint16_t rccal_rslt_l; /* RF rccal result Reg (0x084) */
__IOM uint16_t rccal_rslt_h;
struct
{
__IOM uint16_t rx_lna_map0_l; /* BT rx lna map0 Reg (0x088) */
__IOM uint16_t rx_lna_map0_h;
__IOM uint16_t rx_lna_map1_l; /* BT rx lna map1 Reg (0x08C) */
__IOM uint16_t rx_lna_map1_h;
__IOM uint16_t rx_vga_map0_l; /* BT rx vga map0 Reg (0x090) */
__IOM uint16_t rx_vga_map0_h;
__IOM uint16_t rx_vga_map1_l; /* BT rx vga map1 Reg (0x094) */
__IOM uint16_t rx_vga_map1_h;
__IOM uint16_t rx_vga_map2_l; /* BT rx vga map2 Reg (0x098) */
__IOM uint16_t rx_vga_map2_h;
__IOM uint16_t rx_vga_map3_l; /* BT rx vga map3 Reg (0x09C) */
__IOM uint16_t rx_vga_map3_h;
__IOM uint16_t rx_vga_map4_l; /* BT rx vga map4 Reg (0x0A0) */
__IOM uint16_t rx_vga_map4_h;
__IOM uint16_t rx_vga_map5_l; /* BT rx vga map5 Reg (0x0A4) */
__IOM uint16_t rx_vga_map5_h;
__IOM uint16_t rx_vga_map6_l; /* BT rx vga map6 Reg (0x0A8) */
__IOM uint16_t rx_vga_map6_h;
__IOM uint16_t rx_vga_map7_l; /* BT rx vga map7 Reg (0x0AC) */
__IOM uint16_t rx_vga_map7_h;
__IOM uint16_t rx_pm_reg_l; /* BT rx pm Reg (0x0B0) */
__IOM uint16_t rx_pm_reg_h;
__IOM uint16_t rx_chan_reg_l; /* BT rx chan Reg (0x0B4) */
__IOM uint16_t rx_chan_reg_h;
__IOM uint16_t rx_ctrl_sel_l; /* BT rx control select Reg (0x0B8) */
__IOM uint16_t rx_ctrl_sel_h;
__IOM uint16_t rf_ctrl1_l;
__IOM uint16_t rf_ctrl1_h;
} BT;
} BT_RF_TypeDef;
/* ===========================================================================================================================
*/
/* ================ 2.4G ================ */
/* ===========================================================================================================================
*/
/* RF 2.4G Module Register Typedef */
typedef struct
{
__IOM uint32_t CFG_TOP; /*!< Top-level configuration (0x000) */
__IOM uint32_t EN_AA; /*!< Auto-acknowledgement settings (0x004) */
__IOM uint32_t EN_RXADDR; /*!< Enable RX addresses (0x008) */
__IOM uint32_t SETUP_AW; /*!< Address width & timing stup (0x00C) */
__IOM uint32_t SETUP_RETR; /*!< Automatic retransmission setup (0x010) */
__IOM uint32_t RF_CH; /*!< RF channel (0x014) */
__IOM uint32_t SETUP_RF; /*!< RF settings (0x018) */
__IOM uint32_t STATUS; /*!< Status, SDO output may be adjusted (0x01C) */
__IOM uint32_t OBSERVE_TX; /*!< Transmission observation (0x020) */
__IOM uint32_t RSSI; /*!< TSSI and RSSI indicator/control (0x024) */
__IOM uint32_t RX_ADDR_P0_L; /*!< RX address low 32bit for data pipe 0 (0x028) */
__IOM uint32_t RX_ADDR_P0_H; /*!< RX address high 8bit for data pipe 0 (0x02C) */
__IOM uint32_t RX_ADDR_P1_L; /*!< RX address low 32bit for data pipe 1 (0x030) */
__IOM uint32_t RX_ADDR_P1_H; /*!< RX address high 8bit for data pipe 1 (0x034) */
__IOM uint32_t RX_ADDR_P2TOP5; /*!< Only LSB are set, MSB use RX_ADDR_P1 (0x038) */
__IOM uint32_t BER_RECV_CNT; /*!< Receive total Bit Counter for BER Test (0x03C) */
__IOM uint32_t BER_ERR_CNT; /*!< Receive error Bit Counter for BER Test (0x040) */
__IOM uint32_t AGC_SETTING; /*!< AGC setting (0x044) */
__IOM uint32_t PGA_SETTING; /*!< PGA setting (0x048) */
__IOM uint32_t TX_ADDR_L; /*!< TX address low 32bit (0x04C) */
__IOM uint32_t TX_ADDR_H; /*!< TX address high 8bit (0x050) */
__IOM uint32_t RX_PW_Px_L; /*!< Number of bytes in data pipe0~3 (0x054) */
__IOM uint32_t RX_PW_Px_H; /*!< Number of bytes in data pipe4~5 (0x058) */
__IOM uint32_t ANALOG_CFG0_L; /*!< Analog register 0 low 32bit (0x05C) */
__IOM uint32_t ANALOG_CFG0_H; /*!< Analog register 0 high 32bit (0x060) */
__IOM uint32_t ANALOG_CFG1_L; /*!< Analog register 1 low 32bit (0x064) */
__IOM uint32_t ANALOG_CFG1_H; /*!< Analog register 1 high 32bit (0x068) */
__IOM uint32_t ANALOG_CFG2_L; /*!< Analog register 2 low 32bit (0x06C) */
__IOM uint32_t ANALOG_CFG2_H; /*!< Analog register 2 high 32bit (0x070) */
__IOM uint32_t ANALOG_CFG3_L; /*!< Analog register 3 low 32bit (0x074) */
__IOM uint32_t ANALOG_CFG3_H; /*!< Analog register 3 high 32bit (0x078) */
__IM uint32_t Reserved1; /*!< Reserved1 (0x07C) */
__IOM uint32_t STATUS_FIFO; /*!< FIFO status (0x080) */
__IOM uint32_t RSSIREC; /*!< RSSI recorder feature (0x084) */
__IOM uint32_t TXPROC_CFG; /*!< TX Process configuration (0x088) */
__IOM uint32_t RXPROC_CFG_L; /*!< RX Process configuration (0x08C) */
__IM uint32_t Reserved2; /*!< Reserved2 (0x090) */
__IOM uint32_t DYNPD; /*!< Dynamic payload length (0x094) */
__IOM uint32_t FEATURE; /*!< Features (0x098) */
__IM uint32_t Reserved3[3]; /*!< Reserved3 (0x09C - 0x0A4) */
__IOM uint32_t RXPROC_CFG_H; /*!< PA Ramp Configuration (0x0A8) */
__IOM uint32_t Reserved4; /*!< Reserved4 (0x0AC) */
__IOM uint32_t PREAMBLE; /*!< PREAMBLE (0x0B0) */
__IOM uint32_t GUARD; /*!< PA Ramp Configuration (0x0B4) */
__IM uint32_t Reserved5[2]; /*!< Reserved4 (0x0B8 - 0x0BC) */
__IOM uint32_t CMD_CFG; /*!< Command Configuration (0x0C0) */
__IOM uint32_t TX_FIFO_DATA; /*!< Tx Fifo Data (0x0C4) */
__IOM uint32_t RX_FIFO_DATA; /*!< Rx Fifo Data (0x0C8) */
__IOM uint32_t RX_FIFO_LEN; /*!< Tx Fifo Data Len (0x0CC) */
} RF_2_4G_TypeDef;
#define XC_BT_RF_BASE 0x53021000UL
#define XC_RF_2_4G_BASE 0x53023000UL
#define XC_BT_RF ((BT_RF_TypeDef *)XC_BT_RF_BASE)
#define XC_RF_2_4G ((RF_2_4G_TypeDef *)XC_RF_2_4G_BASE)
#define BLE_COMMON_BASE 0x53022000UL
#define BLE_COMN_RF24G_CTRL ((volatile uint32_t *)(BLE_COMMON_BASE + 0x40))
#endif //__XC_RF_24G_REGISTER_H__
/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2024-03-21 10:47:04
* @LastEditors: sueRimn
* @LastEditTime: 2024-03-21 13:50:06
*/
#ifndef __XC_RF_24G_REGISTER_H__
#define __XC_RF_24G_REGISTER_H__
#include "xc6xxx.h"
#include <stdint.h>
/* ===========================================================================================================================
*/
/* ================ BT RF ================ */
/* ===========================================================================================================================
*/
/* BT RF Register Typedef */
typedef struct
{
__IOM uint16_t ana0_reg_l; /* RF analog0 Reg (0x000) */
__IOM uint16_t ana0_reg_h;
__IOM uint16_t ana1_reg_l; /* RF analog1 Reg (0x004) */
__IOM uint16_t ana1_reg_h;
__IOM uint16_t ana2_reg_l; /* RF analog2 Reg (0x008) */
__IOM uint16_t ana2_reg_h;
__IOM uint16_t ana3_reg_l; /* RF analog3 Reg (0x00C) */
__IOM uint16_t ana3_reg_h;
__IOM uint16_t ana4_reg_l; /* RF analog4 Reg (0x010) */
__IOM uint16_t ana4_reg_h;
__IOM uint16_t ana5_reg_l; /* RF analog5 Reg (0x014) */
__IOM uint16_t ana5_reg_h;
__IOM uint16_t ana6_reg_l; /* RF analog6 Reg (0x018) */
__IOM uint16_t ana6_reg_h;
__IOM uint16_t ana7_reg_l; /* RF analog7 Reg (0x01C) */
__IOM uint16_t ana7_reg_h;
__IOM uint16_t ana8_reg_l; /* RF analog8 Reg (0x020) */
__IOM uint16_t ana8_reg_h;
__IOM uint16_t ana9_reg_l; /* RF analog9 Reg (0x024) */
__IOM uint16_t ana9_reg_h;
__IOM uint16_t ana10_reg_l; /* RF analog10 Reg (0x028) */
__IOM uint16_t ana10_reg_h;
__IOM uint16_t ana11_reg_l; /* RF analog11 Reg (0x02C) */
__IOM uint16_t ana11_reg_h;
__IOM uint16_t ana12_reg_l; /* RF analog12 Reg (0x030) */
__IOM uint16_t ana12_reg_h;
__IOM uint16_t ana13_reg_l; /* RF analog13 Reg (0x034) */
__IOM uint16_t ana13_reg_h;
__IOM uint16_t ana14_reg_l; /* RF analog14 Reg (0x038) */
__IOM uint16_t ana14_reg_h;
__IOM uint16_t ana15_reg_l; /* RF analog15 Reg (0x03C) */
__IOM uint16_t ana15_reg_h;
__IOM uint16_t ana16_reg_l; /* RF analog16 Reg (0x040) */
__IOM uint16_t ana16_reg_h;
__IOM uint16_t ana17_reg_l; /* RF analog17 Reg (0x044) */
__IOM uint16_t ana17_reg_h;
__IOM uint16_t ana18_reg_l; /* RF analog18 Reg (0x048) */
__IOM uint16_t ana18_reg_h;
__IOM uint16_t ana19_reg_l; /* RF analog19 Reg (0x04C) */
__IOM uint16_t ana19_reg_h;
__IOM uint16_t ana20_reg_l; /* RF analog20 Reg (0x050) */
__IOM uint16_t ana20_reg_h;
__IOM uint16_t ana21_reg_l; /* RF analog21 Reg (0x054) */
__IOM uint16_t ana21_reg_h;
__IOM uint32_t reserved1[1]; /* Reserved (0x058) - (0x05c) */
__IOM uint16_t ana23_reg_l;
__IOM uint16_t ana23_reg_h;
__IOM uint16_t ana24_reg_l; /* RF analog24 Reg (0x060) */
__IOM uint16_t ana24_reg_h;
__IOM uint16_t ana25_reg_l; /* RF analog25 Reg (0x064) */
__IOM uint16_t ana25_reg_h;
__IOM uint16_t ana26_reg_l; /* RF analog26 Reg (0x068) */
__IOM uint16_t ana26_reg_h;
__IOM uint16_t ana27_reg_l; /* RF analog27 Reg (0x06C) */
__IOM uint16_t ana27_reg_h;
__IOM uint16_t ana28_reg_l; /* RF analog28 Reg (0x070) */
__IOM uint16_t ana28_reg_h;
__IOM uint16_t ana29_reg_l; /* RF analog29 Reg (0x074) */
__IOM uint16_t ana29_reg_h;
__IOM uint16_t ana30_reg_l; /* RF analog30 Reg (0x078) */
__IOM uint16_t ana30_reg_h;
__IOM uint16_t ana31_reg_l; /* RF analog31 Reg (0x07C) */
__IOM uint16_t ana31_reg_h;
__IOM uint16_t rccal_reg_l; /* RF rccal Reg (0x080) */
__IOM uint16_t rccal_reg_h;
__IOM uint16_t rccal_rslt_l; /* RF rccal result Reg (0x084) */
__IOM uint16_t rccal_rslt_h;
struct
{
__IOM uint16_t rx_lna_map0_l; /* BT rx lna map0 Reg (0x088) */
__IOM uint16_t rx_lna_map0_h;
__IOM uint16_t rx_lna_map1_l; /* BT rx lna map1 Reg (0x08C) */
__IOM uint16_t rx_lna_map1_h;
__IOM uint16_t rx_vga_map0_l; /* BT rx vga map0 Reg (0x090) */
__IOM uint16_t rx_vga_map0_h;
__IOM uint16_t rx_vga_map1_l; /* BT rx vga map1 Reg (0x094) */
__IOM uint16_t rx_vga_map1_h;
__IOM uint16_t rx_vga_map2_l; /* BT rx vga map2 Reg (0x098) */
__IOM uint16_t rx_vga_map2_h;
__IOM uint16_t rx_vga_map3_l; /* BT rx vga map3 Reg (0x09C) */
__IOM uint16_t rx_vga_map3_h;
__IOM uint16_t rx_vga_map4_l; /* BT rx vga map4 Reg (0x0A0) */
__IOM uint16_t rx_vga_map4_h;
__IOM uint16_t rx_vga_map5_l; /* BT rx vga map5 Reg (0x0A4) */
__IOM uint16_t rx_vga_map5_h;
__IOM uint16_t rx_vga_map6_l; /* BT rx vga map6 Reg (0x0A8) */
__IOM uint16_t rx_vga_map6_h;
__IOM uint16_t rx_vga_map7_l; /* BT rx vga map7 Reg (0x0AC) */
__IOM uint16_t rx_vga_map7_h;
__IOM uint16_t rx_pm_reg_l; /* BT rx pm Reg (0x0B0) */
__IOM uint16_t rx_pm_reg_h;
__IOM uint16_t rx_chan_reg_l; /* BT rx chan Reg (0x0B4) */
__IOM uint16_t rx_chan_reg_h;
__IOM uint16_t rx_ctrl_sel_l; /* BT rx control select Reg (0x0B8) */
__IOM uint16_t rx_ctrl_sel_h;
__IOM uint16_t rf_ctrl1_l;
__IOM uint16_t rf_ctrl1_h;
} BT;
} BT_RF_TypeDef;
/* ===========================================================================================================================
*/
/* ================ 2.4G ================ */
/* ===========================================================================================================================
*/
//#define XC62XX
/* RF 2.4G Module Register Typedef */
typedef struct
{
__IOM uint32_t CFG_TOP; /*!< Top-level configuration (0x000) */
__IOM uint32_t EN_AA; /*!< Auto-acknowledgement settings (0x004) */
__IOM uint32_t EN_RXADDR; /*!< Enable RX addresses (0x008) */
__IOM uint32_t SETUP_AW; /*!< Address width & timing stup (0x00C) */
__IOM uint32_t SETUP_RETR; /*!< Automatic retransmission setup (0x010) */
__IOM uint32_t RF_CH; /*!< RF channel (0x014) */
__IOM uint32_t SETUP_RF; /*!< RF settings (0x018) */
__IOM uint32_t STATUS; /*!< Status, SDO output may be adjusted (0x01C) */
__IOM uint32_t OBSERVE_TX; /*!< Transmission observation (0x020) */
__IOM uint32_t RSSI; /*!< TSSI and RSSI indicator/control (0x024) */
__IOM uint32_t RX_ADDR_P0_L; /*!< RX address low 32bit for data pipe 0 (0x028) */
__IOM uint32_t RX_ADDR_P0_H; /*!< RX address high 8bit for data pipe 0 (0x02C) */
__IOM uint32_t RX_ADDR_P1_L; /*!< RX address low 32bit for data pipe 1 (0x030) */
__IOM uint32_t RX_ADDR_P1_H; /*!< RX address high 8bit for data pipe 1 (0x034) */
__IOM uint32_t RX_ADDR_P2TOP5; /*!< Only LSB are set, MSB use RX_ADDR_P1 (0x038) */
__IOM uint32_t BER_RECV_CNT; /*!< Receive total Bit Counter for BER Test (0x03C) */
__IOM uint32_t BER_ERR_CNT; /*!< Receive error Bit Counter for BER Test (0x040) */
__IOM uint32_t AGC_SETTING; /*!< AGC setting (0x044) */
__IOM uint32_t PGA_SETTING; /*!< PGA setting (0x048) */
__IOM uint32_t TX_ADDR_L; /*!< TX address low 32bit (0x04C) */
__IOM uint32_t TX_ADDR_H; /*!< TX address high 8bit (0x050) */
__IOM uint32_t RX_PW_Px_L; /*!< Number of bytes in data pipe0~3 (0x054) */
__IOM uint32_t RX_PW_Px_H; /*!< Number of bytes in data pipe4~5 (0x058) */
__IOM uint32_t ANALOG_CFG0_L; /*!< Analog register 0 low 32bit (0x05C) */
__IOM uint32_t ANALOG_CFG0_H; /*!< Analog register 0 high 32bit (0x060) */
__IOM uint32_t ANALOG_CFG1_L; /*!< Analog register 1 low 32bit (0x064) */
__IOM uint32_t ANALOG_CFG1_H; /*!< Analog register 1 high 32bit (0x068) */
__IOM uint32_t ANALOG_CFG2_L; /*!< Analog register 2 low 32bit (0x06C) */
__IOM uint32_t ANALOG_CFG2_H; /*!< Analog register 2 high 32bit (0x070) */
__IOM uint32_t ANALOG_CFG3_L; /*!< Analog register 3 low 32bit (0x074) */
__IOM uint32_t ANALOG_CFG3_H; /*!< Analog register 3 high 32bit (0x078) */
__IM uint32_t Reserved1; /*!< Reserved1 (0x07C) */
__IOM uint32_t STATUS_FIFO; /*!< FIFO status (0x080) */
__IOM uint32_t RSSIREC; /*!< RSSI recorder feature (0x084) */
__IOM uint32_t TXPROC_CFG; /*!< TX Process configuration (0x088) */
__IOM uint32_t RXPROC_CFG_L; /*!< RX Process configuration (0x08C) */
__IM uint32_t Reserved2; /*!< Reserved2 (0x090) */
__IOM uint32_t DYNPD; /*!< Dynamic payload length (0x094) */
__IOM uint32_t FEATURE; /*!< Features (0x098) */
__IM uint32_t Reserved3[3]; /*!< Reserved3 (0x09C - 0x0A4) */
__IOM uint32_t RXPROC_CFG_H; /*!< PA Ramp Configuration (0x0A8) */
__IOM uint32_t Reserved4; /*!< Reserved4 (0x0AC) */
__IOM uint32_t PREAMBLE; /*!< PREAMBLE (0x0B0) */
__IOM uint32_t GUARD; /*!< PA Ramp Configuration (0x0B4) */
__IM uint32_t Reserved5[2]; /*!< Reserved4 (0x0B8 - 0x0BC) */
__IOM uint32_t CMD_CFG; /*!< Command Configuration (0x0C0) */
__IOM uint32_t TX_FIFO_DATA; /*!< Tx Fifo Data (0x0C4) */
__IOM uint32_t RX_FIFO_DATA; /*!< Rx Fifo Data (0x0C8) */
__IOM uint32_t RX_FIFO_LEN; /*!< Tx Fifo Data Len (0x0CC) */
#ifdef XC62XX
__IOM uint32_t HW_CONFIG; /*!< FIFO256 hardware version (0x0D0) */
__IOM uint32_t PBT_CONFIG; /*!< Pseudo-Bluetooth configuration (0x0D4) */
__IOM uint32_t PBT_TIMER; /*!< Pseudo Bluetooth timer (0x0D8) */
__IOM uint32_t PBT_SYNC_TIME; /*!< Pseudo Bluetooth timer count value (0x0DC) */
__IOM uint32_t PBT_TX_HEAD; /*!< Pseudo bluetooth emission control word (0x0E0) */
__IOM uint32_t PBT_RX_HEAD; /*!< Pseudo Bluetooth receives the control word (0x0E4) */
__IOM uint32_t PBT_AUTO_TRX_TIME; /*!< Pseudo Bluetooth TRX switching time configuration (0x0E8) */
#endif
} RF_2_4G_TypeDef;
#define XC_BT_RF_BASE 0x53021000UL
#define XC_RF_2_4G_BASE 0x53023000UL
#define XC_BT_RF ((BT_RF_TypeDef *)XC_BT_RF_BASE)
#define XC_RF_2_4G ((RF_2_4G_TypeDef *)XC_RF_2_4G_BASE)
#define BLE_COMMON_BASE 0x53022000UL
#define BLE_COMN_RF24G_CTRL ((volatile uint32_t *)(BLE_COMMON_BASE + 0x40))
#define BLE_COMN_CTRL ((volatile uint32_t *)(BLE_COMMON_BASE + 0x44))
#define BLE_COMN_RFVCO_SCALE ((volatile uint32_t *)(BLE_COMMON_BASE + 0x60))
#define BLE_COMN_RFVCO_SOFTCTL ((volatile uint32_t *)(BLE_COMMON_BASE + 0x64))
#endif //__XC_RF_24G_REGISTER_H__
component/rf24/Drivers/xc_rf24g_register/xc_software_crc.c
+136 -145
View File
@@ -1,145 +1,136 @@
#include "xc_software_crc.h"
#include <stdio.h>
/**
* CRC16-CCITT-FALSE 多项式计算
*/
uint16_t crc16_ccitt_false(uint8_t *crc_data, uint8_t data_len)
{
uint16_t crc_shift = 0xFFFF;
uint16_t poly = 0x1021;
for (uint8_t i = 0; i < data_len; i++) {
crc_shift ^= crc_data[i] << 8;
for (uint8_t j = 0; j < 8; j++) {
if (crc_shift & 0x8000)
crc_shift = (crc_shift << 1) ^ poly;
else
crc_shift = crc_shift << 1;
}
}
return crc_shift;
}
/**
* CRC16-CCITT-FALSE 多项式计算（动态包）
*/
uint16_t crc16_ccitt_false_d(uint8_t *crc_data, uint8_t data_len)
{
uint16_t crc_shift = 0xFFFF;
uint16_t poly = 0x1021;
for (uint8_t i = 0; i < data_len - 1; i++) {
printf("%02x ", crc_data[i]);
crc_shift ^= crc_data[i] << 8;
for (uint8_t j = 0; j < 8; j++) {
if (crc_shift & 0x8000)
crc_shift = (crc_shift << 1) ^ poly;
else
crc_shift = crc_shift << 1;
// printf("%04x ", crc_shift);
}
// printf("\r\n");
}
uint8_t i;
crc_shift ^= crc_data[data_len - 1] << 8;
for (i = 0; i < SURPLUS_UNIT; i++) {
if (crc_shift & 0x8000)
crc_shift = (crc_shift << 1) ^ poly;
else
crc_shift = crc_shift << 1;
// printf("%04x\r\n", crc_shift);
}
printf("\r\n");
return crc_shift;
}
/**
CRC 8/ ROHC 多项式计算
*/
uint8_t crc8_rohc(uint8_t *crc_data, uint8_t data_len)
{
uint8_t crc_shift = 0xFF;
for (uint8_t i = 0; i < data_len; i++) {
crc_shift ^= crc_data[i];
for (uint8_t j = 0; j < 8; j++) {
if (crc_shift & 0x01)
crc_shift = (crc_shift >> 1) ^ 0xE0;
else
crc_shift = (crc_shift >> 1);
}
}
return crc_shift;
}
/**
* 数据字节取反
*/
uint8_t bit_negation(uint8_t data)
{
uint8_t temp = 0;
for (uint8_t i = 0; i < 8; i++) {
if ((data >> i) & 0x1)
temp &= ~(0x1 << i);
else
temp |= (0x1 << i);
}
return temp;
}
/* 字节大小端 */
void byte_bigandsmallend(uint8_t data)
{
uint8_t temp_num = data;
data = 0;
for (uint8_t i = 0; i < 8; i++) {
if (temp_num & 0x80)
data |= 1;
data <<= 1;
}
}
/* 数组每字节大小端 */
void buff_bigandsmallend(uint8_t *buff, uint8_t buff_len)
{
for (uint8_t i = 0; i < buff_len; i++) {
byte_bigandsmallend(buff[i]);
}
}
/**
* 数据白化
*/
void whiten_shift(uint8_t *shifter)
{
*shifter = ((*shifter & 0x30) << 1) | (((*shifter & 0x08) << 1) ^ ((*shifter & 0x40) >> 2)) |
(((*shifter) & 0x7) << 1) | ((*shifter & 0x40) >> 6);
}
/**
* 磐启数据白化公式
*/
uint8_t whiten_data(uint8_t *whiten_data_in, uint8_t data_in_len)
{
uint8_t shift_buffer = 0x7F;
uint8_t whiten_data_out[DATA_NUM];
uint8_t whiten_data_code;
for (uint8_t i = 0; i < data_in_len; i++) {
whiten_data_code = 0x00;
for (uint8_t j = 0; j < 8; j++) {
if (j == 0) {
whiten_data_code = ((shift_buffer & 0x40) << 1) | whiten_data_code;
} else if (j == 1) {
whiten_data_code = (shift_buffer & 0x40) | whiten_data_code;
} else {
whiten_data_code = ((shift_buffer & 0x40) >> (j - 1)) | whiten_data_code;
}
whiten_shift(&shift_buffer);
}
whiten_data_out[i] = whiten_data_in[i] ^ whiten_data_code;
printf("%02x ", whiten_data_out[i]);
whiten_data_in[i] = whiten_data_out[i];
}
printf("\r\n");
return shift_buffer;
}
#include "xc_software_crc.h"
#include "xc6xxx.h"
#include <stdio.h>
uint8_t rf_whiten_buff[DATA_NUM] = {0};
/**
* CRC16-CCITT-FALSE 多项式计算
*/
__RAM_CODE uint16_t crc16_ccitt_false(uint8_t *crc_data, uint8_t data_len, uint16_t crc_seed, uint8_t packet_mode)
{
uint16_t crc_shift = crc_seed;
uint16_t poly = 0x1021;
uint8_t data_bit = 0;
for (uint8_t i = 0; i < data_len - 1; i++) {
crc_shift ^= crc_data[i] << 8;
for (uint8_t j = 0; j < 8; j++) {
if (crc_shift & 0x8000)
crc_shift = (crc_shift << 1) ^ poly;
else
crc_shift = crc_shift << 1;
}
}
crc_shift ^= crc_data[data_len - 1] << 8;
if (packet_mode == PACKET_ENHANCED) {
data_bit = SURPLUS_UNIT;
} else if (packet_mode == PACKET_NORMAL) {
data_bit = 8;
}
for (uint8_t i = 0; i < data_bit; i++) {
if (crc_shift & 0x8000)
crc_shift = (crc_shift << 1) ^ poly;
else
crc_shift = crc_shift << 1;
}
return crc_shift;
}
/**
* CRC8-ROHC 多项式计算
*/
__RAM_CODE uint8_t crc8_rohc(const uint8_t *data, uint8_t length, uint16_t crc_seed, uint8_t packet_mode)
{
uint8_t crc = crc_seed;
for (uint8_t i = 0; i < length; i++) {
crc ^= (uint8_t)data[i];
for (int j = 0; j < 8; j++) {
if (crc & 0x80) {
crc = (crc << 1) ^ 0x07;
} else {
crc <<= 1;
}
if (packet_mode == PACKET_ENHANCED) {
if (i >= length - 1) {
break;
}
}
}
}
return crc;
}
/**
* 数据取反
*/
__RAM_CODE uint16_t bit_negation(uint16_t data, uint8_t data_bit)
{
uint16_t temp = 0;
for (uint8_t i = 0; i < data_bit; i++) {
if ((data >> i) & 0x1)
temp &= ~(0x1 << i);
else
temp |= (0x1 << i);
}
return temp;
}
/* 字节反序 */
__RAM_CODE uint8_t byte_bigandsmallend(uint8_t data)
{
uint8_t temp = 0x00;
for (uint8_t i = 0; i < 8; i++) {
temp = ((data >> i) & 0x01) | temp;
if (i < 7) {
temp = temp << 1;
}
}
return temp;
}
/* 数组字节反序 */
__RAM_CODE void buff_bigandsmallend(uint8_t *buff, uint8_t buff_len)
{
for (uint8_t i = 0; i < buff_len; i++) {
buff[i] = byte_bigandsmallend(buff[i]);
}
}
/**
* 数据白化
*/
__RAM_CODE void whiten_shift(uint8_t *shifter)
{
*shifter = ((*shifter & 0x30) << 1) | (((*shifter & 0x08) << 1) ^ ((*shifter & 0x40) >> 2)) |
(((*shifter) & 0x7) << 1) | ((*shifter & 0x40) >> 6);
}
/**
* 磐启数据白化公式
*/
__RAM_CODE uint8_t whiten_data(uint8_t *whiten_data_in, uint8_t data_in_len, uint8_t shifer_init)
{
uint8_t shift_buffer = shifer_init;
uint8_t whiten_data_out[DATA_NUM];
uint8_t whiten_data_code;
for (uint8_t i = 0; i < data_in_len; i++) {
whiten_data_code = 0x00;
for (uint8_t j = 0; j < 8; j++) {
if (j == 0) {
whiten_data_code = ((shift_buffer & 0x40) << 1) | whiten_data_code;
} else if (j == 1) {
whiten_data_code = (shift_buffer & 0x40) | whiten_data_code;
} else {
whiten_data_code = ((shift_buffer & 0x40) >> (j - 1)) | whiten_data_code;
}
whiten_shift(&shift_buffer);
}
whiten_data_out[i] = whiten_data_in[i] ^ whiten_data_code;
whiten_data_in[i] = whiten_data_out[i];
}
return shift_buffer;
}
component/rf24/Drivers/xc_rf24g_register/xc_software_crc.h
+50 -49
View File
@@ -1,49 +1,50 @@
#ifndef __XC_SOFTWARE_CRC_H__
#define __XC_SOFTWARE_CRC_H__
#include <stdint.h>
#define TELINK_MODE
#define SUPPLEMENTARY_DATA 0x50
#ifdef TELINK_MODE
#define SURPLUS_UNIT 1
#define NUMBER 0x1
#endif
#ifdef BEKEN_MODE
#define SURPLUS_UNIT 1
#define NUMBER 0x1
#endif
#ifdef PANCHIP_MODE
#define SURPLUS_UNIT 2
#define NUMBER 0x3
#endif
typedef struct
{
uint8_t preamble[3];
uint8_t addr_buff[5];
uint16_t contorl;
uint8_t data_buff[32];
uint8_t crc_data[2];
} packet_t;
typedef struct
{
packet_t packt;
uint8_t crc_dat[64];
} sf_crc_t;
#define DATA_NUM 32
uint16_t crc16_ccitt_false(uint8_t *crc_data, uint8_t data_len);
uint16_t crc16_ccitt_false_d(uint8_t *crc_data, uint8_t data_len);
uint8_t crc8_rohc(uint8_t *crc_data, uint8_t data_len);
uint8_t bit_negation(uint8_t data);
void byte_bigandsmallend(uint8_t data);
void buff_bigandsmallend(uint8_t *buff, uint8_t buff_len);
void whiten_shift(uint8_t *shifter);
uint8_t whiten_data(uint8_t *whiten_data_in, uint8_t data_in_len);
#endif //__XC_SOFTWARE_CRC_H__
#ifndef __XC_SOFTWARE_CRC_H__
#define __XC_SOFTWARE_CRC_H__
#include "rf_config.h"
#include <stdint.h>
#if (XINCX_RF_COMPATIBILITY_MODE == 1)
#define PANCHIP_MODE
#elif (XINCX_RF_COMPATIBILITY_MODE == 2)
#define BEKEN_MODE
#elif (XINCX_RF_COMPATIBILITY_MODE ==3)
#define TELINK_MODE
#else
#define HUNTERSUN_MODE
#endif
#define PACKET_NORMAL 0
#define PACKET_ENHANCED 1
#define SUPPLEMENTARY_DATA 0x50
#ifdef TELINK_MODE
#define SURPLUS_UNIT 1
#define NUMBER 0x1
#endif
#ifdef BEKEN_MODE
#define SURPLUS_UNIT 1
#define NUMBER 0x1
#endif
#ifdef PANCHIP_MODE
#define SURPLUS_UNIT 2
#define NUMBER 0x3
#endif
#ifndef SURPLUS_UNIT
#define SURPLUS_UNIT 1
#endif
#define DATA_NUM (64) // 32
extern uint8_t rf_whiten_buff[DATA_NUM];
uint16_t crc16_ccitt_false(uint8_t *crc_data, uint8_t data_len, uint16_t crc_seed, uint8_t packet_mode);
uint8_t crc8_rohc(const uint8_t *data, uint8_t length, uint16_t crc_seed, uint8_t packet_mode);
uint16_t bit_negation(uint16_t data, uint8_t data_bit);
uint8_t byte_bigandsmallend(uint8_t data);
void buff_bigandsmallend(uint8_t *buff, uint8_t buff_len);
void whiten_shift(uint8_t *shifter);
uint8_t whiten_data(uint8_t *whiten_data_in, uint8_t data_in_len, uint8_t shifer_init);
#endif //__XC_SOFTWARE_CRC_H__