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Stair56E UART project

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This commit is contained in:
吴琪
2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc20xx.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc26xx.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc60xx.h
+1323 -1323
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc62xx.h
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/*!
* \file xc62xx.h
*
* \brief The header of xc62xx chip
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC62XX_H__
#define __XC62XX_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __RAM_CODE __attribute__((section("ram_code")))
#define __WEAK __attribute__((weak))
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#define __STATIC_INLINE static __inline
#define FMC_SPI_DMA_OFF
#define SPI_OFF
#define SPI_DMA_OFF
#define UART_DMA_OFF
#define QDEC_USE_P12_P13
#define HFCLK_SRC_XTAL_IS_32M
#define XC62XX_CLOCK_CONFIG
#define XC62XX_ROM_DRIVER_ADDR
#define XC62XX_ADC_CALI_PARA
#define XC62XX_ADC_CHANNEL
#define BOR_VERSION_IS_V2
#define NO_SUPPORT_UART2
#define NO_SUPPORT_HFCLK_RC_16M
#define NO_SUPPORT_HFCLK_BBPLL_96M
#define NO_SUPPORT_HFCLK_BBPLL_128M
#define NO_SUPPORT_LFCLK_XTAL_32768
#define NO_SUPPORT_PWM_CAPTURE
#define NO_SUPPORT_PWM_ADC
#define NO_SUPPORT_PWM_BRAKE
#define NO_SUPPORT_PWM_LOWPOWER
#define NO_SUPPORT_DMA
#define NO_SUPPORT_DMA_LINKLIST
#define NO_SUPPORT_QUAD_SPI
#define NO_SUPPORT_M4FPU_FUNTION
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/****** Device Specific Interrupt Numbers ********************************************************/
/* ToDo: add here your device specific external interrupt numbers
according the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
BLE_IRQn = 0, /*!< Device Interrupt */
CPR_IRQn = 2,
GPIO_IRQn = 3,
RTC_IRQn = 4,
TIMER0_IRQn = 5,
TIMER1_IRQn = 6,
TIMER2_IRQn = 7,
TIMER3_IRQn = 8,
WDT_IRQn = 9,
I2C_IRQn = 10,
UART0_IRQn = 11,
UART1_IRQn = 12,
SPI0_IRQn = 13,
KBS_IRQn = 15,
QDEC_IRQn = 16,
GADC_IRQn = 17,
PWM_IRQn = 18,
AES_IRQn = 19,
USB_IRQn = 20,
AUDIO_IRQn = 21,
RF24G_IRQn = 22,
MPU_IRQn = 24,
I2S_IRQn = 26,
TIMER_AO0_IRQn = 27,
TIMER_AO1_IRQn = 28,
CMP_IRQn = 29,
FMC_IRQn = 30,
CAN_IRQn = 31
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
/* ToDo: set the defines according your Device */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#define __FPU_PRESENT 1 /*!< FPU present or not */
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
/*@}*/ /* end of group <Device>_CMSIS */
#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __XC62XX_H__ */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc65xx.h
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/*!
* \file xc65xx.h
*
* \brief The header of xc65xx chip
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC65XX_H__
#define __XC65XX_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __RAM_CODE __attribute__((section("ram_code")))
#define __WEAK __attribute__((weak))
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#define __STATIC_INLINE static __inline
#define QDEC_USE_P20_P21
#define HFCLK_SRC_XTAL_IS_32M
#define NO_SUPPORT_ROM_FMC_SPI
#define NO_SUPPORT_DMA_LINKLIST
#define NO_SUPPORT_QUAD_SPI
#define NO_SUPPORT_M4FPU_FUNTION
#define NO_SUPPORT_HFCLK_BBPLL_128M
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M4 device */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/****** Device Specific Interrupt Numbers ********************************************************/
/* ToDo: add here your device specific external interrupt numbers
according the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
BLE_IRQn = 0, /*!< Device Interrupt */
DMA_IRQn = 1,
CPR_IRQn = 2,
GPIO_IRQn = 3,
RTC_IRQn = 4,
TIMER0_IRQn = 5,
TIMER1_IRQn = 6,
TIMER2_IRQn = 7,
TIMER3_IRQn = 8,
WDT_IRQn = 9,
I2C_IRQn = 10,
UART0_IRQn = 11,
UART1_IRQn = 12,
SPI0_IRQn = 13,
SPI1_IRQn = 14,
KBS_IRQn = 15,
QDEC_IRQn = 16,
GADC_IRQn = 17,
PWM_IRQn = 18,
AES_IRQn = 19,
USB_IRQn = 20,
AUDIO_IRQn = 21,
RF24G_IRQn = 22,
SPI2_IRQn = 23,
MPU_IRQn = 24,
UART2_IRQn = 25,
I2S_IRQn = 26,
TIMER_AO0_IRQn = 27,
TIMER_AO1_IRQn = 28,
CMP_IRQn = 29,
FMC_IRQn = 30,
CAN_IRQn = 31
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
/* ToDo: set the defines according your Device */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#define __FPU_PRESENT 1 /*!< FPU present or not */
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
/*@}*/ /* end of group <Device>_CMSIS */
#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __XC65XX_H__ */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc6axx.h
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/*!
* \file xc6axx.h
*
* \brief The header of xc6axx chip
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6AXX_H__
#define __XC6AXX_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __RAM_CODE __attribute__((section("ram_code")))
#define __WEAK __attribute__((weak))
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#define __STATIC_INLINE static __inline
#define QDEC_USE_P20_P21
#define HFCLK_SRC_XTAL_IS_24M
#define XC6AXX_TEST_CODE
#define NEW_BLE_COMMON_BASE
#define XC6AXX_ROM_DRIVER_ADDR
#define NO_SUPPORT_ROM_FMC_SPI
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/* ------------------- Processor Exceptions Numbers ----------------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ------------------- Processor Interrupt Numbers ------------------------------ */
BLE_IRQn = 0, /*!< Device Interrupt */
DMA_IRQn = 1,
CPR_IRQn = 2,
GPIO_IRQn = 3,
RTC_IRQn = 4,
TIMER0_IRQn = 5,
TIMER1_IRQn = 6,
TIMER2_IRQn = 7,
TIMER3_IRQn = 8,
WDT_IRQn = 9,
I2C_IRQn = 10,
UART0_IRQn = 11,
UART1_IRQn = 12,
SPI0_IRQn = 13,
SPI1_IRQn = 14,
KBS_IRQn = 15,
QDEC_IRQn = 16,
GADC_IRQn = 17,
PWM_IRQn = 18,
AES_IRQn = 19,
USB_IRQn = 20,
CDC_IRQn = 21,
RF24G_IRQn = 22,
SPI2_IRQn = 23,
FPU_IRQn = 24,
UART2_IRQn = 25,
I2S_IRQn = 26,
TIMER_AO0_IRQn = 27,
TIMER_AO1_IRQn = 28,
CMP_IRQn = 29,
FMC_IRQn = 30,
CAN_IRQn = 31,
BT_IRQn = 32,
BT_DM_IRQn = 33,
BT_DBM_IRQn = 34,
UNUSED_IRQn
/* Interrupts 46 .. 63 are left out */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M# Processor and Core Peripherals */
/* ToDo: set the defines according your Device */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#define __FPU_PRESENT 1 /*!< FPU present or not */
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
#else
#define __FPU_PRESENT 0 /*!< FPU present or not */
#endif
/*@}*/ /* end of group <Device>_CMSIS */
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "compiler.h"
/* =========================================================================================================================== */
/* ================ QDEC ================ */
/* =========================================================================================================================== */
/**
* @brief Quadrature Decoder (QDEC)
*/
typedef struct { /*!< (@ 0x40016000UL) QDEC Structure */
__IOM uint32_t QDEC_CTL; /*!< (@ 0x00000000) QDEC Control Register */
__IOM uint32_t SAMP_CTL; /*!< (@ 0x00000004) QDEC Sample Control Register */
__IM uint32_t SAMPLE; /*!< (@ 0x00000008) QDEC Sample State Register */
__IM uint32_t ACC; /*!< (@ 0x0000000C) QDEC Acc Counter Now Register */
__IM uint32_t ACC_R; /*!< (@ 0x00000010) QDEC Acc Counter Record Register */
__IM uint32_t DB; /*!< (@ 0x00000014) QDEC Double Bounce Counter Now Register */
__IM uint32_t DB_R; /*!< (@ 0x00000018) QDEC Double Bounce Counter Record Register */
__IOM uint32_t INT; /*!< (@ 0x0000001C) QDEC Interrupt Register */
__IOM uint32_t INT_MSK; /*!< (@ 0x00000020) QDEC Interrupt Mask Register */
__IM uint32_t QDEC_STAT; /*!< (@ 0x00000024) QDEC Counter Busy State Register */
} QDEC_TypeDef;
/* =========================================================================================================================== */
/* ================ 2.4G ================ */
/* =========================================================================================================================== */
/* RF 2.4G Module Register Typedef */
typedef struct {
__IOM uint32_t CFG_TOP; /*!< Top-level configuration (0x000) */
__IOM uint32_t EN_AA; /*!< Auto-acknowledgement settings (0x004) */
__IOM uint32_t EN_RXADDR; /*!< Enable RX addresses (0x008) */
__IOM uint32_t SETUP_AW; /*!< Address width & timing stup (0x00C) */
__IOM uint32_t SETUP_RETR; /*!< Automatic retransmission setup (0x010) */
__IOM uint32_t RF_CH; /*!< RF channel (0x014) */
__IOM uint32_t SETUP_RF; /*!< RF settings (0x018) */
__IOM uint32_t STATUS; /*!< Status, SDO output may be adjusted (0x01C) */
__IOM uint32_t OBSERVE_TX; /*!< Transmission observation (0x020) */
__IOM uint32_t RSSI; /*!< TSSI and RSSI indicator/control (0x024) */
__IOM uint32_t RX_ADDR_P0_L; /*!< RX address low 32bit for data pipe 0 (0x028) */
__IOM uint32_t RX_ADDR_P0_H; /*!< RX address high 8bit for data pipe 0 (0x02C) */
__IOM uint32_t RX_ADDR_P1_L; /*!< RX address low 32bit for data pipe 1 (0x030) */
__IOM uint32_t RX_ADDR_P1_H; /*!< RX address high 8bit for data pipe 1 (0x034) */
__IOM uint32_t RX_ADDR_P2TOP5; /*!< Only LSB are set, MSB use RX_ADDR_P1 (0x038) */
__IOM uint32_t BER_RECV_CNT; /*!< Receive total Bit Counter for BER Test (0x03C) */
__IOM uint32_t BER_ERR_CNT; /*!< Receive error Bit Counter for BER Test (0x040) */
__IOM uint32_t AGC_SETTING; /*!< AGC setting (0x044) */
__IOM uint32_t PGA_SETTING; /*!< PGA setting (0x048) */
__IOM uint32_t TX_ADDR_L; /*!< TX address low 32bit (0x04C) */
__IOM uint32_t TX_ADDR_H; /*!< TX address high 8bit (0x050) */
__IOM uint32_t RX_PW_Px_L; /*!< Number of bytes in data pipe0~3 (0x054) */
__IOM uint32_t RX_PW_Px_H; /*!< Number of bytes in data pipe4~5 (0x058) */
__IOM uint32_t ANALOG_CFG0_L; /*!< Analog register 0 low 32bit (0x05C) */
__IOM uint32_t ANALOG_CFG0_H; /*!< Analog register 0 high 32bit (0x060) */
__IOM uint32_t ANALOG_CFG1_L; /*!< Analog register 1 low 32bit (0x064) */
__IOM uint32_t ANALOG_CFG1_H; /*!< Analog register 1 high 32bit (0x068) */
__IOM uint32_t ANALOG_CFG2_L; /*!< Analog register 2 low 32bit (0x06C) */
__IOM uint32_t ANALOG_CFG2_H; /*!< Analog register 2 high 32bit (0x070) */
__IOM uint32_t ANALOG_CFG3_L; /*!< Analog register 3 low 32bit (0x074) */
__IOM uint32_t ANALOG_CFG3_H; /*!< Analog register 3 high 32bit (0x078) */
__IM uint32_t Reserved1; /*!< Reserved1 (0x07C) */
__IOM uint32_t STATUS_FIFO; /*!< FIFO status (0x080) */
__IOM uint32_t RSSIREC; /*!< RSSI recorder feature (0x084) */
__IOM uint32_t TXPROC_CFG; /*!< TX Process configuration (0x088) */
__IOM uint32_t RXPROC_CFG_L; /*!< RX Process configuration (0x08C) */
__IM uint32_t Reserved2; /*!< Reserved2 (0x090) */
__IOM uint32_t DYNPD; /*!< Dynamic payload length (0x094) */
__IOM uint32_t FEATURE; /*!< Features (0x098) */
__IM uint32_t Reserved3[3]; /*!< Reserved3 (0x09C - 0x0A4) */
__IOM uint32_t RXPROC_CFG_H; /*!< PA Ramp Configuration (0x0A8) */
__IM uint32_t Reserved4[5]; /*!< Reserved4 (0x0AC - 0x0BC) */
__IOM uint32_t CMD_CFG; /*!< Command Configuration (0x0C0) */
__IOM uint32_t TX_FIFO_DATA; /*!< Tx Fifo Data (0x0C4) */
__IOM uint32_t RX_FIFO_DATA; /*!< Rx Fifo Data (0x0C8) */
__IOM uint32_t RX_FIFO_LEN; /*!< Tx Fifo Data Len (0x0CC) */
} RF_2_4G_TypeDef;
#ifdef __cplusplus
}
#endif
#endif /* __XC6AXX_H__ */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc6xxx.h
+281 -257
View File
@@ -1,257 +1,281 @@
/*!
* \file xc6xxx.h
*
* \brief CMSIS xc6xxx Device Peripheral Access Layer Header File.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6xxx_H
#define __XC6xxx_H
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
/** @addtogroup Device_Included
* @{
*/
#if defined(XC60XX)
#include "xc60xx.h"
#elif defined(XC_LORA_XX)
#include "xc_lora_xx.h"
#else
#error \
"Please select first the target XC6xxx device used in your application (in xc6xxx.h file)"
#endif
/**
* @}
*/
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
XR_OK = 0,
XR_ERROR,
XR_TIMEOUT,
XR_UNKNOWN = 0xFF,
} eXC_RESULT;
/**
* @}
*/
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/** @addtogroup Exported_macro
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define REG_BIT_VAL_GET(REG, MSK, POS) ((REG & MSK) >> POS)
#define BIT_BUILD(VAL, POS, MSK) ((uint32_t)(((VAL) << POS) & MSK))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) < (b) ? (b) : (a))
// power of 2 macro
#define POW2(pow) (1 << (pow))
// Is A greater than or equal to B macro ?
#define A_MAXEQ_B(a, b) ((a) >= (b))
#define ALIGN_DOWN_ADDR(a, size) (a & (~(size - 1)))
#define ALIGN_UP_ADDR(a, size) ((a + size - 1) & (~(size - 1)))
#ifdef DEBUG_ENABLE
#define DEBUG(fmt, ...) printf(fmt, ##__VA_ARGS__)//printf("[DEBUG] " fmt, ##__VA_ARGS__)
#define PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
#else
#define DEBUG(fmt, ...)
#define PRINT(fmt, ...)
#endif
#define RSTN_VALID (0UL)
#define RSTN_INVALID (1UL)
#ifndef ENABLE
#define ENABLE 0x01
#endif
#ifndef DISABLE
#define DISABLE 0x00
#endif
#ifndef RSTCTL_ENABLE
#define RSTCTL_ENABLE 0x00
#endif
#ifndef RSTCTL_DISABLE
#define RSTCTL_DISABLE 0x01
#endif
#ifndef ASSERT_ERR
#define ASSERT_ERR(cond) \
{ \
}
#endif
/** @brief Enable interrupts globally in the system.
* This macro must be used when the initialization phase is over and the interrupts
* can start being handled by the system.
*/
#define GLOBAL_INT_START() ; \
do { \
__enable_irq(); \
} while(0);
#define GLOBAL_INT_STOP() ; \
do { \
__disable_irq(); \
} while(0);
#define GLOBAL_INT_DISABLE() ; \
do { \
uint32_t irq_temp; \
irq_temp = __disable_irq();
#define GLOBAL_INT_RESTORE() ; \
if(!irq_temp) \
{ \
__enable_irq(); \
} \
} while(0);
/**
* @}
*/
#include "xc_drv_conf.h"
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_Delay delay_ms
void HAL_Delay(unsigned int Delay);
void Error_Handler(void);
#define __HAL_LOCK(__HANDLE__) \
do { \
if ((__HANDLE__)->Lock == HAL_LOCKED) { \
return HAL_BUSY; \
} else { \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
} while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do { \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
} while (0U)
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive
* "#pragma data_alignment=4" must be used instead */
#if defined(__ARMCC_VERSION) && \
(__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif
#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined(__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* __XC6xxx_H */
/*!
* \file xc6xxx.h
*
* \brief CMSIS xc6xxx Device Peripheral Access Layer Header File.
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XC6xxx_H
#define __XC6xxx_H
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
/** @addtogroup Device_Included
* @{
*/
#if defined(XC65XX)
#include "xc65xx.h"
#elif defined(XC62XX)
#include "xc62xx.h"
#elif defined(XC6AXX)
#include "xc6axx.h"
#elif defined(XC20XX)
#include "xc20xx.h"
#elif defined(XC26XX)
#include "xc26xx.h"
#elif defined(XC_LORA_XX)
#include "xc_lora_xx.h"
#else
#error "Please select first the target XC6xxx device used in your application (in xc6xxx.h file)"
#endif
#include "xc_drv_config.h"
/**
* @}
*/
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
XR_OK = 0,
XR_ERROR,
XR_TIMEOUT,
XR_UNKNOWN = 0xFF,
} eXC_RESULT;
/**
* @}
*/
extern __RAM_CODE int sendchar(int c);
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/** @addtogroup Exported_macro
* @{
*/
#define GD_FlASH_RDID 0x1364c8
#define BIT(n) ((1UL << (n)))
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define REG_BIT_VAL_GET(REG, MSK, POS) ((REG & MSK) >> POS)
#define BIT_BUILD(VAL, POS, MSK) ((uint32_t)(((VAL) << POS) & MSK))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) < (b) ? (b) : (a))
// power of 2 macro
#define POW2(pow) (1 << (pow))
// Is A greater than or equal to B macro ?
#define A_MAXEQ_B(a, b) ((a) >= (b))
#define ALIGN_DOWN_ADDR(a, size) (a & (~(size - 1)))
#define ALIGN_UP_ADDR(a, size) ((a + size - 1) & (~(size - 1)))
#if ((defined(DEBUG_ENABLE) && (DEBUG_ENABLE != 1)) || (!defined(DEBUG_ENABLE)))
#define DEBUG_ENABLE 0
#else
#define DEBUG_ENABLE 1
#endif
#if (DEBUG_ENABLE == 1)
#define DEBUG(fmt, ...) printf(fmt, ##__VA_ARGS__)
#define PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
#define RAM_DEBUG(str) \
{ \
const char* s = (str); \
while (*s) { \
sendchar(*s++); \
} \
}
#else
#define DEBUG(fmt, ...)
#define PRINT(fmt, ...)
#define RAM_DEBUG(str)
#endif
#define RSTN_VALID (0UL)
#define RSTN_INVALID (1UL)
#ifndef ENABLE
#define ENABLE 0x01
#endif
#ifndef DISABLE
#define DISABLE 0x00
#endif
#ifndef RSTCTL_ENABLE
#define RSTCTL_ENABLE 0x00
#endif
#ifndef RSTCTL_DISABLE
#define RSTCTL_DISABLE 0x01
#endif
#ifndef ASSERT_ERR
#define ASSERT_ERR(cond) \
{ \
}
#endif
/** @brief Enable interrupts globally in the system.
* This macro must be used when the initialization phase is over and the interrupts
* can start being handled by the system.
*/
#define GLOBAL_INT_START() ; \
do { \
__enable_irq(); \
} while(0);
#define GLOBAL_INT_STOP() ; \
do { \
__disable_irq(); \
} while(0);
#define GLOBAL_INT_DISABLE() ; \
do { \
uint32_t irq_temp; \
irq_temp = __disable_irq();
#define GLOBAL_INT_RESTORE() ; \
if(!irq_temp) \
{ \
__enable_irq(); \
} \
} while(0);
/**
* @}
*/
#include "xc_drv_conf.h"
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_Delay delay_ms
void HAL_Delay(unsigned int Delay);
void Error_Handler(void);
#define __HAL_LOCK(__HANDLE__) \
do { \
if ((__HANDLE__)->Lock == HAL_LOCKED) { \
return HAL_BUSY; \
} else { \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
} while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do { \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
} while (0U)
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive
* "#pragma data_alignment=4" must be used instead */
#if defined(__ARMCC_VERSION) && \
(__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif
#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined(__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* __XCxxxx_H */
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_lora_xx.h
+1041 -1041
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File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_adc.h
+1273 -807
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File diff suppressed because it is too large Load Diff
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_aotimer.h
+208 -208
View File
@@ -1,208 +1,208 @@
#ifndef _XC_REG_AOTIMER_H_
#define _XC_REG_AOTIMER_H_
#include <stdint.h>
#include "xc6xxx.h"
#define XC_REG_AOTIMER_BASE_ADDR 0x40002800
#define XC_REG_AOTIMER_DECODING_MASK 0x0000001F
/**
* @brief AOTIMER_TLC register definition
*/
#define AOTIMER_TLC_REG(i) (*(volatile uint32_t *)(0x40002800 + aotimer_offset[i]))
#define AOTIMER_TLC_ADDR(i) (0x40002800 + aotimer_offset[i])
#define AOTIMER_TLC_OFFSET 0x00000000
__INLINE uint32_t aotimer_tlc_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TLC_REG(reg_idx);
}
__INLINE void aotimer_tlc_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
AOTIMER_TLC_REG(reg_idx) = value;
}
/**
* @brief AOTIMER_TCV register definition
*/
#define AOTIMER_TCV_REG(i) (*(volatile uint32_t *)(0x40002804 + aotimer_offset[i]))
#define AOTIMER_TCV_ADDR(i) (0x40002804 + aotimer_offset[i])
#define AOTIMER_TCV_OFFSET 0x00000004
__INLINE uint32_t aotimer_tcv_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TCV_REG(reg_idx);
}
/**
* @brief AOTIMER_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 TIM 0
* 01 TMS 0
* 00 TES 0
* </pre>
*/
#define AOTIMER_TCR_REG(i) (*(volatile uint32_t *)(0x40002808 + aotimer_offset[i]))
#define AOTIMER_TCR_ADDR(i) (0x40002808 + aotimer_offset[i])
#define AOTIMER_TCR_OFFSET 0x00000008
__INLINE uint32_t aotimer_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TCR_REG(reg_idx);
}
__INLINE void aotimer_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
AOTIMER_TCR_REG(reg_idx) = value;
}
// field definitions
#define TIM_BIT 0x00000004
#define TIM_POS 2
#define TMS_BIT 0x00000002
#define TMS_POS 1
#define TES_BIT 0x00000001
#define TES_POS 0
#define TIM_RST 0x0
#define TMS_RST 0x0
#define TES_RST 0x0
__INLINE void aotimer_tcr_pack(uint32_t reg_idx, uint8_t tim, uint8_t tms, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
AOTIMER_TCR_REG(reg_idx) = (tim << 2) | (tms << 1) | (tes << 0);
}
__INLINE void aotimer_tcr_unpack(uint32_t reg_idx, uint8_t* tim, uint8_t* tms, uint8_t* tes)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
*tim = (localVal & 0x00000004) >> 2;
*tms = (localVal & 0x00000002) >> 1;
*tes = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t aotimer_tcr__tim__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void aotimer_tcr__tim__setf(uint32_t reg_idx, uint8_t tim)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000004) | (tim << 2);
}
__INLINE uint8_t aotimer_tcr__tms__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void aotimer_tcr__tms__setf(uint32_t reg_idx, uint8_t tms)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000002) | (tms << 1);
}
__INLINE uint8_t aotimer_tcr__tes__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void aotimer_tcr__tes__setf(uint32_t reg_idx, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000001) | (tes << 0);
}
/**
* @brief AOTIMER_TIC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 TIC 0
* </pre>
*/
#define AOTIMER_TIC_REG(i) (*(volatile uint32_t *)(0x4000280C + aotimer_offset[i]))
#define AOTIMER_TIC_ADDR(i) (0x4000280C + aotimer_offset[i])
#define AOTIMER_TIC_OFFSET 0x0000000C
__INLINE uint32_t aotimer_tic_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TIC_REG(reg_idx);
}
// field definitions
#define TIC_BIT 0x00000001
#define TIC_POS 0
#define TIC_RST 0x0
__INLINE uint8_t aotimer_tic__tic__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TIC_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief AOTIMER_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 TIS 0
* </pre>
*/
#define AOTIMER_TIS_REG(i) (*(volatile uint32_t *)(0x40002810 + aotimer_offset[i]))
#define AOTIMER_TIS_ADDR(i) (0x40002810 + aotimer_offset[i])
#define AOTIMER_TIS_OFFSET 0x00000010
__INLINE uint32_t aotimer_tis_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TIS_REG(reg_idx);
}
// field definitions
#define TIS_BIT 0x00000001
#define TIS_POS 0
#define TIS_RST 0x0
__INLINE uint8_t aotimer_tis__tis__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TIS_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_AOTIMER_H_
#ifndef _XC_REG_AOTIMER_H_
#define _XC_REG_AOTIMER_H_
#include <stdint.h>
#include "xc6xxx.h"
#define XC_REG_AOTIMER_BASE_ADDR 0x40002800
#define XC_REG_AOTIMER_DECODING_MASK 0x0000001F
/**
* @brief AOTIMER_TLC register definition
*/
#define AOTIMER_TLC_REG(i) (*(volatile uint32_t *)(0x40002800 + aotimer_offset[i]))
#define AOTIMER_TLC_ADDR(i) (0x40002800 + aotimer_offset[i])
#define AOTIMER_TLC_OFFSET 0x00000000
__INLINE uint32_t aotimer_tlc_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TLC_REG(reg_idx);
}
__INLINE void aotimer_tlc_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
AOTIMER_TLC_REG(reg_idx) = value;
}
/**
* @brief AOTIMER_TCV register definition
*/
#define AOTIMER_TCV_REG(i) (*(volatile uint32_t *)(0x40002804 + aotimer_offset[i]))
#define AOTIMER_TCV_ADDR(i) (0x40002804 + aotimer_offset[i])
#define AOTIMER_TCV_OFFSET 0x00000004
__INLINE uint32_t aotimer_tcv_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TCV_REG(reg_idx);
}
/**
* @brief AOTIMER_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 TIM 0
* 01 TMS 0
* 00 TES 0
* </pre>
*/
#define AOTIMER_TCR_REG(i) (*(volatile uint32_t *)(0x40002808 + aotimer_offset[i]))
#define AOTIMER_TCR_ADDR(i) (0x40002808 + aotimer_offset[i])
#define AOTIMER_TCR_OFFSET 0x00000008
__INLINE uint32_t aotimer_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TCR_REG(reg_idx);
}
__INLINE void aotimer_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
AOTIMER_TCR_REG(reg_idx) = value;
}
// field definitions
#define TIM_BIT 0x00000004
#define TIM_POS 2
#define TMS_BIT 0x00000002
#define TMS_POS 1
#define TES_BIT 0x00000001
#define TES_POS 0
#define TIM_RST 0x0
#define TMS_RST 0x0
#define TES_RST 0x0
__INLINE void aotimer_tcr_pack(uint32_t reg_idx, uint8_t tim, uint8_t tms, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
AOTIMER_TCR_REG(reg_idx) = (tim << 2) | (tms << 1) | (tes << 0);
}
__INLINE void aotimer_tcr_unpack(uint32_t reg_idx, uint8_t* tim, uint8_t* tms, uint8_t* tes)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
*tim = (localVal & 0x00000004) >> 2;
*tms = (localVal & 0x00000002) >> 1;
*tes = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t aotimer_tcr__tim__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void aotimer_tcr__tim__setf(uint32_t reg_idx, uint8_t tim)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000004) | (tim << 2);
}
__INLINE uint8_t aotimer_tcr__tms__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void aotimer_tcr__tms__setf(uint32_t reg_idx, uint8_t tms)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000002) | (tms << 1);
}
__INLINE uint8_t aotimer_tcr__tes__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void aotimer_tcr__tes__setf(uint32_t reg_idx, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 1);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
AOTIMER_TCR_REG(reg_idx) = (AOTIMER_TCR_REG(reg_idx) & ~0x00000001) | (tes << 0);
}
/**
* @brief AOTIMER_TIC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 TIC 0
* </pre>
*/
#define AOTIMER_TIC_REG(i) (*(volatile uint32_t *)(0x4000280C + aotimer_offset[i]))
#define AOTIMER_TIC_ADDR(i) (0x4000280C + aotimer_offset[i])
#define AOTIMER_TIC_OFFSET 0x0000000C
__INLINE uint32_t aotimer_tic_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TIC_REG(reg_idx);
}
// field definitions
#define TIC_BIT 0x00000001
#define TIC_POS 0
#define TIC_RST 0x0
__INLINE uint8_t aotimer_tic__tic__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TIC_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief AOTIMER_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 TIS 0
* </pre>
*/
#define AOTIMER_TIS_REG(i) (*(volatile uint32_t *)(0x40002810 + aotimer_offset[i]))
#define AOTIMER_TIS_ADDR(i) (0x40002810 + aotimer_offset[i])
#define AOTIMER_TIS_OFFSET 0x00000010
__INLINE uint32_t aotimer_tis_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return AOTIMER_TIS_REG(reg_idx);
}
// field definitions
#define TIS_BIT 0x00000001
#define TIS_POS 0
#define TIS_RST 0x0
__INLINE uint8_t aotimer_tis__tis__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
uint32_t localVal = AOTIMER_TIS_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_AOTIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_cdc.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_cpr.h
+7019 -7019
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_cprao.h
+2474 -2474
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_dma.h
+4406 -4406
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_fmc.h
+2269 -2269
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_fmc_cache.h
+541 -541
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_gpio.h
+655 -655
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_i2c.h
+2000 -2000
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_i2s.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_offset.h
+67 -67
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@@ -1,67 +1,67 @@
/*!
* \file xc_reg_offset.h
*
* \brief The header of xc registers offset index
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
#ifndef _XC_REG_OFFSET_H_
#define _XC_REG_OFFSET_H_
#define AOTIMER0_IDX 0U
#define AOTIMER1_IDX 1U
// #define AOTIMER_OFFSET {0x00, 0x14}
#define TIMER0_IDX 0U
#define TIMER1_IDX 1U
#define TIMER2_IDX 2U
#define TIMER3_IDX 3U
#define PWM0_IDX 0U
#define PWM1_IDX 1U
#define PWM2_IDX 2U
#define PWM3_IDX 3U
#define PWM4_IDX 4U
#define PWM5_IDX 5U
#define UART0_IDX (uint8_t)0U
#define UART1_IDX (uint8_t)1U
#define UART2_IDX (uint8_t)2U
#define PWM_TIMER0_IDX 0U
#define PWM_TIMER1_IDX 1U
#define PWM_TIMER2_IDX 2U
#define PWM_TIMER3_IDX 3U
#define PWM_TIMER4_IDX 4U
#define PWM_TIMER5_IDX 5U
#if (USE_XIP == 0)
#define SPI0_IDX 0U
#endif
#define SPI1_IDX 1U
#define SPI2_IDX 2U
const static unsigned char aotimer_offset[2] = {0x00, 0x14};
const static unsigned char timer_offset[4] = {0x00, 0x14, 0x28, 0x3C};
const static unsigned short pwm_offset[6] = {0x00, 0x40, 0x400, 0x440, 0x800, 0x840};
const static unsigned short uart_offset[3] ={0x00, 0x1000, 0x1400};
const static unsigned short spi_offset[3] ={0x00, 0x1000, 0x1800};
//#include "xc6xxx.h"
#endif // _XC_REG_OFFSET_H_
/*!
* \file xc_reg_offset.h
*
* \brief The header of xc registers offset index
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
#ifndef _XC_REG_OFFSET_H_
#define _XC_REG_OFFSET_H_
#define AOTIMER0_IDX 0U
#define AOTIMER1_IDX 1U
// #define AOTIMER_OFFSET {0x00, 0x14}
#define TIMER0_IDX 0U
#define TIMER1_IDX 1U
#define TIMER2_IDX 2U
#define TIMER3_IDX 3U
#define PWM0_IDX 0U
#define PWM1_IDX 1U
#define PWM2_IDX 2U
#define PWM3_IDX 3U
#define PWM4_IDX 4U
#define PWM5_IDX 5U
#define UART0_IDX (uint8_t)0U
#define UART1_IDX (uint8_t)1U
#define UART2_IDX (uint8_t)2U
#define PWM_TIMER0_IDX 0U
#define PWM_TIMER1_IDX 1U
#define PWM_TIMER2_IDX 2U
#define PWM_TIMER3_IDX 3U
#define PWM_TIMER4_IDX 4U
#define PWM_TIMER5_IDX 5U
#if (USE_XIP == 0)
#define SPI0_IDX 0U
#endif
#define SPI1_IDX 1U
#define SPI2_IDX 2U
const static unsigned char aotimer_offset[2] = {0x00, 0x14};
const static unsigned char timer_offset[4] = {0x00, 0x14, 0x28, 0x3C};
const static unsigned short pwm_offset[6] = {0x00, 0x40, 0x400, 0x440, 0x800, 0x840};
const static unsigned short uart_offset[3] ={0x00, 0x1000, 0x1400};
const static unsigned short spi_offset[3] ={0x00, 0x1000, 0x1800};
#include "xc6xxx.h"
#endif // _XC_REG_OFFSET_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm.h
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm_comn.h
+487 -487
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@@ -1,487 +1,487 @@
#ifndef _XC_REG_PWM_COMN_H_
#define _XC_REG_PWM_COMN_H_
#include <stdint.h>
#define XC_REG_PWM_COMN_BASE_ADDR 0x40017C00
#define XC_REG_PWM_COMN_DECODING_MASK 0x0000003F
#define PWM_COMMON_REG_SIZE 0x04
/**
* @brief CAP_TIM_VAL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 CAPTURE_VALUE 0x0
* </pre>
*/
#define CAP_TIM_VAL_REG(i) (* ((volatile uint32_t *)(0x40017C00 + i*PWM_COMMON_REG_SIZE)) )
#define CAP_TIM_VAL_ADDR(i) (0x40017C00 + i*PWM_COMMON_REG_SIZE)
#define CAP_TIM_VAL_OFFSET 0x00000000
__INLINE uint32_t cap_tim_val_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return CAP_TIM_VAL_REG(reg_idx);
}
// field definitions
#define CAPTURE_VALUE_MASK 0x0000FFFF
#define CAPTURE_VALUE_LSB 0
#define CAPTURE_VALUE_WIDTH 0x00000010
#define CAPTURE_VALUE_RST 0x0
__INLINE uint16_t cap_tim_val__capture_value__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_VAL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_CAP_TIM_INT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 CAPTURE_UPD2 0
* 01 CAPTURE_UPD1 0
* 00 CAPTURE_UPD0 0
* </pre>
*/
#define PWM_CAP_TIM_INT_REG (*(volatile uint32_t *)(0x40017C0C))
#define PWM_CAP_TIM_INT_ADDR 0x40017C0C
#define PWM_CAP_TIM_INT_OFFSET 0x0000000C
__INLINE uint32_t pwm_cap_tim_int_get(void)
{
return PWM_CAP_TIM_INT_REG;
}
__INLINE void pwm_cap_tim_int_set(uint32_t value)
{
PWM_CAP_TIM_INT_REG = value;
}
// field definitions
#define CAPTURE_UPD2_BIT 0x00000004
#define CAPTURE_UPD2_POS 2
#define CAPTURE_UPD1_BIT 0x00000002
#define CAPTURE_UPD1_POS 1
#define CAPTURE_UPD0_BIT 0x00000001
#define CAPTURE_UPD0_POS 0
#define CAPTURE_UPD2_RST 0x0
#define CAPTURE_UPD1_RST 0x0
#define CAPTURE_UPD0_RST 0x0
__INLINE void pwm_cap_tim_int_pack(uint8_t capture_upd2, uint8_t capture_upd1, uint8_t capture_upd0)
{
ASSERT_ERR(((capture_upd2 << 2) & ~0x00000004) == 0);
ASSERT_ERR(((capture_upd1 << 1) & ~0x00000002) == 0);
ASSERT_ERR(((capture_upd0 << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_REG = (capture_upd2 << 2) | (capture_upd1 << 1) | (capture_upd0 << 0);
}
__INLINE void pwm_cap_tim_int_unpack(uint8_t* capture_upd2, uint8_t* capture_upd1, uint8_t* capture_upd0)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
*capture_upd2 = (localVal & 0x00000004) >> 2;
*capture_upd1 = (localVal & 0x00000002) >> 1;
*capture_upd0 = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd2__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_cap_tim_int__capture_upd2__setf(uint8_t capture_upd2)
{
ASSERT_ERR(((capture_upd2 << 2) & ~0x00000004) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000004) | (capture_upd2 << 2);
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd1__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_cap_tim_int__capture_upd1__setf(uint8_t capture_upd1)
{
ASSERT_ERR(((capture_upd1 << 1) & ~0x00000002) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000002) | (capture_upd1 << 1);
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd0__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_cap_tim_int__capture_upd0__setf(uint8_t capture_upd0)
{
ASSERT_ERR(((capture_upd0 << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000001) | (capture_upd0 << 0);
}
/**
* @brief PWM_CAP_TIM_INT_EN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 capture_upd2_en 0
* 01 capture_upd1_en 0
* 00 capture_upd0_en 0
* </pre>
*/
#define PWM_CAP_TIM_INT_EN_REG (*(volatile uint32_t *)(0x40017C10))
#define PWM_CAP_TIM_INT_EN_ADDR 0x40017C10
#define PWM_CAP_TIM_INT_EN_OFFSET 0x00000010
__INLINE uint32_t pwm_cap_tim_int_en_get(void)
{
return PWM_CAP_TIM_INT_EN_REG;
}
__INLINE void pwm_cap_tim_int_en_set(uint32_t value)
{
PWM_CAP_TIM_INT_EN_REG = value;
}
// field definitions
#define CAPTURE_UPD_2_EN_BIT 0x00000004
#define CAPTURE_UPD_2_EN_POS 2
#define CAPTURE_UPD_1_EN_BIT 0x00000002
#define CAPTURE_UPD_1_EN_POS 1
#define CAPTURE_UPD_0_EN_BIT 0x00000001
#define CAPTURE_UPD_0_EN_POS 0
#define CAPTURE_UPD_2_EN_RST 0x0
#define CAPTURE_UPD_1_EN_RST 0x0
#define CAPTURE_UPD_0_EN_RST 0x0
__INLINE void pwm_cap_tim_int_en_pack(uint8_t capture_upd2_en, uint8_t capture_upd1_en, uint8_t capture_upd0_en)
{
ASSERT_ERR(((capture_upd2_en << 2) & ~0x00000004) == 0);
ASSERT_ERR(((capture_upd1_en << 1) & ~0x00000002) == 0);
ASSERT_ERR(((capture_upd0_en << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_EN_REG = (capture_upd2_en << 2) | (capture_upd1_en << 1) | (capture_upd0_en << 0);
}
__INLINE void pwm_cap_tim_int_en_unpack(uint8_t* capture_upd2_en, uint8_t* capture_upd1_en, uint8_t* capture_upd0_en)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
*capture_upd2_en = (localVal & 0x00000004) >> 2;
*capture_upd1_en = (localVal & 0x00000002) >> 1;
*capture_upd0_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_2_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_2_en__setf(uint8_t capture_upd2_en)
{
ASSERT_ERR(((capture_upd2_en << 2) & ~0x00000004) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000004) | (capture_upd2_en << 2);
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_1_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_1_en__setf(uint8_t capture_upd1_en)
{
ASSERT_ERR(((capture_upd1_en << 1) & ~0x00000002) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000002) | (capture_upd1_en << 1);
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_0_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_0_en__setf(uint8_t capture_upd0_en)
{
ASSERT_ERR(((capture_upd0_en << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000001) | (capture_upd0_en << 0);
}
/**
* @brief PWM_CAP_TIM_INT_RAW register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 capture_upd2_raw 0
* 01 capture_upd1_raw 0
* 00 capture_upd0_raw 0
* </pre>
*/
#define PWM_CAP_TIM_INT_RAW_REG (*(volatile uint32_t *)(0x40017C14))
#define PWM_CAP_TIM_INT_RAW_ADDR 0x40017C14
#define PWM_CAP_TIM_INT_RAW_OFFSET 0x00000014
__INLINE uint32_t pwm_cap_tim_int_raw_get(void)
{
return PWM_CAP_TIM_INT_RAW_REG;
}
// field definitions
#define CAPTURE_UPD_2_RAW_BIT 0x00000004
#define CAPTURE_UPD_2_RAW_POS 2
#define CAPTURE_UPD_1_RAW_BIT 0x00000002
#define CAPTURE_UPD_1_RAW_POS 1
#define CAPTURE_UPD_0_RAW_BIT 0x00000001
#define CAPTURE_UPD_0_RAW_POS 0
#define CAPTURE_UPD_2_RAW_RST 0x0
#define CAPTURE_UPD_1_RAW_RST 0x0
#define CAPTURE_UPD_0_RAW_RST 0x0
__INLINE void pwm_cap_tim_int_raw_unpack(uint8_t* capture_upd2_raw, uint8_t* capture_upd1_raw, uint8_t* capture_upd0_raw)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
*capture_upd2_raw = (localVal & 0x00000004) >> 2;
*capture_upd1_raw = (localVal & 0x00000002) >> 1;
*capture_upd0_raw = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_2_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_1_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_0_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief CAP_TIM_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:19 CLK_DIV_VAL 0x0
* 18:16 CAPTURE_SIG_SEL 0x0
* 14 DBC_EN 0
* 13:08 DBC_STEP 0x0
* 05:04 CAPTURE_MODE 0x0
* 03:02 CAPTURE_PSC 0x0
* 01 capture_enable 0
* 00 COMMON_CNT_ENABLE 0
* </pre>
*/
#define CAP_TIM_CTL_REG(i) (* ((volatile uint32_t *)(0x40017C18 + i*PWM_COMMON_REG_SIZE)) )
#define CAP_TIM_CTL_ADDR(i) (0x40017C18 + i*PWM_COMMON_REG_SIZE)
#define CAP_TIM_CTL_OFFSET 0x00000018
__INLINE uint32_t cap_tim_ctl_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return CAP_TIM_CTL_REG(reg_idx);
}
__INLINE void cap_tim_ctl_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
CAP_TIM_CTL_REG(reg_idx) = value;
}
// field definitions
#define CLK_DIV_VAL_MASK 0x00F80000
#define CLK_DIV_VAL_LSB 19
#define CLK_DIV_VAL_WIDTH 0x00000005
#define CAPTURE_SIG_SEL_MASK 0x00070000
#define CAPTURE_SIG_SEL_LSB 16
#define CAPTURE_SIG_SEL_WIDTH 0x00000003
#define DBC_EN_BIT 0x00004000
#define DBC_EN_POS 14
#define DBC_STEP_MASK 0x00003F00
#define DBC_STEP_LSB 8
#define DBC_STEP_WIDTH 0x00000006
#define CAPTURE_MODE_MASK 0x00000030
#define CAPTURE_MODE_LSB 4
#define CAPTURE_MODE_WIDTH 0x00000002
#define CAPTURE_PSC_MASK 0x0000000C
#define CAPTURE_PSC_LSB 2
#define CAPTURE_PSC_WIDTH 0x00000002
#define CAPTURE_ENABLE_BIT 0x00000002
#define CAPTURE_ENABLE_POS 1
#define COMMON_CNT_ENABLE_BIT 0x00000001
#define COMMON_CNT_ENABLE_POS 0
#define CLK_DIV_VAL_RST 0x0
#define CAPTURE_SIG_SEL_RST 0x0
#define DBC_EN_RST 0x0
#define DBC_STEP_RST 0x0
#define CAPTURE_MODE_RST 0x0
#define CAPTURE_PSC_RST 0x0
#define CAPTURE_ENABLE_RST 0x0
#define COMMON_CNT_ENABLE_RST 0x0
__INLINE void cap_tim_ctl_pack(uint32_t reg_idx, uint8_t clk_div_val, uint8_t capture_sig_sel, uint8_t dbc_en, uint8_t dbc_step, uint8_t capture_mode, uint8_t capture_psc, uint8_t capture_enable, uint8_t common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((clk_div_val << 19) & ~0x00F80000) == 0);
ASSERT_ERR(((capture_sig_sel << 16) & ~0x00070000) == 0);
ASSERT_ERR(((dbc_en << 14) & ~0x00004000) == 0);
ASSERT_ERR(((dbc_step << 8) & ~0x00003F00) == 0);
ASSERT_ERR(((capture_mode << 4) & ~0x00000030) == 0);
ASSERT_ERR(((capture_psc << 2) & ~0x0000000C) == 0);
ASSERT_ERR(((capture_enable << 1) & ~0x00000002) == 0);
ASSERT_ERR(((common_cnt_enable << 0) & ~0x00000001) == 0);
CAP_TIM_CTL_REG(reg_idx) = (clk_div_val << 19) | (capture_sig_sel << 16) | (dbc_en << 14) | (dbc_step << 8) | (capture_mode << 4) | (capture_psc << 2) | (capture_enable << 1) | (common_cnt_enable << 0);
}
__INLINE void cap_tim_ctl_unpack(uint32_t reg_idx, uint8_t* clk_div_val, uint8_t* capture_sig_sel, uint8_t* dbc_en, uint8_t* dbc_step, uint8_t* capture_mode, uint8_t* capture_psc, uint8_t* capture_enable, uint8_t* common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
*clk_div_val = (localVal & 0x00F80000) >> 19;
*capture_sig_sel = (localVal & 0x00070000) >> 16;
*dbc_en = (localVal & 0x00004000) >> 14;
*dbc_step = (localVal & 0x00003F00) >> 8;
*capture_mode = (localVal & 0x00000030) >> 4;
*capture_psc = (localVal & 0x0000000C) >> 2;
*capture_enable = (localVal & 0x00000002) >> 1;
*common_cnt_enable = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t cap_tim_ctl__clk_div_val__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00F80000) >> 19);
}
__INLINE void cap_tim_ctl__clk_div_val__setf(uint32_t reg_idx, uint8_t clk_div_val)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((clk_div_val << 19) & ~0x00F80000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00F80000) | (clk_div_val << 19);
}
__INLINE uint8_t cap_tim_ctl__capture_sig_sel__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00070000) >> 16);
}
__INLINE void cap_tim_ctl__capture_sig_sel__setf(uint32_t reg_idx, uint8_t capture_sig_sel)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_sig_sel << 16) & ~0x00070000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00070000) | (capture_sig_sel << 16);
}
__INLINE uint8_t cap_tim_ctl__dbc_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00004000) >> 14);
}
__INLINE void cap_tim_ctl__dbc_en__setf(uint32_t reg_idx, uint8_t dbc_en)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dbc_en << 14) & ~0x00004000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00004000) | (dbc_en << 14);
}
__INLINE uint8_t cap_tim_ctl__dbc_step__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00003F00) >> 8);
}
__INLINE void cap_tim_ctl__dbc_step__setf(uint32_t reg_idx, uint8_t dbc_step)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dbc_step << 8) & ~0x00003F00) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00003F00) | (dbc_step << 8);
}
__INLINE uint8_t cap_tim_ctl__capture_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000030) >> 4);
}
__INLINE void cap_tim_ctl__capture_mode__setf(uint32_t reg_idx, uint8_t capture_mode)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_mode << 4) & ~0x00000030) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000030) | (capture_mode << 4);
}
__INLINE uint8_t cap_tim_ctl__capture_psc__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x0000000C) >> 2);
}
__INLINE void cap_tim_ctl__capture_psc__setf(uint32_t reg_idx, uint8_t capture_psc)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_psc << 2) & ~0x0000000C) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x0000000C) | (capture_psc << 2);
}
__INLINE uint8_t cap_tim_ctl__capture_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void cap_tim_ctl__capture_enable__setf(uint32_t reg_idx, uint8_t capture_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_enable << 1) & ~0x00000002) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000002) | (capture_enable << 1);
}
__INLINE uint8_t cap_tim_ctl__common_cnt_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void cap_tim_ctl__common_cnt_enable__setf(uint32_t reg_idx, uint8_t common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((common_cnt_enable << 0) & ~0x00000001) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000001) | (common_cnt_enable << 0);
}
#endif // _XC_REG_PWM_COMN_H_
#ifndef _XC_REG_PWM_COMN_H_
#define _XC_REG_PWM_COMN_H_
#include <stdint.h>
#define XC_REG_PWM_COMN_BASE_ADDR 0x40017C00
#define XC_REG_PWM_COMN_DECODING_MASK 0x0000003F
#define PWM_COMMON_REG_SIZE 0x04
/**
* @brief CAP_TIM_VAL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 CAPTURE_VALUE 0x0
* </pre>
*/
#define CAP_TIM_VAL_REG(i) (* ((volatile uint32_t *)(0x40017C00 + i*PWM_COMMON_REG_SIZE)) )
#define CAP_TIM_VAL_ADDR(i) (0x40017C00 + i*PWM_COMMON_REG_SIZE)
#define CAP_TIM_VAL_OFFSET 0x00000000
__INLINE uint32_t cap_tim_val_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return CAP_TIM_VAL_REG(reg_idx);
}
// field definitions
#define CAPTURE_VALUE_MASK 0x0000FFFF
#define CAPTURE_VALUE_LSB 0
#define CAPTURE_VALUE_WIDTH 0x00000010
#define CAPTURE_VALUE_RST 0x0
__INLINE uint16_t cap_tim_val__capture_value__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_VAL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_CAP_TIM_INT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 CAPTURE_UPD2 0
* 01 CAPTURE_UPD1 0
* 00 CAPTURE_UPD0 0
* </pre>
*/
#define PWM_CAP_TIM_INT_REG (*(volatile uint32_t *)(0x40017C0C))
#define PWM_CAP_TIM_INT_ADDR 0x40017C0C
#define PWM_CAP_TIM_INT_OFFSET 0x0000000C
__INLINE uint32_t pwm_cap_tim_int_get(void)
{
return PWM_CAP_TIM_INT_REG;
}
__INLINE void pwm_cap_tim_int_set(uint32_t value)
{
PWM_CAP_TIM_INT_REG = value;
}
// field definitions
#define CAPTURE_UPD2_BIT 0x00000004
#define CAPTURE_UPD2_POS 2
#define CAPTURE_UPD1_BIT 0x00000002
#define CAPTURE_UPD1_POS 1
#define CAPTURE_UPD0_BIT 0x00000001
#define CAPTURE_UPD0_POS 0
#define CAPTURE_UPD2_RST 0x0
#define CAPTURE_UPD1_RST 0x0
#define CAPTURE_UPD0_RST 0x0
__INLINE void pwm_cap_tim_int_pack(uint8_t capture_upd2, uint8_t capture_upd1, uint8_t capture_upd0)
{
ASSERT_ERR(((capture_upd2 << 2) & ~0x00000004) == 0);
ASSERT_ERR(((capture_upd1 << 1) & ~0x00000002) == 0);
ASSERT_ERR(((capture_upd0 << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_REG = (capture_upd2 << 2) | (capture_upd1 << 1) | (capture_upd0 << 0);
}
__INLINE void pwm_cap_tim_int_unpack(uint8_t* capture_upd2, uint8_t* capture_upd1, uint8_t* capture_upd0)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
*capture_upd2 = (localVal & 0x00000004) >> 2;
*capture_upd1 = (localVal & 0x00000002) >> 1;
*capture_upd0 = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd2__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_cap_tim_int__capture_upd2__setf(uint8_t capture_upd2)
{
ASSERT_ERR(((capture_upd2 << 2) & ~0x00000004) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000004) | (capture_upd2 << 2);
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd1__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_cap_tim_int__capture_upd1__setf(uint8_t capture_upd1)
{
ASSERT_ERR(((capture_upd1 << 1) & ~0x00000002) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000002) | (capture_upd1 << 1);
}
__INLINE uint8_t pwm_cap_tim_int__capture_upd0__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_cap_tim_int__capture_upd0__setf(uint8_t capture_upd0)
{
ASSERT_ERR(((capture_upd0 << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_REG = (PWM_CAP_TIM_INT_REG & ~0x00000001) | (capture_upd0 << 0);
}
/**
* @brief PWM_CAP_TIM_INT_EN register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 capture_upd2_en 0
* 01 capture_upd1_en 0
* 00 capture_upd0_en 0
* </pre>
*/
#define PWM_CAP_TIM_INT_EN_REG (*(volatile uint32_t *)(0x40017C10))
#define PWM_CAP_TIM_INT_EN_ADDR 0x40017C10
#define PWM_CAP_TIM_INT_EN_OFFSET 0x00000010
__INLINE uint32_t pwm_cap_tim_int_en_get(void)
{
return PWM_CAP_TIM_INT_EN_REG;
}
__INLINE void pwm_cap_tim_int_en_set(uint32_t value)
{
PWM_CAP_TIM_INT_EN_REG = value;
}
// field definitions
#define CAPTURE_UPD_2_EN_BIT 0x00000004
#define CAPTURE_UPD_2_EN_POS 2
#define CAPTURE_UPD_1_EN_BIT 0x00000002
#define CAPTURE_UPD_1_EN_POS 1
#define CAPTURE_UPD_0_EN_BIT 0x00000001
#define CAPTURE_UPD_0_EN_POS 0
#define CAPTURE_UPD_2_EN_RST 0x0
#define CAPTURE_UPD_1_EN_RST 0x0
#define CAPTURE_UPD_0_EN_RST 0x0
__INLINE void pwm_cap_tim_int_en_pack(uint8_t capture_upd2_en, uint8_t capture_upd1_en, uint8_t capture_upd0_en)
{
ASSERT_ERR(((capture_upd2_en << 2) & ~0x00000004) == 0);
ASSERT_ERR(((capture_upd1_en << 1) & ~0x00000002) == 0);
ASSERT_ERR(((capture_upd0_en << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_EN_REG = (capture_upd2_en << 2) | (capture_upd1_en << 1) | (capture_upd0_en << 0);
}
__INLINE void pwm_cap_tim_int_en_unpack(uint8_t* capture_upd2_en, uint8_t* capture_upd1_en, uint8_t* capture_upd0_en)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
*capture_upd2_en = (localVal & 0x00000004) >> 2;
*capture_upd1_en = (localVal & 0x00000002) >> 1;
*capture_upd0_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_2_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_2_en__setf(uint8_t capture_upd2_en)
{
ASSERT_ERR(((capture_upd2_en << 2) & ~0x00000004) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000004) | (capture_upd2_en << 2);
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_1_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_1_en__setf(uint8_t capture_upd1_en)
{
ASSERT_ERR(((capture_upd1_en << 1) & ~0x00000002) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000002) | (capture_upd1_en << 1);
}
__INLINE uint8_t pwm_cap_tim_int_en__capture_upd_0_en__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_EN_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_cap_tim_int_en__capture_upd_0_en__setf(uint8_t capture_upd0_en)
{
ASSERT_ERR(((capture_upd0_en << 0) & ~0x00000001) == 0);
PWM_CAP_TIM_INT_EN_REG = (PWM_CAP_TIM_INT_EN_REG & ~0x00000001) | (capture_upd0_en << 0);
}
/**
* @brief PWM_CAP_TIM_INT_RAW register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 capture_upd2_raw 0
* 01 capture_upd1_raw 0
* 00 capture_upd0_raw 0
* </pre>
*/
#define PWM_CAP_TIM_INT_RAW_REG (*(volatile uint32_t *)(0x40017C14))
#define PWM_CAP_TIM_INT_RAW_ADDR 0x40017C14
#define PWM_CAP_TIM_INT_RAW_OFFSET 0x00000014
__INLINE uint32_t pwm_cap_tim_int_raw_get(void)
{
return PWM_CAP_TIM_INT_RAW_REG;
}
// field definitions
#define CAPTURE_UPD_2_RAW_BIT 0x00000004
#define CAPTURE_UPD_2_RAW_POS 2
#define CAPTURE_UPD_1_RAW_BIT 0x00000002
#define CAPTURE_UPD_1_RAW_POS 1
#define CAPTURE_UPD_0_RAW_BIT 0x00000001
#define CAPTURE_UPD_0_RAW_POS 0
#define CAPTURE_UPD_2_RAW_RST 0x0
#define CAPTURE_UPD_1_RAW_RST 0x0
#define CAPTURE_UPD_0_RAW_RST 0x0
__INLINE void pwm_cap_tim_int_raw_unpack(uint8_t* capture_upd2_raw, uint8_t* capture_upd1_raw, uint8_t* capture_upd0_raw)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
*capture_upd2_raw = (localVal & 0x00000004) >> 2;
*capture_upd1_raw = (localVal & 0x00000002) >> 1;
*capture_upd0_raw = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_2_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000004) >> 2);
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_1_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE uint8_t pwm_cap_tim_int_raw__capture_upd_0_raw__getf(void)
{
uint32_t localVal = PWM_CAP_TIM_INT_RAW_REG;
return ((localVal & 0x00000001) >> 0);
}
/**
* @brief CAP_TIM_CTL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:19 CLK_DIV_VAL 0x0
* 18:16 CAPTURE_SIG_SEL 0x0
* 14 DBC_EN 0
* 13:08 DBC_STEP 0x0
* 05:04 CAPTURE_MODE 0x0
* 03:02 CAPTURE_PSC 0x0
* 01 capture_enable 0
* 00 COMMON_CNT_ENABLE 0
* </pre>
*/
#define CAP_TIM_CTL_REG(i) (* ((volatile uint32_t *)(0x40017C18 + i*PWM_COMMON_REG_SIZE)) )
#define CAP_TIM_CTL_ADDR(i) (0x40017C18 + i*PWM_COMMON_REG_SIZE)
#define CAP_TIM_CTL_OFFSET 0x00000018
__INLINE uint32_t cap_tim_ctl_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
return CAP_TIM_CTL_REG(reg_idx);
}
__INLINE void cap_tim_ctl_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 2);
CAP_TIM_CTL_REG(reg_idx) = value;
}
// field definitions
#define CLK_DIV_VAL_MASK 0x00F80000
#define CLK_DIV_VAL_LSB 19
#define CLK_DIV_VAL_WIDTH 0x00000005
#define CAPTURE_SIG_SEL_MASK 0x00070000
#define CAPTURE_SIG_SEL_LSB 16
#define CAPTURE_SIG_SEL_WIDTH 0x00000003
#define DBC_EN_BIT 0x00004000
#define DBC_EN_POS 14
#define DBC_STEP_MASK 0x00003F00
#define DBC_STEP_LSB 8
#define DBC_STEP_WIDTH 0x00000006
#define CAPTURE_MODE_MASK 0x00000030
#define CAPTURE_MODE_LSB 4
#define CAPTURE_MODE_WIDTH 0x00000002
#define CAPTURE_PSC_MASK 0x0000000C
#define CAPTURE_PSC_LSB 2
#define CAPTURE_PSC_WIDTH 0x00000002
#define CAPTURE_ENABLE_BIT 0x00000002
#define CAPTURE_ENABLE_POS 1
#define COMMON_CNT_ENABLE_BIT 0x00000001
#define COMMON_CNT_ENABLE_POS 0
#define CLK_DIV_VAL_RST 0x0
#define CAPTURE_SIG_SEL_RST 0x0
#define DBC_EN_RST 0x0
#define DBC_STEP_RST 0x0
#define CAPTURE_MODE_RST 0x0
#define CAPTURE_PSC_RST 0x0
#define CAPTURE_ENABLE_RST 0x0
#define COMMON_CNT_ENABLE_RST 0x0
__INLINE void cap_tim_ctl_pack(uint32_t reg_idx, uint8_t clk_div_val, uint8_t capture_sig_sel, uint8_t dbc_en, uint8_t dbc_step, uint8_t capture_mode, uint8_t capture_psc, uint8_t capture_enable, uint8_t common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((clk_div_val << 19) & ~0x00F80000) == 0);
ASSERT_ERR(((capture_sig_sel << 16) & ~0x00070000) == 0);
ASSERT_ERR(((dbc_en << 14) & ~0x00004000) == 0);
ASSERT_ERR(((dbc_step << 8) & ~0x00003F00) == 0);
ASSERT_ERR(((capture_mode << 4) & ~0x00000030) == 0);
ASSERT_ERR(((capture_psc << 2) & ~0x0000000C) == 0);
ASSERT_ERR(((capture_enable << 1) & ~0x00000002) == 0);
ASSERT_ERR(((common_cnt_enable << 0) & ~0x00000001) == 0);
CAP_TIM_CTL_REG(reg_idx) = (clk_div_val << 19) | (capture_sig_sel << 16) | (dbc_en << 14) | (dbc_step << 8) | (capture_mode << 4) | (capture_psc << 2) | (capture_enable << 1) | (common_cnt_enable << 0);
}
__INLINE void cap_tim_ctl_unpack(uint32_t reg_idx, uint8_t* clk_div_val, uint8_t* capture_sig_sel, uint8_t* dbc_en, uint8_t* dbc_step, uint8_t* capture_mode, uint8_t* capture_psc, uint8_t* capture_enable, uint8_t* common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
*clk_div_val = (localVal & 0x00F80000) >> 19;
*capture_sig_sel = (localVal & 0x00070000) >> 16;
*dbc_en = (localVal & 0x00004000) >> 14;
*dbc_step = (localVal & 0x00003F00) >> 8;
*capture_mode = (localVal & 0x00000030) >> 4;
*capture_psc = (localVal & 0x0000000C) >> 2;
*capture_enable = (localVal & 0x00000002) >> 1;
*common_cnt_enable = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t cap_tim_ctl__clk_div_val__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00F80000) >> 19);
}
__INLINE void cap_tim_ctl__clk_div_val__setf(uint32_t reg_idx, uint8_t clk_div_val)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((clk_div_val << 19) & ~0x00F80000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00F80000) | (clk_div_val << 19);
}
__INLINE uint8_t cap_tim_ctl__capture_sig_sel__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00070000) >> 16);
}
__INLINE void cap_tim_ctl__capture_sig_sel__setf(uint32_t reg_idx, uint8_t capture_sig_sel)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_sig_sel << 16) & ~0x00070000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00070000) | (capture_sig_sel << 16);
}
__INLINE uint8_t cap_tim_ctl__dbc_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00004000) >> 14);
}
__INLINE void cap_tim_ctl__dbc_en__setf(uint32_t reg_idx, uint8_t dbc_en)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dbc_en << 14) & ~0x00004000) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00004000) | (dbc_en << 14);
}
__INLINE uint8_t cap_tim_ctl__dbc_step__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00003F00) >> 8);
}
__INLINE void cap_tim_ctl__dbc_step__setf(uint32_t reg_idx, uint8_t dbc_step)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((dbc_step << 8) & ~0x00003F00) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00003F00) | (dbc_step << 8);
}
__INLINE uint8_t cap_tim_ctl__capture_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000030) >> 4);
}
__INLINE void cap_tim_ctl__capture_mode__setf(uint32_t reg_idx, uint8_t capture_mode)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_mode << 4) & ~0x00000030) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000030) | (capture_mode << 4);
}
__INLINE uint8_t cap_tim_ctl__capture_psc__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x0000000C) >> 2);
}
__INLINE void cap_tim_ctl__capture_psc__setf(uint32_t reg_idx, uint8_t capture_psc)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_psc << 2) & ~0x0000000C) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x0000000C) | (capture_psc << 2);
}
__INLINE uint8_t cap_tim_ctl__capture_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void cap_tim_ctl__capture_enable__setf(uint32_t reg_idx, uint8_t capture_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((capture_enable << 1) & ~0x00000002) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000002) | (capture_enable << 1);
}
__INLINE uint8_t cap_tim_ctl__common_cnt_enable__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 2);
uint32_t localVal = CAP_TIM_CTL_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void cap_tim_ctl__common_cnt_enable__setf(uint32_t reg_idx, uint8_t common_cnt_enable)
{
ASSERT_ERR(reg_idx <= 2);
ASSERT_ERR(((common_cnt_enable << 0) & ~0x00000001) == 0);
CAP_TIM_CTL_REG(reg_idx) = (CAP_TIM_CTL_REG(reg_idx) & ~0x00000001) | (common_cnt_enable << 0);
}
#endif // _XC_REG_PWM_COMN_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_pwm_timer.h
+453 -453
View File
@@ -1,453 +1,453 @@
#ifndef _XC_REG_PWM_TIMER_H_
#define _XC_REG_PWM_TIMER_H_
#include <stdint.h>
#include "xc_reg_offset.h"
#define XC_REG_PWM_TIMER_BASE_ADDR 0x40017D00
#define XC_REG_PWM_TIMER_DECODING_MASK 0x000000FF
#define PWM_TIMER_REG_SIZE 0x14
#define PWM_LOAD_CNT2_REG_SIZE 0x04
/**
* @brief PWM_TIMER_LOADCOUNT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 TIMER_LC 0x0
* </pre>
*/
#define PWM_TIMER_LOADCOUNT_REG(i) (* ((volatile uint32_t *)(0x40017D00 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_LOADCOUNT_ADDR(i) (0x40017D00 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_LOADCOUNT_OFFSET 0x00000000
__INLINE uint32_t pwm_timer_loadcount_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_LOADCOUNT_REG(reg_idx);
}
__INLINE void pwm_timer_loadcount_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_LOADCOUNT_REG(reg_idx) = value;
}
// field definitions
#define TIMER_LC_MASK 0x0000FFFF
#define TIMER_LC_LSB 0
#define TIMER_LC_WIDTH 0x00000010
#define TIMER_LC_RST 0x0
__INLINE uint16_t pwm_timer_loadcount__timer_lc__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_LOADCOUNT_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_timer_loadcount__timer_lc__setf(uint32_t reg_idx, uint16_t timer_lc)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_lc << 0) & ~0x0000FFFF) == 0);
PWM_TIMER_LOADCOUNT_REG(reg_idx) = timer_lc << 0;
}
/**
* @brief PWM_TIMER_CURRENTVAL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 TIMER_CV 0x0
* </pre>
*/
#define PWM_TIMER_CURRENTVAL_REG(i) (* ((volatile uint32_t *)(0x40017D04 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_CURRENTVAL_ADDR(i) (0x40017D04 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_CURRENTVAL_OFFSET 0x00000004
__INLINE uint32_t pwm_timer_currentval_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_CURRENTVAL_REG(reg_idx);
}
// field definitions
#define TIMER_CV_MASK 0x0000FFFF
#define TIMER_CV_LSB 0
#define TIMER_CV_WIDTH 0x00000010
#define TIMER_CV_RST 0x0
__INLINE uint16_t pwm_timer_currentval__timer_cv__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CURRENTVAL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_CONTROLREG register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 TIMER_ON10OPWM_EN 0
* 03 TIMER_PWM 0
* 02 TIMER_INT_MASK 0
* 01 TIMER_MODE 0
* 00 TIMER_EN 0
* </pre>
*/
#define PWM_TIMER_CONTROLREG_REG(i) (* ((volatile uint32_t *)(0x40017D08 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_CONTROLREG_ADDR(i) (0x40017D08 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_CONTROLREG_OFFSET 0x00000008
__INLINE uint32_t pwm_timer_controlreg_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_CONTROLREG_REG(reg_idx);
}
__INLINE void pwm_timer_controlreg_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_CONTROLREG_REG(reg_idx) = value;
}
// field definitions
#define TIMER_ON10OPWM_EN_BIT 0x00000010
#define TIMER_ON10OPWM_EN_POS 4
#define TIMER_PWM_BIT 0x00000008
#define TIMER_PWM_POS 3
#define TIMER_INT_MASK_BIT 0x00000004
#define TIMER_INT_MASK_POS 2
#define TIMER_MODE_BIT 0x00000002
#define TIMER_MODE_POS 1
#define TIMER_EN_BIT 0x00000001
#define TIMER_EN_POS 0
#define TIMER_ON10OPWM_EN_RST 0x0
#define TIMER_PWM_RST 0x0
#define TIMER_INT_MASK_RST 0x0
#define TIMER_MODE_RST 0x0
#define TIMER_EN_RST 0x0
__INLINE void pwm_timer_controlreg_pack(uint32_t reg_idx, uint8_t timer_int_mask, uint8_t timer_mode, uint8_t timer_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_int_mask << 2) & ~0x00000004) == 0);
ASSERT_ERR(((timer_mode << 1) & ~0x00000002) == 0);
ASSERT_ERR(((timer_en << 0) & ~0x00000001) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (timer_int_mask << 2) | (timer_mode << 1) | (timer_en << 0);
}
__INLINE void pwm_timer_controlreg_unpack(uint32_t reg_idx, uint8_t* timer_on10opwm_en, uint8_t* timer_pwm, uint8_t* timer_int_mask, uint8_t* timer_mode, uint8_t* timer_en)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
*timer_on10opwm_en = (localVal & 0x00000010) >> 4;
*timer_pwm = (localVal & 0x00000008) >> 3;
*timer_int_mask = (localVal & 0x00000004) >> 2;
*timer_mode = (localVal & 0x00000002) >> 1;
*timer_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_timer_controlreg__timer_on10opwm_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t pwm_timer_controlreg__timer_pwm__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE uint8_t pwm_timer_controlreg__timer_int_mask__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_timer_controlreg__timer_int_mask__setf(uint32_t reg_idx, uint8_t timer_int_mask)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_int_mask << 2) & ~0x00000004) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000004) | (timer_int_mask << 2);
}
__INLINE uint8_t pwm_timer_controlreg__timer_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_timer_controlreg__timer_mode__setf(uint32_t reg_idx, uint8_t timer_mode)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_mode << 1) & ~0x00000002) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000002) | (timer_mode << 1);
}
__INLINE uint8_t pwm_timer_controlreg__timer_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_timer_controlreg__timer_en__setf(uint32_t reg_idx, uint8_t timer_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_en << 0) & ~0x00000001) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000001) | (timer_en << 0);
}
/**
* @brief PWM_TIMER_EOI register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 Timer_EOI 0
* </pre>
*/
#define PWM_TIMER_EOI_REG(i) (* ((volatile uint32_t *)(0x40017D0C + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_EOI_ADDR(i) (0x40017D0C + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_EOI_OFFSET 0x0000000C
__INLINE uint32_t pwm_timer_eoi_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_EOI_REG(reg_idx);
}
// field definitions
#define TIMER_EOI_BIT 0x00000001
#define TIMER_EOI_POS 0
#define TIMER_EOI_RST 0x0
__INLINE uint8_t pwm_timer_eoi__timer_eoi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_EOI_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_INTSTAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 Timer_IS 0
* </pre>
*/
#define PWM_TIMER_INTSTAT_REG(i) (* ((volatile uint32_t *)(0x40017D10 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_INTSTAT_ADDR(i) (0x40017D10 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_INTSTAT_OFFSET 0x00000010
__INLINE uint32_t pwm_timer_intstat_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_INTSTAT_REG(reg_idx);
}
// field definitions
#define TIMER_IS_BIT 0x00000001
#define TIMER_IS_POS 0
#define TIMER_IS_RST 0x0
__INLINE uint8_t pwm_timer_intstat__timer_is__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_INTSTAT_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 Timers_IS 0x0
* </pre>
*/
#define PWM_TIMER_A_TIS_REG (*(volatile uint32_t *)(0x40017DA0))
#define PWM_TIMER_A_TIS_ADDR 0x40017DA0
#define PWM_TIMER_A_TIS_OFFSET 0x000000A0
__INLINE uint32_t pwm_timer_a_tis_get(void)
{
return PWM_TIMER_A_TIS_REG;
}
// field definitions
#define TIMERS_IS_MASK 0x0000003F
#define TIMERS_IS_LSB 0
#define TIMERS_IS_WIDTH 0x00000006
#define TIMERS_IS_RST 0x0
__INLINE uint8_t pwm_timer_a_tis__timers_is__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TIS_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TEOI register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 TIMERS_EOI 0x0
* </pre>
*/
#define PWM_TIMER_A_TEOI_REG (*(volatile uint32_t *)(0x40017DA4))
#define PWM_TIMER_A_TEOI_ADDR 0x40017DA4
#define PWM_TIMER_A_TEOI_OFFSET 0x000000A4
__INLINE uint32_t pwm_timer_a_teoi_get(void)
{
return PWM_TIMER_A_TEOI_REG;
}
// field definitions
#define TIMERS_EOI_MASK 0x0000003F
#define TIMERS_EOI_LSB 0
#define TIMERS_EOI_WIDTH 0x00000006
#define TIMERS_EOI_RST 0x0
__INLINE uint8_t pwm_timer_a_teoi__timers_eoi__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TEOI_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TRIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 TIMERS_RIS 0x0
* </pre>
*/
#define PWM_TIMER_A_TRIS_REG (*(volatile uint32_t *)(0x40017DA8))
#define PWM_TIMER_A_TRIS_ADDR 0x40017DA8
#define PWM_TIMER_A_TRIS_OFFSET 0x000000A8
__INLINE uint32_t pwm_timer_a_tris_get(void)
{
return PWM_TIMER_A_TRIS_REG;
}
// field definitions
#define TIMERS_RIS_MASK 0x0000003F
#define TIMERS_RIS_LSB 0
#define TIMERS_RIS_WIDTH 0x00000006
#define TIMERS_RIS_RST 0x0
__INLINE uint8_t pwm_timer_a_tris__timers_ris__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TRIS_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_TCOMP register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 TIMERS_COMP 0x0
* </pre>
*/
#define PWM_TIMER_TCOMP_REG (*(volatile uint32_t *)(0x40017DAC))
#define PWM_TIMER_TCOMP_ADDR 0x40017DAC
#define PWM_TIMER_TCOMP_OFFSET 0x000000AC
__INLINE uint32_t pwm_timer_tcomp_get(void)
{
return PWM_TIMER_TCOMP_REG;
}
// field definitions
#define TIMERS_COMP_MASK 0xFFFFFFFF
#define TIMERS_COMP_LSB 0
#define TIMERS_COMP_WIDTH 0x00000020
#define TIMERS_COMP_RST 0x0
__INLINE uint32_t pwm_timer_tcomp__timers_comp__getf(void)
{
uint32_t localVal = PWM_TIMER_TCOMP_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_LOADCOUNT2 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 11:00 TIMER_LC2 0x0
* </pre>
*/
#define PWM_TIMER_LOADCOUNT2_REG(i) (* ((volatile uint32_t *)(0x40017DB0 + i*PWM_LOAD_CNT2_REG_SIZE)) )
#define PWM_TIMER_LOADCOUNT2_ADDR(i) (0x40017DB0 + i*PWM_LOAD_CNT2_REG_SIZE)
#define PWM_TIMER_LOADCOUNT2_OFFSET 0x000000B0
__INLINE uint32_t pwm_timer_loadcount2_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_LOADCOUNT2_REG(reg_idx);
}
__INLINE void pwm_timer_loadcount2_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_LOADCOUNT2_REG(reg_idx) = value;
}
// field definitions
#define TIMER_LC2_MASK 0x00000FFF
#define TIMER_LC2_LSB 0
#define TIMER_LC2_WIDTH 0x0000000C
#define TIMER_LC2_RST 0x0
__INLINE uint16_t pwm_timer_loadcount2__timer_lc2__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_LOADCOUNT2_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000FFF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_timer_loadcount2__timer_lc2__setf(uint32_t reg_idx, uint16_t timer_lc2)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_lc2 << 0) & ~0x00000FFF) == 0);
PWM_TIMER_LOADCOUNT2_REG(reg_idx) = timer_lc2 << 0;
}
#endif // _XC_REG_PWM_TIMER_H_
#ifndef _XC_REG_PWM_TIMER_H_
#define _XC_REG_PWM_TIMER_H_
#include <stdint.h>
#include "xc_reg_offset.h"
#define XC_REG_PWM_TIMER_BASE_ADDR 0x40017D00
#define XC_REG_PWM_TIMER_DECODING_MASK 0x000000FF
#define PWM_TIMER_REG_SIZE 0x14
#define PWM_LOAD_CNT2_REG_SIZE 0x04
/**
* @brief PWM_TIMER_LOADCOUNT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 TIMER_LC 0x0
* </pre>
*/
#define PWM_TIMER_LOADCOUNT_REG(i) (* ((volatile uint32_t *)(0x40017D00 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_LOADCOUNT_ADDR(i) (0x40017D00 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_LOADCOUNT_OFFSET 0x00000000
__INLINE uint32_t pwm_timer_loadcount_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_LOADCOUNT_REG(reg_idx);
}
__INLINE void pwm_timer_loadcount_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_LOADCOUNT_REG(reg_idx) = value;
}
// field definitions
#define TIMER_LC_MASK 0x0000FFFF
#define TIMER_LC_LSB 0
#define TIMER_LC_WIDTH 0x00000010
#define TIMER_LC_RST 0x0
__INLINE uint16_t pwm_timer_loadcount__timer_lc__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_LOADCOUNT_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_timer_loadcount__timer_lc__setf(uint32_t reg_idx, uint16_t timer_lc)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_lc << 0) & ~0x0000FFFF) == 0);
PWM_TIMER_LOADCOUNT_REG(reg_idx) = timer_lc << 0;
}
/**
* @brief PWM_TIMER_CURRENTVAL register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 TIMER_CV 0x0
* </pre>
*/
#define PWM_TIMER_CURRENTVAL_REG(i) (* ((volatile uint32_t *)(0x40017D04 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_CURRENTVAL_ADDR(i) (0x40017D04 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_CURRENTVAL_OFFSET 0x00000004
__INLINE uint32_t pwm_timer_currentval_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_CURRENTVAL_REG(reg_idx);
}
// field definitions
#define TIMER_CV_MASK 0x0000FFFF
#define TIMER_CV_LSB 0
#define TIMER_CV_WIDTH 0x00000010
#define TIMER_CV_RST 0x0
__INLINE uint16_t pwm_timer_currentval__timer_cv__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CURRENTVAL_REG(reg_idx);
ASSERT_ERR((localVal & ~0x0000FFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_CONTROLREG register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04 TIMER_ON10OPWM_EN 0
* 03 TIMER_PWM 0
* 02 TIMER_INT_MASK 0
* 01 TIMER_MODE 0
* 00 TIMER_EN 0
* </pre>
*/
#define PWM_TIMER_CONTROLREG_REG(i) (* ((volatile uint32_t *)(0x40017D08 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_CONTROLREG_ADDR(i) (0x40017D08 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_CONTROLREG_OFFSET 0x00000008
__INLINE uint32_t pwm_timer_controlreg_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_CONTROLREG_REG(reg_idx);
}
__INLINE void pwm_timer_controlreg_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_CONTROLREG_REG(reg_idx) = value;
}
// field definitions
#define TIMER_ON10OPWM_EN_BIT 0x00000010
#define TIMER_ON10OPWM_EN_POS 4
#define TIMER_PWM_BIT 0x00000008
#define TIMER_PWM_POS 3
#define TIMER_INT_MASK_BIT 0x00000004
#define TIMER_INT_MASK_POS 2
#define TIMER_MODE_BIT 0x00000002
#define TIMER_MODE_POS 1
#define TIMER_EN_BIT 0x00000001
#define TIMER_EN_POS 0
#define TIMER_ON10OPWM_EN_RST 0x0
#define TIMER_PWM_RST 0x0
#define TIMER_INT_MASK_RST 0x0
#define TIMER_MODE_RST 0x0
#define TIMER_EN_RST 0x0
__INLINE void pwm_timer_controlreg_pack(uint32_t reg_idx, uint8_t timer_int_mask, uint8_t timer_mode, uint8_t timer_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_int_mask << 2) & ~0x00000004) == 0);
ASSERT_ERR(((timer_mode << 1) & ~0x00000002) == 0);
ASSERT_ERR(((timer_en << 0) & ~0x00000001) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (timer_int_mask << 2) | (timer_mode << 1) | (timer_en << 0);
}
__INLINE void pwm_timer_controlreg_unpack(uint32_t reg_idx, uint8_t* timer_on10opwm_en, uint8_t* timer_pwm, uint8_t* timer_int_mask, uint8_t* timer_mode, uint8_t* timer_en)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
*timer_on10opwm_en = (localVal & 0x00000010) >> 4;
*timer_pwm = (localVal & 0x00000008) >> 3;
*timer_int_mask = (localVal & 0x00000004) >> 2;
*timer_mode = (localVal & 0x00000002) >> 1;
*timer_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t pwm_timer_controlreg__timer_on10opwm_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000010) >> 4);
}
__INLINE uint8_t pwm_timer_controlreg__timer_pwm__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000008) >> 3);
}
__INLINE uint8_t pwm_timer_controlreg__timer_int_mask__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void pwm_timer_controlreg__timer_int_mask__setf(uint32_t reg_idx, uint8_t timer_int_mask)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_int_mask << 2) & ~0x00000004) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000004) | (timer_int_mask << 2);
}
__INLINE uint8_t pwm_timer_controlreg__timer_mode__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void pwm_timer_controlreg__timer_mode__setf(uint32_t reg_idx, uint8_t timer_mode)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_mode << 1) & ~0x00000002) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000002) | (timer_mode << 1);
}
__INLINE uint8_t pwm_timer_controlreg__timer_en__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_CONTROLREG_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void pwm_timer_controlreg__timer_en__setf(uint32_t reg_idx, uint8_t timer_en)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_en << 0) & ~0x00000001) == 0);
PWM_TIMER_CONTROLREG_REG(reg_idx) = (PWM_TIMER_CONTROLREG_REG(reg_idx) & ~0x00000001) | (timer_en << 0);
}
/**
* @brief PWM_TIMER_EOI register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 Timer_EOI 0
* </pre>
*/
#define PWM_TIMER_EOI_REG(i) (* ((volatile uint32_t *)(0x40017D0C + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_EOI_ADDR(i) (0x40017D0C + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_EOI_OFFSET 0x0000000C
__INLINE uint32_t pwm_timer_eoi_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_EOI_REG(reg_idx);
}
// field definitions
#define TIMER_EOI_BIT 0x00000001
#define TIMER_EOI_POS 0
#define TIMER_EOI_RST 0x0
__INLINE uint8_t pwm_timer_eoi__timer_eoi__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_EOI_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_INTSTAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 Timer_IS 0
* </pre>
*/
#define PWM_TIMER_INTSTAT_REG(i) (* ((volatile uint32_t *)(0x40017D10 + i*PWM_TIMER_REG_SIZE)) )
#define PWM_TIMER_INTSTAT_ADDR(i) (0x40017D10 + i*PWM_TIMER_REG_SIZE)
#define PWM_TIMER_INTSTAT_OFFSET 0x00000010
__INLINE uint32_t pwm_timer_intstat_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_INTSTAT_REG(reg_idx);
}
// field definitions
#define TIMER_IS_BIT 0x00000001
#define TIMER_IS_POS 0
#define TIMER_IS_RST 0x0
__INLINE uint8_t pwm_timer_intstat__timer_is__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_INTSTAT_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 Timers_IS 0x0
* </pre>
*/
#define PWM_TIMER_A_TIS_REG (*(volatile uint32_t *)(0x40017DA0))
#define PWM_TIMER_A_TIS_ADDR 0x40017DA0
#define PWM_TIMER_A_TIS_OFFSET 0x000000A0
__INLINE uint32_t pwm_timer_a_tis_get(void)
{
return PWM_TIMER_A_TIS_REG;
}
// field definitions
#define TIMERS_IS_MASK 0x0000003F
#define TIMERS_IS_LSB 0
#define TIMERS_IS_WIDTH 0x00000006
#define TIMERS_IS_RST 0x0
__INLINE uint8_t pwm_timer_a_tis__timers_is__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TIS_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TEOI register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 TIMERS_EOI 0x0
* </pre>
*/
#define PWM_TIMER_A_TEOI_REG (*(volatile uint32_t *)(0x40017DA4))
#define PWM_TIMER_A_TEOI_ADDR 0x40017DA4
#define PWM_TIMER_A_TEOI_OFFSET 0x000000A4
__INLINE uint32_t pwm_timer_a_teoi_get(void)
{
return PWM_TIMER_A_TEOI_REG;
}
// field definitions
#define TIMERS_EOI_MASK 0x0000003F
#define TIMERS_EOI_LSB 0
#define TIMERS_EOI_WIDTH 0x00000006
#define TIMERS_EOI_RST 0x0
__INLINE uint8_t pwm_timer_a_teoi__timers_eoi__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TEOI_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_A_TRIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 05:00 TIMERS_RIS 0x0
* </pre>
*/
#define PWM_TIMER_A_TRIS_REG (*(volatile uint32_t *)(0x40017DA8))
#define PWM_TIMER_A_TRIS_ADDR 0x40017DA8
#define PWM_TIMER_A_TRIS_OFFSET 0x000000A8
__INLINE uint32_t pwm_timer_a_tris_get(void)
{
return PWM_TIMER_A_TRIS_REG;
}
// field definitions
#define TIMERS_RIS_MASK 0x0000003F
#define TIMERS_RIS_LSB 0
#define TIMERS_RIS_WIDTH 0x00000006
#define TIMERS_RIS_RST 0x0
__INLINE uint8_t pwm_timer_a_tris__timers_ris__getf(void)
{
uint32_t localVal = PWM_TIMER_A_TRIS_REG;
ASSERT_ERR((localVal & ~0x0000003F) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_TCOMP register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 TIMERS_COMP 0x0
* </pre>
*/
#define PWM_TIMER_TCOMP_REG (*(volatile uint32_t *)(0x40017DAC))
#define PWM_TIMER_TCOMP_ADDR 0x40017DAC
#define PWM_TIMER_TCOMP_OFFSET 0x000000AC
__INLINE uint32_t pwm_timer_tcomp_get(void)
{
return PWM_TIMER_TCOMP_REG;
}
// field definitions
#define TIMERS_COMP_MASK 0xFFFFFFFF
#define TIMERS_COMP_LSB 0
#define TIMERS_COMP_WIDTH 0x00000020
#define TIMERS_COMP_RST 0x0
__INLINE uint32_t pwm_timer_tcomp__timers_comp__getf(void)
{
uint32_t localVal = PWM_TIMER_TCOMP_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief PWM_TIMER_LOADCOUNT2 register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 11:00 TIMER_LC2 0x0
* </pre>
*/
#define PWM_TIMER_LOADCOUNT2_REG(i) (* ((volatile uint32_t *)(0x40017DB0 + i*PWM_LOAD_CNT2_REG_SIZE)) )
#define PWM_TIMER_LOADCOUNT2_ADDR(i) (0x40017DB0 + i*PWM_LOAD_CNT2_REG_SIZE)
#define PWM_TIMER_LOADCOUNT2_OFFSET 0x000000B0
__INLINE uint32_t pwm_timer_loadcount2_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
return PWM_TIMER_LOADCOUNT2_REG(reg_idx);
}
__INLINE void pwm_timer_loadcount2_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 5);
PWM_TIMER_LOADCOUNT2_REG(reg_idx) = value;
}
// field definitions
#define TIMER_LC2_MASK 0x00000FFF
#define TIMER_LC2_LSB 0
#define TIMER_LC2_WIDTH 0x0000000C
#define TIMER_LC2_RST 0x0
__INLINE uint16_t pwm_timer_loadcount2__timer_lc2__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 5);
uint32_t localVal = PWM_TIMER_LOADCOUNT2_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000FFF) == 0);
return (localVal >> 0);
}
__INLINE void pwm_timer_loadcount2__timer_lc2__setf(uint32_t reg_idx, uint16_t timer_lc2)
{
ASSERT_ERR(reg_idx <= 5);
ASSERT_ERR(((timer_lc2 << 0) & ~0x00000FFF) == 0);
PWM_TIMER_LOADCOUNT2_REG(reg_idx) = timer_lc2 << 0;
}
#endif // _XC_REG_PWM_TIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_qdec.h
+665 -665
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_rf.h
+522 -483
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_rtc.h
+3058 -3059
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_spi.h
+1376 -1376
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_timer.h
+207 -207
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@@ -1,207 +1,207 @@
#ifndef _XC_REG_TIMER_H_
#define _XC_REG_TIMER_H_
#include <stdint.h>
#define XC_REG_TIMER_BASE_ADDR 0x40003000
#define XC_REG_TIMER_DECODING_MASK 0x0000001F
/**
* @brief TIMER_TLC register definition
*/
#define TIMER_TLC_REG(i) (*(volatile uint32_t *)(0x40003000 + timer_offset[i]))
#define TIMER_TLC_ADDR(i) (0x40003000 + timer_offset[i])
#define TIMER_TLC_OFFSET 0x00000000
__INLINE uint32_t timer_tlc_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TLC_REG(reg_idx);
}
__INLINE void timer_tlc_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 3);
TIMER_TLC_REG(reg_idx) = value;
}
/**
* @brief TIMER_TCV register definition
*/
#define TIMER_TCV_REG(i) (*(volatile uint32_t *)(0x40003004 + timer_offset[i]))
#define TIMER_TCV_ADDR(i) (0x40003004 + timer_offset[i])
#define TIMER_TCV_OFFSET 0x00000004
__INLINE uint32_t timer_tcv_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TCV_REG(reg_idx);
}
/**
* @brief TIMER_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 TIM 0
* 01 TMS 0
* 00 TES 0
* </pre>
*/
#define TIMER_TCR_REG(i) (*(volatile uint32_t *)(0x40003008 + timer_offset[i]))
#define TIMER_TCR_ADDR(i) (0x40003008 + timer_offset[i])
#define TIMER_TCR_OFFSET 0x00000008
__INLINE uint32_t timer_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TCR_REG(reg_idx);
}
__INLINE void timer_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 3);
TIMER_TCR_REG(reg_idx) = value;
}
// field definitions
#define TIM_BIT 0x00000004
#define TIM_POS 2
#define TMS_BIT 0x00000002
#define TMS_POS 1
#define TES_BIT 0x00000001
#define TES_POS 0
#define TIM_RST 0x0
#define TMS_RST 0x0
#define TES_RST 0x0
__INLINE void timer_tcr_pack(uint32_t reg_idx, uint8_t tim, uint8_t tms, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
TIMER_TCR_REG(reg_idx) = (tim << 2) | (tms << 1) | (tes << 0);
}
__INLINE void timer_tcr_unpack(uint32_t reg_idx, uint8_t* tim, uint8_t* tms, uint8_t* tes)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
*tim = (localVal & 0x00000004) >> 2;
*tms = (localVal & 0x00000002) >> 1;
*tes = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t timer_tcr__tim__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void timer_tcr__tim__setf(uint32_t reg_idx, uint8_t tim)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000004) | (tim << 2);
}
__INLINE uint8_t timer_tcr__tms__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void timer_tcr__tms__setf(uint32_t reg_idx, uint8_t tms)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000002) | (tms << 1);
}
__INLINE uint8_t timer_tcr__tes__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void timer_tcr__tes__setf(uint32_t reg_idx, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000001) | (tes << 0);
}
/**
* @brief TIMER_TIC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 INTR 0
* </pre>
*/
#define TIMER_TIC_REG(i) (*(volatile uint32_t *)(0x4000300C + timer_offset[i]))
#define TIMER_TIC_ADDR(i) (0x4000300C + timer_offset[i])
#define TIMER_TIC_OFFSET 0x0000000C
__INLINE uint32_t timer_tic_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TIC_REG(reg_idx);
}
// field definitions
#define INTR_BIT 0x00000001
#define INTR_POS 0
#define INTR_RST 0x0
__INLINE uint8_t timer_tic__intr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TIC_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief TIMER_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 STAT 0
* </pre>
*/
#define TIMER_TIS_REG(i) (*(volatile uint32_t *)(0x40003010 + timer_offset[i]))
#define TIMER_TIS_ADDR(i) (0x40003010 + timer_offset[i])
#define TIMER_TIS_OFFSET 0x00000010
__INLINE uint32_t timer_tis_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TIS_REG(reg_idx);
}
// field definitions
#define STAT_BIT 0x00000001
#define STAT_POS 0
#define STAT_RST 0x0
__INLINE uint8_t timer_tis__stat__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TIS_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_TIMER_H_
#ifndef _XC_REG_TIMER_H_
#define _XC_REG_TIMER_H_
#include <stdint.h>
#define XC_REG_TIMER_BASE_ADDR 0x40003000
#define XC_REG_TIMER_DECODING_MASK 0x0000001F
/**
* @brief TIMER_TLC register definition
*/
#define TIMER_TLC_REG(i) (*(volatile uint32_t *)(0x40003000 + timer_offset[i]))
#define TIMER_TLC_ADDR(i) (0x40003000 + timer_offset[i])
#define TIMER_TLC_OFFSET 0x00000000
__INLINE uint32_t timer_tlc_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TLC_REG(reg_idx);
}
__INLINE void timer_tlc_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 3);
TIMER_TLC_REG(reg_idx) = value;
}
/**
* @brief TIMER_TCV register definition
*/
#define TIMER_TCV_REG(i) (*(volatile uint32_t *)(0x40003004 + timer_offset[i]))
#define TIMER_TCV_ADDR(i) (0x40003004 + timer_offset[i])
#define TIMER_TCV_OFFSET 0x00000004
__INLINE uint32_t timer_tcv_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TCV_REG(reg_idx);
}
/**
* @brief TIMER_TCR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 TIM 0
* 01 TMS 0
* 00 TES 0
* </pre>
*/
#define TIMER_TCR_REG(i) (*(volatile uint32_t *)(0x40003008 + timer_offset[i]))
#define TIMER_TCR_ADDR(i) (0x40003008 + timer_offset[i])
#define TIMER_TCR_OFFSET 0x00000008
__INLINE uint32_t timer_tcr_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TCR_REG(reg_idx);
}
__INLINE void timer_tcr_set(uint32_t reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 3);
TIMER_TCR_REG(reg_idx) = value;
}
// field definitions
#define TIM_BIT 0x00000004
#define TIM_POS 2
#define TMS_BIT 0x00000002
#define TMS_POS 1
#define TES_BIT 0x00000001
#define TES_POS 0
#define TIM_RST 0x0
#define TMS_RST 0x0
#define TES_RST 0x0
__INLINE void timer_tcr_pack(uint32_t reg_idx, uint8_t tim, uint8_t tms, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
TIMER_TCR_REG(reg_idx) = (tim << 2) | (tms << 1) | (tes << 0);
}
__INLINE void timer_tcr_unpack(uint32_t reg_idx, uint8_t* tim, uint8_t* tms, uint8_t* tes)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
*tim = (localVal & 0x00000004) >> 2;
*tms = (localVal & 0x00000002) >> 1;
*tes = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t timer_tcr__tim__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000004) >> 2);
}
__INLINE void timer_tcr__tim__setf(uint32_t reg_idx, uint8_t tim)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tim << 2) & ~0x00000004) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000004) | (tim << 2);
}
__INLINE uint8_t timer_tcr__tms__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000002) >> 1);
}
__INLINE void timer_tcr__tms__setf(uint32_t reg_idx, uint8_t tms)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tms << 1) & ~0x00000002) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000002) | (tms << 1);
}
__INLINE uint8_t timer_tcr__tes__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TCR_REG(reg_idx);
return ((localVal & 0x00000001) >> 0);
}
__INLINE void timer_tcr__tes__setf(uint32_t reg_idx, uint8_t tes)
{
ASSERT_ERR(reg_idx <= 3);
ASSERT_ERR(((tes << 0) & ~0x00000001) == 0);
TIMER_TCR_REG(reg_idx) = (TIMER_TCR_REG(reg_idx) & ~0x00000001) | (tes << 0);
}
/**
* @brief TIMER_TIC register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 INTR 0
* </pre>
*/
#define TIMER_TIC_REG(i) (*(volatile uint32_t *)(0x4000300C + timer_offset[i]))
#define TIMER_TIC_ADDR(i) (0x4000300C + timer_offset[i])
#define TIMER_TIC_OFFSET 0x0000000C
__INLINE uint32_t timer_tic_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TIC_REG(reg_idx);
}
// field definitions
#define INTR_BIT 0x00000001
#define INTR_POS 0
#define INTR_RST 0x0
__INLINE uint8_t timer_tic__intr__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TIC_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief TIMER_TIS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 STAT 0
* </pre>
*/
#define TIMER_TIS_REG(i) (*(volatile uint32_t *)(0x40003010 + timer_offset[i]))
#define TIMER_TIS_ADDR(i) (0x40003010 + timer_offset[i])
#define TIMER_TIS_OFFSET 0x00000010
__INLINE uint32_t timer_tis_get(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
return TIMER_TIS_REG(reg_idx);
}
// field definitions
#define STAT_BIT 0x00000001
#define STAT_POS 0
#define STAT_RST 0x0
__INLINE uint8_t timer_tis__stat__getf(uint32_t reg_idx)
{
ASSERT_ERR(reg_idx <= 3);
uint32_t localVal = TIMER_TIS_REG(reg_idx);
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_TIMER_H_
component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_uart.h
+883 -883
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component/xc6xx_drivers/Drivers/CMSIS/Device/xc_m0_register/xc_reg_wdt.h
+270 -270
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@@ -1,270 +1,270 @@
#ifndef _XC_REG_WDT_H_
#define _XC_REG_WDT_H_
#include <stdint.h>
#define XC_REG_WDT_BASE_ADDR 0x40004000
#define XC_REG_WDT_DECODING_MASK 0x0000001F
/**
* @brief WDT_CR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04:02 WDT_RPL 0x0
* 01 WDT_RMOD 0
* 00 WDT_EN 0
* </pre>
*/
#define WDT_CR_REG (*(volatile uint32_t *)(0x40004000))
#define WDT_CR_ADDR 0x40004000
#define WDT_CR_OFFSET 0x00000000
__INLINE uint32_t wdt_cr_get(void)
{
return WDT_CR_REG;
}
__INLINE void wdt_cr_set(uint32_t value)
{
WDT_CR_REG = value;
}
// field definitions
#define WDT_RPL_MASK 0x0000001C
#define WDT_RPL_LSB 2
#define WDT_RPL_WIDTH 0x00000003
#define WDT_RMOD_BIT 0x00000002
#define WDT_RMOD_POS 1
#define WDT_EN_BIT 0x00000001
#define WDT_EN_POS 0
#define WDT_RPL_RST 0x0
#define WDT_RMOD_RST 0x0
#define WDT_EN_RST 0x0
__INLINE void wdt_cr_pack(uint8_t wdt_rpl, uint8_t wdt_rmod, uint8_t wdt_en)
{
ASSERT_ERR(((wdt_rpl << 2) & ~0x0000001C) == 0);
ASSERT_ERR(((wdt_rmod << 1) & ~0x00000002) == 0);
ASSERT_ERR(((wdt_en << 0) & ~0x00000001) == 0);
WDT_CR_REG = (wdt_rpl << 2) | (wdt_rmod << 1) | (wdt_en << 0);
}
__INLINE void wdt_cr_unpack(uint8_t* wdt_rpl, uint8_t* wdt_rmod, uint8_t* wdt_en)
{
uint32_t localVal = WDT_CR_REG;
*wdt_rpl = (localVal & 0x0000001C) >> 2;
*wdt_rmod = (localVal & 0x00000002) >> 1;
*wdt_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t wdt_cr__wdt_rpl__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x0000001C) >> 2);
}
__INLINE void wdt_cr__wdt_rpl__setf(uint8_t wdt_rpl)
{
ASSERT_ERR(((wdt_rpl << 2) & ~0x0000001C) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x0000001C) | (wdt_rpl << 2);
}
__INLINE uint8_t wdt_cr__wdt_rmod__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void wdt_cr__wdt_rmod__setf(uint8_t wdt_rmod)
{
ASSERT_ERR(((wdt_rmod << 1) & ~0x00000002) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x00000002) | (wdt_rmod << 1);
}
__INLINE uint8_t wdt_cr__wdt_en__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void wdt_cr__wdt_en__setf(uint8_t wdt_en)
{
ASSERT_ERR(((wdt_en << 0) & ~0x00000001) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x00000001) | (wdt_en << 0);
}
/**
* @brief WDT_TORR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03:00 WDT_TOP 0x0
* </pre>
*/
#define WDT_TORR_REG (*(volatile uint32_t *)(0x40004004))
#define WDT_TORR_ADDR 0x40004004
#define WDT_TORR_OFFSET 0x00000004
__INLINE uint32_t wdt_torr_get(void)
{
return WDT_TORR_REG;
}
__INLINE void wdt_torr_set(uint32_t value)
{
WDT_TORR_REG = value;
}
// field definitions
#define WDT_TOP_MASK 0x0000000F
#define WDT_TOP_LSB 0
#define WDT_TOP_WIDTH 0x00000004
#define WDT_TOP_RST 0x0
__INLINE uint8_t wdt_torr__wdt_top__getf(void)
{
uint32_t localVal = WDT_TORR_REG;
ASSERT_ERR((localVal & ~0x0000000F) == 0);
return (localVal >> 0);
}
__INLINE void wdt_torr__wdt_top__setf(uint8_t wdt_top)
{
ASSERT_ERR(((wdt_top << 0) & ~0x0000000F) == 0);
WDT_TORR_REG = wdt_top << 0;
}
/**
* @brief WDT_CCVR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 WDT_CCVR 0x0
* </pre>
*/
#define WDT_CCVR_REG (*(volatile uint32_t *)(0x40004008))
#define WDT_CCVR_ADDR 0x40004008
#define WDT_CCVR_OFFSET 0x00000008
__INLINE uint32_t wdt_ccvr_get(void)
{
return WDT_CCVR_REG;
}
__INLINE void wdt_ccvr_set(uint32_t value)
{
WDT_CCVR_REG = value;
}
// field definitions
#define WDT_CCVR_MASK 0xFFFFFFFF
#define WDT_CCVR_LSB 0
#define WDT_CCVR_WIDTH 0x00000020
#define WDT_CCVR_RST 0x0
__INLINE uint32_t wdt_ccvr__getf(void)
{
uint32_t localVal = WDT_CCVR_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief WDT_CRR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 WDT_CRR 0x0
* </pre>
*/
#define WDT_CRR_REG (*(volatile uint32_t *)(0x4000400C))
#define WDT_CRR_ADDR 0x4000400C
#define WDT_CRR_OFFSET 0x0000000C
__INLINE void wdt_crr_set(uint32_t value)
{
WDT_CRR_REG = value;
}
// field definitions
#define WDT_CRR_MASK 0x000000FF
#define WDT_CRR_LSB 0
#define WDT_CRR_WIDTH 0x00000008
#define WDT_CRR_RST 0x0
__INLINE void wdt_crr__setf(uint8_t wdt_crr)
{
ASSERT_ERR(((wdt_crr << 0) & ~0x000000FF) == 0);
WDT_CRR_REG = wdt_crr << 0;
}
/**
* @brief WDT_STAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 WDT_STAT 0
* </pre>
*/
#define WDT_STAT_REG (*(volatile uint32_t *)(0x40004010))
#define WDT_STAT_ADDR 0x40004010
#define WDT_STAT_OFFSET 0x00000010
__INLINE uint32_t wdt_stat_get(void)
{
return WDT_STAT_REG;
}
// field definitions
#define WDT_STAT_BIT 0x00000001
#define WDT_STAT_POS 0
#define WDT_STAT_RST 0x0
__INLINE uint8_t wdt_stat__getf(void)
{
uint32_t localVal = WDT_STAT_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief WDT_ICR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 WDT_ICR 0
* </pre>
*/
#define WDT_ICR_REG (*(volatile uint32_t *)(0x40004014))
#define WDT_ICR_ADDR 0x40004014
#define WDT_ICR_OFFSET 0x00000014
__INLINE uint32_t wdt_icr_get(void)
{
return WDT_ICR_REG;
}
// field definitions
#define WDT_ICR_BIT 0x00000001
#define WDT_ICR_POS 0
#define WDT_ICR_RST 0x0
__INLINE uint8_t wdt_icr__getf(void)
{
uint32_t localVal = WDT_ICR_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_WDT_H_
#ifndef _XC_REG_WDT_H_
#define _XC_REG_WDT_H_
#include <stdint.h>
#define XC_REG_WDT_BASE_ADDR 0x40004000
#define XC_REG_WDT_DECODING_MASK 0x0000001F
/**
* @brief WDT_CR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 04:02 WDT_RPL 0x0
* 01 WDT_RMOD 0
* 00 WDT_EN 0
* </pre>
*/
#define WDT_CR_REG (*(volatile uint32_t *)(0x40004000))
#define WDT_CR_ADDR 0x40004000
#define WDT_CR_OFFSET 0x00000000
__INLINE uint32_t wdt_cr_get(void)
{
return WDT_CR_REG;
}
__INLINE void wdt_cr_set(uint32_t value)
{
WDT_CR_REG = value;
}
// field definitions
#define WDT_RPL_MASK 0x0000001C
#define WDT_RPL_LSB 2
#define WDT_RPL_WIDTH 0x00000003
#define WDT_RMOD_BIT 0x00000002
#define WDT_RMOD_POS 1
#define WDT_EN_BIT 0x00000001
#define WDT_EN_POS 0
#define WDT_RPL_RST 0x0
#define WDT_RMOD_RST 0x0
#define WDT_EN_RST 0x0
__INLINE void wdt_cr_pack(uint8_t wdt_rpl, uint8_t wdt_rmod, uint8_t wdt_en)
{
ASSERT_ERR(((wdt_rpl << 2) & ~0x0000001C) == 0);
ASSERT_ERR(((wdt_rmod << 1) & ~0x00000002) == 0);
ASSERT_ERR(((wdt_en << 0) & ~0x00000001) == 0);
WDT_CR_REG = (wdt_rpl << 2) | (wdt_rmod << 1) | (wdt_en << 0);
}
__INLINE void wdt_cr_unpack(uint8_t* wdt_rpl, uint8_t* wdt_rmod, uint8_t* wdt_en)
{
uint32_t localVal = WDT_CR_REG;
*wdt_rpl = (localVal & 0x0000001C) >> 2;
*wdt_rmod = (localVal & 0x00000002) >> 1;
*wdt_en = (localVal & 0x00000001) >> 0;
}
__INLINE uint8_t wdt_cr__wdt_rpl__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x0000001C) >> 2);
}
__INLINE void wdt_cr__wdt_rpl__setf(uint8_t wdt_rpl)
{
ASSERT_ERR(((wdt_rpl << 2) & ~0x0000001C) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x0000001C) | (wdt_rpl << 2);
}
__INLINE uint8_t wdt_cr__wdt_rmod__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x00000002) >> 1);
}
__INLINE void wdt_cr__wdt_rmod__setf(uint8_t wdt_rmod)
{
ASSERT_ERR(((wdt_rmod << 1) & ~0x00000002) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x00000002) | (wdt_rmod << 1);
}
__INLINE uint8_t wdt_cr__wdt_en__getf(void)
{
uint32_t localVal = WDT_CR_REG;
return ((localVal & 0x00000001) >> 0);
}
__INLINE void wdt_cr__wdt_en__setf(uint8_t wdt_en)
{
ASSERT_ERR(((wdt_en << 0) & ~0x00000001) == 0);
WDT_CR_REG = (WDT_CR_REG & ~0x00000001) | (wdt_en << 0);
}
/**
* @brief WDT_TORR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03:00 WDT_TOP 0x0
* </pre>
*/
#define WDT_TORR_REG (*(volatile uint32_t *)(0x40004004))
#define WDT_TORR_ADDR 0x40004004
#define WDT_TORR_OFFSET 0x00000004
__INLINE uint32_t wdt_torr_get(void)
{
return WDT_TORR_REG;
}
__INLINE void wdt_torr_set(uint32_t value)
{
WDT_TORR_REG = value;
}
// field definitions
#define WDT_TOP_MASK 0x0000000F
#define WDT_TOP_LSB 0
#define WDT_TOP_WIDTH 0x00000004
#define WDT_TOP_RST 0x0
__INLINE uint8_t wdt_torr__wdt_top__getf(void)
{
uint32_t localVal = WDT_TORR_REG;
ASSERT_ERR((localVal & ~0x0000000F) == 0);
return (localVal >> 0);
}
__INLINE void wdt_torr__wdt_top__setf(uint8_t wdt_top)
{
ASSERT_ERR(((wdt_top << 0) & ~0x0000000F) == 0);
WDT_TORR_REG = wdt_top << 0;
}
/**
* @brief WDT_CCVR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 WDT_CCVR 0x0
* </pre>
*/
#define WDT_CCVR_REG (*(volatile uint32_t *)(0x40004008))
#define WDT_CCVR_ADDR 0x40004008
#define WDT_CCVR_OFFSET 0x00000008
__INLINE uint32_t wdt_ccvr_get(void)
{
return WDT_CCVR_REG;
}
__INLINE void wdt_ccvr_set(uint32_t value)
{
WDT_CCVR_REG = value;
}
// field definitions
#define WDT_CCVR_MASK 0xFFFFFFFF
#define WDT_CCVR_LSB 0
#define WDT_CCVR_WIDTH 0x00000020
#define WDT_CCVR_RST 0x0
__INLINE uint32_t wdt_ccvr__getf(void)
{
uint32_t localVal = WDT_CCVR_REG;
ASSERT_ERR((localVal & ~0xFFFFFFFF) == 0);
return (localVal >> 0);
}
/**
* @brief WDT_CRR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 WDT_CRR 0x0
* </pre>
*/
#define WDT_CRR_REG (*(volatile uint32_t *)(0x4000400C))
#define WDT_CRR_ADDR 0x4000400C
#define WDT_CRR_OFFSET 0x0000000C
__INLINE void wdt_crr_set(uint32_t value)
{
WDT_CRR_REG = value;
}
// field definitions
#define WDT_CRR_MASK 0x000000FF
#define WDT_CRR_LSB 0
#define WDT_CRR_WIDTH 0x00000008
#define WDT_CRR_RST 0x0
__INLINE void wdt_crr__setf(uint8_t wdt_crr)
{
ASSERT_ERR(((wdt_crr << 0) & ~0x000000FF) == 0);
WDT_CRR_REG = wdt_crr << 0;
}
/**
* @brief WDT_STAT register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 WDT_STAT 0
* </pre>
*/
#define WDT_STAT_REG (*(volatile uint32_t *)(0x40004010))
#define WDT_STAT_ADDR 0x40004010
#define WDT_STAT_OFFSET 0x00000010
__INLINE uint32_t wdt_stat_get(void)
{
return WDT_STAT_REG;
}
// field definitions
#define WDT_STAT_BIT 0x00000001
#define WDT_STAT_POS 0
#define WDT_STAT_RST 0x0
__INLINE uint8_t wdt_stat__getf(void)
{
uint32_t localVal = WDT_STAT_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
/**
* @brief WDT_ICR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 WDT_ICR 0
* </pre>
*/
#define WDT_ICR_REG (*(volatile uint32_t *)(0x40004014))
#define WDT_ICR_ADDR 0x40004014
#define WDT_ICR_OFFSET 0x00000014
__INLINE uint32_t wdt_icr_get(void)
{
return WDT_ICR_REG;
}
// field definitions
#define WDT_ICR_BIT 0x00000001
#define WDT_ICR_POS 0
#define WDT_ICR_RST 0x0
__INLINE uint8_t wdt_icr__getf(void)
{
uint32_t localVal = WDT_ICR_REG;
ASSERT_ERR((localVal & ~0x00000001) == 0);
return (localVal >> 0);
}
#endif // _XC_REG_WDT_H_