Stair56E UART project
This commit is contained in:
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;/*****************************************************************************
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; * @file: startup_xinc.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
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; * Device xinc.
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; *****************************************************************************/
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Stack_Size EQU 0x00000600
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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; ToDo: Add here the vectors for the device specific external interrupts handler
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DCD 0 ; 0 BLE Handler
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DCD DMAS_Handler ; 1
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DCD CPR_Handler ; 2
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DCD GPIO_Handler ; 3
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DCD RTC_Handler ; 4
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DCD TIMER0_Handler ; 5
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DCD TIMER1_Handler
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DCD TIMER2_Handler
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DCD TIMER3_Handler
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DCD WDT_Handler
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DCD I2C_Handler
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DCD UART0_Handler
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DCD UART1_Handler
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DCD SPI0_Handler
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DCD SPI1_Handler
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DCD 0
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DCD 0
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DCD GADC_Handler ; 17
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DCD 0 ; 18
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DCD 0 ; 19
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DCD 0 ; 20
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DCD 0 ; 21
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DCD RF24G_Handler ; 22
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DCD PWM_Handler ; 23
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DCD BOR_Handler ; 24
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DCD 0 ; 25
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DCD 0 ; 26
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DCD AOTIMER0_Handler ; 27
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DCD AOTIMER1_Handler ; 28
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DCD CMP_Handler ; 29
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DCD FMC_Handler ; 30
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DCD CAN_Handler ; 31
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR r0, =0x4000013C ; remap
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LDR r1, =0x10000001
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STR r1, [r0]
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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;EXPORT BLE_Handler [WEAK]
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EXPORT DMAS_Handler [WEAK]
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EXPORT CPR_Handler [WEAK]
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EXPORT GPIO_Handler [WEAK]
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EXPORT RTC_Handler [WEAK]
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EXPORT TIMER0_Handler [WEAK]
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EXPORT TIMER1_Handler [WEAK]
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EXPORT TIMER2_Handler [WEAK]
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EXPORT TIMER3_Handler [WEAK]
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EXPORT WDT_Handler [WEAK]
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EXPORT I2C_Handler [WEAK]
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EXPORT UART0_Handler [WEAK]
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EXPORT UART1_Handler [WEAK]
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EXPORT SPI0_Handler [WEAK]
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EXPORT SPI1_Handler [WEAK]
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;EXPORT KBS_Handler [WEAK]
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;EXPORT QDEC_Handler [WEAK]
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EXPORT GADC_Handler [WEAK]
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EXPORT AOTIMER0_Handler [WEAK]
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EXPORT AOTIMER1_Handler [WEAK]
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EXPORT CMP_Handler [WEAK]
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EXPORT FMC_Handler [WEAK]
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EXPORT CAN_Handler [WEAK]
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;EXPORT SIM_Handler [WEAK]
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;EXPORT AES_Handler [WEAK]
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EXPORT PendSV_Handler [WEAK]
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EXPORT SysTick_Handler [WEAK]
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EXPORT RF24G_Handler [WEAK]
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EXPORT PWM_Handler [WEAK]
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EXPORT BOR_Handler [WEAK]
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PendSV_Handler
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SysTick_Handler
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;BLE_Handler
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DMAS_Handler
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CPR_Handler
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GPIO_Handler
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RTC_Handler
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TIMER0_Handler
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TIMER1_Handler
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TIMER2_Handler
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TIMER3_Handler
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WDT_Handler
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I2C_Handler
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UART0_Handler
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UART1_Handler
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SPI0_Handler
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SPI1_Handler
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;KBS_Handler
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;QDEC_Handler
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GADC_Handler
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;SIM_Handler
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;AES_Handler
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AOTIMER0_Handler
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AOTIMER1_Handler
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CMP_Handler
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FMC_Handler
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CAN_Handler
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RF24G_Handler
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PWM_Handler
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BOR_Handler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, = (Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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END
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@@ -0,0 +1,232 @@
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/*!
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* \file system_it_xinc.c
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*
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* \brief Target system interruption implementation
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*
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* \copyright Revised BSD License, see section \ref LICENSE.
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*
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* \code
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*
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* _ __ _ ________ _
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* | |/ /(_)___ / ____/ /_ (_)___
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* | // / __ \/ / / __ \/ / __ \
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* / |/ / / / / /___/ / / / / /_/ /
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* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
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* /_/
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* (C) 2022-2025 XinChip
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*
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* \endcode
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*
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* \author ( XinChip ) Alex-J
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*
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* \author ( XinChip )
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*/
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/*-----------------------------------------------------------------------------------
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INCLUDE HEADE FILES
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------------------------------------------------------------------------------------*/
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#include "system_it_xinc.h"
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/*------------------------------------------------------------------------------------
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Func Prototype
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-------------------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------------
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Functions
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-------------------------------------------------------------------------------------*/
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/**
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****************************************************************************************
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* @brief This function handles NMI exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void NMI_Handler(void)
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{
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/* USER CODE BEGIN NonMaskableInt_IRQn */
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DEBUG("%s\n", __func__);
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/* USER CODE END NonMaskableInt_IRQn */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Hard Fault exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void HardFault_Handler(void)
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{
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/* USER CODE BEGIN HardFault_IRQn */
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DEBUG("%s\n", __func__);
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/* USER CODE END HardFault_IRQn */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Memory Manage exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void MemManage_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Bus Fault exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void BusFault_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles Usage Fault exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void UsageFault_Handler(void)
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{
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
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while (1)
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{
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}
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}
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/**
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****************************************************************************************
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* @brief This function handles SVCall exception.
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*
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* @param[in]
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* @param[in]
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****************************************************************************************
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*/
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void SVC_Handler(void)
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{
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/* USER CODE BEGIN SVCall_IRQn */
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DEBUG("%s\n", __func__);
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/* USER CODE END SVCall_IRQn */
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while (1)
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{
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|
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}
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}
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|
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/**
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****************************************************************************************
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* @brief This function handles Debug Monitor exception.
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*
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* @param[in]
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* @param[in]
|
||||
****************************************************************************************
|
||||
*/
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void DebugMon_Handler(void)
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{
|
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/* USER CODE BEGIN */
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DEBUG("%s\n", __func__);
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/* USER CODE END */
|
||||
while (1)
|
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{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************
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||||
* @brief This function handles PendSVC exception.
|
||||
*
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||||
* @param[in]
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||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
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void PendSV_Handler(void)
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{
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/* USER CODE BEGIN PendSV_IRQn */
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DEBUG("%s\n", __func__);
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||||
/* USER CODE END PendSV_IRQn */
|
||||
while (1)
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/****************************** Hard Fault Handler Functions *******************************/
|
||||
/*------------------------------------------------------------------------------------
|
||||
Private Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
void HardFault_Handler_c(unsigned int * HardFault_args)
|
||||
{
|
||||
/*栈帧里面内容：*/
|
||||
unsigned int stack_r0; //压栈的 R0
|
||||
unsigned int stack_r1; //压栈的 R1
|
||||
unsigned int stack_r2; //压栈的 R2
|
||||
unsigned int stack_r3; //压栈的 R3
|
||||
unsigned int stack_r12; //压栈的 R12
|
||||
unsigned int stack_lr; //压栈的 lr
|
||||
unsigned int stack_pc; //压栈的 pc
|
||||
unsigned int stack_psr; //压栈的 psr
|
||||
|
||||
stack_r0 = ((unsigned int)HardFault_args[0]);
|
||||
stack_r1 = ((unsigned int)HardFault_args[1]);
|
||||
stack_r2 = ((unsigned int)HardFault_args[2]);
|
||||
stack_r3 = ((unsigned int)HardFault_args[3]);
|
||||
stack_r12 = ((unsigned int)HardFault_args[4]);
|
||||
stack_lr = ((unsigned int)HardFault_args[5]);
|
||||
stack_pc = ((unsigned int)HardFault_args[6]);
|
||||
stack_psr = ((unsigned int)HardFault_args[7]);
|
||||
|
||||
DEBUG("----%s----\n", __func__);
|
||||
DEBUG("R0=%x\n",stack_r0);
|
||||
DEBUG("R1=%x\n",stack_r1);
|
||||
DEBUG("R2=%x\n",stack_r2);
|
||||
DEBUG("R3=%x\n",stack_r3);
|
||||
DEBUG("R12=%x\n",stack_r12);
|
||||
DEBUG("LR[R14]=%x\n",stack_lr);
|
||||
DEBUG("PC[R15]=%x\n",stack_pc);
|
||||
DEBUG("PSR=%x\n",stack_psr);
|
||||
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
|
||||
DEBUG("---------------------------\n");
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*******************************************************************************************/
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
/*!
|
||||
* \file system_it_xinc.h
|
||||
*
|
||||
* \brief The header of system_it_xinc.c
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __SYSTEM_IT_XINC_H__
|
||||
#define __SYSTEM_IT_XINC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "xc6xxx.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
void NMI_Handler( void );
|
||||
void HardFault_Handler( void );
|
||||
void MemManage_Handler( void );
|
||||
void BusFault_Handler( void );
|
||||
void UsageFault_Handler( void );
|
||||
void SVC_Handler( void );
|
||||
void DebugMon_Handler( void );
|
||||
void PendSV_Handler( void );
|
||||
|
||||
void HardFault_Handler_c(unsigned int * HardFault_args);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_IT_XINC_H__ */
|
||||
|
||||
@@ -0,0 +1,120 @@
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system
|
||||
*
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include <stdio.h>
|
||||
|
||||
#include "xc6xxx.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
#define __DEBUG_OUT_PORT 0
|
||||
#define readl(addr) (*(volatile unsigned int *) (addr))
|
||||
#define writel(addr, value) (*(volatile unsigned int *) (addr) = (value))
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
#define VECTOR_NUM 48
|
||||
|
||||
void set_vector(void)
|
||||
{
|
||||
#if (USE_XIP == 1)
|
||||
__disable_irq();
|
||||
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
|
||||
*_vector_table = (uint32_t *)(0x10000000);
|
||||
i < VECTOR_NUM; i++) // copy vertor table
|
||||
{
|
||||
_vector_table[i] = *Pvector++;
|
||||
}
|
||||
|
||||
*((volatile unsigned int *)(0x4000013C)) =
|
||||
0x10000001; // inter vertor table remap
|
||||
__enable_irq();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void WDT_ResetInit(void)
|
||||
{
|
||||
cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
|
||||
|
||||
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
|
||||
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
|
||||
|
||||
cpr_rstctl_wdtrst_mask_set(
|
||||
(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
|
||||
|
||||
cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
|
||||
wdt_cr__wdt_en__setf(DISABLE);
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
|
||||
WDT_ResetInit();
|
||||
|
||||
#if (USE_XIP == 1)
|
||||
|
||||
set_vector();
|
||||
#endif
|
||||
writel(0x40000040, readl(0x40000040) | (0x01 << 4) | 0xFFFF0000);
|
||||
|
||||
}
|
||||
|
||||
__RAM_CODE int sendchar(int c)
|
||||
{
|
||||
unsigned int status;
|
||||
#if (__DEBUG_OUT_PORT == 1)
|
||||
for (;;) {
|
||||
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
|
||||
status &= 0x20;
|
||||
if (status == 0x20)
|
||||
break;
|
||||
}
|
||||
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
|
||||
return (1);
|
||||
#else
|
||||
for (;;) {
|
||||
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
|
||||
status &= 0x20;
|
||||
if (status == 0x20)
|
||||
break;
|
||||
}
|
||||
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
|
||||
return (1);
|
||||
#endif
|
||||
}
|
||||
|
||||
struct __FILE
|
||||
{
|
||||
int handle; /* Add whatever you need here */
|
||||
};
|
||||
|
||||
FILE __stdout;
|
||||
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
|
||||
|
||||
int ferror(FILE *f)
|
||||
{
|
||||
/* Your implementation of ferror */
|
||||
return EOF;
|
||||
}
|
||||
|
||||
void _ttywrch(int ch) { sendchar(ch); }
|
||||
|
||||
void _sys_exit(int return_code)
|
||||
{
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
@@ -0,0 +1,256 @@
|
||||
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_xinc.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
|
||||
; * Device xinc.
|
||||
; *****************************************************************************/
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; ToDo: Add here the vectors for the device specific external interrupts handler
|
||||
DCD BLE_Handler ; 0
|
||||
DCD DMA_Handler ; 1
|
||||
DCD CPR_Handler ; 2
|
||||
DCD GPIO_Handler ; 3
|
||||
DCD RTC_Handler ; 4
|
||||
DCD TIMER0_Handler ; 5
|
||||
DCD TIMER1_Handler ; 6
|
||||
DCD TIMER2_Handler ; 7
|
||||
DCD TIMER3_Handler ; 8
|
||||
DCD WDT_Handler ; 9
|
||||
DCD I2C_Handler ; 10
|
||||
DCD UART0_Handler ; 11
|
||||
DCD UART1_Handler ; 12
|
||||
DCD SPI0_Handler ; 13
|
||||
DCD SPI1_Handler ; 14
|
||||
DCD 0 ; 15
|
||||
DCD 0 ; 16
|
||||
DCD GADC_Handler ; 17
|
||||
DCD PWM_Handler ; 18
|
||||
DCD AES_Handler ; 19
|
||||
DCD USB_Handler ; 20
|
||||
DCD AUDIO_Handler ; 21
|
||||
DCD RF24G_Handler ; 22
|
||||
DCD SPI2_Handler ; 23
|
||||
DCD 0 ; 24
|
||||
DCD UART2_Handler ; 25
|
||||
DCD I2S_Handler ; 26
|
||||
DCD AOTIMER0_Handler ; 27
|
||||
DCD AOTIMER1_Handler ; 28
|
||||
DCD CMP_Handler ; 29
|
||||
DCD FMC_Handler ; 30
|
||||
DCD CAN_Handler ; 31
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR r0, =0x4000013C ; remap
|
||||
LDR r1, =0x10000001
|
||||
STR r1, [r0]
|
||||
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
IMPORT HardFault_Handler_c ;函数声明
|
||||
movs r0, #4 ;判断主栈指针还是进程栈指针
|
||||
mov r1, lr
|
||||
tst r0, r1
|
||||
beq hf_used_msp ;如果是主栈指针
|
||||
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
|
||||
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
|
||||
bx r1
|
||||
hf_used_msp
|
||||
mrs r0, msp ;把主栈指针地址赋给 R0
|
||||
ldr r1, =HardFault_Handler_c
|
||||
bx r1
|
||||
;EXPORT HardFault_Handler [WEAK]
|
||||
;B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT BLE_Handler [WEAK]
|
||||
EXPORT DMA_Handler [WEAK]
|
||||
EXPORT CPR_Handler [WEAK]
|
||||
EXPORT GPIO_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT TIMER0_Handler [WEAK]
|
||||
EXPORT TIMER1_Handler [WEAK]
|
||||
EXPORT TIMER2_Handler [WEAK]
|
||||
EXPORT TIMER3_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT I2C_Handler [WEAK]
|
||||
EXPORT UART0_Handler [WEAK]
|
||||
EXPORT UART1_Handler [WEAK]
|
||||
EXPORT SPI0_Handler [WEAK]
|
||||
EXPORT SPI1_Handler [WEAK]
|
||||
;EXPORT KBS_Handler [WEAK]
|
||||
;EXPORT QDEC_Handler [WEAK]
|
||||
EXPORT GADC_Handler [WEAK]
|
||||
EXPORT PWM_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
|
||||
EXPORT USB_Handler [WEAK];20
|
||||
EXPORT AUDIO_Handler [WEAK];21
|
||||
EXPORT RF24G_Handler [WEAK];22
|
||||
EXPORT SPI2_Handler [WEAK];23
|
||||
;EXPORT MPU_Handler [WEAK];24
|
||||
EXPORT UART2_Handler [WEAK];25
|
||||
EXPORT I2S_Handler [WEAK];26
|
||||
EXPORT AOTIMER0_Handler [WEAK];27
|
||||
EXPORT AOTIMER1_Handler [WEAK];28
|
||||
EXPORT CMP_Handler [WEAK];29
|
||||
EXPORT FMC_Handler [WEAK];30
|
||||
EXPORT CAN_Handler [WEAK];31
|
||||
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
BLE_Handler
|
||||
RF24G_Handler
|
||||
DMA_Handler
|
||||
CPR_Handler
|
||||
GPIO_Handler
|
||||
RTC_Handler
|
||||
TIMER0_Handler
|
||||
TIMER1_Handler
|
||||
TIMER2_Handler
|
||||
TIMER3_Handler
|
||||
WDT_Handler
|
||||
I2C_Handler
|
||||
I2S_Handler
|
||||
UART0_Handler
|
||||
UART1_Handler
|
||||
UART2_Handler
|
||||
SPI0_Handler
|
||||
SPI1_Handler
|
||||
SPI2_Handler
|
||||
;KBS_Handler
|
||||
;QDEC_Handler
|
||||
GADC_Handler
|
||||
PWM_Handler
|
||||
AUDIO_Handler
|
||||
;SIM_Handler
|
||||
AES_Handler
|
||||
AOTIMER0_Handler
|
||||
AOTIMER1_Handler
|
||||
CMP_Handler
|
||||
FMC_Handler
|
||||
CAN_Handler
|
||||
USB_Handler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
@@ -0,0 +1,256 @@
|
||||
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_xinc.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
|
||||
; * Device xinc.
|
||||
; *****************************************************************************/
|
||||
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; ToDo: Add here the vectors for the device specific external interrupts handler
|
||||
DCD BLE_Handler ; 0
|
||||
DCD DMA_Handler ; 1
|
||||
DCD CPR_Handler ; 2
|
||||
DCD GPIO_Handler ; 3
|
||||
DCD RTC_Handler ; 4
|
||||
DCD TIMER0_Handler ; 5
|
||||
DCD TIMER1_Handler ; 6
|
||||
DCD TIMER2_Handler ; 7
|
||||
DCD TIMER3_Handler ; 8
|
||||
DCD WDT_Handler ; 9
|
||||
DCD I2C_Handler ; 10
|
||||
DCD UART0_Handler ; 11
|
||||
DCD UART1_Handler ; 12
|
||||
DCD SPI0_Handler ; 13
|
||||
DCD SPI1_Handler ; 14
|
||||
DCD 0 ; 15
|
||||
DCD 0 ; 16
|
||||
DCD GADC_Handler ; 17
|
||||
DCD PWM_Handler ; 18
|
||||
DCD AES_Handler ; 19
|
||||
DCD USB_Handler ; 20
|
||||
DCD AUDIO_Handler ; 21
|
||||
DCD RF24G_Handler ; 22
|
||||
DCD SPI2_Handler ; 23
|
||||
DCD 0 ; 24
|
||||
DCD UART2_Handler ; 25
|
||||
DCD I2S_Handler ; 26
|
||||
DCD AOTIMER0_Handler ; 27
|
||||
DCD AOTIMER1_Handler ; 28
|
||||
DCD CMP_Handler ; 29
|
||||
DCD FMC_Handler ; 30
|
||||
DCD CAN_Handler ; 31
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR r0, =0x4000013C ; remap
|
||||
LDR r1, =0x10000001
|
||||
STR r1, [r0]
|
||||
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
IMPORT HardFault_Handler_c ;函数声明
|
||||
movs r0, #4 ;判断主栈指针还是进程栈指针
|
||||
mov r1, lr
|
||||
tst r0, r1
|
||||
beq hf_used_msp ;如果是主栈指针
|
||||
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
|
||||
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
|
||||
bx r1
|
||||
hf_used_msp
|
||||
mrs r0, msp ;把主栈指针地址赋给 R0
|
||||
ldr r1, =HardFault_Handler_c
|
||||
bx r1
|
||||
;EXPORT HardFault_Handler [WEAK]
|
||||
;B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT BLE_Handler [WEAK]
|
||||
EXPORT DMA_Handler [WEAK]
|
||||
EXPORT CPR_Handler [WEAK]
|
||||
EXPORT GPIO_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT TIMER0_Handler [WEAK]
|
||||
EXPORT TIMER1_Handler [WEAK]
|
||||
EXPORT TIMER2_Handler [WEAK]
|
||||
EXPORT TIMER3_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT I2C_Handler [WEAK]
|
||||
EXPORT UART0_Handler [WEAK]
|
||||
EXPORT UART1_Handler [WEAK]
|
||||
EXPORT SPI0_Handler [WEAK]
|
||||
EXPORT SPI1_Handler [WEAK]
|
||||
;EXPORT KBS_Handler [WEAK]
|
||||
;EXPORT QDEC_Handler [WEAK]
|
||||
EXPORT GADC_Handler [WEAK]
|
||||
EXPORT PWM_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
|
||||
EXPORT USB_Handler [WEAK];20
|
||||
EXPORT AUDIO_Handler [WEAK];21
|
||||
EXPORT RF24G_Handler [WEAK];22
|
||||
EXPORT SPI2_Handler [WEAK];23
|
||||
;EXPORT MPU_Handler [WEAK];24
|
||||
EXPORT UART2_Handler [WEAK];25
|
||||
EXPORT I2S_Handler [WEAK];26
|
||||
EXPORT AOTIMER0_Handler [WEAK];27
|
||||
EXPORT AOTIMER1_Handler [WEAK];28
|
||||
EXPORT CMP_Handler [WEAK];29
|
||||
EXPORT FMC_Handler [WEAK];30
|
||||
EXPORT CAN_Handler [WEAK];31
|
||||
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
BLE_Handler
|
||||
RF24G_Handler
|
||||
DMA_Handler
|
||||
CPR_Handler
|
||||
GPIO_Handler
|
||||
RTC_Handler
|
||||
TIMER0_Handler
|
||||
TIMER1_Handler
|
||||
TIMER2_Handler
|
||||
TIMER3_Handler
|
||||
WDT_Handler
|
||||
I2C_Handler
|
||||
I2S_Handler
|
||||
UART0_Handler
|
||||
UART1_Handler
|
||||
UART2_Handler
|
||||
SPI0_Handler
|
||||
SPI1_Handler
|
||||
SPI2_Handler
|
||||
;KBS_Handler
|
||||
;QDEC_Handler
|
||||
GADC_Handler
|
||||
PWM_Handler
|
||||
AUDIO_Handler
|
||||
;SIM_Handler
|
||||
AES_Handler
|
||||
AOTIMER0_Handler
|
||||
AOTIMER1_Handler
|
||||
CMP_Handler
|
||||
FMC_Handler
|
||||
CAN_Handler
|
||||
USB_Handler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
END
|
||||
@@ -0,0 +1,18 @@
|
||||
#ifndef __APP_64M__
|
||||
#define __APP_64M__
|
||||
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
|
||||
#define __write_hw_reg32(reg, val) ((*reg) = (val))
|
||||
#define __read_hw_reg32(reg, val) ((val) = (*reg))
|
||||
#define CPR_CTLAPBCLKEN_GRCTL ((volatile unsigned *)(0x40000000 + 0x070))
|
||||
#define CPR_AOCLKEN_GRCTL ((volatile unsigned *)(0x40002400 + 0x7C))
|
||||
#define AO_GPIO_MODE ((volatile unsigned *)(0x40002000 + 0x0044))
|
||||
#define AO_GPIO_CTL ((volatile unsigned *)(0x40002000 + 0x0048))
|
||||
|
||||
void use_64m_crtstal_init(void);
|
||||
void rf_64M_set_rx_channel(uint16_t channel);
|
||||
void rf_64M_set_tx_channel(uint16_t channel);
|
||||
void testpin_64M_config(void);
|
||||
void Init_rtc_gpio(uint32_t num, uint8_t inter_mode);
|
||||
#endif //__APP_64M__
|
||||
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* @Descripttion:
|
||||
* @version:
|
||||
* @Author: sueRimn
|
||||
* @Date: 2023-12-12 14:23:55
|
||||
* @LastEditors: sueRimn
|
||||
* @LastEditTime: 2024-06-07 13:46:09
|
||||
*/
|
||||
/*!
|
||||
* \file main.h
|
||||
*
|
||||
* \brief The head file of main.c
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MAIN_H__
|
||||
#define __MAIN_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "rf_config.h"
|
||||
#include "xc6xxx.h"
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
#include "rf_compatible_normal.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
#define DEBUG_LOG
|
||||
|
||||
#define SEND_TIMERMS_CNT 7
|
||||
#define RECV_TIMERMS_OUT (7 + SEND_TIMERMS_CNT)
|
||||
#define XC_SEND_NUM 1000U
|
||||
|
||||
#define RF_TX_TIMERx TIMER0_IDX
|
||||
#define RF_RX_TIMERx TIMER0_IDX
|
||||
|
||||
#define RF_CONFIRMED_VALUE 5
|
||||
|
||||
#define GPIO_TEST 1
|
||||
#define TEST_GPIO_1 GPIO_1
|
||||
#if XC62XX
|
||||
#define TEST_GPIO_2 GPIO_0
|
||||
#else
|
||||
#define TEST_GPIO_2 GPIO_21
|
||||
#endif
|
||||
/*------------------------------------------------------------------------------------
|
||||
TypeDef
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Global Variables
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
extern bool rf_send_timer_flag;
|
||||
/*------------------------------------------------------------------------------------
|
||||
Exported Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
void rf_buff_info(uint8_t *buff, uint16_t len);
|
||||
void rf_2M_reg_info(void);
|
||||
void rf_dump_log(void);
|
||||
uint8_t rf_data_config(uint8_t *buff, uint16_t len);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MAIN_H__ */
|
||||
@@ -0,0 +1,25 @@
|
||||
#ifndef __RF_COMPATIBLE_NORMAL__
|
||||
#define __RF_COMPATIBLE_NORMAL__
|
||||
#include "rf_config.h"
|
||||
#include "xc6xxx_rf_2_4g.h"
|
||||
#include "xc_software_crc.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define RF_ADDR_LEN XINCX_RF_TX_ADDR_WIDTH // 5U
|
||||
#define RF_RECV_EXTEN_LEN 3U
|
||||
#define RF_MAX_RECV_LEN 60U
|
||||
#define RF_CRC_INIT_VALUE 0xFFFF
|
||||
#define PANCHIP_WHITEN_INIT_VAL (0x7F)
|
||||
|
||||
extern uint16_t rf_addr_crc;
|
||||
extern uint8_t panchip_addr_whiten;
|
||||
extern uint8_t addr_buff[5];
|
||||
|
||||
void rf_addr_map(uint8_t *addr_buff);
|
||||
uint16_t rf_get_addr_crc(void);
|
||||
uint8_t rf_recv_addr(void);
|
||||
void rf_compatible_config(void);
|
||||
uint32_t rf_rx_normal_manage(void);
|
||||
uint32_t rf_tx_normal_manage(uint8_t *buff, uint8_t length);
|
||||
|
||||
#endif //__RF_COMPATIBLE_NORMAL__
|
||||
@@ -0,0 +1,585 @@
|
||||
#ifndef SDK_CONFIG_H
|
||||
#define SDK_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
// <e> XINCX_RF_NORMAL_PEACKET_MODE - RF normal packet mode
|
||||
// <i> Configure the frame format, which is a static packet format and can only communicate in one direction.
|
||||
#ifndef XINCX_RF_NORMAL_PACKET_MODE
|
||||
#define XINCX_RF_NORMAL_PACKET_MODE 1
|
||||
#endif
|
||||
|
||||
// <o>XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
|
||||
//==========================================================
|
||||
// <0=> Xinchip
|
||||
// <1=> Panchip
|
||||
// <2=> Beken
|
||||
// <3=> Telink
|
||||
// <4=> Huntersun
|
||||
#ifndef XINCX_RF_COMPATIBILITY_MODE
|
||||
#define XINCX_RF_COMPATIBILITY_MODE 0
|
||||
#endif
|
||||
|
||||
#if (XINCX_RF_NORMAL_PACKET_MODE == 1)
|
||||
|
||||
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
|
||||
// <0=> TX Mode
|
||||
// <1=> RX Mode
|
||||
// <2=> TRX Mode
|
||||
#ifndef XINCX_RF_MODE
|
||||
#define XINCX_RF_MODE 0
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
|
||||
// <0x02=> 1M
|
||||
// <0x0A=> 2M
|
||||
// <0x22=> 250k
|
||||
// <0x2A=> 125k
|
||||
#ifndef XINCX_RF_TRANS_RATE
|
||||
#define XINCX_RF_TRANS_RATE 0x02
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
|
||||
#ifndef XINCX_2_4G_CHANNEL
|
||||
#define XINCX_2_4G_CHANNEL 2440
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
|
||||
// <3=> 3 Bytes
|
||||
// <4=> 4 Bytes
|
||||
// <5=> 5 Bytes
|
||||
#ifndef XINCX_RF_TX_ADDR_WIDTH
|
||||
#define XINCX_RF_TX_ADDR_WIDTH 5
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_ADDR_L - rf Address Set
|
||||
#ifndef XINCX_2_4G_ADDR_L
|
||||
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7 // 0xCCDDEEDD
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_ADDR_H - rf Address Set
|
||||
#ifndef XINCX_2_4G_ADDR_H
|
||||
#define XINCX_2_4G_ADDR_H 0xe7 // 0xAA
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_POWER - rf Power Set
|
||||
// <1=> -10dbm
|
||||
// <2=> -9dbm
|
||||
// <4=> -4dbm
|
||||
// <6=> 0dbm
|
||||
// <8=> 3dbm
|
||||
// <9=> 5dbm
|
||||
// <12=> 7dbm
|
||||
// <14=> 8dbm
|
||||
// <16=> 9dbm
|
||||
// <19=> 10dbm
|
||||
// <24=> 11dbm
|
||||
// <30=> 12dbm
|
||||
// <36=> 13dbm
|
||||
#ifndef XINCX_POWER
|
||||
#define XINCX_POWER 0x00006
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_RF_NVIC_MODE
|
||||
#define XINCX_RF_NVIC_MODE 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
|
||||
// <i> Payload length. Configuration of the load length during communication.
|
||||
//==========================================================
|
||||
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
|
||||
// #ifndef XINCX_2_4G_PIPE0_LEN
|
||||
// #define XINCX_2_4G_PIPE0_LEN 32
|
||||
// #endif
|
||||
|
||||
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE1_LEN
|
||||
#define XINCX_2_4G_PIPE1_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE2_LEN
|
||||
#define XINCX_2_4G_PIPE2_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE3_LEN
|
||||
#define XINCX_2_4G_PIPE3_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE4_LEN
|
||||
#define XINCX_2_4G_PIPE4_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE5_LEN
|
||||
#define XINCX_2_4G_PIPE5_LEN 32
|
||||
#endif
|
||||
|
||||
//
|
||||
|
||||
// XINCX_RF_CRC_ENABLE - RF CRC Enable
|
||||
//==========================================================
|
||||
#ifndef XINCX_RF_CRC_ENABLE
|
||||
#define XINCX_RF_CRC_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
|
||||
// <0=> 0 Byte
|
||||
// <1=> 1 Byte
|
||||
// <2=> 2 Bytes
|
||||
#ifndef XINCX_2_4G_CRC_BYTE
|
||||
#define XINCX_2_4G_CRC_BYTE 2
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
|
||||
//==========================================================
|
||||
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
|
||||
#ifndef XINCX_2_4G_GUARD_CFG
|
||||
#define XINCX_2_4G_GUARD_CFG 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
|
||||
#ifndef XINCX_2_4G_LONG_PLD_TYPE
|
||||
#define XINCX_2_4G_LONG_PLD_TYPE 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
|
||||
#ifndef XINCX_2_4G_PREAMBLE_NUM
|
||||
#define XINCX_2_4G_PREAMBLE_NUM 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
|
||||
#ifndef XINCX_2_4G_PREAMBLE_TYPE
|
||||
#define XINCX_2_4G_PREAMBLE_TYPE 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
|
||||
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
|
||||
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
|
||||
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
|
||||
#ifndef XINCX_2_4G_LONG_PLD
|
||||
#define XINCX_2_4G_LONG_PLD 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
|
||||
#ifndef XINCX_2_4G_FEC
|
||||
#define XINCX_2_4G_FEC 0
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
|
||||
#ifndef XINCX_2_4G_WHITEN
|
||||
#define XINCX_2_4G_WHITEN 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
|
||||
#ifndef XINCX_2_4G_DPL
|
||||
#define XINCX_2_4G_DPL 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
|
||||
#ifndef XINCX_2_4G_ACK_PAY
|
||||
#define XINCX_2_4G_ACK_PAY 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
|
||||
#ifndef XINCX_2_4G_DYN_ACK
|
||||
#define XINCX_2_4G_DYN_ACK 0
|
||||
#endif
|
||||
|
||||
//
|
||||
|
||||
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
|
||||
//==========================================================
|
||||
|
||||
// XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
|
||||
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
|
||||
// not receive the correct ACK.
|
||||
#ifndef XINCX_2_4G_RETRANS_CNT
|
||||
#define XINCX_2_4G_RETRANS_CNT 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
|
||||
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
|
||||
// kbit/s.
|
||||
#ifndef XINCX_2_4G_RETRANS_DELAY
|
||||
#define XINCX_2_4G_RETRANS_DELAY 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DYNPD - 2.4g dynpd
|
||||
#ifndef XINCX_2_4G_DYNPD
|
||||
#define XINCX_2_4G_DYNPD 0x00
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
|
||||
//==========================================================
|
||||
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE0_ENAA
|
||||
#define XINCX_2_4G_PIPE0_ENAA 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE1_ENAA
|
||||
#define XINCX_2_4G_PIPE1_ENAA 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE2_ENAA
|
||||
#define XINCX_2_4G_PIPE2_ENAA 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE3_ENAA
|
||||
#define XINCX_2_4G_PIPE3_ENAA 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE4_ENAA
|
||||
#define XINCX_2_4G_PIPE4_ENAA 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE5_ENAA
|
||||
#define XINCX_2_4G_PIPE5_ENAA 0
|
||||
#endif
|
||||
|
||||
// XINCX_RF_PIPE_ENABLE
|
||||
#ifndef XINCX_RF_PIPE_ENABLE
|
||||
#define XINCX_RF_PIPE_ENABLE 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
// </e> //XINCX_RF_PEACKET_MODE normal normal
|
||||
|
||||
// <e> XINCX_RF_EMHAMCED_PEACKET_MODE - RF enhanced packet mode
|
||||
// <i> Configure the frame format, which is a dynamic packet configuration, which can communicate in both directions,and
|
||||
// <i> ACK can dynamically carry data.
|
||||
#ifndef XINCX_RF_EMHAMCED_PACKET_MODE
|
||||
#define XINCX_RF_EMHAMCED_PACKET_MODE 0
|
||||
#endif
|
||||
|
||||
#if (XINCX_RF_EMHAMCED_PACKET_MODE == 1)
|
||||
|
||||
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
|
||||
// <0=> TX Mode
|
||||
// <1=> RX Mode
|
||||
#ifndef XINCX_RF_MODE
|
||||
#define XINCX_RF_MODE 0
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
|
||||
// <0x02=> 1M
|
||||
// <0x0A=> 2M
|
||||
// <0x22=> 250k
|
||||
// <0x2A=> 125k
|
||||
#ifndef XINCX_RF_TRANS_RATE
|
||||
#define XINCX_RF_TRANS_RATE 0x02
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
|
||||
#ifndef XINCX_2_4G_CHANNEL
|
||||
#define XINCX_2_4G_CHANNEL 2440
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
|
||||
// <3=> 3 Bytes
|
||||
// <4=> 4 Bytes
|
||||
// <5=> 5 Bytes
|
||||
#ifndef XINCX_RF_TX_ADDR_WIDTH
|
||||
#define XINCX_RF_TX_ADDR_WIDTH 5
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_ADDR_L - rf Address Set
|
||||
#ifndef XINCX_2_4G_ADDR_L
|
||||
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_ADDR_H - rf Address Set
|
||||
#ifndef XINCX_2_4G_ADDR_H
|
||||
#define XINCX_2_4G_ADDR_H 0xe7
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_POWER - rf Power Set
|
||||
// <1=> -10dbm
|
||||
// <2=> -9dbm
|
||||
// <4=> -4dbm
|
||||
// <6=> 0dbm
|
||||
// <8=> 3dbm
|
||||
// <9=> 5dbm
|
||||
// <12=> 7dbm
|
||||
// <14=> 8dbm
|
||||
// <16=> 9dbm
|
||||
// <19=> 10dbm
|
||||
// <24=> 11dbm
|
||||
// <30=> 12dbm
|
||||
// <36=> 13dbm
|
||||
#ifndef XINCX_POWER
|
||||
#define XINCX_POWER 0x00006
|
||||
#endif
|
||||
|
||||
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
|
||||
// <0=> Disable
|
||||
// <1=> Enable
|
||||
#ifndef XINCX_RF_NVIC_MODE
|
||||
#define XINCX_RF_NVIC_MODE 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
|
||||
// <i> Payload length. Configuration of the load length during communication.
|
||||
//==========================================================
|
||||
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
|
||||
// #ifndef XINCX_2_4G_PIPE0_LEN
|
||||
// #define XINCX_2_4G_PIPE0_LEN 32
|
||||
// #endif
|
||||
|
||||
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE1_LEN
|
||||
#define XINCX_2_4G_PIPE1_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE2_LEN
|
||||
#define XINCX_2_4G_PIPE2_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE3_LEN
|
||||
#define XINCX_2_4G_PIPE3_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE4_LEN
|
||||
#define XINCX_2_4G_PIPE4_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
|
||||
#ifndef XINCX_2_4G_PIPE5_LEN
|
||||
#define XINCX_2_4G_PIPE5_LEN 32
|
||||
#endif
|
||||
|
||||
// XINCX_RF_CRC_ENABLE - RF CRC Enable
|
||||
//==========================================================
|
||||
#ifndef XINCX_RF_CRC_ENABLE
|
||||
#define XINCX_RF_CRC_ENABLE 1
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
|
||||
// <0=> 0 Byte
|
||||
// <1=> 1 Byte
|
||||
// <2=> 2 Bytes
|
||||
#ifndef XINCX_2_4G_CRC_BYTE
|
||||
#define XINCX_2_4G_CRC_BYTE 2
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
|
||||
//==========================================================
|
||||
|
||||
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
|
||||
#ifndef XINCX_2_4G_GUARD_CFG
|
||||
#define XINCX_2_4G_GUARD_CFG 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
|
||||
#ifndef XINCX_2_4G_LONG_PLD_TYPE
|
||||
#define XINCX_2_4G_LONG_PLD_TYPE 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
|
||||
#ifndef XINCX_2_4G_PREAMBLE_NUM
|
||||
#define XINCX_2_4G_PREAMBLE_NUM 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
|
||||
#ifndef XINCX_2_4G_PREAMBLE_TYPE
|
||||
#define XINCX_2_4G_PREAMBLE_TYPE 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
|
||||
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
|
||||
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
|
||||
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
|
||||
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
|
||||
#ifndef XINCX_2_4G_LONG_PLD
|
||||
#define XINCX_2_4G_LONG_PLD 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
|
||||
#ifndef XINCX_2_4G_FEC
|
||||
#define XINCX_2_4G_FEC 1
|
||||
#endif
|
||||
|
||||
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
|
||||
#ifndef XINCX_2_4G_WHITEN
|
||||
#define XINCX_2_4G_WHITEN 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
|
||||
#ifndef XINCX_2_4G_DPL
|
||||
#define XINCX_2_4G_DPL 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
|
||||
#ifndef XINCX_2_4G_ACK_PAY
|
||||
#define XINCX_2_4G_ACK_PAY 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
|
||||
#ifndef XINCX_2_4G_DYN_ACK
|
||||
#define XINCX_2_4G_DYN_ACK 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_DYNPD - 2.4g dynpd
|
||||
#ifndef XINCX_2_4G_DYNPD
|
||||
#define XINCX_2_4G_DYNPD 0x3f
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
|
||||
//==========================================================
|
||||
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE0_ENAA
|
||||
#define XINCX_2_4G_PIPE0_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE1_ENAA
|
||||
#define XINCX_2_4G_PIPE1_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE2_ENAA
|
||||
#define XINCX_2_4G_PIPE2_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE3_ENAA
|
||||
#define XINCX_2_4G_PIPE3_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE4_ENAA
|
||||
#define XINCX_2_4G_PIPE4_ENAA 1
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
|
||||
#ifndef XINCX_2_4G_PIPE5_ENAA
|
||||
#define XINCX_2_4G_PIPE5_ENAA 1
|
||||
#endif
|
||||
// <o.0..5> XINCX_RF_PIPE_ENABLE
|
||||
#ifndef XINCX_RF_PIPE_ENABLE
|
||||
#define XINCX_RF_PIPE_ENABLE 1
|
||||
#endif
|
||||
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
|
||||
//==========================================================
|
||||
|
||||
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
|
||||
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
|
||||
// not receive the correct ACK.
|
||||
// <0=> No retransmission
|
||||
// <1=> 1 time
|
||||
// <2=> 2 times
|
||||
// <3=> 3 times
|
||||
// <4=> 4 times
|
||||
// <5=> 5 times
|
||||
// <6=> 6 times
|
||||
// <7=> 7 times
|
||||
// <8=> 8 times
|
||||
// <9=> 9 times
|
||||
// <10=> 10 times
|
||||
// <11=> 11 times
|
||||
// <12=> 12 times
|
||||
// <13=> 13 times
|
||||
// <14=> 14 times
|
||||
// <15=> 15 times
|
||||
#ifndef XINCX_2_4G_RETRANS_CNT
|
||||
#define XINCX_2_4G_RETRANS_CNT 0
|
||||
#endif
|
||||
|
||||
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
|
||||
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
|
||||
// kbit/s.
|
||||
// <0=> 250us
|
||||
// <1=> 500us
|
||||
// <2=> 750us
|
||||
// <3=> 1000us
|
||||
// <4=> 1250us
|
||||
// <5=> 1500us
|
||||
// <6=> 1750us
|
||||
// <7=> 2000us
|
||||
// <8=> 2250us
|
||||
// <9=> 2500us
|
||||
// <10=> 2750us
|
||||
// <11=> 3000us
|
||||
// <12=> 3250us
|
||||
// <13=> 3500us
|
||||
// <14=> 3750us
|
||||
// <15=> 4000us
|
||||
#ifndef XINCX_2_4G_RETRANS_DELAY
|
||||
#define XINCX_2_4G_RETRANS_DELAY 3
|
||||
#endif
|
||||
|
||||
#endif
|
||||
// </e> //XINCX_RF_PEACKET_MODE enhanced normal
|
||||
|
||||
// RF 2.4g Compatibility configuration
|
||||
//==========================================================
|
||||
// Compatibility configuration, when you need to be compatible with other RF chips, you don't need to configure this
|
||||
// option when using our company's chips.
|
||||
// XINCX_2_4G_PREAMBLE - 2.4g preamble
|
||||
#ifndef XINCX_2_4G_PREAMBLE
|
||||
#define XINCX_2_4G_PREAMBLE 0x710f5555
|
||||
#endif
|
||||
|
||||
// XINCX_2_4G_GUARD - 2.4g guard
|
||||
#ifndef XINCX_2_4G_GUARD
|
||||
#define XINCX_2_4G_GUARD 0x8fc9
|
||||
#endif
|
||||
//
|
||||
|
||||
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
|
||||
//==========================================================
|
||||
// Crystal capacitor array, adjust to modify the frequency offset of the crystal oscillator.
|
||||
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
|
||||
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
|
||||
#ifdef XC62XX
|
||||
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
|
||||
#else
|
||||
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
|
||||
#endif
|
||||
#endif
|
||||
//
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // SDK_CONFIG_H
|
||||
@@ -0,0 +1,99 @@
|
||||
#include "app_64m.h"
|
||||
|
||||
void use_64m_crtstal_init(void)
|
||||
{
|
||||
testpin_64M_config();
|
||||
xc_pwr_pwrkey_init();
|
||||
Init_rtc_gpio(4, 0x00);
|
||||
}
|
||||
|
||||
__RAM_CODE void rf_64M_set_rx_channel(uint16_t channel)
|
||||
{
|
||||
channel -= 1;
|
||||
uint16_t ch = channel % 2;
|
||||
XC_RF_2_4G->RF_CH &= ~(0x3fff);
|
||||
switch (ch) {
|
||||
case 0:
|
||||
XC_RF_2_4G->RF_CH |= (channel / 2);
|
||||
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16));
|
||||
break;
|
||||
case 1:
|
||||
XC_RF_2_4G->RF_CH |= (channel / 2);
|
||||
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16) | 0x80008000);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
(*(volatile unsigned int *)(0x53023010)) &= ~((1 << 24) | (2 << 28));
|
||||
}
|
||||
|
||||
__RAM_CODE void rf_64M_set_tx_channel(uint16_t channel)
|
||||
{
|
||||
uint16_t ch = channel % 2;
|
||||
XC_RF_2_4G->RF_CH &= ~(0x3fff);
|
||||
switch (ch) {
|
||||
case 0:
|
||||
XC_RF_2_4G->RF_CH |= (channel / 2);
|
||||
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16));
|
||||
break;
|
||||
case 1:
|
||||
XC_RF_2_4G->RF_CH |= (channel / 2 + 1);
|
||||
*((uint32_t volatile *)0x53022064) = (((channel / 2) << 16) | 0x80008000);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
(*(volatile unsigned int *)(0x53023010)) |= ((0x3 << 16) | (1 << 24) | (2 << 28));
|
||||
}
|
||||
|
||||
void testpin_64M_config(void)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = (*(volatile unsigned int *)(0x53022040));
|
||||
val |= (0x7 << 4) | (0x7);
|
||||
(*(volatile unsigned int *)(0x53022040)) = val; // TPORT_DATA0_SEL set
|
||||
|
||||
val = (*(volatile unsigned int *)(0x40000134));
|
||||
(*(volatile unsigned int *)(0x40000134)) = ((val & ~(0xf << 28)) | (1 << 28)); // testpin1_ctrl[3:0]=1
|
||||
// printf("after 0x40000134=0x%x, 0x40000134=0x%x\n", *(volatile unsigned int *)(0x40000134),
|
||||
// *(volatile unsigned int *)(0x40000134));
|
||||
|
||||
val = (*(volatile unsigned int *)(0x53023010));
|
||||
val &= ~(3 << 28);
|
||||
|
||||
#if 1 // diag = 0xc //diag = 0x3
|
||||
|
||||
val |= (0x3 << 20) | (0x3 << 16 | 1 << 24 | 2 << 28); // 0xc
|
||||
(*(volatile unsigned int *)(0x53023010)) = val; // diag_sel[3:0] set
|
||||
#endif
|
||||
|
||||
// LOGI("after 0x53022040=0x%x, 0x53022010=0x%x\n", *(volatile unsigned int *)(0x53022040),
|
||||
//*(volatile unsigned int *)(0x53023010));
|
||||
|
||||
uint32_t addr_val = 0;
|
||||
|
||||
xc_gpio_fun_sel(GPIO_4, GPIO_Dx);
|
||||
xc_gpio_mux_ctl(GPIO_4, GPIO_Mux3); // en test_pin[1]
|
||||
addr_val = 0x40000174;
|
||||
*((uint32_t volatile *)addr_val) = 7;
|
||||
}
|
||||
|
||||
void Init_rtc_gpio(uint32_t num, uint8_t inter_mode)
|
||||
{
|
||||
uint32_t val;
|
||||
// if(!((inter_mode>=0x08) &&(inter_mode<=0x0c))) return;
|
||||
__write_hw_reg32(CPR_CTLAPBCLKEN_GRCTL, 0x20002);
|
||||
__write_hw_reg32(CPR_AOCLKEN_GRCTL, 0x20002);
|
||||
|
||||
__read_hw_reg32(AO_GPIO_MODE, val);
|
||||
val &= ~(0x0f << (num << 2));
|
||||
val |= (inter_mode << (num << 2));
|
||||
__write_hw_reg32(AO_GPIO_MODE, val);
|
||||
|
||||
__read_hw_reg32(AO_GPIO_CTL, val);
|
||||
val |= (1 << (8 + num));
|
||||
__write_hw_reg32(AO_GPIO_CTL, val);
|
||||
// rtc_ao_gpio_mode__aogpio_debounce_en3__setf(1);
|
||||
NVIC_EnableIRQ(RTC_IRQn);
|
||||
}
|
||||
@@ -0,0 +1,532 @@
|
||||
/*!
|
||||
* \file main.c
|
||||
*
|
||||
* \brief Target main implementation
|
||||
*
|
||||
* \copyright Revised BSD License, see section \ref LICENSE.
|
||||
*
|
||||
* \code
|
||||
*
|
||||
* _ __ _ ________ _
|
||||
* | |/ /(_)___ / ____/ /_ (_)___
|
||||
* | // / __ \/ / / __ \/ / __ \
|
||||
* / |/ / / / / /___/ / / / / /_/ /
|
||||
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
|
||||
* /_/
|
||||
* (C) 2022-2025 XinChip
|
||||
*
|
||||
* \endcode
|
||||
*
|
||||
* \author ( XinChip ) Alex-J
|
||||
*
|
||||
* \author ( XinChip )
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------------
|
||||
INCLUDE HEADE FILES
|
||||
------------------------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Macros
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Global Variables
|
||||
-------------------------------------------------------------------------------------*/
|
||||
bool rf_tx_timer_flag = false;
|
||||
bool rf_trx_tx_flag = false;
|
||||
|
||||
uint32_t rx_cnt = 0;
|
||||
uint32_t tx_cnt = 0;
|
||||
uint8_t tx_buff[256] = {0};
|
||||
uint8_t rx_buff[256] = {0};
|
||||
/*------------------------------------------------------------------------------------
|
||||
Func Prototype
|
||||
-------------------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------------
|
||||
Functions
|
||||
-------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @brief
|
||||
*
|
||||
* @param[in]
|
||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
||||
void timer_init(uint8_t timer_id, uint32_t timer_cnt)
|
||||
{
|
||||
LOGI("timer_init\r\n");
|
||||
|
||||
uint32_t timerx_us = timer_cnt * 1000;
|
||||
Timer_InitCfg_t timer_cfg;
|
||||
|
||||
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32M_DIV;
|
||||
timer_cfg.timer_div_clk = TIMER_DIV_CLK_1MHzOr1K;
|
||||
timer_cfg.timer_mode = TIMER_MODE_CYCLE;
|
||||
|
||||
xc_timer_init(timer_id, &timer_cfg);
|
||||
xc_timer_set_value(timer_id, timerx_us);
|
||||
xc_timer_start(timer_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief timer0_Callback
|
||||
* @param void * - context
|
||||
*
|
||||
* @retval void
|
||||
*/
|
||||
void timer0_callback(void *context)
|
||||
{
|
||||
#if (XINCX_RF_MODE == TX_MODE)
|
||||
rf_tx_timer_flag = true;
|
||||
#elif (XINCX_RF_MODE == TRX_MODE)
|
||||
rf_trx_tx_flag = true;
|
||||
#endif //(XINCX_RF_MODE)
|
||||
}
|
||||
|
||||
/**
|
||||
****************************************************************************************
|
||||
* @brief Clock Initialization
|
||||
*
|
||||
* @param[in]
|
||||
* @param[in]
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
void clock_init(void)
|
||||
{
|
||||
CLOCK_InitCfg_t clock_cfg;
|
||||
|
||||
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
|
||||
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
|
||||
#if (RC_32K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
|
||||
#endif //(RC_32K)
|
||||
|
||||
#if (XTAL_32K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
|
||||
#endif // (XTAL_32K)
|
||||
|
||||
#if (XTAL_32768K)
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
|
||||
#endif // (XTAL_32768K)
|
||||
#ifdef XC62XX
|
||||
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
|
||||
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
|
||||
#else
|
||||
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
|
||||
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
|
||||
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
|
||||
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
|
||||
}
|
||||
#endif
|
||||
xc_clock_init_cfg(&clock_cfg);
|
||||
|
||||
SysTick_Config(xc_clock_hfclk_in_get() / 100);
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
#ifdef DEBUG_LOG
|
||||
/**
|
||||
* @brief RF 2.4g register information printing
|
||||
* @param void
|
||||
* @retval void
|
||||
*/
|
||||
void rf_2M_reg_info(void)
|
||||
{
|
||||
/* Register information printing */
|
||||
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
|
||||
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
|
||||
LOGI("RXPROC_CFG_L: 0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
|
||||
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
|
||||
LOGI("rccal_reg_l: 0x%08x\r\n", XC_BT_RF->rccal_reg_l);
|
||||
LOGI("ana2_reg_l: 0x%08x\r\n", XC_BT_RF->ana2_reg_l);
|
||||
LOGI("ana3_reg_l: 0x%08x\r\n", XC_BT_RF->ana3_reg_l);
|
||||
LOGI("ana4_reg_l: 0x%08x\r\n", XC_BT_RF->ana4_reg_l);
|
||||
LOGI("ana5_reg_l: 0x%08x\r\n", XC_BT_RF->ana5_reg_l);
|
||||
LOGI("ana14_reg_l: 0x%08x\r\n", XC_BT_RF->ana14_reg_l);
|
||||
LOGI("ana15_reg_l: 0x%08x\r\n", XC_BT_RF->ana15_reg_l);
|
||||
LOGI("ana16_reg_l: 0x%08x\r\n", XC_BT_RF->ana16_reg_l);
|
||||
LOGI("ana17_reg_l: 0x%08x\r\n", XC_BT_RF->ana17_reg_l);
|
||||
LOGI("ana18_reg_l: 0x%08x\r\n", XC_BT_RF->ana18_reg_l);
|
||||
LOGI("ana21_reg_l: 0x%08x\r\n", XC_BT_RF->ana21_reg_l);
|
||||
LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rf 2.4g dump log
|
||||
* @param void
|
||||
*
|
||||
* @retval void
|
||||
*/
|
||||
void rf_dump_log(void)
|
||||
{
|
||||
LOGI("***************** 2.4G Param ******************\n");
|
||||
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
|
||||
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
|
||||
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
|
||||
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
|
||||
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
|
||||
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
|
||||
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
|
||||
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
|
||||
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
|
||||
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
|
||||
LOGI("RX_ADDR_P0: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
|
||||
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
|
||||
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
|
||||
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
|
||||
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
|
||||
LOGI("PGA_SETTING: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
|
||||
LOGI("TX_ADDR: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
|
||||
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
|
||||
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
|
||||
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
|
||||
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
|
||||
LOGI("RXPROC_CFG: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
|
||||
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
|
||||
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
|
||||
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
|
||||
#ifdef XC62XX
|
||||
LOGI("HW_CONFIG: 0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
|
||||
LOGI("PBT_CONFIG: 0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
|
||||
LOGI("PBT_TIMER: 0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
|
||||
LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
|
||||
LOGI("PBT_TX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
|
||||
LOGI("PBT_RX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
|
||||
LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
|
||||
#endif
|
||||
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
|
||||
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
|
||||
LOGI("***********************************************\n");
|
||||
LOGI("\r\n");
|
||||
}
|
||||
#endif // DEBUG_LOG
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g data config
|
||||
* @param uint8_t * - buff
|
||||
* uint8 - len
|
||||
* @retval uint8_t - 0
|
||||
*/
|
||||
uint8_t rf_data_config(uint8_t *buff, uint16_t len)
|
||||
{
|
||||
if (len == 0) {
|
||||
return RF_FAIL;
|
||||
}
|
||||
|
||||
for (uint16_t i = 0; i < len; i++) {
|
||||
buff[i] = i;
|
||||
}
|
||||
return RF_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g buff info
|
||||
* @param uint8_t * - buff
|
||||
* uint8_t len
|
||||
* @retval void
|
||||
*/
|
||||
void rf_buff_info(uint8_t *buff, uint16_t len)
|
||||
{
|
||||
for (uint16_t i = 0; i < len; i++)
|
||||
LOGI("%02x ", buff[i]);
|
||||
LOGI("\r\n");
|
||||
}
|
||||
|
||||
void app_uart_init(void)
|
||||
{
|
||||
GPIO_InitCfg_t gpio_cfg = {0};
|
||||
|
||||
gpio_cfg.Mux = GPIO_Mux0;
|
||||
gpio_cfg.Pull = GPIO_PULLUP;
|
||||
gpio_cfg.Int = NOT_INT;
|
||||
gpio_cfg.FunSel = UART0_TX;
|
||||
|
||||
gpio_cfg.Pin = GPIO_18;
|
||||
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
gpio_cfg.FunSel = UART0_RX;
|
||||
gpio_cfg.Pin = GPIO_19;
|
||||
gpio_cfg.Dir = GPIO_DIR_INPUT;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
|
||||
UART_InitCfg_t uart_cfg = {0};
|
||||
|
||||
uart_cfg.Parity = UART_PARITY_DISABLE;
|
||||
uart_cfg.StopBits = UART_STOP_1_BITS;
|
||||
uart_cfg.WordLength = UART_DATA_8_BITS;
|
||||
uart_cfg.BaudRate = UART_BAUDRATE_115200;
|
||||
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
|
||||
|
||||
xc_uart_init(UART0_IDX, &uart_cfg);
|
||||
}
|
||||
|
||||
void rf_switch_mode(uint8_t mode, uint16_t channel)
|
||||
{
|
||||
CE_CTL_LOW;
|
||||
uint8_t rf_mode = 0;
|
||||
switch (mode) {
|
||||
case TRX_MODE:
|
||||
case TX_MODE:
|
||||
break;
|
||||
case RX_MODE:
|
||||
rf_mode = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
LOGI("The mode is set incorrectly\n");
|
||||
return;
|
||||
}
|
||||
set_rf_mode(mode);
|
||||
rf_set_channel(channel);
|
||||
#ifdef XC62XX
|
||||
XC_RF_2_4G->STATUS = ((XC_RF_2_4G->CFG_TOP >> 30) & 0x3 << 7) | ((XC_RF_2_4G->CFG_TOP >> 4) & 0x7 << 4);
|
||||
#else
|
||||
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
|
||||
#endif
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
rf_wr_cmd(FLUSH_TX);
|
||||
|
||||
if (rf_mode) {
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
}
|
||||
|
||||
void main_loop(void)
|
||||
{
|
||||
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
|
||||
#if (XINCX_RF_MODE == TX_MODE)
|
||||
if (rf24g_tx_irq_flag) {
|
||||
rf_data_config(tx_buff, XINCX_2_4G_PIPE0_LEN);
|
||||
rf_tx_normal_manage(tx_buff, XINCX_2_4G_PIPE0_LEN);
|
||||
}
|
||||
#else
|
||||
rf_rx_normal_manage();
|
||||
#endif
|
||||
#else
|
||||
#if ((!XINCX_RF_NVIC_MODE) && (XINCX_RF_MODE != TRX_MODE))
|
||||
#if (XINCX_RF_MODE == TX_MODE)
|
||||
// 轮询发射
|
||||
rf_data_config(tx_buff, BUFF_LEN);
|
||||
tx_buff[0] = tx_cnt;
|
||||
tx_stat = rf_tx_event(tx_buff, BUFF_LEN);
|
||||
#if (XINCX_RF_EMHAMCED_PACKET_MODE)
|
||||
if (tx_stat == TX_DATA_OK) {
|
||||
uint16_t ack_len = rf_rx_packet(rx_buff);
|
||||
LOGI("yes ack len:%d\n", ack_len);
|
||||
rx_cnt++;
|
||||
rf_buff_info(rx_buff, ack_len);
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
} else if (tx_stat == TX_RETRANS_MAX) {
|
||||
LOGI("no ack\n");
|
||||
}
|
||||
tx_cnt += 1;
|
||||
LOGI("tx_cnt:%d, rx_cnt:%d\n", tx_cnt, rx_cnt);
|
||||
#else
|
||||
tx_cnt += 1;
|
||||
LOGI("tx_cnt:%d\n", tx_cnt);
|
||||
#endif
|
||||
delay_ms(10);
|
||||
#else
|
||||
|
||||
// 轮询接收
|
||||
uint16_t len = rf_rx_event(rx_buff);
|
||||
|
||||
/* Receiving end polling data processing */
|
||||
if (len != 0) {
|
||||
/* Entering standby mode */
|
||||
CE_CTL_LOW;
|
||||
/* Receive Count */
|
||||
rx_cnt += 1;
|
||||
// rf_buff_info(rx_buff, len);
|
||||
LOGI("rx_cnt:%d,len:%d\n", rx_cnt, len);
|
||||
/* Receive read data buffer reset */
|
||||
memset(rx_buff, 0, len);
|
||||
len = 0;
|
||||
/* Entering the receiver */
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
#endif
|
||||
#elif (XINCX_RF_MODE != TRX_MODE)
|
||||
// 中断接收
|
||||
if (rf24g_rx_irq_flag) {
|
||||
rf24g_rx_irq_flag = false;
|
||||
CE_CTL_LOW;
|
||||
uint16_t len = recv_len;
|
||||
if (len) {
|
||||
memcpy(rx_buff, recv_buf, len);
|
||||
/* Receive Count */
|
||||
rx_cnt += 1;
|
||||
// rf_buff_info(rx_buff, len);
|
||||
LOGI("rx_cnt:%d,len:%d\n", rx_cnt, len);
|
||||
/* Receive read data buffer reset */
|
||||
memset(rx_buff, 0, len);
|
||||
memset(recv_buf, 0, len);
|
||||
len = 0;
|
||||
}
|
||||
// rf_wr_cmd(FLUSH_RX);
|
||||
/* Entering the receiver */
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
// 中断发射
|
||||
if (rf24g_tx_irq_flag) {
|
||||
rf24g_tx_irq_flag = false;
|
||||
#if (XINCX_RF_EMHAMCED_PACKET_MODE)
|
||||
if (tx_stat == TX_DATA_OK) {
|
||||
uint16_t ack_len = rf_rx_packet(rx_buff);
|
||||
LOGI("yes ack len:%d\n", ack_len);
|
||||
rx_cnt++;
|
||||
rf_buff_info(rx_buff, ack_len);
|
||||
rf_wr_cmd(FLUSH_RX);
|
||||
} else if (tx_stat == TX_RETRANS_MAX) {
|
||||
LOGI("no ack\n");
|
||||
}
|
||||
tx_cnt += 1;
|
||||
LOGI("tx_cnt:%d, rx_cnt:%d\n", tx_cnt, rx_cnt);
|
||||
#else
|
||||
tx_cnt += 1;
|
||||
LOGI("tx_cnt:%d\n", tx_cnt);
|
||||
#endif
|
||||
tx_stat = TX_DATA_INVALID;
|
||||
rf_data_config(tx_buff, BUFF_LEN);
|
||||
tx_buff[0] = tx_cnt;
|
||||
rf_tx_packet(tx_buff, BUFF_LEN);
|
||||
delay_ms(10);
|
||||
}
|
||||
|
||||
#endif //!(XINCX_RF_NVIC_MODE)
|
||||
|
||||
#if (XINCX_RF_MODE == TRX_MODE)
|
||||
if (rf_trx_tx_flag) {
|
||||
rf_trx_tx_flag = false;
|
||||
tx_cnt += 1;
|
||||
/* 切换发射模式 */
|
||||
rf_switch_mode(TX_MODE, XINCX_2_4G_CHANNEL);
|
||||
tx_buff[0] = tx_cnt;
|
||||
/* 开始发射等到发送完成中断 */
|
||||
rf_tx_packet(tx_buff, 32);
|
||||
#if GPIO_TEST
|
||||
xc_gpio_write_pin(TEST_GPIO_2, GPIO_PIN_SET);
|
||||
#endif
|
||||
}
|
||||
|
||||
// 收发切换(中断触发)，含有接收超时配置
|
||||
if (rf24g_rx_irq_flag) {
|
||||
rf24g_rx_irq_flag = false;
|
||||
uint16_t len = recv_len;
|
||||
CE_CTL_LOW;
|
||||
if (len) {
|
||||
#if GPIO_TEST
|
||||
xc_gpio_write_pin(TEST_GPIO_1, GPIO_PIN_SET);
|
||||
#endif
|
||||
memcpy(rx_buff, recv_buf, len);
|
||||
/* Receive Count */
|
||||
rx_cnt += 1;
|
||||
// rf_buff_info(rx_buff, len);
|
||||
//LOGI("rx_buff[0]:%02x,rx_cnt:%d, len:%d\n", rx_buff[0], rx_cnt, len);
|
||||
/* Receive read data buffer reset */
|
||||
memset(rx_buff, 0, len);
|
||||
len = 0;
|
||||
recv_len = 0;
|
||||
#if GPIO_TEST
|
||||
xc_gpio_write_pin(TEST_GPIO_1, GPIO_PIN_RESET);
|
||||
#endif
|
||||
}
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
|
||||
if (rf24g_tx_irq_flag) {
|
||||
rf24g_tx_irq_flag = false;
|
||||
//LOGI("tx_cnt:%d\n",tx_cnt);
|
||||
#if GPIO_TEST
|
||||
xc_gpio_write_pin(TEST_GPIO_2, GPIO_PIN_RESET);
|
||||
#endif
|
||||
/* 切换接收模式 */
|
||||
rf_switch_mode(RX_MODE, XINCX_2_4G_CHANNEL);
|
||||
}
|
||||
|
||||
#endif // XINCX_RF_MODE
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief main
|
||||
* @details
|
||||
* @param[in] void
|
||||
* @param[out] void
|
||||
* @retval int - 0
|
||||
* @retval void
|
||||
* @par identifier
|
||||
* reserve
|
||||
* @par other
|
||||
* void
|
||||
* @par change log
|
||||
* Alex created on 2023-05-31
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
/* Clock initialization */
|
||||
clock_init();
|
||||
|
||||
/* Serial port initialization */
|
||||
app_uart_init();
|
||||
|
||||
/* rf 2.4g initialization configuration */
|
||||
rf24g_init();
|
||||
|
||||
rf_compatible_config();
|
||||
|
||||
#if (XINCX_RF_TRANS_RATE == DR_2M)
|
||||
/* Set 2M mode register configuration */
|
||||
/* Don't move this function interface */
|
||||
rf_2M_config();
|
||||
#endif //(XINCX_RF_TRANS_RATE == DR_2M)
|
||||
|
||||
#if (XINCX_RF_NVIC_MODE)
|
||||
/* Enable RF2.4G interrupts */
|
||||
NVIC_EnableIRQ(RF24G_IRQn);
|
||||
/* Configure the RF2.4G interrupt priority */
|
||||
NVIC_SetPriority(RF24G_IRQn, 0);
|
||||
#endif // XINCX_RF_NVIC_MODE
|
||||
|
||||
/* Set the communication mode */
|
||||
rf_switch_mode(XINCX_RF_MODE, XINCX_2_4G_CHANNEL);
|
||||
#if (XINCX_RF_MODE == TRX_MODE)
|
||||
|
||||
timer_init(RF_TX_TIMERx, SEND_TIMERMS_CNT);
|
||||
#endif
|
||||
#ifdef DEBUG_LOG
|
||||
/* Register information printing */
|
||||
rf_dump_log();
|
||||
#endif // DEBUG_LOG
|
||||
#if GPIO_TEST
|
||||
void gpio_test(void);
|
||||
gpio_test();
|
||||
#endif
|
||||
while (1) {
|
||||
main_loop();
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_test(void)
|
||||
{
|
||||
GPIO_InitCfg_t gpio_cfg = {0};
|
||||
|
||||
gpio_cfg.Mux = GPIO_Mux0;
|
||||
gpio_cfg.Pull = GPIO_PULLDOWN;
|
||||
gpio_cfg.Int = NOT_INT;
|
||||
gpio_cfg.FunSel = GPIO_Dx;
|
||||
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
|
||||
|
||||
gpio_cfg.Pin = TEST_GPIO_1;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
xc_gpio_write_pin(TEST_GPIO_1, GPIO_PIN_RESET);
|
||||
|
||||
gpio_cfg.Pin = TEST_GPIO_2;
|
||||
xc_gpio_init(&gpio_cfg);
|
||||
xc_gpio_write_pin(TEST_GPIO_2, GPIO_PIN_RESET);
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
#include "rf_compatible_normal.h"
|
||||
uint16_t crc = 0;
|
||||
uint8_t panchip_data_length = XINCX_2_4G_PIPE0_LEN - XINCX_2_4G_CRC_BYTE;
|
||||
|
||||
uint16_t rf_addr_crc = 0;
|
||||
uint8_t panchip_addr_whiten;
|
||||
uint8_t addr_buff[5] = {0};
|
||||
uint32_t send_cnt = 0;
|
||||
uint32_t recv_cnt = 0;
|
||||
/**
|
||||
* @brief Rf 2.4g get addr
|
||||
* @param uint8_t *addr_buff
|
||||
*
|
||||
* @retval void
|
||||
*/
|
||||
void rf_addr_map(uint8_t *addr_buff)
|
||||
{
|
||||
uint8_t addr_xsb = (XC_RF_2_4G->CFG_TOP >> 11) & (0x1);
|
||||
LOGI("addr_xsb %02x\r\n", addr_xsb);
|
||||
if (!addr_xsb) {
|
||||
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
|
||||
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
|
||||
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
|
||||
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
|
||||
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
|
||||
} else {
|
||||
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
|
||||
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
|
||||
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
|
||||
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
|
||||
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RF 2.4g get address crc
|
||||
* @param void
|
||||
* @retval crc data
|
||||
*/
|
||||
uint16_t rf_get_addr_crc(void)
|
||||
{
|
||||
#if (1 == XINCX_2_4G_CRC_BYTE)
|
||||
return crc8_rohc(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
|
||||
#elif (2 == XINCX_2_4G_CRC_BYTE)
|
||||
return crc16_ccitt_false(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Address whitening and writing
|
||||
* @param void
|
||||
* @retval uint8_t whiten_addr
|
||||
*/
|
||||
uint8_t rf_recv_addr(void)
|
||||
{
|
||||
uint16_t whiten_addr = whiten_data((uint8_t *)addr_buff, RF_ADDR_LEN, PANCHIP_WHITEN_INIT_VAL);
|
||||
|
||||
/* Set PTX address */
|
||||
set_rf_txaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
|
||||
(addr_buff[4]));
|
||||
/* Set PRX address */
|
||||
set_rf_pipe0_rxaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
|
||||
(addr_buff[4]));
|
||||
return whiten_addr;
|
||||
}
|
||||
|
||||
void rf_compatible_config(void)
|
||||
{
|
||||
#if (XINCX_RF_COMPATIBILITY_MODE == BELKEN_PACKET)
|
||||
#if XC62XX
|
||||
set_rf_retr(XINCX_2_4G_RETRANS_CNT, XINCX_2_4G_RETRANS_DELAY);
|
||||
|
||||
XC_RF_2_4G->FEATURE &= ~(1 << 5);
|
||||
|
||||
rf_set_ack_type(1);
|
||||
|
||||
rf_set_freq_dev(RF_FREQ_DEV);
|
||||
#endif
|
||||
#elif (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
|
||||
|
||||
XC_RF_2_4G->FEATURE |= (1 << 11) | (2 << 12) | (1 << 14) | (1 << 18);
|
||||
XC_RF_2_4G->PREAMBLE = 0x710f55;
|
||||
|
||||
/* 白化cc2500、同步字中断、CRC中断 */
|
||||
XC_RF_2_4G->CFG_TOP |= (1 << 30) | (1 << 22);
|
||||
/* get addr */
|
||||
rf_addr_map(addr_buff);
|
||||
/* Calculate the CRC of the address block */
|
||||
rf_addr_crc = rf_get_addr_crc();
|
||||
/* The address range is whitened and the whitened address is rewritten */
|
||||
panchip_addr_whiten = rf_recv_addr();
|
||||
#if XC62XX
|
||||
rf_set_whiten_value(panchip_addr_whiten);
|
||||
rf_set_fifo_len(1);
|
||||
#else
|
||||
XC_RF_2_4G->FEATURE |= (1 << 5);
|
||||
XC_RF_2_4G->CFG_TOP &= ~(0x7f << 23);
|
||||
XC_RF_2_4G->CFG_TOP |= (panchip_addr_whiten << 23);
|
||||
#endif
|
||||
set_rf_crc(CRC_0BYTE);
|
||||
#endif
|
||||
}
|
||||
|
||||
uint8_t rf_panchip_normal_recv_data_cfg(uint8_t *buff, uint8_t len)
|
||||
{
|
||||
if (len == 0) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
uint16_t crc_data = 0;
|
||||
/* Whiten */
|
||||
whiten_data(buff, len + 2, panchip_addr_whiten);
|
||||
/* CRC */
|
||||
crc = ~crc16_ccitt_false(buff, len, rf_addr_crc, PACKET_NORMAL);
|
||||
crc_data = ((buff[len] << 8) | (buff[len + 1]));
|
||||
|
||||
if (crc == crc_data) {
|
||||
buff_bigandsmallend(buff, len);
|
||||
} else {
|
||||
len = 0;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
uint8_t rf_panchip_normal_send_data_cfg(uint8_t *buff, uint8_t len)
|
||||
{
|
||||
if (len == 0) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
buff_bigandsmallend(buff, len);
|
||||
crc = ~crc16_ccitt_false(buff, panchip_data_length, rf_addr_crc, PACKET_NORMAL);
|
||||
|
||||
buff[panchip_data_length] = (crc >> 8) & 0xff;
|
||||
buff[panchip_data_length + 1] = crc & 0xff;
|
||||
|
||||
/* Whiten */
|
||||
whiten_data(buff, len + 2, panchip_addr_whiten);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t rf_rx_normal_manage(void)
|
||||
{
|
||||
if (rf24g_rx_irq_flag) {
|
||||
rf24g_rx_irq_flag = false;
|
||||
/* Entering standby mode */
|
||||
CE_CTL_LOW;
|
||||
uint8_t len = recv_len;
|
||||
|
||||
#if (DEBUG_PIN)
|
||||
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
|
||||
#endif
|
||||
len = rf_panchip_normal_recv_data_cfg(recv_buf, len - 2);
|
||||
if (len) {
|
||||
#if (DEBUG_PIN)
|
||||
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
|
||||
#endif
|
||||
// rf_buff_info(recv_buf, len);
|
||||
/* Receive Count */
|
||||
recv_cnt++;
|
||||
LOGI("recv:%d, len:%d\r\n", recv_cnt, len);
|
||||
|
||||
/* Receive read data buffer reset */
|
||||
memset(recv_buf, 0, len);
|
||||
len = 0;
|
||||
}
|
||||
|
||||
#if (DEBUG_PIN)
|
||||
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
|
||||
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
|
||||
#endif
|
||||
/* Entering the receiver */
|
||||
CE_CTL_HIGH;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t rf_tx_normal_manage(uint8_t *buff, uint8_t length)
|
||||
{
|
||||
if (rf24g_tx_irq_flag) {
|
||||
rf24g_tx_irq_flag = false;
|
||||
buff[0] = send_cnt++;
|
||||
/* Filling in software frame number */
|
||||
LOGI("data len:%d, send_cnt:%d\n", length - XINCX_2_4G_CRC_BYTE, send_cnt);
|
||||
// rf_buff_info(buff, length);
|
||||
rf_panchip_normal_send_data_cfg(buff, length - XINCX_2_4G_CRC_BYTE);
|
||||
/* data transmission */
|
||||
rf_tx_packet(buff, length);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user