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Stair56E UART project

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This commit is contained in:
吴琪
2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
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project/example/2.4g/RF24_ACK_Payload/app/src/app_data.c
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#include "app_data.h"
#include "rtt_platform.h"
#include "xc_drv_gpio.h"
uint8_t addr_buff[5] = {0};
uint8_t ack_pid = 0;
uint8_t rf_send_ack_stat = TX_DATA_INVALID;
uint16_t rf_addr_crc = 0;
uint8_t ack_buff[128] = {0};
uint8_t panchip_addr_whiten;
uint8_t panchip_contorl_whiten;
/**
* @brief Rf 2.4g get addr
* @param uint8_t *addr_buff
*
* @retval void
*/
void rf_addr_map(uint8_t *addr_buff)
{
uint8_t addr_xsb = (XC_RF_2_4G->CFG_TOP >> 11) & (0x1);
LOGI("addr_xsb %02x\r\n", addr_xsb);
if (!addr_xsb) {
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
} else {
addr_buff[1] = (XC_RF_2_4G->TX_ADDR_L >> 24) & 0xff;
addr_buff[2] = (XC_RF_2_4G->TX_ADDR_L >> 16) & 0xff;
addr_buff[3] = (XC_RF_2_4G->TX_ADDR_L >> 8) & 0xff;
addr_buff[4] = (XC_RF_2_4G->TX_ADDR_L >> 0) & 0xff;
addr_buff[0] = (XC_RF_2_4G->TX_ADDR_H >> 0) & 0xff;
}
}
/**
* @brief Rf 2.4g get addr length
* @param uint8_t *addr_buff
*
* @retval void
*/
uint8_t read_addr_wid(uint8_t *addr_buff)
{
uint8_t addr_wid = 0;
switch (XC_RF_2_4G->SETUP_AW & 0xff) {
case 0xa5:
addr_wid = 3;
#ifdef BEKEN_MODE
addr_wid = 5;
addr_buff[3] = 0xe7;
addr_buff[4] = 0xe7;
#endif
break;
case 0xaa:
addr_wid = 4;
#ifdef BEKEN_MODE
addr_wid = 4;
addr_buff[4] = 0xe7;
#endif
break;
case 0xaf:
addr_wid = 5;
break;
default:
addr_wid = 0;
break;
}
return addr_wid;
}
/**
* @brief Rf 2.4g panchip ack data config
* @param uint8_t *addr_buff
* @param uint8_t *ack_buff_cfg
* @param uint8_t ack_payload_len
* @retval uint16_t ack_crc_data
*/
__RAM_CODE uint16_t rf_enhanced_package_grouping(uint8_t *data_buff, uint8_t data_len)
{
uint16_t ack_control = (data_len << RF_RECV_EXTEN_LEN);
// uint8_t ack_crc_buff[64] = {0};
uint16_t ack_crc_data = 0;
uint8_t temp_buff[64] = {0};
ack_pid += 1;
#if (COMPATILBE_MODE == PAN2416)
if (ack_pid > 1)
#else
if (ack_pid > 3)
#endif
ack_pid = 0;
ack_control = (ack_control & ~(0x3 << 1)) | (ack_pid << DATA_CONTROL_BIT) | DATA_CONTROL_NOACK;
#if (COMPATILBE_MODE == PAN2416)
/* 数据反序 */
buff_bigandsmallend(data_buff, data_len);
#endif
temp_buff[0] = ack_control >> DATA_CONTROL_BIT;
temp_buff[1] = ((ack_control & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) |
((data_buff[0] >> DATA_CONTROL_BIT) & (~DATA_ANALYSIS_BIT_H));
if (data_len == 0) {
temp_buff[1] &= DATA_ANALYSIS_BIT_H;
}
/* 数据填入 */
for (uint8_t i = 0; i < data_len; i++) {
if (i == (data_len - 1)) {
temp_buff[i + 2] = (data_buff[data_len - 1] & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT;
} else {
temp_buff[i + 2] =
((data_buff[i] & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) | (data_buff[i + 1] >> DATA_CONTROL_BIT);
}
}
for (uint8_t i = 0; i < data_len + RF_RECV_EXTEN_LEN; i++) {
data_buff[i] = temp_buff[i];
}
#if (1 == XINCX_2_4G_CRC_BYTE)
ack_crc_data = crc8_rohc(ack_crc_buff, data_len + RF_RECV_EXTEN_LEN - 1, RF_CRC_INIT_VALUE, PACKET_ENHANCED);
data_buff[data_len + 1] =
(data_buff[data_len + 1] & DATA_ANALYSIS_BIT_H) | ((ack_crc_data >> DATA_CONTROL_BIT) & (~DATA_ANALYSIS_BIT_H));
data_buff[data_len + 2] = (ack_crc_data << DATA_SPLICE_BIT) & (DATA_ANALYSIS_BIT_H);
memset(&ack_buff[0], 0, sizeof(ack_buff));
whiten_data(&ack_crc_buff[addr_len], data_len, PANCHIP_WHITEN_INIT_VAL);
if (data_len < sizeof(ack_buff))
memcpy(&ack_buff[0], &ack_crc_buff[0], data_len);
else
LOGI("err %s,%d\r\n", __func__, __LINE__);
#elif (2 == XINCX_2_4G_CRC_BYTE)
/* 计算CRC */
ack_crc_data = crc16_ccitt_false(data_buff, data_len + RF_RECV_EXTEN_LEN - 1, rf_addr_crc, PACKET_ENHANCED);
#if (COMPATILBE_MODE == PAN2416)
/* CRC 取反 */
ack_crc_data = ~ack_crc_data;
#endif
/* CRC 放入数据包 */
data_buff[data_len + 1] = (data_buff[data_len + 1] & DATA_ANALYSIS_BIT_H) |
((ack_crc_data >> (DATA_CONTROL_BIT + BIT3)) & (~DATA_ANALYSIS_BIT_H));
data_buff[data_len + 2] = (ack_crc_data >> DATA_CONTROL_BIT) & 0xff;
data_buff[data_len + 3] =
((ack_crc_data & DATA_ANALYSIS_BIT_L) << DATA_SPLICE_BIT) | (SUPPLEMENTARY_DATA >> DATA_CONTROL_BIT);
#if (COMPATILBE_MODE == PAN2416)
/* 白化数据 */
whiten_data(&data_buff[0], data_len + 5, panchip_addr_whiten);
data_buff[data_len + 3] = (data_buff[data_len + 3] & 0xf0) | 0x04;
#endif
if (data_len + 1 < sizeof(ack_buff)) {
for (uint8_t i = 0; i < data_len + 5; i++) {
ack_buff[i] = data_buff[i];
}
} else
LOGI("err %s,%d\r\n", __func__, __LINE__);
#endif
return ack_crc_data;
}
/**
* @brief Rf 2.4g recv enhanced crc
* @param uint8_t *buff
* @param uint8_t buff_len
* @retval uint16_t crc data
*/
__RAM_CODE uint16_t rf_recv_dyn_crc(uint8_t *buff, uint8_t buff_len)
{
uint8_t ack_crc_buff[64] = {0};
for (uint8_t i = 0; i < buff_len; i++) {
ack_crc_buff[i] = buff[i];
}
ack_crc_buff[buff_len - 1] &= DATA_ANALYSIS_BIT_H;
#if (1 == XINCX_2_4G_CRC_BYTE)
return crc8_rohc(ack_crc_buff, buff_len, rf_addr_crc, PACKET_ENHANCED);
#elif (2 == XINCX_2_4G_CRC_BYTE)
return crc16_ccitt_false(ack_crc_buff, buff_len, rf_addr_crc, PACKET_ENHANCED);
#endif
}
/**
* @brief Rf 2.4g recv enhanced packet data parsing
* @param uint8_t *buff
* @param uint8_t buff_len
*/
__RAM_CODE void rf_enhanced_packet(uint8_t *buff, uint8_t buff_len)
{
uint8_t temp_buff[128] = {0};
if (buff_len < sizeof(temp_buff))
memcpy((char *)&temp_buff, (char *)buff, buff_len);
else
LOGI("err %s,%d\r\n", __func__, __LINE__);
for (uint8_t i = 0; i < buff_len; i++) {
buff[i] = ((temp_buff[i + 1] & (~DATA_ANALYSIS_BIT_H)) << DATA_CONTROL_BIT) |
((temp_buff[i + 2] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
}
}
/**
* @brief Rf 2.4g recv enhanced packet data acquisition and parsing
* @param uint8_t *buff
* @retval uint8_t len
*/
__RAM_CODE uint8_t rf_enhanced_recv_data(uint8_t *buff)
{
uint16_t calc_crc_data = 0;
uint16_t recv_crc_data = 0;
uint8_t len = 0;
if ((XC_RF_2_4G->STATUS & MASK_RX_DR) == MASK_RX_DR) {
CE_CTL_LOW;
rf_wr_cmd(R_RX_PLOAD);
/* Get control field */
buff[0] = XC_RF_2_4G->RX_FIFO_DATA;
#if (COMPATILBE_MODE == PAN2416)
panchip_contorl_whiten = whiten_data(&buff[0], 1, panchip_addr_whiten);
len = ((buff[0] & 0xfe) >> 1);
#elif (COMPATILBE_MODE == BEKEN)
len = ((buff[0] & 0xfe) >> 2);
#endif
/* Get complete data */
if (len > RF_RECV_AMX_LEN) {
len = RF_RECV_AMX_LEN;
}
for (uint8_t i = 1; i < len + RF_RECV_EXTEN_LEN + 2; i++) {
buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
}
/* Clear FIFO and STATUS */
rf_wr_cmd(FLUSH_RX);
XC_RF_2_4G->STATUS = MASK_RX_DR;
#if (COMPATILBE_MODE == PAN2416)
/* Bleaching */
whiten_data(&buff[1], len + 5, panchip_contorl_whiten);
#endif
/* CRC veify */
calc_crc_data = rf_recv_dyn_crc(buff, len + RF_RECV_EXTEN_LEN - 1);
recv_crc_data = ((buff[len + 1] & (~DATA_ANALYSIS_BIT_H)) << (DATA_CONTROL_BIT + BIT3)) |
((buff[len + 2] & 0xff) << DATA_CONTROL_BIT) |
((buff[len + 3] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
#if (COMPATILBE_MODE == PAN2416)
recv_crc_data = ~recv_crc_data;
#endif
if (recv_crc_data == calc_crc_data) {
/* Verify correctly and parse the data */
rf_enhanced_packet(buff, len + RF_RECV_EXTEN_LEN + 1);
#if (COMPATILBE_MODE == PAN2416)
buff_bigandsmallend(buff, len + RF_RECV_EXTEN_LEN + 1);
#endif
rf_send_ack_stat = TX_DATA_OK;
} else {
/* The verification failed and data was discarded. Procedure */
memset(buff, 0, len);
len = 0;
}
} else {
rf_send_ack_stat = TX_RETRANS_MAX;
}
return len;
}
project/example/2.4g/RF24_ACK_Payload/app/src/app_rf.c
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#include "app_rf.h"
rf_timer_stat_t timer_stat = RF_FREE_TIMER_INTER;
#define TEST_PIN_USB 1
uint8_t ret = TX_DATA_INVALID;
uint32_t count = 0;
uint32_t send_ok = 0;
uint32_t send_max = 0;
uint8_t rf_ack_len = ACK_LEN;
uint16_t recv_crc_data = 0;
uint16_t calc_crc_data = 0;
bool rf_send_timer_flag = false;
bool rf_recv_timer_flag = false;
bool rf_prx_ack_flag = false;
uint8_t data_len = 0;
rf_data_typedef_t rf_data_t;
uint8_t send_buff[35] = {0};
uint32_t send_cnt = 0;
uint32_t recv_timer_cnt = 0;
uint32_t recv_crc_err = 0;
uint32_t recv_crc_ok = 0;
uint32_t recv_cnt = 0;
extern uint8_t rf_send_ack_stat;
Timer_InitCfg_t timer_cfg = {
.timer_src_clk = TIMER_CLK_SRC_32M_DIV,
.timer_div_clk = TIMER_DIV_CLK_16MHzOr16K,
};
// #if DEBUG_PIN
/**
* @brief Test pin config
* @param void
* @retval void
*/
void gpio_test(void)
{
// LOGI("gpio\r\n");
GPIO_InitCfg_t gpio_cfg;
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.FunSel = GPIO_Dx;
gpio_cfg.Pull = GPIO_PULLDOWN;
gpio_cfg.Int = NOT_INT;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
// #if TEST_PIN_NO_USB
gpio_cfg.Pin = TEST_PIN_1;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_2;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_3;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_5;
xc_gpio_init(&gpio_cfg);
// #endif
gpio_cfg.Pin = TEST_PIN_4;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_6;
xc_gpio_init(&gpio_cfg);
// #if TEST_PIN_NO_USB
gpio_cfg.Pin = TEST_PIN_7;
xc_gpio_init(&gpio_cfg);
gpio_cfg.Pin = TEST_PIN_8;
xc_gpio_init(&gpio_cfg);
// #endif
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
// xc_gpio_write_pin(GPIO_9, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_8, GPIO_PIN_RESET);
gpio_cfg.Pull = GPIO_PULLDOWN;
gpio_cfg.Dir = GPIO_DIR_INPUT;
gpio_cfg.Pin = GPIO_4;
xc_gpio_init(&gpio_cfg);
}
// #endif // DEBUG_PIN
/**
* @brief RF 2.4g DEBUG PIN config
* @param uint8_t gpio_id - The parameters can be GPIO 2 ~ 9, GPIO 18 ~ 25, and GPIO 14
* @retval void
*/
void rf_debug_pin(uint8_t gpio_id)
{
uint32_t val;
val = (*(volatile unsigned int *)(0x53022040));
val |= 0x7 << 4;
(*(volatile unsigned int *)(0x53022040)) = val; // TPORT_DATA0_SEL set
val = (*(volatile unsigned int *)(0x53023010));
val &= ~(3 << 28);
val |= (0xa << 16 | 1 << 24 | 2 << 28); // 0xc
(*(volatile unsigned int *)(0x53023010)) = val; // diag_sel[3:0] set
LOGI("after 0x53022040=0x%x, 0x53022010=0x%x\n", *(volatile unsigned int *)(0x53022040),
*(volatile unsigned int *)(0x53023010));
uint32_t addr_val = 0;
switch (gpio_id) {
case GPIO_3:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000170;
break;
case GPIO_4:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000174;
break;
case GPIO_2:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux2); // en test_pin[8]
addr_val = 0x40000178;
break;
case GPIO_6:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x4000017c;
break;
case GPIO_7:
case GPIO_20:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000180;
break;
case GPIO_8:
case GPIO_21:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000184;
break;
case GPIO_9:
case GPIO_14:
case GPIO_22:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000188;
break;
case GPIO_18:
case GPIO_23:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x4000018c;
break;
case GPIO_19:
case GPIO_24:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000190;
break;
case GPIO_12:
case GPIO_25:
xc_gpio_fun_sel(gpio_id, GPIO_Dx);
xc_gpio_mux_ctl(gpio_id, GPIO_Mux3); // en test_pin[8]
addr_val = 0x40000194;
break;
default:
LOGI("test pin id error\n");
break;
}
*((uint32_t volatile *)addr_val) = 7;
}
/**
* @brief RF 2.4g get address crc
* @param void
* @retval crc data
*/
uint16_t rf_get_addr_crc(void)
{
#if (1 == XINCX_2_4G_CRC_BYTE)
return crc8_rohc(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#elif (2 == XINCX_2_4G_CRC_BYTE)
return crc16_ccitt_false(addr_buff, RF_ADDR_LEN, RF_CRC_INIT_VALUE, PACKET_NORMAL);
#endif
}
///**
// * @brief RF 2.4g buff info
// * @param uint8_t * - buff
// * uint8_t len
// * @retval void
// */
// void rf_buff_info(uint8_t *buff, uint8_t len)
//{
// for (uint8_t i = 0; i < len; i++)
// LOGI("%02x ", buff[i]);
// LOGI("\r\n");
//}
/**
* @brief RF 2.4g panchip tx data config
* @param uint8_t *buff
* @param uint8_t *data_buff
* @param uint8_t data_len
* @retval uint16_t crc data
*/
__RAM_CODE void rf_rx_ack_payload_event(uint8_t *buff, uint8_t len)
{
// /* ACK data filling */
// rf_data_config(ack_buff, len);
/* Dynamic packet grouping */
rf_enhanced_package_grouping(buff, len);
/* ACK pyaload data fill FIFO */
rf_recv_sf_ack_payload(buff, len);
}
/**
* @brief RF 2.4g setting agc
* @param uint8_t adc_rssi_mean
* @param uint8_t agc_gain_delay
* @retval void
*/
void rf_set_agc(uint8_t adc_rssi_mean, uint8_t agc_gain_delay)
{
XC_RF_2_4G->AGC_SETTING &= ~(0xf << 16);
XC_RF_2_4G->AGC_SETTING |= (adc_rssi_mean << 16) | (agc_gain_delay << 18);
}
/**
* @brief RF 2.4g pwr down and up
* @param void
* @retval void
*/
void rf_pwr_down_up(void)
{
XC_RF_2_4G->CFG_TOP &= ~(1 << 1);
XC_RF_2_4G->CFG_TOP |= (1 << 1);
}
__RAM_CODE uint8_t rf_tx2rx_payload_event(rf_data_typedef_t *rf_data, uint8_t *ack_buff)
{
uint8_t send_len = rf_data->data_length + 5;
/* Modulation frequency offset */
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_SEND_DEV);
/* Set receive length */
set_rf_pipe_rx_payLen(send_len, send_len, send_len, send_len, send_len, send_len);
/* Set send mode */
set_rf_mode(TX_MODE);
/* Set the sending frequency */
set_rf_channel(XINCX_2_4G_CHANNEL);
/* data transmission */
rf_enhanced_package_grouping(send_buff, rf_data->data_length);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
#endif
ret = rf_tx_event(send_buff, send_len);
CE_CTL_LOW;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
#endif
#if 1
/* Modulation frequency offset */
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_RECV_DEV);
/* 切换到接收模式 */
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN + 5);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_SET);
#endif
/* 等待接收ACK数据 */
#if (COMPATILBE_MODE == PANCHIP_PACKET)
delay_ms(3);
#else
delay_ms(2);
#endif
do {
if (recv_timer_cnt >= (RF_RECV_TIMER + 5)) {
rf_send_ack_stat = TX_RETRANS_MAX;
break;
}
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
#endif // DEBUG_PIN
delay_us(BIT_TIMER);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
#endif // DEBUG_PIN
recv_len = rf_enhanced_recv_data(ack_buff);
if (rf_send_ack_stat == TX_DATA_OK) {
recv_cnt += 1;
break;
} else if (rf_send_ack_stat == TX_RETRANS_MAX) {
break;
}
recv_timer_cnt += 1;
} while (!recv_len);
CE_CTL_LOW;
rf_send_ack_stat = TX_DATA_INVALID;
rf_wr_cmd(FLUSH_RX);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
#endif // DEBUG_PIN
#endif
recv_timer_cnt = 0;
return recv_len;
}
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
/**
* @brief Timer initialize
* @param uint8_t timer_id
* @param uint32_t timer_cnt
* @retval void
*/
void timer_init(uint8_t timer_id, uint32_t timer_cnt)
{
#if !XINCX_RF_MODE
timer_cfg.timer_mode = TIMER_MODE_CYCLE; // TIMER_MODE_CYCLE//TIMER_MODE_SINGLE
#else
timer_cfg.timer_mode = TIMER_MODE_CYCLE; // TIMER_MODE_CYCLE//TIMER_MODE_SINGLE
#endif
xc_timer_init(timer_id, &timer_cfg);
xc_timer_set_value(timer_id, timer_cnt);
}
/**
* @brief RF 2.4g tx maage
* @param rf_data_typedef_t *rf_data,
* @retval uint32_t rf_data->cnt
*/
__RAM_CODE uint32_t rf_tx_manage(rf_data_typedef_t *rf_data)
{
uint8_t ack_buff[64] = {0};
static uint32_t send_cnt = 0;
if (send_cnt < XC_SEND_NUM) {
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
#endif
rf_send_timer_flag = false;
rf_data->cnt += 1;
/* Filling in software frame number */
rf_data->data_length = 32;
rf_data_config(send_buff, rf_data->data_length);
uint8_t ack_len = rf_tx2rx_payload_event(rf_data, ack_buff);
send_cnt += 1;
LOGI("send_cnt:%d, recv_cnt:%d, recv_len:%d\r\n", send_cnt, recv_cnt, ack_len);
LOGI("ack data(len:%d):%02x\n\n", ack_len, ack_buff[0]);
// rf_buff_info(ack_buff, ack_len);
memset(rf_data->buff, 0, sizeof(rf_data->buff));
memset(ack_buff, 0xff, sizeof(ack_buff));
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
#endif
rf_send_ack_stat = TX_DATA_INVALID;
}
if (send_cnt == XC_SEND_NUM) {
rf_data->cnt += 1;
send_cnt += 1;
/* Turn off the send timer */
xc_timer_stop(RF_TX_TIMERx);
}
return rf_data->cnt;
}
/**
* @brief timer0 callback
* @param void *context
* @retval void
*/
__RAM_CODE void timer0_callback(void *context)
{
#if XINCX_RF_MODE
xc_timer_stop(RF_RX_TIMERx);
switch (timer_stat) {
case RF_SEND_TIMER_INTER /* 动态 ACk 发射完成 */:
/* code */
timer_stat = RF_FREE_TIMER_INTER;
#if DEBUG_PIN
// xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
#endif // DEBUG_PIN
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
#endif
CE_CTL_LOW;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
rf_prx_ack_flag = true;
if (recv_len <= BUFF_LEN_MAX) {
} else {
LOGI("err %s,%d\r\n", __func__, __LINE__);
}
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_RESET);
#endif // DEBUG_PIN
break;
case RF_RECV_TIMER_INTER /* 动态收包完成 */:
/* code */
xc_timer_stop(RF_RX_TIMERx);
timer_stat = RF_FREE_TIMER_INTER;
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_RESET);
#endif // DEBUG_PIN
for (uint8_t i = 1; i < recv_len + RF_RECV_EXTEN_LEN + 1; i++) {
rf_data_t.buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
}
CE_CTL_LOW;
rf_wr_cmd(FLUSH_RX);
XC_RF_2_4G->STATUS |= MASK_RX_DR | MASK_RX_SYNC;
NVIC_EnableIRQ(RF24G_IRQn);
// rf_buff_info(rf_data_t.buff, recv_len+10);
xc_rf_send_ack(rf_data_t.buff, recv_len);
recv_cnt += 1;
break;
case RF_FREE_TIMER_INTER /* 其他状态 */:
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN);
/* code */
break;
default:
break;
}
#else
rf_send_timer_flag = true;
#endif
}
#endif
/**
* @brief RF 2.4g software send ack packet
* @param uint8_t *buff
* @param uint8_t recv_len
* @retval void
*/
__RAM_CODE void xc_rf_send_ack(uint8_t *buff, uint8_t recv_len)
{
#if (1 == XINCX_2_4G_CRC_BYTE)
/* Set the length of the data to be sent */
set_rf_pipe_rx_payLen(rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN,
rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN,
rf_ack_len + RF_RECV_EXTEN_LEN, rf_ack_len + RF_RECV_EXTEN_LEN);
/* Set send mode */
set_rf_mode(TX_MODE);
/* Set the transmission frequency */
set_rf_channel(XINCX_2_4G_CHANNEL);
CE_CTL_HIGH;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l |= (1 << 5);
/* Theoretical CRC calculation of received data */
calc_crc_data = rf_recv_dyn_crc(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
/* Get the actual CRC for receiving data */
recv_crc_data = ((rf_data_t.buff[recv_len + 1] & (~BIT7)) << DATA_CONTROL_BIT) |
((rf_data_t.buff[recv_len + 2] & BIT7) >> DATA_SPLICE_BIT);
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l |= (1 << 4);
/* CRC check */
if (calc_crc_data == recv_crc_data) {
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
#endif // DEBUG_PIN
/* Wait for sending to complete */
xc_timer_set_value(RF_RX_TIMERx, 10 + (rf_ack_len + 9) * BIT_TIMER);
xc_timer_start(RF_RX_TIMERx);
/* Data parsing */
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
#elif (2 == XINCX_2_4G_CRC_BYTE)
set_rf_pipe_rx_payLen(rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2,
rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2,
rf_ack_len + RF_RECV_EXTEN_LEN + 2, rf_ack_len + RF_RECV_EXTEN_LEN + 2);
set_rf_mode(TX_MODE);
/* 调制频偏 */
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_SEND_DEV);
set_rf_channel(XINCX_2_4G_CHANNEL);
/* 发射 ACk */
CE_CTL_HIGH;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l |= (1 << 5);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_SET);
#endif // DEBUG_PIN
#if (COMPATILBE_MODE == PANCHIP_PACKET)
whiten_data(&rf_data_t.buff[1], recv_len + RF_RECV_EXTEN_LEN, panchip_contorl_whiten);
#endif //(COMPATILBE_MODE == PAN2416)
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_RESET);
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_SET);
#endif // DEBUG_PIN
calc_crc_data = rf_recv_dyn_crc(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
recv_crc_data = ((rf_data_t.buff[recv_len + 1] & (~DATA_ANALYSIS_BIT_H)) << (DATA_CONTROL_BIT + BIT3)) |
((rf_data_t.buff[recv_len + 2] & 0xff) << DATA_CONTROL_BIT) |
((rf_data_t.buff[recv_len + 3] & DATA_ANALYSIS_BIT_H) >> DATA_SPLICE_BIT);
// rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
// rf_buff_info(rf_data_t.buff, recv_len + 3);
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l |= (1 << 4);
#if (COMPATILBE_MODE == PANCHIP_PACKET)
recv_crc_data = ~recv_crc_data;
#endif //(COMPATILBE_MODE == PANCHIP_PACKET)
// LOGI("calc_crc_data:0x%02x,recv_crc_data:0x%02x\nrecv_len:%d\n panchip_addr_whiten:%02x\n", calc_crc_data,
// recv_crc_data, recv_len, panchip_addr_whiten);
if (calc_crc_data == recv_crc_data) { /* CRC正确，继续发射ACK*/
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_4, GPIO_PIN_SET);
#endif // DEBUG_PIN
#if (BEKEN_PACKET == COMPATILBE_MODE)
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN - 1);
/* Wait for sending to complete */
xc_timer_stop(RF_RX_TIMERx);
xc_timer_set_value(RF_RX_TIMERx, (rf_ack_len + 10) * BIT_TIMER);
#elif (COMPATILBE_MODE == PANCHIP_PACKET)
/* Wait for sending to complete */
xc_timer_set_value(RF_RX_TIMERx, 120 + (rf_ack_len + 3 + 5 + 4) * BIT_TIMER);
/* Albino data is parsed into valid data */
rf_enhanced_packet(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN + 1);
buff_bigandsmallend(rf_data_t.buff, recv_len + RF_RECV_EXTEN_LEN + 1);
#endif
xc_timer_start(RF_RX_TIMERx);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_5, GPIO_PIN_SET);
#endif
timer_stat = RF_SEND_TIMER_INTER;
recv_crc_ok += 1;
#endif
} else { /* CRC错误，停止发射ACK并重新填入ACK数据，转接收模式 */
CE_CTL_LOW;
/* txlo spi en,1=work,默认0 */
XC_BT_RF->ana31_reg_l &= ~(1 << 5);
XC_BT_RF->ana31_reg_l &= ~(1 << 4);
memset(rf_data_t.buff, 0, recv_len);
recv_len = 0;
rf_wr_cmd(FLUSH_RX);
rf_data_config(ack_buff, rf_ack_len);
/* ACK data config */
rf_rx_ack_payload_event(ack_buff, rf_ack_len); // 96MHz 32bytes 402us
rf_set_rx_mode(XINCX_2_4G_CHANNEL, XINCX_2_4G_PIPE0_LEN);
timer_stat = RF_FREE_TIMER_INTER;
recv_crc_err += 1;
}
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_6, GPIO_PIN_RESET);
#endif
#if DEBUG_PIN
// xc_gpio_write_pin(TEST_PIN_3, GPIO_PIN_RESET);
#endif // DEBUG_PIN
}
/**
* @brief Set rf 2.4g rx mode
* @param uint16_t channel
* @retval void
*/
__RAM_CODE void rf_set_rx_mode(uint16_t channel, uint16_t fifo_len)
{
CE_CTL_LOW;
#if DEBUG_PIN
// xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_SET);
#endif // DEBUG_PIN
/* 调制频偏 */
XC_RF_2_4G->TXPROC_CFG = ((XC_RF_2_4G->TXPROC_CFG & (~0x1FF)) | RF_FREQ_RECV_DEV);
/* Set receive length */
set_rf_pipe_rx_payLen(fifo_len, fifo_len, fifo_len, fifo_len, fifo_len, fifo_len);
/* Set recv mode */
set_rf_mode(RX_MODE);
/* Set the receiving frequency */
set_rf_channel(channel);
/* AFC manual configuration */
set_rf_afc();
rf_wr_cmd(FLUSH_RX);
XC_RF_2_4G->STATUS |= MASK_RX_DR;
#if DEBUG_PIN
// xc_gpio_write_pin(TEST_PIN_7, GPIO_PIN_RESET);
#endif
CE_CTL_HIGH;
}
/**
* @brief rf 2.4g enhanced pack data loading fifo
* @param uint8_t *buff
* @param uint8_t len
* @retval void
*/
__RAM_CODE void rf_recv_sf_ack_payload(uint8_t *buff, uint8_t len)
{
rf_wr_cmd(FLUSH_TX);
XC_RF_2_4G->STATUS = MASK_TX_DS | MASK_MAX_RT;
rf_wr_cmd(W_TX_PLOAD);
#if (1 == XINCX_2_4G_CRC_BYTE)
for (uint8_t i = 0; i < rf_ack_len + RF_RECV_EXTEN_LEN; i++)
XC_RF_2_4G->TX_FIFO_DATA = ack_buff[i];
#elif (2 == XINCX_2_4G_CRC_BYTE)
for (uint8_t i = 0; i < rf_ack_len + RF_RECV_EXTEN_LEN + 1; i++) {
XC_RF_2_4G->TX_FIFO_DATA = ack_buff[i];
}
#endif
}
/**
* @brief rf 2.4g enhanced pack data loading fifo
* @param uint8_t *buff
* @param uint8_t len
* @retval void
*/
__RAM_CODE uint8_t rf_recv_enhanced_data(uint8_t *buff)
{
#if (XINCX_RF_TRANS_RATE == RATE_250K)
delay_us(60);
#endif
rf_wr_cmd(R_RX_PLOAD);
delay_us(BIT_TIMER * 3); // 接收第1字节
rf_data_t.buff[0] = XC_RF_2_4G->RX_FIFO_DATA;
/* 获取动态包长度 */
#if (COMPATILBE_MODE == PANCHIP_PACKET)
panchip_contorl_whiten = whiten_data(&rf_data_t.buff[0], 1, panchip_addr_whiten);
recv_len = rf_data_t.buff[0] >> 1;
#else
recv_len = rf_data_t.buff[0] >> 2;
#endif
if (recv_len > RF_RECV_AMX_LEN) {
recv_len = RF_RECV_AMX_LEN;
XC_RF_2_4G->RX_PW_Px_L =
(recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) | ((recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) << 8);
}
if (!recv_len) {
CE_CTL_LOW;
rf_wr_cmd(FLUSH_RX);
rf_data_config(ack_buff, rf_ack_len);
/* ACK data config */
rf_rx_ack_payload_event(ack_buff, rf_ack_len); // 96MHz 32bytes 402us
CE_CTL_HIGH;
return 0;
}
XC_RF_2_4G->RX_PW_Px_L =
(recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) | ((recv_len + RF_RECV_EXTEN_LEN + EXTEND_LEN) << 8);
/* timer 定时退出接收 */
#if (COMPATILBE_MODE == PANCHIP_PACKET)
xc_timer_set_value(RF_RX_TIMERx, (recv_len + 1 + RF_RECV_EXTEN_LEN) * BIT_TIMER + ACK_DELAY);
xc_timer_start(RF_RX_TIMERx);
#else
xc_timer_set_value(RF_RX_TIMERx, (recv_len + 2) * BIT_TIMER + ACK_DELAY);
xc_timer_start(RF_RX_TIMERx);
#endif
timer_stat = RF_RECV_TIMER_INTER;
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_2, GPIO_PIN_SET);
#endif // DEBUG_PIN
return recv_len;
}
/**
* @brief Receive data processing and start replying ACK
* @param void
* @retval void
*/
__RAM_CODE void rf_pwm_recv_data(void)
{
NVIC_DisableIRQ(RF24G_IRQn); //
xc_timer_stop(RF_RX_TIMERx);
rf_prx_ack_flag = false;
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_SET);
#endif // DEBUG_PIN
rf_recv_enhanced_data(rf_data_t.buff);
#if DEBUG_PIN
xc_gpio_write_pin(TEST_PIN_1, GPIO_PIN_RESET);
#endif // DEBUG_PIN
}
#if (XINCX_RF_COMPATIBILITY_MODE == PANCHIP_PACKET)
void rf_24g_callback(void *context)
{
uint16_t rf_stat = XC_RF_2_4G->STATUS;
#ifdef XC62XX
if (rf_stat & MASK_RX_SYNC) {
// XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
// printf("-----------------------------1\n");
XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
rf_pwm_recv_data();
}
if (rf_stat & MASK_PBT_CRC_FAIL) {
XC_RF_2_4G->STATUS |= MASK_PBT_CRC_FAIL;
}
#endif
// /* Reception is interrupted when it completes */
// if (rf_stat & MASK_RX_DR) {
// rf24g_rx_irq_flag = true;
// CE_CTL_LOW;
// #if (1 == XINCX_RF_ADV_NVIC_MODE)
// recv_len = rf_rx_event(recv_adv_buf);
// #endif // XINCX_RF_ADV_NVIC_MODE
// #if (1 == XINCX_RF_NVIC_MODE)
// recv_len = rf_rx_event(recv_buf);
// #endif // XINCX_RF_NVIC_MODE
// XC_RF_2_4G->STATUS |= MASK_RX_DR;
// #ifdef XC62XX
// XC_RF_2_4G->STATUS |= MASK_RX_SYNC;
// #endif
// }
/* The sending is interrupted when it completes */
if (rf_stat & MASK_TX_DS) {
rf24g_tx_irq_flag = true;
tx_stat = TX_DATA_OK;
XC_RF_2_4G->STATUS |= MASK_TX_DS;
}
/* The launch timeout is interrupted */
if (rf_stat & MASK_MAX_RT) {
rf24g_tx_irq_flag = true;
tx_stat = TX_RETRANS_MAX;
XC_RF_2_4G->STATUS |= MASK_MAX_RT;
}
}
#endif
/**
* @brief PWM 0 Capture the callback function
* @param void *context
* @retval uint8_t 0
*/
__RAM_CODE uint8_t pwm_capture_ch0_callback(void *context)
{
rf_pwm_recv_data();
return 0;
}
/**
* @brief PWM 1 Capture the callback function
* @param void *context
* @retval uint8_t 0
*/
__RAM_CODE uint8_t pwm_capture_ch1_callback(void *context)
{
rf_pwm_recv_data();
return 0;
}
/**
* @brief PWM 2 Capture the callback function
* @param void *context
* @retval uint8_t 0
*/
__RAM_CODE uint8_t pwm_capture_ch2_callback(void *context)
{
rf_pwm_recv_data();
return 0;
}
/**
* @brief Address whitening and writing
* @param void
* @retval uint8_t whiten_addr
*/
uint8_t rf_recv_addr(void)
{
uint16_t whiten_addr = whiten_data((uint8_t *)addr_buff, RF_ADDR_LEN, PANCHIP_WHITEN_INIT_VAL);
/* Set PTX address */
set_rf_txaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
/* Set PRX address */
set_rf_pipe0_rxaddr((addr_buff[0] << 0) | (addr_buff[1] << 8) | (addr_buff[2] << 16) | (addr_buff[3] << 24),
(addr_buff[4]));
return whiten_addr;
}
void rf_set_agc_map(uint8_t agc_gain_1th, uint8_t agc_setp)
{
uint8_t agc_map[5] = {0};
for (uint8_t i = 0; i < sizeof(agc_map); i++) {
agc_map[i] = agc_gain_1th - i * agc_setp;
}
XC_RF_2_4G->PGA_SETTING = agc_map[0] | (agc_map[1] << 8) | (agc_map[2] << 16) | (agc_map[3] << 24);
XC_RF_2_4G->TX_ADDR_H &= ~(0xFF << 8);
XC_RF_2_4G->TX_ADDR_H |= (agc_map[4] << 8);
}
project/example/2.4g/RF24_ACK_Payload/app/src/main.c
+504
View File
@@ -0,0 +1,504 @@
/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
bool rf_send_timer_flag = false;
uint8_t recv_ack_buff[256] = {0};
uint8_t ack_buff[256] = {0};
uint32_t ack_payload_cnt = 0;
uint32_t ack_payload_error = 0;
uint32_t tx_cnt, rx_cnt;
uint8_t tx_len, rx_len;
uint8_t tx_buff[256], rx_buff[256];
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void timer_init(uint8_t timer_id, uint32_t timer_cnt)
{
LOGI("timer_init\r\n");
uint32_t timerx_us = timer_cnt * 1000;
Timer_InitCfg_t timer_cfg;
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32M_DIV;
timer_cfg.timer_div_clk = TIMER_DIV_CLK_1MHzOr1K;
timer_cfg.timer_mode = TIMER_MODE_CYCLE;
xc_timer_init(timer_id, &timer_cfg);
xc_timer_set_value(timer_id, timerx_us);
xc_timer_start(timer_id);
}
/**
* @brief Timer0_Callback
* @param void * - context
*
* @retval void
*/
void timer0_callback(void *context)
{
#if !(XINCX_RF_MODE)
rf_send_timer_flag = true;
#endif // !(XINCX_RF_MODE)
}
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
#ifdef XC62XX
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
#else
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
#endif
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
#ifdef DEBUG_LOG
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x%08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x%08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
#ifdef XC62XX
LOGI("HW_CONFIG: 0x%08x\r\n", XC_RF_2_4G->HW_CONFIG);
LOGI("PBT_CONFIG: 0x%08x\r\n", XC_RF_2_4G->PBT_CONFIG);
LOGI("PBT_TIMER: 0x%08x\r\n", XC_RF_2_4G->PBT_TIMER);
LOGI("PBT_SYNC_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_SYNC_TIME);
LOGI("PBT_TX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_TX_HEAD);
LOGI("PBT_RX_HEAD: 0x%08x\r\n", XC_RF_2_4G->PBT_RX_HEAD);
LOGI("PBT_AUTO_TRX_TIME: 0x%08x\r\n", XC_RF_2_4G->PBT_AUTO_TRX_TIME);
#endif
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
#endif
/**
* @brief RF 2.4g data config
* @param uint8_t * - buff
* uint8 - len
* @retval uint8_t - 0
*/
uint8_t rf_data_config(uint8_t *buff, uint8_t len)
{
if (len == 0) {
return RF_FAIL;
}
for (uint8_t i = 0; i < len; i++) {
buff[i] = i;
}
return RF_SUCCESS;
}
/**
* @brief RF ack payload config
* @param void
* @retval void
*/
void rf_ack_payload_config(void)
{
#if (XINCX_RF_TRANS_RATE == RATE_250K)
XC_RF_2_4G->SETUP_RETR = 0xf0;
#endif //(XINCX_RF_TRANS_RATE == RATE_250K)
}
/**
* @brief RF ack tx fifo
* @param uint8_t * - ack_buff
* @param uint8_t - buff_len
* @retval void
*/
void rf_ackpayload_tx_fifo(uint8_t *rx_send_ack_buff, uint8_t buff_len)
{
rf_wr_cmd(W_ACK_PLOAD);
for (uint8_t i = 0; i < buff_len; i++) {
XC_RF_2_4G->TX_FIFO_DATA = rx_send_ack_buff[i];
}
}
/**
* @brief RF ack recv event
* @param uint8_t * - ack_buff
* @param uint8_t - buff_len
* @retval void
*/
uint8_t rf_recv_ackpayload_event(uint8_t *tx_recv_ack_buff)
{
rf_wr_cmd(R_RX_PL_WID);
uint8_t ack_len = XC_RF_2_4G->RX_FIFO_LEN & 0xff;
if (ack_len) {
rf_wr_cmd(R_RX_PLOAD);
for (uint8_t i = 0; i < ack_len; i++) {
tx_recv_ack_buff[i] = XC_RF_2_4G->RX_FIFO_DATA;
}
}
rf_wr_cmd(FLUSH_RX);
XC_RF_2_4G->STATUS = MASK_RX_DR;
return ack_len;
}
/**
* @brief RF 2.4g tx manage
* @param void
* @retval void
*/
__RAM_CODE void rf_tx_manage(void)
{
uint8_t ack_status = TX_DATA_INVALID;
uint8_t ack_len = 0;
static uint32_t ack_cnt = 0;
if (rf_send_timer_flag) {
rf_send_timer_flag = false;
tx_cnt += 1;
rf_data_config(tx_buff, BUFF_LEN);
/* Filling in software frame number */
tx_buff[0] = tx_cnt;
/* data transmission */
ack_status = rf_tx_event(tx_buff, BUFF_LEN);
/* Response data processing */
if (ack_status == TX_DATA_OK) {
ack_status = TX_DATA_INVALID;
ack_len = rf_recv_ackpayload_event(ack_buff);
XC_RF_2_4G->STATUS = MASK_ALL_INTER;
}
if (ack_len != 0) {
ack_cnt += 1;
for (uint8_t i = 0; i < ack_len; i++) {
// LOGI("%0d ", ack_buff[i]);
}
LOGI("\r\n");
ack_len = 0;
/* Clear response data*/
memset(ack_buff, 0, sizeof(ack_buff));
}
LOGI("send_cnt:%d,ack_cnt:%d\r\n", tx_cnt,ack_cnt);
}
}
/**
* @brief RF 2.4g rx manage
* @param void
* @retval void
*/
#if !(XINCX_RF_NVIC_MODE)
__RAM_CODE void rf_rx_manage(void)
{
static uint32_t conut = 0;
static uint32_t recv_cnt = 0;
static uint32_t recv_err = 0;
/* Receive event processing */
rx_len = rf_rx_event(rx_buff);
/* Receiving end polling data processing */
if (len != 0) {
/* Entering standby mode */
CE_CTL_LOW;
/* ack payoad */
// rf_ackpayload_tx_fifo(tx_buff, BUFF_LEN);
memcpy(rx_buff, recv_buf, rx_len);
rf_ackpayload_tx_fifo(rx_buff, rx_len);
/* Receive Count */
rx_cnt += 1;
LOGI("recv:%d\r\n", conut);
/* Receiving data processing */
if (rx_buff[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE) {
LOGI("%d\r\n", recv_cnt);
recv_cnt += 1;
} else {
recv_err += 1;
}
rf_buff_info(rx_buff, len);
/* Receive read data buffer reset */
memset(tx_buff, 0, rx_len);
rx_len = 0;
/* Entering the receiver */
CE_CTL_HIGH;
}
}
#else
__RAM_CODE void rf_rx_manage(void)
{
static uint32_t conut = 0;
static uint32_t recv_cnt = 0;
static uint32_t recv_err = 0;
if (rf24g_rx_irq_flag) {
rf24g_rx_irq_flag = false;
rx_len = recv_len;
/* Entering standby mode */
CE_CTL_LOW;
/* Ack payoad */
memcpy(rx_buff, recv_buf, rx_len);
rf_ackpayload_tx_fifo(rx_buff, rx_len);
if ((rx_len != 0) && (recv_buf[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE)) {
recv_cnt += 1;
} else {
recv_err += 1;
}
//rf_buff_info(recv_buf, rx_len);
/* Receive Count */
rx_cnt += 1;
xc_timer_set_value(RF_RX_TIMERx, 3000000);
xc_timer_start(RF_RX_TIMERx);
LOGI("recv:%d\r\n", rx_cnt);
/* Receive read data buffer reset */
memset(recv_buf, 0, rx_len);
rx_len = 0;
recv_len = 0;
/* Entering the receiver */
CE_CTL_HIGH;
}
}
#endif //!(XINCX_RF_NVIC_MODE)
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint8_t len)
{
for (uint8_t i = 0; i < len; i++)
LOGI("%d ", buff[i]);
LOGI("\r\n");
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
/**
* @brief main
* @details
* @param[in] void
* @param[out] void
* @retval int - 0
* @retval void
* @par identifier
* reserve
* @par other
* void
* @par change log
* Alex created on 2023-05-31
*/
int main(void)
{
/* Clock initialization */
clock_init();
/* Serial port initialization */
app_uart_init();
/* rf 2.4g initialization configuration */
rf24g_init();
/* Set up ACKPAYLOD */
rf_ack_payload_config();
/* Set testing frequency points */
rf_set_channel(XINCX_2_4G_CHANNEL);
#if (XINCX_RF_TRANS_RATE == DR_2M)
/* Set 2M mode register configuration */
/* Don't move this function interface */
rf_2M_config();
#endif //(XINCX_RF_TRANS_RATE == DR_2M)
#ifdef DEBUG_LOG
/* Register information printing */
rf_dump_log();
#endif // DEBUG_LOG
#if XINCX_RF_MODE
#if (XINCX_RF_NVIC_MODE)
/* Enable RF2.4G interrupts */
NVIC_EnableIRQ(RF24G_IRQn);
/* Configure the RF2.4G interrupt priority */
NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
/* ACK data packaging filling */
rf_data_config(ack_buff, sizeof(ack_buff));
/* Fill in TX FIFO */
rf_ackpayload_tx_fifo(ack_buff, sizeof(ack_buff));
/* Receive timeout setting :ms */
timer_init(RF_RX_TIMERx, RECV_TIMERMS_OUT);
/* RX enters receiver */
CE_CTL_HIGH;
#else
/* Launch data packaging filling */
rf_data_config(tx_buff, BUFF_LEN);
/* Set emission interval */
timer_init(RF_TX_TIMERx, SEND_TIMERMS_CNT);
#endif // XINCX_RF_MODE
for (;;) {
#if XINCX_RF_MODE
/* receive */
rf_rx_manage();
#else
/* sending */
rf_tx_manage();
#endif // XINCX_RF_MODE
}
}