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Stair56E UART project

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This commit is contained in:
吴琪
2026-08-05 19:07:52 +08:00
parent 7ca1af130d
commit f5654b70cc
2500 changed files with 619007 additions and 282610 deletions
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project/example/2.4g/RF24_ACK_SLEEP/app/Startup/lora/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD 0 ; 0 BLE Handler
DCD DMAS_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler
DCD TIMER2_Handler
DCD TIMER3_Handler
DCD WDT_Handler
DCD I2C_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD SPI0_Handler
DCD SPI1_Handler
DCD 0
DCD 0
DCD GADC_Handler ; 17
DCD 0 ; 18
DCD 0 ; 19
DCD 0 ; 20
DCD 0 ; 21
DCD RF24G_Handler ; 22
DCD PWM_Handler ; 23
DCD BOR_Handler ; 24
DCD 0 ; 25
DCD 0 ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
;EXPORT BLE_Handler [WEAK]
EXPORT DMAS_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT AOTIMER0_Handler [WEAK]
EXPORT AOTIMER1_Handler [WEAK]
EXPORT CMP_Handler [WEAK]
EXPORT FMC_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
;EXPORT SIM_Handler [WEAK]
;EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT RF24G_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT BOR_Handler [WEAK]
PendSV_Handler
SysTick_Handler
;BLE_Handler
DMAS_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
;SIM_Handler
;AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
RF24G_Handler
PWM_Handler
BOR_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_ACK_SLEEP/app/Startup/system_it_xinc.c
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/*!
* \file system_it_xinc.c
*
* \brief Target system interruption implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "system_it_xinc.h"
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief This function handles NMI exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END NonMaskableInt_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Hard Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END HardFault_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Memory Manage exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Bus Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Usage Fault exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles SVCall exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END SVCall_IRQn */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles Debug Monitor exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN */
DEBUG("%s\n", __func__);
/* USER CODE END */
while (1)
{
}
}
/**
****************************************************************************************
* @brief This function handles PendSVC exception.
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn */
DEBUG("%s\n", __func__);
/* USER CODE END PendSV_IRQn */
while (1)
{
}
}
/****************************** Hard Fault Handler Functions *******************************/
/*------------------------------------------------------------------------------------
Private Functions
-------------------------------------------------------------------------------------*/
void HardFault_Handler_c(unsigned int * HardFault_args)
{
/*栈帧里面内容：*/
unsigned int stack_r0; //压栈的 R0
unsigned int stack_r1; //压栈的 R1
unsigned int stack_r2; //压栈的 R2
unsigned int stack_r3; //压栈的 R3
unsigned int stack_r12; //压栈的 R12
unsigned int stack_lr; //压栈的 lr
unsigned int stack_pc; //压栈的 pc
unsigned int stack_psr; //压栈的 psr
stack_r0 = ((unsigned int)HardFault_args[0]);
stack_r1 = ((unsigned int)HardFault_args[1]);
stack_r2 = ((unsigned int)HardFault_args[2]);
stack_r3 = ((unsigned int)HardFault_args[3]);
stack_r12 = ((unsigned int)HardFault_args[4]);
stack_lr = ((unsigned int)HardFault_args[5]);
stack_pc = ((unsigned int)HardFault_args[6]);
stack_psr = ((unsigned int)HardFault_args[7]);
DEBUG("----%s----\n", __func__);
DEBUG("R0=%x\n",stack_r0);
DEBUG("R1=%x\n",stack_r1);
DEBUG("R2=%x\n",stack_r2);
DEBUG("R3=%x\n",stack_r3);
DEBUG("R12=%x\n",stack_r12);
DEBUG("LR[R14]=%x\n",stack_lr);
DEBUG("PC[R15]=%x\n",stack_pc);
DEBUG("PSR=%x\n",stack_psr);
DEBUG("SCB_SHCSR=%x\n",SCB->SHCSR);
DEBUG("---------------------------\n");
while(1);
}
/*******************************************************************************************/
project/example/2.4g/RF24_ACK_SLEEP/app/Startup/system_it_xinc.h
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/*!
* \file system_it_xinc.h
*
* \brief The header of system_it_xinc.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SYSTEM_IT_XINC_H__
#define __SYSTEM_IT_XINC_H__
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void NMI_Handler( void );
void HardFault_Handler( void );
void MemManage_Handler( void );
void BusFault_Handler( void );
void UsageFault_Handler( void );
void SVC_Handler( void );
void DebugMon_Handler( void );
void PendSV_Handler( void );
void HardFault_Handler_c(unsigned int * HardFault_args);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_IT_XINC_H__ */
project/example/2.4g/RF24_ACK_SLEEP/app/Startup/system_xinc.c
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/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
*
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include <stdio.h>
#include "xc6xxx.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define __DEBUG_OUT_PORT 0
#define readl(addr) (*(volatile unsigned int *) (addr))
#define writel(addr, value) (*(volatile unsigned int *) (addr) = (value))
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
#define VECTOR_NUM 48
void set_vector(void)
{
#if (USE_XIP == 1)
__disable_irq();
for (uint32_t i = 0, *Pvector = (uint32_t *)(0x11001000 + 0),
*_vector_table = (uint32_t *)(0x10000000);
i < VECTOR_NUM; i++) // copy vertor table
{
_vector_table[i] = *Pvector++;
}
*((volatile unsigned int *)(0x4000013C)) =
0x10000001; // inter vertor table remap
__enable_irq();
#endif
}
static void WDT_ResetInit(void)
{
cpr_ctlapbclken_grctl__wdt_pclk_en__setf(ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_ENABLE);
cpr_rstctl_ctlapb_sw__wdt_rstn__setf(RSTCTL_DISABLE);
cpr_rstctl_wdtrst_mask_set(
(WDT_SYS_RSTN_MASK_DISABLE | WDT_M0_RSTN_MASK_ENABLE));
cpr_lp_ctl__wdt_tclk_en__setf(ENABLE);
wdt_cr__wdt_en__setf(DISABLE);
}
void SystemInit(void)
{
WDT_ResetInit();
#if (USE_XIP == 1)
set_vector();
#endif
writel(0x40000040, readl(0x40000040) | (0x01 << 4) | 0xFFFF0000);
}
__RAM_CODE int sendchar(int c)
{
unsigned int status;
#if (__DEBUG_OUT_PORT == 1)
for (;;) {
status = (*((volatile unsigned *)(0x40011000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40011000 + 0x00))) = c;
return (1);
#else
for (;;) {
status = (*((volatile unsigned *)(0x40010000 + 0x14)));
status &= 0x20;
if (status == 0x20)
break;
}
(*((volatile unsigned *)(0x40010000 + 0x00))) = c;
return (1);
#endif
}
struct __FILE
{
int handle; /* Add whatever you need here */
};
FILE __stdout;
__RAM_CODE int fputc(int ch, FILE *f) { return (sendchar(ch)); }
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
void _ttywrch(int ch) { sendchar(ch); }
void _sys_exit(int return_code)
{
label:
goto label; /* endless loop */
}
project/example/2.4g/RF24_ACK_SLEEP/app/Startup/xc60xx/startup_xinc.s
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;/*****************************************************************************
; * @file: startup_xinc.s
; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the
; * Device xinc.
; *****************************************************************************/
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD BLE_Handler ; 0
DCD DMA_Handler ; 1
DCD CPR_Handler ; 2
DCD GPIO_Handler ; 3
DCD RTC_Handler ; 4
DCD TIMER0_Handler ; 5
DCD TIMER1_Handler ; 6
DCD TIMER2_Handler ; 7
DCD TIMER3_Handler ; 8
DCD WDT_Handler ; 9
DCD I2C_Handler ; 10
DCD UART0_Handler ; 11
DCD UART1_Handler ; 12
DCD SPI0_Handler ; 13
DCD SPI1_Handler ; 14
DCD 0 ; 15
DCD 0 ; 16
DCD GADC_Handler ; 17
DCD PWM_Handler ; 18
DCD AES_Handler ; 19
DCD USB_Handler ; 20
DCD AUDIO_Handler ; 21
DCD RF24G_Handler ; 22
DCD SPI2_Handler ; 23
DCD 0 ; 24
DCD UART2_Handler ; 25
DCD I2S_Handler ; 26
DCD AOTIMER0_Handler ; 27
DCD AOTIMER1_Handler ; 28
DCD CMP_Handler ; 29
DCD FMC_Handler ; 30
DCD CAN_Handler ; 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR r0, =0x4000013C ; remap
LDR r1, =0x10000001
STR r1, [r0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT HardFault_Handler_c ;函数声明
movs r0, #4 ;判断主栈指针还是进程栈指针
mov r1, lr
tst r0, r1
beq hf_used_msp ;如果是主栈指针
mrs r0, psp ;否则是进程栈指针,把进程栈指针地址付给 R0
ldr r1, =HardFault_Handler_c ;跳转到 HardFault 中断程序
bx r1
hf_used_msp
mrs r0, msp ;把主栈指针地址赋给 R0
ldr r1, =HardFault_Handler_c
bx r1
;EXPORT HardFault_Handler [WEAK]
;B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BLE_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT CPR_Handler [WEAK]
EXPORT GPIO_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT TIMER2_Handler [WEAK]
EXPORT TIMER3_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT I2C_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
;EXPORT KBS_Handler [WEAK]
;EXPORT QDEC_Handler [WEAK]
EXPORT GADC_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT USB_Handler [WEAK];20
EXPORT AUDIO_Handler [WEAK];21
EXPORT RF24G_Handler [WEAK];22
EXPORT SPI2_Handler [WEAK];23
;EXPORT MPU_Handler [WEAK];24
EXPORT UART2_Handler [WEAK];25
EXPORT I2S_Handler [WEAK];26
EXPORT AOTIMER0_Handler [WEAK];27
EXPORT AOTIMER1_Handler [WEAK];28
EXPORT CMP_Handler [WEAK];29
EXPORT FMC_Handler [WEAK];30
EXPORT CAN_Handler [WEAK];31
PendSV_Handler
SysTick_Handler
BLE_Handler
RF24G_Handler
DMA_Handler
CPR_Handler
GPIO_Handler
RTC_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
WDT_Handler
I2C_Handler
I2S_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
;KBS_Handler
;QDEC_Handler
GADC_Handler
PWM_Handler
AUDIO_Handler
;SIM_Handler
AES_Handler
AOTIMER0_Handler
AOTIMER1_Handler
CMP_Handler
FMC_Handler
CAN_Handler
USB_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
END
project/example/2.4g/RF24_ACK_SLEEP/app/api/main.h
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/*
* @Descripttion:
* @version:
* @Author: sueRimn
* @Date: 2023-12-12 14:23:55
* @LastEditors: sueRimn
* @LastEditTime: 2024-06-07 13:46:09
*/
/*!
* \file main.h
*
* \brief The head file of main.c
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H__
#define __MAIN_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "rf_config.h"
#include "xc6xxx.h"
#include "xc6xxx_rf_2_4g.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
#define DEBUG_LOG
#define RECV_TIME_OUT 2200
#define SEND_INTERVAL_NOSLEEP 950
#define SEND_INTERVAL_SLEEP 986
#define SEND_INTERVAL_DEEPSLEEP 932
#define RECV_NOSLEEP_DURATION 936
#define RECV_SLEEP_DURATION 970
#define RECV_DEEPSLEEP_DURATION 919
#define XC_SEND_NUM 1000U
#define RF_TX_TIMERx TIMER0_IDX
#define RF_RX_TIMERx TIMER0_IDX
#define RF_CONFIRMED_VALUE 5
#define NO_SLEEP_DEMO 0
#define SLEEP_DEMO 1
#define DEEPSLEEP_DEMO 2
#define SLEEP_MODE DEEPSLEEP_DEMO
/*------------------------------------------------------------------------------------
TypeDef
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
extern bool rf_send_timer_flag;
extern bool rf24g_handler_flag;
/*------------------------------------------------------------------------------------
Exported Functions
-------------------------------------------------------------------------------------*/
void rf_tx_manage(void);
bool rf_rx_manage(void);
void rf_buff_info(uint8_t *buff, uint8_t len);
void rf_2M_reg_info(void);
void rf_dump_log(void);
uint8_t rf_data_init(uint8_t *buff,uint16_t len);
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H__ */
project/example/2.4g/RF24_ACK_SLEEP/app/rf_config/rf_config.h
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#ifndef SDK_CONFIG_H
#define SDK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> XINCX_RF_NORMAL_PEACKET_MODE - RF normal packet mode
// <i> Configure the frame format, which is a static packet format and can only communicate in one direction.
#ifndef XINCX_RF_NORMAL_PACKET_MODE
#define XINCX_RF_NORMAL_PACKET_MODE 1
#endif
// <o>XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <0=> Xinchip
#ifndef XINCX_RF_COMPATIBILITY_MODE
#define XINCX_RF_COMPATIBILITY_MODE 0
#endif
#if (XINCX_RF_NORMAL_PACKET_MODE == 1)
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2440
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7//0xCCDDEEDD
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7//0xAA
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 0
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
//
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 0
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 0
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 0
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 0
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 0
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 0
#endif
//
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 0
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x00
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 0
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 0
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 0
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 0
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 0
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 0
#endif
// XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 0
#endif
#endif
// </e> //XINCX_RF_PEACKET_MODE normal normal
// <e> XINCX_RF_EMHAMCED_PEACKET_MODE - RF enhanced packet mode
// <i> Configure the frame format, which is a dynamic packet configuration, which can communicate in both directions,and
// <i> ACK can dynamically carry data.
#ifndef XINCX_RF_EMHAMCED_PACKET_MODE
#define XINCX_RF_EMHAMCED_PACKET_MODE 0
#endif
#if (XINCX_RF_EMHAMCED_PACKET_MODE == 1)
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_RF_MODE - RF Tx or Rx Mode
// <0=> TX Mode
// <1=> RX Mode
#ifndef XINCX_RF_MODE
#define XINCX_RF_MODE 0
#endif
// <o> XINCX_RF_TRANS_RATE - RF Transmission Rate Config
// <0x02=> 1M
// <0x0A=> 2M
// <0x22=> 250k
// <0x2A=> 125k
#ifndef XINCX_RF_TRANS_RATE
#define XINCX_RF_TRANS_RATE 0x02
#endif
// <o> XINCX_2_4G_CHANNEL - 2.4g Channel Set
#ifndef XINCX_2_4G_CHANNEL
#define XINCX_2_4G_CHANNEL 2440
#endif
// <o> XINCX_RF_TX_ADDR_WIDTH - RF Tx Addr Width
// <3=> 3 Bytes
// <4=> 4 Bytes
// <5=> 5 Bytes
#ifndef XINCX_RF_TX_ADDR_WIDTH
#define XINCX_RF_TX_ADDR_WIDTH 5
#endif
// <o> XINCX_2_4G_ADDR_L - rf Address Set
#ifndef XINCX_2_4G_ADDR_L
#define XINCX_2_4G_ADDR_L 0xe7e7e7e7
#endif
// <o> XINCX_2_4G_ADDR_H - rf Address Set
#ifndef XINCX_2_4G_ADDR_H
#define XINCX_2_4G_ADDR_H 0xe7
#endif
// <o> XINCX_RF_POWER - rf Power Set
// <1=> -10dbm
// <2=> -9dbm
// <4=> -4dbm
// <6=> 0dbm
// <8=> 3dbm
// <9=> 5dbm
// <12=> 7dbm
// <14=> 8dbm
// <16=> 9dbm
// <19=> 10dbm
// <24=> 11dbm
// <30=> 12dbm
// <36=> 13dbm
#ifndef XINCX_POWER
#define XINCX_POWER 0x00006
#endif
// <o> XINCX_RF_NVIC_MODE - RF NVIC Mode
// <0=> Disable
// <1=> Enable
#ifndef XINCX_RF_NVIC_MODE
#define XINCX_RF_NVIC_MODE 1
#endif
// XINCX_2_4G_PIPE_RX_PAYLEN - 2.4g Pipe Rx Payload Len
// <i> Payload length. Configuration of the load length during communication.
//==========================================================
// XINCX_2_4G_PIPE0_LEN - 2.4g Pipe0 Rx Payload Len
// #ifndef XINCX_2_4G_PIPE0_LEN
// #define XINCX_2_4G_PIPE0_LEN 32
// #endif
// XINCX_2_4G_PIPE1_LEN - 2.4g Pipe1 Rx Payload Len
#ifndef XINCX_2_4G_PIPE1_LEN
#define XINCX_2_4G_PIPE1_LEN 32
#endif
// XINCX_2_4G_PIPE2_LEN - 2.4g Pipe2 Rx Payload Len
#ifndef XINCX_2_4G_PIPE2_LEN
#define XINCX_2_4G_PIPE2_LEN 32
#endif
// XINCX_2_4G_PIPE3_LEN - 2.4g Pipe3 Rx Payload Len
#ifndef XINCX_2_4G_PIPE3_LEN
#define XINCX_2_4G_PIPE3_LEN 32
#endif
// XINCX_2_4G_PIPE4_LEN - 2.4g Pipe4 Rx Payload Len
#ifndef XINCX_2_4G_PIPE4_LEN
#define XINCX_2_4G_PIPE4_LEN 32
#endif
// XINCX_2_4G_PIPE5_LEN - 2.4g Pipe5 Rx Payload Len
#ifndef XINCX_2_4G_PIPE5_LEN
#define XINCX_2_4G_PIPE5_LEN 32
#endif
// XINCX_RF_CRC_ENABLE - RF CRC Enable
//==========================================================
#ifndef XINCX_RF_CRC_ENABLE
#define XINCX_RF_CRC_ENABLE 1
#endif
// <o> XINCX_2_4G_CRC_BYTE - 2.4g CRC Bytes Set
// <0=> 0 Byte
// <1=> 1 Byte
// <2=> 2 Bytes
#ifndef XINCX_2_4G_CRC_BYTE
#define XINCX_2_4G_CRC_BYTE 2
#endif
// XINCX_2_4G_FEATURE_PARAM - 2.4g Feature Parameters
//==========================================================
// XINCX_2_4G_GUARD_CFG - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_GUARD_CFG
#define XINCX_2_4G_GUARD_CFG 0
#endif
// XINCX_2_4G_LONG_PLD_TYPE - 2.4g Long Pld Type
#ifndef XINCX_2_4G_LONG_PLD_TYPE
#define XINCX_2_4G_LONG_PLD_TYPE 0
#endif
// XINCX_2_4G_PREAMBLE_NUM - 2.4g Preamble
#ifndef XINCX_2_4G_PREAMBLE_NUM
#define XINCX_2_4G_PREAMBLE_NUM 0
#endif
// XINCX_2_4G_PREAMBLE_TYPE - 2.4g Preamble Type
#ifndef XINCX_2_4G_PREAMBLE_TYPE
#define XINCX_2_4G_PREAMBLE_TYPE 0
#endif
// XINCX_2_4G_CRC_SCOPE_GUARD - 2.4g CRC Scope Guard
#ifndef XINCX_2_4G_CRC_SCOPE_GUARD
#define XINCX_2_4G_CRC_SCOPE_GUARD 0
#endif
// XINCX_2_4G_CRC_SCOPE_HEADER - 2.4g CRC Scope Header
#ifndef XINCX_2_4G_CRC_SCOPE_HEADER
#define XINCX_2_4G_CRC_SCOPE_HEADER 1
#endif
// XINCX_2_4G_CRC_SCOPE_ADDR - 2.4g CRC Scope Addr
#ifndef XINCX_2_4G_CRC_SCOPE_ADDR
#define XINCX_2_4G_CRC_SCOPE_ADDR 1
#endif
// <q> XINCX_2_4G_LONG_PLD - 2.4g Long Payload Feature
#ifndef XINCX_2_4G_LONG_PLD
#define XINCX_2_4G_LONG_PLD 1
#endif
// <q> XINCX_2_4G_FEC - 2.4g FEC&Interleave Feature
#ifndef XINCX_2_4G_FEC
#define XINCX_2_4G_FEC 1
#endif
// <q> XINCX_2_4G_WHITEN - 2.4g Whiten Feature
#ifndef XINCX_2_4G_WHITEN
#define XINCX_2_4G_WHITEN 1
#endif
// XINCX_2_4G_DPL - 2.4g Dynamic Payload Length Feature
#ifndef XINCX_2_4G_DPL
#define XINCX_2_4G_DPL 1
#endif
// XINCX_2_4G_ACK_PAY - 2.4g Payload on ACK
#ifndef XINCX_2_4G_ACK_PAY
#define XINCX_2_4G_ACK_PAY 1
#endif
// XINCX_2_4G_DYN_ACK - 2.4g W_TX_PAYLOAD_NOACK Command
#ifndef XINCX_2_4G_DYN_ACK
#define XINCX_2_4G_DYN_ACK 1
#endif
// XINCX_2_4G_DYNPD - 2.4g dynpd
#ifndef XINCX_2_4G_DYNPD
#define XINCX_2_4G_DYNPD 0x3f
#endif
// XINCX_2_4G_AUTO_ACK - 2.4g Auto Acknowledgement
//==========================================================
// XINCX_2_4G_PIPE0_ENAA - 2.4g Pipe0 Auto Ack
#ifndef XINCX_2_4G_PIPE0_ENAA
#define XINCX_2_4G_PIPE0_ENAA 1
#endif
// XINCX_2_4G_PIPE1_ENAA - 2.4g Pipe1 Auto Ack
#ifndef XINCX_2_4G_PIPE1_ENAA
#define XINCX_2_4G_PIPE1_ENAA 1
#endif
// XINCX_2_4G_PIPE2_ENAA - 2.4g Pipe2 Auto Ack
#ifndef XINCX_2_4G_PIPE2_ENAA
#define XINCX_2_4G_PIPE2_ENAA 1
#endif
// XINCX_2_4G_PIPE3_ENAA - 2.4g Pipe3 Auto Ack
#ifndef XINCX_2_4G_PIPE3_ENAA
#define XINCX_2_4G_PIPE3_ENAA 1
#endif
// XINCX_2_4G_PIPE4_ENAA - 2.4g Pipe4 Auto Ack
#ifndef XINCX_2_4G_PIPE4_ENAA
#define XINCX_2_4G_PIPE4_ENAA 1
#endif
// XINCX_2_4G_PIPE5_ENAA - 2.4g Pipe5 Auto Ack
#ifndef XINCX_2_4G_PIPE5_ENAA
#define XINCX_2_4G_PIPE5_ENAA 1
#endif
// <o.0..5> XINCX_RF_PIPE_ENABLE
#ifndef XINCX_RF_PIPE_ENABLE
#define XINCX_RF_PIPE_ENABLE 1
#endif
// XINCX_2_4G_TRANS_PARAM - 2.4g Transmission Parameters
//==========================================================
// <o> XINCX_2_4G_RETRANS_CNT - 2.4g Retransmit Count
// <i> Number of retransmissions. The maximum number of times a hardware can automatically transmit an ACK if it does
// not receive the correct ACK.
// <0=> No retransmission
// <1=> 1 time
// <2=> 2 times
// <3=> 3 times
// <4=> 4 times
// <5=> 5 times
// <6=> 6 times
// <7=> 7 times
// <8=> 8 times
// <9=> 9 times
// <10=> 10 times
// <11=> 11 times
// <12=> 12 times
// <13=> 13 times
// <14=> 14 times
// <15=> 15 times
#ifndef XINCX_2_4G_RETRANS_CNT
#define XINCX_2_4G_RETRANS_CNT 0
#endif
// <o> XINCX_2_4G_RETRANS_DELAY - 2.4g Retransmission Delay
// <i> Retransmission delay. For 32 bytes of data, the minimum configuration is 500 us for 1 Mbit/s and 1500 us for 250
// kbit/s.
// <0=> 250us
// <1=> 500us
// <2=> 750us
// <3=> 1000us
// <4=> 1250us
// <5=> 1500us
// <6=> 1750us
// <7=> 2000us
// <8=> 2250us
// <9=> 2500us
// <10=> 2750us
// <11=> 3000us
// <12=> 3250us
// <13=> 3500us
// <14=> 3750us
// <15=> 4000us
#ifndef XINCX_2_4G_RETRANS_DELAY
#define XINCX_2_4G_RETRANS_DELAY 3
#endif
#endif
// </e> //XINCX_RF_PEACKET_MODE enhanced normal
// RF 2.4g Compatibility configuration
//==========================================================
// Compatibility configuration, when you need to be compatible with other RF chips, you don't need to configure this
// option when using our company's chips.
// XINCX_2_4G_PREAMBLE - 2.4g preamble
#ifndef XINCX_2_4G_PREAMBLE
#define XINCX_2_4G_PREAMBLE 0x710f5555
#endif
// XINCX_2_4G_GUARD - 2.4g guard
#ifndef XINCX_2_4G_GUARD
#define XINCX_2_4G_GUARD 0x8fc9
#endif
//
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
//==========================================================
// Crystal capacitor array, adjust to modify the frequency offset of the crystal oscillator.
// XINCX_2_4G_CRY_CPT_ARRAY - 2.4g Crystal capacitor array
#ifndef XINCX_2_4G_CRY_CPT_ARRAY
#ifdef XC62XX
#define XINCX_2_4G_CRY_CPT_ARRAY 0x38
#else
#define XINCX_2_4G_CRY_CPT_ARRAY 0x36
#endif
#endif
//
// <<< end of configuration section >>>
#endif // SDK_CONFIG_H
project/example/2.4g/RF24_ACK_SLEEP/app/src/main.c
+773
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/*!
* \file main.c
*
* \brief Target main implementation
*
* \copyright Revised BSD License, see section \ref LICENSE.
*
* \code
*
* _ __ _ ________ _
* | |/ /(_)___ / ____/ /_ (_)___
* | // / __ \/ / / __ \/ / __ \
* / |/ / / / / /___/ / / / / /_/ /
* /_/|_/_/_/ /_/\____/_/ /_/_/ .___/
* /_/
* (C) 2022-2025 XinChip
*
* \endcode
*
* \author ( XinChip ) Alex-J
*
* \author ( XinChip )
*/
/*-----------------------------------------------------------------------------------
INCLUDE HEADE FILES
------------------------------------------------------------------------------------*/
#include "main.h"
/*------------------------------------------------------------------------------------
Macros
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Global Variables
-------------------------------------------------------------------------------------*/
bool rf_timer_flag = false;
uint32_t send_cnt = 0;
uint8_t rx_len, tx_len;
uint32_t rx_cnt = 0;
uint32_t tx_cnt = 0;
uint8_t tx_buff[256] = {0};
uint8_t rx_buff[256] = {0};
/*------------------------------------------------------------------------------------
Func Prototype
-------------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------------
Functions
-------------------------------------------------------------------------------------*/
/**
****************************************************************************************
* @brief
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void timer_init(uint8_t timer_id)
{
/* Timer for sleep-wake*/
Timer_InitCfg_t timer_cfg;
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32K;
timer_cfg.timer_div_clk = TIMER_DIV_CLK_32000Hz;
timer_cfg.timer_mode = TIMER_MODE_SINGLE;
xc_timer_init(timer_id, &timer_cfg);
}
void timer_start(uint8_t timer_id, uint32_t timer_cnt)
{
uint32_t timerx_us = timer_cnt * 1000;
xc_timer_set_value(timer_id, timerx_us);
xc_timer_start(timer_id);
}
void timer_stop(uint8_t timer_id)
{
xc_timer_stop(timer_id);
}
/**
* @brief timer0_Callback
* @param void * - context
*
* @retval void
*/
void timer0_callback(void *context)
{
rf_timer_flag = true;
}
/**
****************************************************************************************
* @brief Clock Initialization
*
* @param[in]
* @param[in]
****************************************************************************************
*/
void clock_init(void)
{
CLOCK_InitCfg_t clock_cfg;
clock_cfg.hfclk_src = CLOCK_HFCLK_SRC_XTAL;
clock_cfg.hfclk_in = CLOCK_HFCLK_IN_32M;
#if (RC_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
#endif //(RC_32K)
#if (XTAL_32K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32K)
#if (XTAL_32768K)
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_XTAL;
#endif // (XTAL_32768K)
#ifdef XC62XX
clock_cb.lfclk_src = CLOCK_LFCLK_SRC_RC;
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
#else
if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_XTAL) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32768;
} else if (clock_cfg.lfclk_src == CLOCK_LFCLK_SRC_RC) {
clock_cfg.lfclk_in = CLOCK_LFCLK_IN_32K;
}
#endif
xc_clock_init_cfg(&clock_cfg);
SysTick_Config(xc_clock_hfclk_in_get() / 100);
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
#ifdef DEBUG_LOG
/**
* @brief RF 2.4g register information printing
* @param void
* @retval void
*/
void rf_2M_reg_info(void)
{
/* Register information printing */
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG_L: 0x%08x\r\n", XC_RF_2_4G->RXPROC_CFG_L);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("rccal_reg_l: 0x%08x\r\n", XC_BT_RF->rccal_reg_l);
LOGI("ana2_reg_l: 0x%08x\r\n", XC_BT_RF->ana2_reg_l);
LOGI("ana3_reg_l: 0x%08x\r\n", XC_BT_RF->ana3_reg_l);
LOGI("ana4_reg_l: 0x%08x\r\n", XC_BT_RF->ana4_reg_l);
LOGI("ana5_reg_l: 0x%08x\r\n", XC_BT_RF->ana5_reg_l);
LOGI("ana14_reg_l: 0x%08x\r\n", XC_BT_RF->ana14_reg_l);
LOGI("ana15_reg_l: 0x%08x\r\n", XC_BT_RF->ana15_reg_l);
LOGI("ana16_reg_l: 0x%08x\r\n", XC_BT_RF->ana16_reg_l);
LOGI("ana17_reg_l: 0x%08x\r\n", XC_BT_RF->ana17_reg_l);
LOGI("ana18_reg_l: 0x%08x\r\n", XC_BT_RF->ana18_reg_l);
LOGI("ana21_reg_l: 0x%08x\r\n", XC_BT_RF->ana21_reg_l);
LOGI("AON_RF_AONREG: 0x%08x\r\n", cprao_aon_rf_aonreg_get()); // 0x36
}
/**
* @brief Rf 2.4g dump log
* @param void
*
* @retval void
*/
void rf_dump_log(void)
{
LOGI("***************** 2.4G Param ******************\n");
LOGI("CFG_TOP: 0x%08x\r\n", XC_RF_2_4G->CFG_TOP);
LOGI("EN_AA: 0x%08x\r\n", XC_RF_2_4G->EN_AA);
LOGI("EN_RXADDR: 0x%08x\r\n", XC_RF_2_4G->EN_RXADDR);
LOGI("SETUP_AW: 0x%08x\r\n", XC_RF_2_4G->SETUP_AW);
LOGI("SETUP_RETR: 0x%08x\r\n", XC_RF_2_4G->SETUP_RETR);
LOGI("RF_CH: 0x%08x\r\n", XC_RF_2_4G->RF_CH);
LOGI("SETUP_RF: 0x%08x\r\n", XC_RF_2_4G->SETUP_RF);
LOGI("STATUS: 0x%08x\r\n", XC_RF_2_4G->STATUS);
LOGI("OBSERVE_TX: 0x%08x\r\n", XC_RF_2_4G->OBSERVE_TX);
LOGI("RSSI: 0x%08x\r\n", XC_RF_2_4G->RSSI);
LOGI("RX_ADDR_P0: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P0_H), XC_RF_2_4G->RX_ADDR_P0_L);
LOGI("RX_ADDR_P1: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RX_ADDR_P1_H), XC_RF_2_4G->RX_ADDR_P1_L);
LOGI("RX_ADDR_P2TOP5:0x%08x\r\n", XC_RF_2_4G->RX_ADDR_P2TOP5);
LOGI("BER_RESULT: 0x%08x%08x\r\n", XC_RF_2_4G->BER_ERR_CNT, XC_RF_2_4G->BER_RECV_CNT);
LOGI("AGC_SETTING: 0x%08x\r\n", XC_RF_2_4G->AGC_SETTING);
LOGI("PGA_SETTING: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF00) >> 8, XC_RF_2_4G->PGA_SETTING);
LOGI("TX_ADDR: 0x%02x %08x\r\n", ((XC_RF_2_4G->TX_ADDR_H) & 0xFF), XC_RF_2_4G->TX_ADDR_L);
LOGI("RX_PW_PX: 0x%04x %08x\r\n", 0xFFFF & (XC_RF_2_4G->RX_PW_Px_H), XC_RF_2_4G->RX_PW_Px_L);
LOGI("STATUS_FIFO: 0x%08x\r\n", XC_RF_2_4G->STATUS_FIFO);
LOGI("RSSIREC: 0x%08x\r\n", XC_RF_2_4G->RSSIREC);
LOGI("TXPROC_CFG: 0x%08x\r\n", XC_RF_2_4G->TXPROC_CFG);
LOGI("RXPROC_CFG: 0x%02x %08x\r\n", 0xFF & (XC_RF_2_4G->RXPROC_CFG_H), XC_RF_2_4G->RXPROC_CFG_L);
LOGI("DYNPD: 0x%08x\r\n", XC_RF_2_4G->DYNPD);
LOGI("FEATURE: 0x%08x\r\n", XC_RF_2_4G->FEATURE);
LOGI("PGA_SETTING_H: 0x%08x\r\n", XC_RF_2_4G->TX_ADDR_H);
LOGI("TX_POWER 0x%08x\r\n", (XC_BT_RF->ana21_reg_l >> 6) & 0x3f);
LOGI("ana11_reg_l: 0x%08x\r\n", XC_BT_RF->ana11_reg_l);
LOGI("***********************************************\n");
LOGI("\r\n");
}
#endif // DEBUG_LOG
/**
* @brief RF 2.4g data init
* @param uint8_t * - buff
* uint8 - len
* @retval uint8_t - 0
*/
uint8_t rf_data_init(uint8_t *buff,uint16_t len)
{
for (uint8_t i = 0; i < len; i++) {
buff[i] = i;
}
return RF_SUCCESS;
}
/**
* @brief RF 2.4g tx manage
* @param rf_data_typedef_t * - rf_data
* @retval uint8_t - cnt
*/
void rf_tx_manage(void)
{
//if ((send_cnt < XC_SEND_NUM)) {
rf_timer_flag = false;
send_cnt += 1;
/* Filling in software frame number */
tx_buff[0] = send_cnt;
LOGI("send_cnt:%d\r\n", send_cnt);
rf_buff_info(tx_buff,tx_len);
/* data transmission */
rf_tx_packet(tx_buff, tx_len);
delay_ms(2);
//}
}
/**
* @brief RF 2.4g rx manage
* @param rf_data_typedef_t * - rf_data
* @retval uint32_t - 0
*/
#if !(XINCX_RF_NVIC_MODE)
bool rf_rx_manage(void)
{
static uint32_t conut = 0;
/* Receive event processing */
uint8_t len = rf_rx_event(rx_buff);
/* Receiving end polling data processing */
if (len != 0) {
/* Entering standby mode */
CE_CTL_LOW;
/* Receiving data processing */
if (rx_buff[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE) {
LOGI("%d\r\n", conut);
}
rf_buff_info(rx_buff, len);
/* Receive Count */
conut += 1;
/* Receive read data buffer reset */
memset(rx_buff, 0, len);
len = 0;
/* Entering the receiver */
CE_CTL_HIGH;
}
return 0;
}
#else
bool rf_rx_manage(void)
{
static uint32_t conut = 0;
if (rf24g_rx_irq_flag) {
uint8_t len = recv_len;
rf24g_rx_irq_flag = false;
/* Entering standby mode */
CE_CTL_LOW;
if ((len != 0) && (recv_buf[RF_CONFIRMED_VALUE] == RF_CONFIRMED_VALUE)) {
LOGI("%d\r\n", recv_buf[0]);
}
rf_buff_info(recv_buf, len);
/* Receive Count */
conut += 1;
LOGI("recv:%d\r\n", conut);
/* Receive read data buffer reset */
memset(recv_buf, 0, len);
len = 0;
/* Entering the receiver */
CE_CTL_HIGH;
return true;
}
return false;
}
#endif //!(XINCX_RF_NVIC_MODE)
/**
* @brief RF 2.4g buff info
* @param uint8_t * - buff
* uint8_t len
* @retval void
*/
void rf_buff_info(uint8_t *buff, uint8_t len)
{
for (uint8_t i = 0; i < len; i++)
LOGI("%02x ", buff[i]);
LOGI("\r\n");
}
void app_uart_init(void)
{
GPIO_InitCfg_t gpio_cfg = {0};
gpio_cfg.Mux = GPIO_Mux0;
gpio_cfg.Pull = GPIO_PULLUP;
gpio_cfg.Int = NOT_INT;
gpio_cfg.FunSel = UART0_TX;
gpio_cfg.Pin = GPIO_18;
gpio_cfg.Dir = GPIO_DIR_OUTPUT;
xc_gpio_init(&gpio_cfg);
gpio_cfg.FunSel = UART0_RX;
gpio_cfg.Pin = GPIO_19;
gpio_cfg.Dir = GPIO_DIR_INPUT;
xc_gpio_init(&gpio_cfg);
UART_InitCfg_t uart_cfg = {0};
uart_cfg.Parity = UART_PARITY_DISABLE;
uart_cfg.StopBits = UART_STOP_1_BITS;
uart_cfg.WordLength = UART_DATA_8_BITS;
uart_cfg.BaudRate = UART_BAUDRATE_115200;
uart_cfg.HardwareFlowControl = UART_HWFC_DISABLE;
xc_uart_init(UART0_IDX, &uart_cfg);
}
static void system_sleep_init()
{
uint32_t wake_it_src;
#if (USE_XIP == 1)
#if (USE_ROM_FLASH)
FMC_SPI_Init_Oprt();
#else // (USE_ROM_FLASH)
xc_fmc_spi_init_oprt();
#endif // (USE_ROM_FLASH)
#endif
#if (USE_XIP != 1)
SPI_InitCfg_t spi_cfg = {0};
spi_cfg.Mode = SPI_MODE_MASTER;
spi_cfg.DataSize = SSI_CTRL0_DFS_LEN_8BIT;
spi_cfg.Direction = SSI_CTRL0_TMOD_WR;
spi_cfg.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
spi_cfg.CLKPolarity = SSI_CTRL0_SCPOL_LOW;
spi_cfg.CLKPhase = SPI_CPHA_LEAD;
spi_cfg.FirstBit = SPI_FirstBit_MSB;
xc_spi_init(XC_SPI0, &spi_cfg);
SPI_Flash_PowerDown(XC_SPI0);
#endif
xc_pwr_gpio_sleep_config();
wake_it_src = GPIO_IRQn_WAKE | RTC_IRQn_WAKE|TIMER_AO0_IRQn_WAKE| TIMER0_IRQn_WAKE | MPU_IRQn_WAKE;
xc_pwr_wake_it_set(wake_it_src);
}
static void system_lightsleep_cfg()
{
#if (USE_XIP != 1)
cprao_aon_puctrl1_set(0x4); /* puctrl1= 0x4 , SSI0RX must pulldown*/
#endif
cprao_aon_sys_time_set((RST_READY_TIME << 12) | (OSC32_STABLE_TIME));
xc_pwr_pd_lightsleep_set();
xc_pwr_sleepsrc_mask_set(0x1e001e);
xc_pwr_osc_off();
}
void system_deepsleep_cfg()
{
#if (USE_XIP!=1)
cprao_aon_puctrl1_set(0xf);
#endif
cprao_aon_sys_time_set((RST_READY_TIME<<12) | (OSC32_STABLE_TIME));
xc_pwr_pd_deepsleep_set();
delay_us(100);
xc_pwr_sleepsrc_mask_set(0x1e001e);
xc_pwr_osc_off();
}
void DeepSleep_Demo()
{
system_sleep_init();
// PWRKEY Initialization is required after deep sleep wakeup
xc_pwr_pwrkey_init();
xc_pwr_pwrkey_deepsleep_wake_config(GPIO_2, DEEP_SLEEP_GPIO_WAKE_HIGH_LEVEL);
xc_pwr_pwrkey_deepsleep_wake_config(GPIO_3, DEEP_SLEEP_GPIO_WAKE_LOW_LEVEL);
system_deepsleep_cfg();
while(1)
{
xc_deep_sleep();
}
}
static void sleep_init(void)
{
system_sleep_init();
system_lightsleep_cfg();
/* Timer for sleep-wake*/
Timer_InitCfg_t timer_cfg;
timer_cfg.timer_src_clk = TIMER_CLK_SRC_32K;
timer_cfg.timer_div_clk = TIMER_DIV_CLK_32000Hz;
timer_cfg.timer_mode = TIMER_MODE_SINGLE;
xc_timer_init(TIMER0_IDX, &timer_cfg);
}
void xc_adc_powerdown(void);
void xc_adc_wakeup(void);
void xc_rc32k_soft_calib_disable(void);
void xc_rc32k_soft_calib_enable(void);
void wakeup_timer_set(uint32_t time)
{
cprao_aon_reg1__timer_ao_sleep_clksw__setf(0);
AOTimer_InitCfg_t aotimer_cfg;
aotimer_cfg.aotimer_mode = AOTIMER_MODE_CYCLE;
// Timer0 Config & Start
xc_aotimer_init(AOTIMER0_IDX, &aotimer_cfg);
xc_aotimer_set_value(AOTIMER0_IDX, time);
xc_aotimer_start(AOTIMER0_IDX);
}
__RAM_CODE void xc_mcu_sleep(void)
{
xc_adc_powerdown();
xc_pwr_usb_off();
xc_pwr_rc16m_off();
xc_pwr_rc32k_calib_off();
xc_pwr_opa_tempsensor_off();
xc_pwr_opa_volr_off();
xc_pwr_revddldo_off();
xc_pwr_dcdc_close();
xc_pwr_rfdigital_off();
xc_pwr_rc32k_calib_off();
cprao_aon_reg4__bb_coreldo_normal_sw_mux__setf(1);
xc_pwr_modem_off();
xc_pwr_pd_lightsleep_set();
#if (USE_XIP == 1)
#if (USE_ROM_FLASH)
FMC_SPI_Flash_PowerDown();
#else // (USE_ROM_FLASH)
// xc_fmc_spi_flash_power_down();
#endif // (USE_ROM_FLASH)
xc_pwr_rom_off();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
// cpr_fmc_ctl_set(0x3000 | (1 << 9)); // close FMC
for (int i = 0; i < 10; i++) {
__NOP();
__NOP();
__NOP();
}
#endif
// __disable_irq();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__WFI();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
// cpr_fmc_ctl_set(0x3503);
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
xc_pwr_rom_on();
for (int i = 0; i < 10; i++) {
__NOP();
__NOP();
__NOP();
}
#if (USE_ROM_FLASH)
FMC_SPI_Flash_WakeUp();
#else // (USE_ROM_FLASH)
// xc_fmc_spi_flash_wake_up();
#endif // (USE_ROM_FLASH)
xc_pwr_ao_timer_pclk32m_Set();
// __enable_irq();
#ifdef USED_DCDC
xc_pwr_dcdc_open();
#endif
xc_pwr_modem_on();
xc_pwr_rfdigital_on();
xc_adc_wakeup();
}
void Sleep_Demo()
{
uint32_t duration_timer = (500*1000); //500ms
xc_rc32k_calib_by_soft();
sleep_init();
xc_fmc_spi_init_oprt();
xc_fmc_spi_flash_wake_up();
while(1){
// Checks for sleep have to be done with interrupt disabled
GLOBAL_INT_DISABLE();
xc_timer_set_value(TIMER0_IDX, duration_timer);
xc_timer_start(TIMER0_IDX);
// Before you sleep, turn off the peripheral to make sure it doesn't generate interrupts,
// and then turn it on again after you sleep up.
// For example, timer interrupts
xc_rc32k_soft_calib_disable();
xc_mcu_sleep();
xc_timer_stop(TIMER0_IDX);
xc_rc32k_soft_calib_enable();
GLOBAL_INT_RESTORE();
// The delay can be omitted, rc32k will calibrate every time it wakes up, and it takes 2ms.
delay_ms(3);
}
}
/**
* @brief main
* @details
* @param[in] void
* @param[out] void
* @retval int - 0
* @retval void
* @par identifier
* reserve
* @par other
* void
* @par change log
* Alex created on 2023-05-31
*/
int main(void)
{
tx_len = BUFF_LEN;
/* Clock initialization */
clock_init();
/* Serial port initialization */
app_uart_init();
#if SLEEP_DEMO == SLEEP_MODE
xc_rc32k_calib_by_soft();
system_sleep_init();
system_lightsleep_cfg();
xc_fmc_spi_init_oprt();
xc_fmc_spi_flash_wake_up();
#elif DEEPSLEEP_DEMO == SLEEP_MODE
system_sleep_init();
xc_pwr_pwrkey_init();
system_deepsleep_cfg();
#else
#endif
/* rf 2.4g initialization configuration */
rf24g_init();
/* Set testing frequency points */
rf_set_channel(XINCX_2_4G_CHANNEL);
#if (XINCX_RF_TRANS_RATE == DR_2M)
/* Set 2M mode register configuration */
/* Don't move this function interface */
rf_2M_config();
#endif //(XINCX_RF_TRANS_RATE == DR_2M)
#if (XINCX_RF_NVIC_MODE)
/* Enable RF2.4G interrupts */
NVIC_EnableIRQ(RF24G_IRQn);
/* Configure the RF2.4G interrupt priority */
NVIC_SetPriority(RF24G_IRQn, 0);
#endif // XINCX_RF_NVIC_MODE
#ifdef DEBUG_LOG
#if DEEPSLEEP_DEMO != SLEEP_MODE
/* Register information printing */
rf_dump_log();
#endif
#endif // DEBUG_LOG
#if XINCX_RF_MODE
/* Set emission interval */
timer_init(RF_RX_TIMERx);
/* RX enters receiver */
CE_CTL_HIGH;
#else
/* Set emission interval */
timer_init(RF_TX_TIMERx);
#endif // XINCX_RF_MODE
for (;;) {
#if XINCX_RF_MODE
rf_timer_flag = false;
/* timer start */
timer_start(RF_RX_TIMERx, RECV_TIME_OUT);
while(rf_timer_flag == false)
{
/* receive */
if(rf_rx_manage())
{
timer_stop(RF_RX_TIMERx);
rf_timer_flag = false;
break;
}
}
CE_CTL_LOW;
#if SLEEP_DEMO == SLEEP_MODE
// Checks for sleep have to be done with interrupt disabled
GLOBAL_INT_DISABLE();
/* timer start */
timer_start(RF_RX_TIMERx, RECV_SLEEP_DURATION);
xc_rc32k_soft_calib_disable();
xc_mcu_sleep();
xc_timer_stop(RF_RX_TIMERx);
xc_rc32k_soft_calib_enable();
delay_us(200);
GLOBAL_INT_RESTORE();
#elif DEEPSLEEP_DEMO == SLEEP_MODE
wakeup_timer_set(RECV_DEEPSLEEP_DURATION*1000);
xc_deep_sleep();
#else
rf_timer_flag = false;
/* timer start */
timer_start(RF_RX_TIMERx, RECV_NOSLEEP_DURATION);
while(rf_timer_flag == false)
{
}
#endif /* SLEEP MODE */
CE_CTL_HIGH;
#else /* XINCX_RF_MODE */
/* Launch data packaging filling */
rf_data_init(tx_buff,tx_len);
/* sending */
rf_tx_manage();
#if SLEEP_DEMO == SLEEP_MODE
// Checks for sleep have to be done with interrupt disabled
GLOBAL_INT_DISABLE();
/* timer start */
timer_start(RF_TX_TIMERx, SEND_INTERVAL_SLEEP);
xc_rc32k_soft_calib_disable();
xc_mcu_sleep();
xc_timer_stop(RF_TX_TIMERx);
xc_rc32k_soft_calib_enable();
GLOBAL_INT_RESTORE();
#elif DEEPSLEEP_DEMO == SLEEP_MODE
wakeup_timer_set(SEND_INTERVAL_DEEPSLEEP*1000);
xc_deep_sleep();
#else
/* timer start */
timer_start(RF_TX_TIMERx, SEND_INTERVAL_NOSLEEP);
while(rf_timer_flag == false)
{
}
rf_timer_flag = false;
#endif /* SLEEP MODE */
#endif // XINCX_RF_MODE
}
}